Renesas SH7751 Group, SH7751R Group User Manual

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

SH7751 Group, SH7751R Group

User’s Manual: Hardware

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Rev.3.01 Sep 2013

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1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

Notice

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems;

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.

6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations.

10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products.

11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its

(Note 2) “Renesas Electronics product(s)” means any product develope d or manufactured by or for Renesas Electronics.

equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.

anti-crime systems; and safety equipment etc.

majority-owned subsidiaries.

(2012.4)

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General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.

5. Reading from/Writing to Reserved Bit of Each Register

Note: Treat the reserved bit of register used in each module as follows except in cases where the

specifications for values which are read from or written to the bit are provided in the description. The bit is always read as 0. The write value should be 0 or one, which has been read immediately before writing. Writing the value, which has been read immediately before writing has the advantage of preventing the bit from being affected on its extended function when the function is assigned.

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Preface

The SH-4 (SH7751 Group (SH7751, SH7751R)) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system.

The SH7751 Group is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and PCI controller (PCIC). This series can be used in a wide range of multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA.

Target Readers: This manual is designed for use by people who design application systems using the SH7751 or SH7751R. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required.

This hardware manual contains revisions related to the addition of R-mask functionality. Be sure to check the text for the updated content.

Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7751 and SH7751R. The SH-4 Software Manual contains detailed information of executable instructions. Please read the Software Manual together with this manual.

How to Use the Book:

• To understand general functions

→ Read the manual from the beginning.

The manual explains the CPU, system control functions, peripheral functions and electrical

characteristics in that order.

• To understanding CPU functions

→ Refer to the separate SH-4 Software Manual.

Explanatory Note: Bit sequence: upper bit at left, and lower bit at right

List of Related Documents: The latest documents are available on our Web site. Please make

sure that you have the latest version. (http://www.renesas.com/)

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• User manuals for SH7751 and SH7751R

Name of Document Document No.

SH7751 Group, SH7751R Group Hardware Manual This manual

SH-4 Software Manual REJ09B0318-0600

• User manuals for development tools

Name of Document Document No.

SuperH™ C/C++ Compiler, Assembler, Optimizing Linkage Editor User's

Manual

SuperH™ RISC engine Simulator/Debugger User's Manual REJ10B0210-0300

High-performance Embedded Workshop User's Manual REJ10J1554-0100

REJ10B0047-0100H

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Main Revisions for This Edition

Item Page Revision (See Manual for Details)

All ⎯ Added ONPAC-BGA products (HD6417750SBA200V)

1.1 SH7751/SH7751R Group Features

Table 1.1 SH7751/SH7751R Group Features

2 Table amended

Item Features

CPU

Item Features

Product lineup

SH7751 1.8 V 167 MHz HD6417751BP167 256-pin BGA

HD6417751F167 256-pin QFP

SH7751R 1.5 V 240 MHz HD6417751RBP240 256-pin BGA

HD6417751RBA240H

HD6417751RF240 256-pin QFP

HD6417751RBG240 292-pin BGA

•

Renesas Electronics original SuperH architecture

Abbreviation Voltage

Operating Frequency Model No.

Package

22.2.1 PCI Configuration Register 0 (PCICONF0)

22.12.5 Notes on Parity Error Detection during Master Access

23.1 Absolute Maximum Ratings

Table 23.1 Absolute Maximum Ratings

857 Note amended

Note: * The vendor ID H'1054 specifies Hitachi, Ltd., but

the SH7751 and SH7751R are now products of Renesas Electronics Corp. For information on these products, contact Renesas Electronics Corp.

980,

Newly added

981

983 Table amended and note added

Item Symbol Value Unit

I/O, RTC, CPG power supply voltage V

Internal power supply voltage VDD, V

Input voltage Vin –0.3 to V

Operating temperature T

Storage temperature T

DDQ

DD-RTC

DD-CPG

–20 to 75, –40 to 85*2 °C

opr

–55 to 125 °C

stg

Notes: 1. HD6417751R only.

2. HD6417751RBA240HV only.

–0.3 to 2.5

DD-PLL1/2

–0.3 to 4.2

–0.3 to 4.6*

–0.3 to 2.1*

+0.3 V

DDQ

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Item Page Revision (See Manual for Details)

23.2 DC Characteristics

Table 23.2 DC

982, 983

Table title amended and note added

Notes: 3. Ta = –40 to 85°C for the HD6417751RBA240HV. Characteristics (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV)

Ta = –20 to +75°C*3

Table 23.4 DC Characteristics (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*3)

988,. 989

Table title amended and note added

Notes: 3. This is the case when the device in use is an

HD6417751RBA240HV running at 200 MHz.

4. Ta = –40 to 85°C for the HD6417751RBA240HV.

Ta = –20 to +75°C*4

23.3 AC Characteristics

996 Table title amended

Table 23.9 Clock Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV)

Table 23.11 Clock Timing (HD6417751RBP200 (V), HD6417751RBG200 (V),

997 Table title amended and note added

Note: * This is the case when the device in use is an

HD6417751RBA240HV running at 200 MHz.

HD6417751RBA240HV*)

23.3.1 Clock and Control Signal Timing

Table 23.14 Clock and Control Signal Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV)

= 3.0 to 3.6 V, VDD =

DDQ

998, 999

Table title and table amended and note added

Item Symbol Min Max Unit Figure

Standby return oscillation settling time 1*

Standby return oscillation settling time 2*

Standby return oscillation settling time 3*1 t

2 — ms

OSC2

2 — ms

OSC3

2 — ms

OSC4

Notes: 1. When the oscillation settling time of the crystal

resonator is 1 ms or less.

2. Ta = –40 to 85°C for the HD6417751RBA240HV.

1.5 V, Ta = –20 to 75°C*2, C

= 30 pF

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Item Page Revision (See Manual for Details)

23.3.1 Clock and Control Signal Timing

Table 23.16 Clock and Control Signal Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*2)

= 3.0 to 3.6 V, VDD =

DDQ

1.5 V, Ta = –20 to 75°C*3, C

= 30 pF

23.3.2 Control Signal Timing

Table 23.19 Control Signal Timing

1002, 1003

Table title and table amended and note added

Item Symbol Min Max Unit Figure

Standby return oscillation settling time 1*

Standby return oscillation settling time 2*

Standby return oscillation settling time 3*1 t

2 — ms

OSC2

2 — ms

OSC3

2 — ms

OSC4

Notes: 1. When the oscillation settling time of the crystal

resonator is 1 ms or less.

2. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz.

3. Ta = –40 to 85°C for the HD6417751RBA240HV.

1012 Table amended and note added

HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV

Item Symbol Min Max Min Max Min Max Min Max Unit Figure

Notes: 1. V

= 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to

DDQ

HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 RBA240HV

*1 *

75°C*3, CL = 30 pF, PLL2 on

2. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz.

3. Ta = –40 to 85°C for the HD6417751RBA240HV.

23.3.3 Bus Timing

Table 23.21 Bus Timing (1)

1016, 1017

Table amended and note added

HD6417751 RBP240 (V) HD6417751 RBG240 (V)

Item Symbol Min Max Min Max Min Max Min Max Unit Notes

Notes: 1. V

HD6417751 RBA240HV

= 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to

DDQ

HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 RBA240HV

75°C*3, CL = 30 pF, PLL2 on

2. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz.

3. Ta = –40 to 85°C for the HD6417751RBA240HV.

HD6417751 RF240 (V)

HD6417751 RF200 (V)

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Item Page Revision (See Manual for Details)

23.3.4 Peripheral Module Signal Timing

Table 23.23 Peripheral Module Signal Timing (1)

1067 to 1069

Table amended and note added

HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751

Module Item Symbol Min Max Min Max Min Max Min Max Unit Figure Notes

Notes: 1. V

RBA240HV

= 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to

DDQ

HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 RBA240HV

*2 *2 *2

HD6417751 RF240 (V)

75°C*4, CL = 30 pF, PLL2 on

3. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz.

4. Ta = –40 to 85°C for the HD6417751RBA240HV.

Table 23.25 PCIC Signal Timing (in PCIREQ/PCIGNT NonPort Mode) (1)

1076

Table title amended and note added

Notes: 1. HD6417751RF240 (V), HD6417751RF200 (V)

2. Ta = –40 to 85°C for the HD6417751RBA240HV.

HD6417751RBP240 (V), HD6417751RBP200 (V), HD6417751RBG240 (V), HD6417751RBG200 (V), HD6417751RBA240HV, HD6417751RF240 (V), HD6417751RF200 (V):

= 3.0 to 3.6 V, VDD =

DDQ

Asterisk "*" in table changed to "*1"

"3.0 (3.5*)" → "3.0 (3.5*1)"

1.5 V, Ta = –20 to 75°C*2, = 30 pF

Table 23.27 PCIC Signal Timing (With PCIREQ/PCIGNT Port

1079 Table title amended and note added

Note: * Ta = –40 to 85°C for the HD6417751RBA240HV.

Settings in Non-Host Mode) (1)

HD6417751RBP240 (V), HD6417751RBP200 (V), HD6417751RBG240 (V), HD6417751RBG200 (V), HD6417751RBA240HV, HD6417751RF240 (V), HD6417751RF200 (V):

= 3.0 to 3.6 V, VDD =

DDQ

1.5 V, Ta = –20 to 75°C*, = 30 pF

HD6417751 RF200 (V)

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Item Page Revision (See Manual for Details)

Appendix B Package

1092 Figure title amended

Dimensions

Figure B.2 Package Dimensions (256-pin BGA: Devices Other than HD6417751RBA240HV)

Figure B.4 Package

1094 Figure newly added

Dimensions

(256-Pin BGA: HD6417750RBA240HV)

D.2 Handling of Unused Pins

Table D.4 Handling of

1105 Table amended

Pin Name I/O Handling

AD31–AD0 I/O Pull up to 3.3 V*

Pins When PCI Is Not Used

Appendix H Product Lineup

Table H.1 SH7751/SH7751R Product Lineup

1125 Table note amended

Notes: 1. Contact a Renesas sales office regarding

product versions with specifications for a wider temperature range (−40 to +85°C). The wide temperature range (−40 to +85°C) is the standard specification for the HD6417751RBA240HV.

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All trademarks and registered trademarks are the property of their respective owners.

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Contents

Section 1 Overview................................................................................................1

1.1 SH7751/SH7751R Group Features ........................................................................................ 1

1.2 Block Diagram ....................................................................................................................... 9

1.3 Pin Arrangement ..................................................................................................................10

1.4 Pin Functions ....................................................................................................................... 13

1.4.1 Pin Functions (256-Pin QFP).................................................................................. 13

1.4.2 Pin Functions (256-Pin BGA)................................................................................. 24

1.4.3 Pin Functions (292-Pin BGA)................................................................................. 35

Section 2 Programming Model ............................................................................47

2.1 Data Formats ........................................................................................................................ 47

2.2 Register Configuration ......................................................................................................... 48

2.2.1 Privileged Mode and Banks.................................................................................... 48

2.2.2 General Registers.................................................................................................... 51

2.2.3 Floating-Point Registers.......................................................................................... 53

2.2.4 Control Registers ....................................................................................................55

2.2.5 System Registers..................................................................................................... 56

2.3 Memory-Mapped Registers.................................................................................................. 58

2.4 Data Format in Registers...................................................................................................... 59

2.5 Data Formats in Memory ..................................................................................................... 59

2.6 Processor States ................................................................................................................... 60

2.7 Processor Modes .................................................................................................................. 62

Section 3 Memory Management Unit (MMU) ....................................................63

3.1 Overview.............................................................................................................................. 63

3.1.1 Features................................................................................................................... 63

3.1.2 Role of the MMU.................................................................................................... 63

3.1.3 Register Configuration............................................................................................ 66

3.1.4 Caution.................................................................................................................... 66

3.2 Register Descriptions ...........................................................................................................67

3.3 Address Space ...................................................................................................................... 71

3.3.1 Physical Address Space .......................................................................................... 71

3.3.2 External Memory Space.......................................................................................... 74

3.3.3 Virtual Address Space............................................................................................. 75

3.3.4 On-Chip RAM Space.............................................................................................. 76

3.3.5 Address Translation ................................................................................................ 76

3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode ......................77

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3.3.7 Address Space Identifier (ASID)............................................................................ 77

3.4 TLB Functions ..................................................................................................................... 78

3.4.1 Unified TLB (UTLB) Configuration ...................................................................... 78

3.4.2 Instruction TLB (ITLB) Configuration................................................................... 82

3.4.3 Address Translation Method................................................................................... 82

3.5 MMU Functions...................................................................................................................85

3.5.1 MMU Hardware Management................................................................................ 85

3.5.2 MMU Software Management ................................................................................. 85

3.5.3 MMU Instruction (LDTLB).................................................................................... 85

3.5.4 Hardware ITLB Miss Handling .............................................................................. 86

3.5.5 Avoiding Synonym Problems................................................................................. 87

3.6 MMU Exceptions................................................................................................................. 88

3.6.1 Instruction TLB Multiple Hit Exception................................................................. 88

3.6.2 Instruction TLB Miss Exception............................................................................. 88

3.6.3 Instruction TLB Protection Violation Exception.................................................... 89

3.6.4 Data TLB Multiple Hit Exception .......................................................................... 90

3.6.5 Data TLB Miss Exception ...................................................................................... 91

3.6.6 Data TLB Protection Violation Exception.............................................................. 92

3.6.7 Initial Page Write Exception................................................................................... 93

3.7 Memory-Mapped TLB Configuration ................................................................................. 94

3.7.1 ITLB Address Array ............................................................................................... 94

3.7.2 ITLB Data Array 1.................................................................................................. 95

3.7.3 ITLB Data Array 2.................................................................................................. 96

3.7.4 UTLB Address Array.............................................................................................. 97

3.7.5 UTLB Data Array 1 ................................................................................................ 98

3.7.6 UTLB Data Array 2 ................................................................................................ 99

3.8 Usage Notes ....................................................................................................................... 100

Section 4 Caches................................................................................................101

4.1 Overview............................................................................................................................ 101

4.1.1 Features................................................................................................................. 101

4.1.2 Register Configuration.......................................................................................... 102

4.2 Register Descriptions ......................................................................................................... 103

4.3 Operand Cache (OC) ......................................................................................................... 105

4.3.1 Configuration........................................................................................................ 105

4.3.2 Read Operation ..................................................................................................... 108

4.3.3 Write Operation .................................................................................................... 109

4.3.4 Write-Back Buffer ................................................................................................ 111

4.3.5 Write-Through Buffer........................................................................................... 111

4.3.6 RAM Mode........................................................................................................... 111

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4.3.7 OC Index Mode .................................................................................................... 113

4.3.8 Coherency between Cache and External Memory................................................ 113

4.3.9 Prefetch Operation ................................................................................................ 113

4.3.10 Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced

Mode..................................................................................................................... 114

4.4 Instruction Cache (IC)........................................................................................................ 116

4.4.1 Configuration........................................................................................................ 116

4.4.2 Read Operation ..................................................................................................... 119

4.4.3 IC Index Mode...................................................................................................... 120

4.5 Memory-Mapped Cache Configuration (SH7751)............................................................. 120

4.5.1 IC Address Array.................................................................................................. 120

4.5.2 IC Data Array........................................................................................................ 122

4.5.3 OC Address Array ................................................................................................ 123

4.5.4 OC Data Array...................................................................................................... 124

4.6 Memory-Mapped Cache Configuration (SH7751R) .......................................................... 125

4.6.1 IC Address Array.................................................................................................. 125

4.6.2 IC Data Array........................................................................................................ 127

4.6.3 OC Address Array ................................................................................................ 128

4.6.4 OC Data Array...................................................................................................... 129

4.6.5 Summary of Memory-Mapped OC Addresses...................................................... 130

4.7 Store Queues ...................................................................................................................... 131

4.7.1 SQ Configuration.................................................................................................. 131

4.7.2 SQ Writes.............................................................................................................. 131

4.7.3 Transfer to External Memory................................................................................ 132

4.7.4 Determination of SQ Access Exception................................................................ 133

4.7.5 SQ Read (SH7751R only)..................................................................................... 133

4.7.6 SQ Usage Notes (SH7751 Only) .......................................................................... 134

Section 5 Exceptions..........................................................................................137

5.1 Overview............................................................................................................................ 137

5.1.1 Features................................................................................................................. 137

5.1.2 Register Configuration.......................................................................................... 137

5.2 Register Descriptions ......................................................................................................... 138

5.3 Exception Handling Functions ........................................................................................... 139

5.3.1 Exception Handling Flow ..................................................................................... 139

5.3.2 Exception Handling Vector Addresses ................................................................. 139

5.4 Exception Types and Priorities .......................................................................................... 140

5.5 Exception Flow ..................................................................................................................143

5.5.1 Exception Flow..................................................................................................... 143

5.5.2 Exception Source Acceptance............................................................................... 144

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5.5.3 Exception Requests and BL Bit ............................................................................ 146

5.5.4 Return from Exception Handling.......................................................................... 146

5.6 Description of Exceptions.................................................................................................. 146

5.6.1 Resets.................................................................................................................... 147

5.6.2 General Exceptions............................................................................................... 152

5.6.3 Interrupts............................................................................................................... 166

5.6.4 Priority Order with Multiple Exceptions .............................................................. 169

5.7 Usage Notes ....................................................................................................................... 170

5.8 Restrictions ........................................................................................................................ 171

Section 6 Floating-Point Unit............................................................................173

6.1 Overview............................................................................................................................ 173

6.2 Data Formats...................................................................................................................... 173

6.2.1 Floating-Point Format........................................................................................... 173

6.2.2 Non-Numbers (NaN) ............................................................................................ 175

6.2.3 Denormalized Numbers ........................................................................................ 176

6.3 Registers ............................................................................................................................ 177

6.3.1 Floating-Point Registers ....................................................................................... 177

6.3.2 Floating-Point Status/Control Register (FPSCR) ................................................. 179

6.3.3 Floating-Point Communication Register (FPUL)................................................. 180

6.4 Rounding............................................................................................................................ 181

6.5 Floating-Point Exceptions.................................................................................................. 181

6.6 Graphics Support Functions............................................................................................... 183

6.6.1 Geometric Operation Instructions......................................................................... 183

6.6.2 Pair Single-Precision Data Transfer...................................................................... 184

6.7 Usage Notes ....................................................................................................................... 185

6.7.1 Rounding Mode and Underflow Flag ................................................................... 185

6.7.2 Setting of Overflow Flag by FIPR or FTRV Instruction ...................................... 186

6.7.3 Sign of Operation Result when Using FIPR or FTRV Instruction ....................... 187

6.7.4 Notes on Double-Precision FADD and FSUB Instructions.................................. 187

Section 7 Instruction Set.................................................................................... 189

7.1 Execution Environment ..................................................................................................... 189

7.2 Addressing Modes ............................................................................................................. 191

7.3 Instruction Set .................................................................................................................... 195

7.4 Usage Notes ....................................................................................................................... 207

7.4.1 Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction

(H'FFFD) .............................................................................................................. 207

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Section 8 Pipelining ...........................................................................................211

8.1 Pipelines............................................................................................................................. 211

8.2 Parallel-Executability ......................................................................................................... 218

8.3 Execution Cycles and Pipeline Stalling ............................................................................. 222

8.4 Usage Notes ....................................................................................................................... 238

Section 9 Power-Down Modes ..........................................................................239

9.1 Overview............................................................................................................................ 239

9.1.1 Types of Power-Down Modes .............................................................................. 239

9.1.2 Register Configuration.......................................................................................... 241

9.1.3 Pin Configuration.................................................................................................. 241

9.2 Register Descriptions ......................................................................................................... 242

9.2.1 Standby Control Register (STBCR)...................................................................... 242

9.2.2 Peripheral Module Pin High Impedance Control.................................................. 244

9.2.3 Peripheral Module Pin Pull-Up Control................................................................ 244

9.2.4 Standby Control Register 2 (STBCR2)................................................................. 245

9.2.5 Clock Stop Register 00 (CLKSTP00)................................................................... 246

9.2.6 Clock Stop Clear Register 00 (CLKSTPCLR00).................................................. 247

9.3 Sleep Mode ........................................................................................................................ 248

9.3.1 Transition to Sleep Mode...................................................................................... 248

9.3.2 Exit from Sleep Mode........................................................................................... 248

9.4 Deep Sleep Mode ............................................................................................................... 248

9.4.1 Transition to Deep Sleep Mode ............................................................................248

9.4.2 Exit from Deep Sleep Mode ................................................................................. 249

9.5 Pin Sleep Mode ..................................................................................................................249

9.5.1 Transition to Pin Sleep Mode ............................................................................... 249

9.5.2 Exit from Pin Sleep Mode..................................................................................... 249

9.6 Standby Mode ....................................................................................................................249

9.6.1 Transition to Standby Mode.................................................................................. 249

9.6.2 Exit from Standby Mode....................................................................................... 250

9.6.3 Clock Pause Function ........................................................................................... 251

9.7 Module Standby Function .................................................................................................. 251

9.7.1 Transition to Module Standby Function ............................................................... 251

9.7.2 Exit from Module Standby Function .................................................................... 252

9.8 Hardware Standby Mode ................................................................................................... 253

9.8.1 Transition to Hardware Standby Mode................................................................. 253

9.8.2 Exit from Hardware Standby Mode...................................................................... 253

9.8.3 Usage Notes .......................................................................................................... 254

9.9 STATUS Pin Change Timing ............................................................................................ 254

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9.9.1 In Reset ................................................................................................................. 255

9.9.2 In Exit from Standby Mode .................................................................................. 256

9.9.3 In Exit from Sleep Mode ...................................................................................... 257

9.9.4 In Exit from Deep Sleep Mode ............................................................................. 260

9.9.5 Hardware Standby Mode Timing.......................................................................... 262

9.10 Usage Notes ....................................................................................................................... 264

9.10.1 Note on Current Consumption .............................................................................. 264

Section 10 Clock Oscillation Circuits ...............................................................267

10.1 Overview............................................................................................................................ 267

10.1.1 Features................................................................................................................. 267

10.2 Overview of CPG............................................................................................................... 269

10.2.1 Block Diagram of CPG......................................................................................... 269

10.2.2 CPG Pin Configuration ......................................................................................... 272

10.2.3 CPG Register Configuration ................................................................................. 272

10.3 Clock Operating Modes ..................................................................................................... 273

10.4 CPG Register Description.................................................................................................. 275

10.4.1 Frequency Control Register (FRQCR) ................................................................. 275

10.5 Changing the Frequency .................................................................................................... 278

10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off) ............ 278

10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)............. 278

10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On) ....................... 279

10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off) ...................... 279

10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ................................ 279

10.6 Output Clock Control......................................................................................................... 280

10.7 Overview of Watchdog Timer ........................................................................................... 280

10.7.1 Block Diagram...................................................................................................... 280

10.7.2 Register Configuration.......................................................................................... 281

10.8 WDT Register Descriptions............................................................................................... 281

10.8.1 Watchdog Timer Counter (WTCNT).................................................................... 281

10.8.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 282

10.8.3 Notes on Register Access ..................................................................................... 284

10.9 Using the WDT.................................................................................................................. 285

10.9.1 Standby Clearing Procedure ................................................................................. 285

10.9.2 Frequency Changing Procedure............................................................................ 285

10.9.3 Using Watchdog Timer Mode .............................................................................. 286

10.9.4 Using Interval Timer Mode .................................................................................. 286

10.10 Notes on Board Design ...................................................................................................... 287

10.11 Usage Notes ....................................................................................................................... 289

10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7751 Only)................. 289

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Section 11 Realtime Clock (RTC) .....................................................................291

11.1 Overview............................................................................................................................ 291

11.1.1 Features................................................................................................................. 291

11.1.2 Block Diagram ...................................................................................................... 292

11.1.3 Pin Configuration.................................................................................................. 293

11.1.4 11.1.4 Register Configuration ............................................................................... 293

11.2 Register Descriptions......................................................................................................... 295

11.2.1 64 Hz Counter (R64CNT)..................................................................................... 295

11.2.2 Second Counter (RSECCNT) ............................................................................... 296

11.2.3 Minute Counter (RMINCNT) ............................................................................... 296

11.2.4 Hour Counter (RHRCNT)..................................................................................... 297

11.2.5 Day-of-Week Counter (RWKCNT)...................................................................... 297

11.2.6 Day Counter (RDAYCNT) ................................................................................... 298

11.2.7 Month Counter (RMONCNT) .............................................................................. 298

11.2.8 Year Counter (RYRCNT) ..................................................................................... 299

11.2.9 Second Alarm Register (RSECAR) ...................................................................... 300

11.2.10 Minute Alarm Register (RMINAR)...................................................................... 300

11.2.11 Hour Alarm Register (RHRAR) ........................................................................... 301

11.2.12 Day-of-Week Alarm Register (RWKAR)............................................................. 301

11.2.13 Day Alarm Register (RDAYAR).......................................................................... 302

11.2.14 Month Alarm Register (RMONAR) ..................................................................... 303

11.2.15 RTC Control Register 1 (RCR1)........................................................................... 303

11.2.16 RTC Control Register 2 (RCR2)........................................................................... 305

11.2.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR)

(SH7751R Only)................................................................................................... 308

11.3 Operation ........................................................................................................................... 309

11.3.1 Time Setting Procedures ....................................................................................... 309

11.3.2 Time Reading Procedures ..................................................................................... 311

11.3.3 Alarm Function ..................................................................................................... 312

11.4 Interrupts............................................................................................................................ 313

11.5 Usage Notes ....................................................................................................................... 313

11.5.1 Register Initialization............................................................................................ 313

11.5.2 Carry Flag and Interrupt Flag in Standby Mode ...................................................313

11.5.3 Crystal Oscillation Circuit .................................................................................... 313

Section 12 Timer Unit (TMU) ...........................................................................315

12.1 Overview............................................................................................................................ 315

12.1.1 Features................................................................................................................. 315

12.1.2 Block Diagram ...................................................................................................... 316

12.1.3 Pin Configuration.................................................................................................. 316

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12.1.4 Register Configuration.......................................................................................... 317

12.2 Register Descriptions......................................................................................................... 318

12.2.1 Timer Output Control Register (TOCR) ............................................................... 318

12.2.2 Timer Start Register (TSTR) ................................................................................ 319

12.2.3 Timer Start Register 2 (TSTR2) ........................................................................... 320

12.2.4 Timer Constant Registers (TCOR) ....................................................................... 321

12.2.5 Timer Counters (TCNT) ....................................................................................... 321

12.2.6 Timer Control Registers (TCR) ............................................................................ 322

12.2.7 Input Capture Register 2 (TCPR2) ....................................................................... 326

12.3 Operation ........................................................................................................................... 327

12.3.1 Counter Operation ................................................................................................ 327

12.3.2 Input Capture Function ......................................................................................... 330

12.4 Interrupts............................................................................................................................ 332

12.5 Usage Notes ....................................................................................................................... 332

12.5.1 Register Writes ..................................................................................................... 332

12.5.2 TCNT Register Reads ........................................................................................... 333

12.5.3 Resetting the RTC Frequency Divider.................................................................. 333

12.5.4 External Clock Frequency .................................................................................... 333

Section 13 Bus State Controller (BSC) ............................................................. 335

13.1 Overview............................................................................................................................ 335

13.1.1 Features................................................................................................................. 335

13.1.2 Block Diagram...................................................................................................... 337

13.1.3 Pin Configuration.................................................................................................. 338

13.1.4 Register Configuration.......................................................................................... 340

13.1.5 Overview of Areas ................................................................................................ 341

13.1.6 PCMCIA Support ................................................................................................. 344

13.2 Register Descriptions......................................................................................................... 348

13.2.1 Bus Control Register 1 (BCR1) ............................................................................ 348

13.2.2 Bus Control Register 2 (BCR2) ............................................................................ 357

13.2.3 Bus Control Register 3 (BCR3) (SH7751R Only)................................................ 359

13.2.4 Bus Control Register 4 (BCR4) (SH7751R Only)................................................ 361

13.2.5 Wait Control Register 1 (WCR1) ......................................................................... 363

13.2.6 Wait Control Register 2 (WCR2) ......................................................................... 366

13.2.7 Wait Control Register 3 (WCR3) ......................................................................... 374

13.2.8 Memory Control Register (MCR)......................................................................... 376

13.2.9 PCMCIA Control Register (PCR) ........................................................................ 383

13.2.10 Synchronous DRAM Mode Register (SDMR) ..................................................... 386

13.2.11 Refresh Timer Control/Status Register (RTCSR)................................................. 388

13.2.12 Refresh Timer Counter (RTCNT)......................................................................... 390

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13.2.13 Refresh Time Constant Register (RTCOR) .......................................................... 391

13.2.14 Refresh Count Register (RFCR) ........................................................................... 392

13.2.15 Notes on Accessing Refresh Control Registers .................................................... 392

13.3 Operation ........................................................................................................................... 393

13.3.1 Endian/Access Size and Data Alignment.............................................................. 393

13.3.2 Areas ..................................................................................................................... 400

13.3.3 SRAM Interface .................................................................................................... 405

13.3.4 DRAM Interface ................................................................................................... 413

13.3.5 Synchronous DRAM Interface ............................................................................. 427

13.3.6 Burst ROM Interface ............................................................................................ 457

13.3.7 PCMCIA Interface ................................................................................................ 460

13.3.8 MPX Interface....................................................................................................... 471

13.3.9 Byte Control SRAM Interface .............................................................................. 485

13.3.10 Waits between Access Cycles............................................................................... 489

13.3.11 Bus Arbitration ..................................................................................................... 490

13.3.12 Master Mode......................................................................................................... 493

13.3.13 Slave Mode ........................................................................................................... 494

13.3.14 Cooperation between Master and Slave................................................................ 495

13.3.15 Notes on Usage ..................................................................................................... 495

Section 14 Direct Memory Access Controller (DMAC) ...................................497

14.1 Overview............................................................................................................................ 497

14.1.1 Features................................................................................................................. 497

14.1.2 Block Diagram (SH7751) ..................................................................................... 500

14.1.3 Pin Configuration (SH7751) ................................................................................. 501

14.1.4 Register Configuration (SH7751) .........................................................................502

14.2 Register Descriptions......................................................................................................... 504

14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ........................................... 504

14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)................................... 505

14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3).......................... 506

14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3).................................... 507

14.2.5 DMA Operation Register (DMAOR) ................................................................... 515

14.3 Operation ........................................................................................................................... 517

14.3.1 DMA Transfer Procedure ..................................................................................... 517

14.3.2 DMA Transfer Requests ....................................................................................... 520

14.3.3 Channel Priorities ................................................................................................. 523

14.3.4 Types of DMA Transfer........................................................................................ 526

14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 535

14.3.6 Ending DMA Transfer .......................................................................................... 549

14.4 Examples of Use ................................................................................................................ 552

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14.4.1 Examples of Transfer between External Memory and an External Device

with DACK........................................................................................................... 552

14.5 On-Demand Data Transfer Mode (DDT Mode) ................................................................ 553

14.5.1 Operation .............................................................................................................. 553

14.5.2 Pins in DDT Mode................................................................................................ 555

14.5.3 Transfer Request Acceptance on Each Channel ................................................... 558

14.5.4 Notes on Use of DDT Module .............................................................................. 580

14.6 Configuration of the DMAC (SH7751R)........................................................................... 583

14.6.1 Block Diagram of the DMAC............................................................................... 583

14.6.2 Pin Configuration (SH7751R) .............................................................................. 584

14.6.3 Register Configuration (SH7751R) ...................................................................... 585

14.7 Register Descriptions (SH7751R)...................................................................................... 588

14.7.1 DMA Source Address Registers 0−7 (SAR0−SAR7)........................................... 588

14.7.2 DMA Destination Address Registers 0−7 (DAR0−DAR7) .................................. 588

14.7.3 DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7) ......................... 589

14.7.4 DMA Channel Control Registers 0−7 (CHCR0−CHCR7) ................................... 589

14.7.5 DMA Operation Register (DMAOR) ................................................................... 593

14.8 Operation (SH7751R) ........................................................................................................ 595

14.8.1 Channel Specification for a Normal DMA Transfer............................................. 595

14.8.2 Channel Specification for DDT-Mode DMA Transfer ......................................... 595

14.8.3 Transfer Channel Notification in DDT Mode....................................................... 596

14.8.4 Clearing Request Queues by DTR Format ........................................................... 597

14.8.5 Interrupt-Request Codes ....................................................................................... 597

14.9 Usage Notes ....................................................................................................................... 600

Section 15 Serial Communication Interface (SCI)............................................603

15.1 Overview............................................................................................................................ 603

15.1.1 Features................................................................................................................. 603

15.1.2 Block Diagram...................................................................................................... 605

15.1.3 Pin Configuration.................................................................................................. 606

15.1.4 Register Configuration.......................................................................................... 606

15.2 Register Descriptions......................................................................................................... 607

15.2.1 Receive Shift Register (SCRSR1) ........................................................................ 607

15.2.2 Receive Data Register (SCRDR1) ........................................................................ 607

15.2.3 Transmit Shift Register (SCTSR1) ....................................................................... 608

15.2.4 Transmit Data Register (SCTDR1)....................................................................... 608

15.2.5 Serial Mode Register (SCSMR1).......................................................................... 609

15.2.6 Serial Control Register (SCSCR1)........................................................................ 611

15.2.7 Serial Status Register (SCSSR1) .......................................................................... 615

15.2.8 Serial Port Register (SCSPTR1) ........................................................................... 619

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15.2.9 Bit Rate Register (SCBRR1) ................................................................................ 623

15.3 Operation ........................................................................................................................... 631

15.3.1 Overview............................................................................................................... 631

15.3.2 Operation in Asynchronous Mode ........................................................................633

15.3.3 Multiprocessor Communication Function............................................................. 644

15.3.4 Operation in Synchronous Mode .......................................................................... 655

15.4 SCI Interrupt Sources and DMAC ..................................................................................... 665

15.5 Usage Notes ....................................................................................................................... 666

Section 16 Serial Communication Interface with FIFO (SCIF) ........................671

16.1 Overview............................................................................................................................ 671

16.1.1 Features................................................................................................................. 671

16.1.2 Block Diagram ...................................................................................................... 673

16.1.3 Pin Configuration.................................................................................................. 674

16.1.4 Register Configuration.......................................................................................... 674

16.2 Register Descriptions......................................................................................................... 675

16.2.1 Receive Shift Register (SCRSR2)......................................................................... 675

16.2.2 Receive FIFO Data Register (SCFRDR2) ............................................................ 675

16.2.3 Transmit Shift Register (SCTSR2) ....................................................................... 676

16.2.4 Transmit FIFO Data Register (SCFTDR2) ........................................................... 676

16.2.5 Serial Mode Register (SCSMR2).......................................................................... 677

16.2.6 Serial Control Register (SCSCR2)........................................................................ 679

16.2.7 Serial Status Register (SCFSR2) .......................................................................... 682

16.2.8 Bit Rate Register (SCBRR2) ................................................................................ 688

16.2.9 FIFO Control Register (SCFCR2) ........................................................................ 689

16.2.10 FIFO Data Count Register (SCFDR2).................................................................. 692

16.2.11 Serial Port Register (SCSPTR2) ........................................................................... 693

16.2.12 Line Status Register (SCLSR2) ............................................................................ 700

16.3 Operation ........................................................................................................................... 701

16.3.1 Overview............................................................................................................... 701

16.3.2 Serial Operation ....................................................................................................703

16.4 SCIF Interrupt Sources and the DMAC............................................................................. 713

16.5 Usage Notes ....................................................................................................................... 714

Section 17 Smart Card Interface........................................................................719

17.1 Overview............................................................................................................................ 719

17.1.1 Features................................................................................................................. 719

17.1.2 Block Diagram ...................................................................................................... 720

17.1.3 Pin Configuration.................................................................................................. 721

17.1.4 Register Configuration.......................................................................................... 721

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17.2 Register Descriptions......................................................................................................... 722

17.2.1 Smart Card Mode Register (SCSCMR1) .............................................................. 722

17.2.2 Serial Mode Register (SCSMR1).......................................................................... 723

17.2.3 Serial Control Register (SCSCR1)........................................................................ 724

17.2.4 Serial Status Register (SCSSR1) .......................................................................... 725

17.3 Operation ........................................................................................................................... 726

17.3.1 Overview .............................................................................................................. 726

17.3.2 Pin Connections .................................................................................................... 727

17.3.3 Data Format .......................................................................................................... 728

17.3.4 Register Settings ................................................................................................... 729

17.3.5 Clock..................................................................................................................... 731

17.3.6 Data Transfer Operations...................................................................................... 734

17.4 Usage Notes ....................................................................................................................... 741

Section 18 I/O Ports...........................................................................................747

18.1 Overview............................................................................................................................ 747

18.1.1 Features................................................................................................................. 747

18.1.2 Block Diagrams .................................................................................................... 748

18.1.3 Pin Configuration.................................................................................................. 755

18.1.4 Register Configuration.......................................................................................... 758

18.2 Register Descriptions......................................................................................................... 759

18.2.1 Port Control Register A (PCTRA) ........................................................................ 759

18.2.2 Port Data Register A (PDTRA) ............................................................................ 760

18.2.3 Port Control Register B (PCTRB) ........................................................................ 761

18.2.4 Port Data Register B (PDTRB)............................................................................. 762

18.2.5 GPIO Interrupt Control Register (GPIOIC).......................................................... 763

18.2.6 Serial Port Register (SCSPTR1) ........................................................................... 764

18.2.7 Serial Port Register (SCSPTR2) ........................................................................... 766

Section 19 Interrupt Controller (INTC)............................................................. 769

19.1 Overview............................................................................................................................ 769

19.1.1 Features................................................................................................................. 769

19.1.2 Block Diagram...................................................................................................... 769

19.1.3 Pin Configuration.................................................................................................. 771

19.1.4 Register Configuration.......................................................................................... 771

19.2 Interrupt Sources................................................................................................................ 772

19.2.1 NMI Interrupt........................................................................................................ 772

19.2.2 IRL Interrupts ....................................................................................................... 773

19.2.3 On-Chip Peripheral Module Interrupts ................................................................. 775

19.2.4 Interrupt Exception Handling and Priority............................................................ 776

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19.3 Register Descriptions......................................................................................................... 780

19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ................................................ 780

19.3.2 Interrupt Control Register (ICR)........................................................................... 781

19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00) .................................... 783

19.3.4 Interrupt Factor Register 00 (INTREQ00)............................................................ 784

19.3.5 Interrupt Mask Register 00 (INTMSK00)............................................................. 784

19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) ...........................................785

19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation ........................... 786

19.4 INTC Operation ................................................................................................................. 787

19.4.1 Interrupt Operation Sequence ............................................................................... 787

19.4.2 Multiple Interrupts ................................................................................................789

19.4.3 Interrupt Masking with MAI Bit........................................................................... 789

19.5 Interrupt Response Time.................................................................................................... 790

19.6 Usage Notes ....................................................................................................................... 791

19.6.1 NMI Interrupts (SH7751 Only)............................................................................. 791

Section 20 User Break Controller (UBC) ..........................................................795

20.1 Overview............................................................................................................................ 795

20.1.1 Features................................................................................................................. 795

20.1.2 Block Diagram ...................................................................................................... 796

20.2 Register Descriptions......................................................................................................... 798

20.2.1 Access to UBC Registers ...................................................................................... 798

20.2.2 Break Address Register A (BARA) ...................................................................... 799

20.2.3 Break ASID Register A (BASRA)........................................................................ 800

20.2.4 Break Address Mask Register A (BAMRA)......................................................... 800

20.2.5 Break Bus Cycle Register A (BBRA)................................................................... 801

20.2.6 Break Address Register B (BARB) ...................................................................... 803

20.2.7 Break ASID Register B (BASRB) ........................................................................ 803

20.2.8 Break Address Mask Register B (BAMRB) ......................................................... 803

20.2.9 Break Data Register B (BDRB) ............................................................................ 803

20.2.10 Break Data Mask Register B (BDMRB)............................................................... 804

20.2.11 Break Bus Cycle Register B (BBRB) ................................................................... 805

20.2.12 Break Control Register (BRCR) ........................................................................... 805

20.3 Operation ........................................................................................................................... 808

20.3.1 Explanation of Terms Relating to Accesses.......................................................... 808

20.3.2 Explanation of Terms Relating to Instruction Intervals ........................................ 808

20.3.3 User Break Operation Sequence ...........................................................................809

20.3.4 Instruction Access Cycle Break ............................................................................ 810

20.3.5 Operand Access Cycle Break................................................................................ 811

20.3.6 Condition Match Flag Setting ............................................................................... 812

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20.3.7 Program Counter (PC) Value Saved ..................................................................... 812

20.3.8 Contiguous A and B Settings for Sequential Conditions ...................................... 813

20.3.9 Usage Notes .......................................................................................................... 814

20.4 User Break Debug Support Function................................................................................. 816

20.5 Examples of Use ................................................................................................................ 818

20.6 User Break Controller Stop Function................................................................................. 820

20.6.1 Transition to User Break Controller Stopped State............................................... 820

20.6.2 Cancelling the User Break Controller Stopped State............................................ 820

20.6.3 Examples of Stopping and Restarting the User Break Controller......................... 821

Section 21 High-performance User Debug Interface (H-UDI) ........................823

21.1 Overview............................................................................................................................ 823

21.1.1 Features................................................................................................................. 823

21.1.2 Block Diagram...................................................................................................... 823

21.1.3 Pin Configuration.................................................................................................. 825

21.1.4 Register Configuration.......................................................................................... 826

21.2 Register Descriptions......................................................................................................... 827

21.2.1 Instruction Register (SDIR) .................................................................................. 827

21.2.2 Data Register (SDDR) .......................................................................................... 828

21.2.3 Bypass Register (SDBPR) .................................................................................... 828

21.2.4 Interrupt Factor Register (SDINT)........................................................................ 829

21.2.5 Boundary Scan Register (SDBSR) ....................................................................... 829

21.3 Operation ........................................................................................................................... 843

21.3.1 TAP Control ......................................................................................................... 843

21.3.2 H-UDI Reset ......................................................................................................... 844

21.3.3 H-UDI Interrupt .................................................................................................... 844

21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) ............................. 845

21.4 Usage Notes ....................................................................................................................... 845

Section 22 PCI Controller (PCIC)..................................................................... 847

22.1 Overview............................................................................................................................ 847

22.1.1 Features................................................................................................................. 847

22.1.2 Block Diagram...................................................................................................... 848

22.1.3 Pin Configuration.................................................................................................. 849

22.1.4 Register Configuration.......................................................................................... 850

22.2 PCIC Register Descriptions ............................................................................................... 856

22.2.1 PCI Configuration Register 0 (PCICONF0) ......................................................... 856

22.2.2 PCI Configuration Register 1 (PCICONF1) ......................................................... 857

22.2.3 PCI Configuration Register 2 (PCICONF2) ......................................................... 863

22.2.4 PCI Configuration Register 3 (PCICONF3) ......................................................... 865

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22.2.5 PCI Configuration Register 4 (PCICONF4) ......................................................... 867

22.2.6 PCI Configuration Register 5 (PCICONF5) ......................................................... 869

22.2.7 PCI Configuration Register 6 (PCICONF6) ......................................................... 871

22.2.8 PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10

(PCICONF10)....................................................................................................... 873

22.2.9 PCI Configuration Register 11 (PCICONF11) ..................................................... 874

22.2.10 PCI Configuration Register 12 (PCICONF12) ..................................................... 875

22.2.11 PCI Configuration Register 13 (PCICONF13) ..................................................... 875

22.2.12 PCI Configuration Register 14 (PCICONF14) ..................................................... 876

22.2.13 PCI Configuration Register 15 (PCICONF15) ..................................................... 877

22.2.14 PCI Configuration Register 16 (PCICONF16) ..................................................... 879

22.2.15 PCI Configuration Register 17 (PCICONF17) ..................................................... 881

22.2.16 Reserved Area....................................................................................................... 883

22.2.17 PCI Control Register (PCICR).............................................................................. 884

22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0])................................................... 888

22.2.19 PCI Local Address Register [1:0] (PCILAR [1:0])............................................... 890

22.2.20 PCI Interrupt Register (PCIINT)........................................................................... 892

22.2.21 PCI Interrupt Mask Register (PCIINTM) ............................................................. 895

22.2.22 PCI Address Data Register at Error (PCIALR) ....................................................897

22.2.23 PCI Command Data Register at Error (PCICLR)................................................. 898

22.2.24 PCI Arbiter Interrupt Register (PCIAINT) ........................................................... 900

22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM).............................................. 902

22.2.26 PCI Error Bus Master Data Register (PCIBMLR)................................................ 903

22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT) ...................................... 904

22.2.28 PCI DMA Transfer PCI Address Register [3:0] (PCIDPA [3:0])......................... 905

22.2.29 PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0]) ...... 907

22.2.30 PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0]) ................................ 908

22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0])............................................... 910

22.2.32 PIO Address Register (PCIPAR).......................................................................... 913

22.2.33 Memory Space Base Register (PCIMBR)............................................................. 915

22.2.34 I/O Space Base Register (PCIIOBR) .................................................................... 917

22.2.35 PCI Power Management Interrupt Register (PCIPINT) .......................................918

22.2.36 PCI Power Management Interrupt Mask Register (PCIPINTM).......................... 919

22.2.37 PCI Clock Control Register (PCICLKR).............................................................. 920

22.2.38 PCIC-BSC Registers............................................................................................. 921

22.2.39 Port Control Register (PCIPCTR)......................................................................... 923

22.2.40 Port Data Register (PCIPDTR)............................................................................. 926

22.2.41 PIO Data Register (PCIPDR)................................................................................ 927

22.3 Description of Operation.................................................................................................... 928

22.3.1 Operating Modes................................................................................................... 928

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22.3.2 PCI Commands ..................................................................................................... 929

22.3.3 PCIC Initialization ................................................................................................ 930

22.3.4 Local Register Access........................................................................................... 931

22.3.5 Host Functions ...................................................................................................... 931

22.3.6 PCI Bus Arbitration in Non-host Mode ................................................................ 934

22.3.7 PIO Transfers........................................................................................................ 934

22.3.8 Target Transfers.................................................................................................... 937

22.3.9 DMA Transfers ..................................................................................................... 940

22.3.10 Transfer Contention within PCIC......................................................................... 946

22.3.11 PCI Bus Basic Interface........................................................................................ 947

22.4 Endians .............................................................................................................................. 959

22.4.1 Internal Bus (Peripheral Bus) Interface for Peripheral Modules........................... 959

22.4.2 Endian Control for Local Bus............................................................................... 961

22.4.3 Endian Control in DMA Transfers ....................................................................... 961

22.4.4 Endian Control in Target Transfers (Memory Read/Memory Write) ................... 963

22.4.5 Endian Control in Target Transfers (I/O Read/I/O Write).................................... 966

22.4.6 Endian Control in Target Transfers

(Configuration Read/Configuration Write)........................................................... 966

22.5 Resetting ............................................................................................................................ 968

22.6 Interrupts............................................................................................................................ 969

22.6.1 Interrupts from PCIC to CPU ............................................................................... 969

22.6.2 Interrupts from External PCI Devices................................................................... 970

22.6.3 INTA..................................................................................................................... 971

22.7 Error Detection .................................................................................................................. 971

22.8 PCIC Clock........................................................................................................................ 971

22.9 Power Management ........................................................................................................... 972

22.9.1 Power Management Overview.............................................................................. 972

22.9.2 Stopping the Clock ............................................................................................... 973

22.9.3 Compatibility with Standby and Sleep ................................................................. 976

22.10 Port Functions .................................................................................................................... 976

22.11 Version Management ......................................................................................................... 977

22.12 Usage Notes ....................................................................................................................... 977

22.12.1 Notes on Arbiter Interrupt Usage (SH7751 Only) ................................................ 977

22.12.2 Notes on I/O Read and I/O Write Commands (SH7751 Only)............................. 980

22.12.3 Notes on Configuration-Read and Configuration-Write Commands

(SH7751 Only)...................................................................................................... 980

22.12.4 Notes on Target Read/Write Cycle Timing (SH7751 Only)................................. 980

22.12.5 Notes on Parity Error Detection during Master Access........................................ 980

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Section 23 Electrical Characteristics .................................................................983

23.1 Absolute Maximum Ratings .............................................................................................. 983

23.2 DC Characteristics ............................................................................................................. 984

23.3 AC Characteristics ............................................................................................................. 996

23.3.1 Clock and Control Signal Timing ......................................................................... 998

23.3.2 Control Signal Timing ........................................................................................ 1012

23.3.3 Bus Timing ......................................................................................................... 1016

23.3.4 Peripheral Module Signal Timing....................................................................... 1067

23.3.5 AC Characteristic Test Conditions ..................................................................... 1081

23.3.6 Change in Delay Time Based on Load Capacitance ........................................... 1082

Appendix A Address List ................................................................................1083

Appendix B Package Dimensions....................................................................1091

Appendix C Mode Pin Settings .......................................................................1095

Appendix D Pin Functions...............................................................................1099

D.1 Pin States.......................................................................................................................... 1099

D.2 Handling of Unused Pins ................................................................................................. 1104

D.3 Note on Pin Processing .................................................................................................... 1105

Appendix E Synchronous DRAM Address Multiplexing Tables...................1107

Appendix F Instruction Prefetching and Its Side Effects.................................1119

Appendix G Power-On and Power-Off Procedures.........................................1121

G.1 Power-On Stipulations ..................................................................................................... 1121

G.2 Power-Off Stipulations .................................................................................................... 1121

G.3 Common Stipulations for Power-On and Power-Off....................................................... 1124

Appendix H Product Lineup ............................................................................1125

Appendix I Version Registers..........................................................................1127

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Renesas SH7751 Group, SH7751R Group User Manual

Specifications and Main Features

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User Manual