Renesas SH7709S User Manual

SH7709S

The revision list can be viewed directly by clicking the title page.

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

Group

Hardware Manual

Renesas 32-Bit RISC Microcomputer

SuperH RISC engine Family/SH7700 Series

Rev.5.00

2003.9.18

Renesas 32-Bit RISC Microcomputer

SuperH RISC engine Family/SH7700 Series

SH7709S Group

Hardware Manual

REJ09B0081-0500O

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due con sideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual prope rty rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology C orp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of pu bl i cation of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to inf ormation published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, in cludin g product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before maki n g a final decision on the applicability of the in f ormation and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Rev. 5.00, 09/03, page iv of xliv

General Precautions on Handling of Product

1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.

3. Processing before Initialization Note: When power is f i rst supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefin ed or reserved addresses i s prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.

Rev. 5.00, 09/03, page v of xliv

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configurati on of Thi s Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note

When designing an application system that includes this LSI, take notes into a ccount. Each se c tion includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual.

11.Index

Rev. 5.00, 09/03, page vi of xliv

Preface

This LSI is a microprocessor with the 32-bit SH-3 CPU as its core and peripheral functions necessary for configuring a user system.

This LSI is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timer, three serial communication interfaces, realtime clock (RTC), use break controller (UBC), bus state controller (BSC) and I/O ports.

This LSI can be used as a microcomputer for devices that require both high speed and low power consumption.

Target Readers: This manual is designed for use by people who design application systems using the SH7709S. To use this manual, basic knowledge of electric circuits, logic circuits and micro computers is required.

Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7709S. The SH3, SH-3E, SH3-DSP Programming Manual contains detailed information of executable instructions. Please read the Programming Manual together with this manual.

How to Use the Book:

• To understand general functions  Read the manual from the beginning.

The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order.

• To understanding CPU function s  Refer to the separate SH3, SH-3E, SH3-DSP Programming Manual.

Explanatory Note: Bit sequence: upper bit at left, and lower bit at right

List of Related Documents: The latest documents are available on our Web site. Please make

sure that you have the latest version. (http://www.renesas.com/eng/)

• User manuals for SH7709S

Name of Document Document No.

SH7709S Group Hardware Manual This manual SH3, SH-3E, SH3-DSP Programming Manual ADE-602-156

Rev. 5.00, 09/03, page vii of xliv

• User manuals for development tools

Name of Document Document No.

C/C++ Compiler, Assembler, Opti miz ing Lin kag e Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual ADE-702-186 Embedded Workshop User’s Manual ADE-702-201

Rev. 5.00, 09/03, page viii of xliv

List of Items Revised or Added for This Version

Section Page Description

1.2 Block Diagram

Figure 1.1 Block Diagram

2.5.1 Processor States

5.4 Memory-Mapped

Cache

5.4.1 Address Array

113

ASERAM deleted from figure

UDI

INTC

CPG/WDT

ASERAM deleted from legend Description amended In the power-on reset state, the internal states of the CPU and the

on-chip supporting module registers are initialized. In the manual reset state, the internal states of the CPU and registers of on-chip supporting modules other than the bus state controller (BSC) are initialized. the register configurations in the relevant sections for further details.

Description amended This operation is used to invalidate the address specification for a

cache. Write back will take place when the U bit of the entry that received a hit is 1. Note that, when a 0 is written to the V bit, a 0 should always be written to the U bit of the same entry, too.

BRIDGE

I bus 2

External bus

interface

Refer to

Rev. 5.0, 09/03, page ix of xliv

Section Page Description

5.4.3 Examples of Usage

115, 116

(1) Invalidating a Specific Entry Description amended

A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry’s U and V bits. The A bit is cleared to 0, and an address is specified for the entry address and the way. If the U bit of the way of the entry in question was set to 1, the entry is written back and the V and U bits specified by the write data are written to.

In the following example, the write data is specified in R0 and the address is specified in R1.

; R0 = H'0000 0000 LRU = H'000, U = 0, V = 0 ; R1 = H'F000 ;

MOV.L R0, @R1

To invalidate all entries and ways, write 0 to the following addresses.

Addresses

This involves a total of 1, 024 writes. The above operation should be performed using a non-cacheable area.

(2) Invalidating a Specific Address Newly added (3) Reading Data from a Specific Entry Description amended

; R0 = H'F100 004C; Data array access, Entry = H'04, ; Way = 0, Longword address = 3 ;

MOV.L R0, @R1 ; Longword 3 is read.

6.2.6 Interrupt Exception Handling and Priority

127

IPR (bit numbers) for SCI amended (Before)IPRB(3-0) → (After)IPRB

Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)

6.3.6 Interrupt Request Register 0 (IRR0)

138

Description amended When clearing an IRQ5R–IRQ0R bit to 0, read the bit while bit set

to 1, and then write 0. In this case, 0 should be written only to the bits to be cleared and 1 to the other bits. The co nten ts of the bits to which 1 is written do not change.

8.2.1 Standby Control Register (STBCR)

184

Description added Bit 1—Module Standby 1 (MSTP1) Before switching the RTC to module standby, access at least one

among the registers RTC, SCI, and TMU.

Rev. 5.0, 09/03, page x of xliv

1080, Way = 1, Entry = H'08, A = 0

F000 0000 F000 0010 F000 0020

F000 3FF0

(7-4)

Section Page Description

8.3.3 Precautions

187

Newley added when Using the Sleep Mode

8.5.1 Transition to Module Standby Function

191

Note *3 added to bit table

3. Before putting the RTC into module standby status, first

Note:

access one or more of the RTC, SCI, and TMU registers. The RTC may then be put into module standby status.

9.3 Clock Operating Modes

Table 9.4 Available Combinations of Clock

210

2. under cautions amended

The peripheral clock frequency should not be set higher than the

frequency of the CKIO pin, higher than Mode and FRQCR

Values

9.5.1 Changing the Multiplication Rate

213

Description added

5.Supply of the clock that has been set begins at WDT count overflow, and the processor begins operating again. The WDT stops after it overflows.

When the following three conditions are all met, FRQCR should not be changed while a DMAC transfer is in progress.

• Bits IFC2 to IFC0 are changed.

• STC2 to STC0 are not changed.

• The clock ratio of Iφ (on-chip clock) to Bφ (bus clock) after the

change is other than 1:1.

9.8.2 Changing the Frequency

218, 219

Description added

5.The counter stops at a value of H'00 or H'01. The stop value

depends on the clock ratio. When the following three conditions are all met, FRQCR should

not be changed while a DMAC transfer is in progress.

• Bits IFC2 to IFC0 are changed.

• STC2 to STC0 are not changed.

• The clock ratio of Iφ (on-chip clock) to Bφ (bus clock) after the

change is other than 1:1.

10.1.1 Features

10.2.5 Individual Memory Control Register (MCR)

223 246

Refresh function description deleted Description added Bit 7—Synchronous DRAM Bank Active (RASD): Specifies

whether synchronous DRAM is used in bank active mode or autoprecharge mode. Set auto-precharge mode when areas 2 and 3 are both designated as synchronous DRAM space. The bank active mode should not be used unless the bus width for all areas is 32 bits.

33.34 MHz.

Rev. 5.0, 09/03, page xi of xliv

Section Page Description

10.2.13 MCS0 Control Register (MCSCR0)

258

Description added Bit 6—CS2/CS0 Select (CS2/0)

Only 0 should be used for the CS2/0 bit in MCSCR0. Either 0 or 1 may be used for MCSCR1 to MCSCR7.

10.3.4 Synchronous DRAM Interface

290

Bank Active description added … .In bank active mode, too, all banks become inactive after a

refresh cycle or after the bus is released as the result of bus arbitration. The bank active mode should not be used unless the bus width for all areas is 32 bits.

10.3.6 PCMCIA Interface

Figure 10.32 Basic Timing for PCMCIA

310

Figure amended D15 to D0

Write)

(

Memory Card Interface

10.3.7 Waits between

320

Figure amended

Access Cycles Figure 10.40 Waits

between Access Cycles

CKIO

25 to A0

T2Twait T

10.3.10 MCS[0] to MCS[7] Pin Control

11.6 Usage Notes

13.4.3 Precautions when Using RTC Module Standby

323

387

426

Description amended This enables 32-, 64-, 128-, or 256-Mbit memory to be connected

to area 0 or area 2.

However, only CS2/0 = 0 (area 0) should be used for MCSCR0. Table 10.15 shows MCSCR0 – MCSCR7 settings and MCS[0]–MCS[7] assertion conditions.

Description added

13. DMAC transfers should not be perfor me d in the sleep mode

under conditions other than when the clock ratio of Iφ (on- chip clock) to Bφ (bus clock) is 1:1.

14. When the following three conditions are all met, the

frequency control register (FRQCR) should not be changed while a DMAC transfer is in progress.

• Bits IFC2 to IFC0 are changed.

• STC2 to STC0 in FRQCR are not changed.

• The clock ratio of Iφ (on-chip clock) to Bφ (bus clock) after

the change is other than 1:1.

Newly added

Rev. 5.0, 09/03, page xii of xliv

Section Page Description

16.4 SCIF Interrupts

550

Description amended When the TDFE flag in the serial status register (SCSSR) is set to

1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed when this interrupt is generated. written to the transmit data register (SCFTDR) by the DMAC, 1 is read from the TDFE flag, after which 0 is written to it to clear it.

When the RDF flag in SCSSR is set to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer performed when the RDF flag in SCSSR is set to 1. When receive data less than the receive trigger number is read from the receive data register (SCFRDR) by the DMAC, 1 is read from the RDF flag, after which 0 is written to it to clear it.

16.5 Usage Notes

551

Description amended

1. SCFTDR Writing and TDFE Flag: However, if the number of data bytes written to SCFTDR is equal to or less than the transmit trigger number, set to 1 again even after having been cleared to 0. TDFE clearing should therefore be carried out after data exceeding the specified transmit trigger number has been written to SCFTDR.

2. SCFRDR Reading and RDF Flag: However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will be set to 1 again even after having been cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read.

19.13.2 SC Port Data

610

Title Amended

When data exceeding the transmit trigger number is

the TDFE flag will be

Rev. 5.0, 09/03, page xiii of xliv

Section Page Description

20.3 Bus Master Interface

Figure 20.2 A/D Data Register Access Operation (Reading H'AA40)

622

Figure amended

Upper byte read

CPU

receives

data H'AA

Bus

interface

Module internal data bus

TEMP

[H'40]

23.1 Absolute Maximum Ratings

Table 23.1 Absolute Maximum Ratings

23.2 DC Characteristics

Table 23.2 DC Characteristics

657

659, 662

ADDRn L

[H'40]

Module internal data bus

TEMP

[H'40]

ADDRn L

[H'40]

n = A to D

Lower byte read

CPU

receives

data H'40

Bus

interface

ADDRn H

[H'AA]

ADDRn H

[H'AA]

Caution added

2.Until voltage is applied to all power supplies, a low level is input at the RESETP pin, and CKIO has operated for a maximum of 4 clock cycles, internal circuits remain unsettled, and so pin states are also undefin ed. The system design must ensure that these undefined states do not cause erroneous system operation. Note that the RESETP pin cannot receive a low level signal while a low level signal is being input to the CA pin.

Test conditions for in sleep mode amended

Item Symbol Min Typ Max Unit Test Conditions

Sleep mode

Icc — 15 30

IccQ — 10 20

: When there is no

other external bus cycle other than the refresh cycle.

Vcc = 1.9 V VccQ = 3.3 V

Bφ = 33MHz

Note * added * If the IRL and IRLS interrupts are used, the minimum is 1.9 V.

Rev. 5.0, 09/03, page xiv of xliv

Section Page Description

23.3.6 Synchronous DRAM Timing

690

Tnop cycle deleted from figure

Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4

Figure 23.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 2)

CKIO

25 to A16

12 or A10

15 to A0

CSn

RD/WR

RAS

CAS

DQMxx

D31 to D0

CSD3

RWD

RASD2

CASD2

DQMD

Row address

Read command

Column address

RDS2

BSD

RDH2

CASD2

RDS2

CSD3

RWD

DQMD

RDH2

BSD

CKE

DACKn

(High)

DAKD1

Rev. 5.0, 09/03, page xv of xliv

Section Page Description

A.2 Pin Specifications Table A.2 Pin

Specifications

723

Function information amend ed for VCC–RTC, VCC–PLL1, VCC– PLL2, and V

Pin Pin No.

(FP-208C,

FP-208E)

–

3 E2 Power

RTC

145

VCC–

150

PLL1

–

PLL2 V

29, 81,

134, 154, 175

Pin No.

(BP-

240A)

F16, E17

L3, L4, U11, T11, J17, J16, E18, C19, C12, D12

I/O Function

RTC oscillator power

supply

supply (2.0/1.9/1.8/1.7 V)

Power supply

PLL power supply (2.0/1.9/1.8/1.7 V)

Internal power supply (2.0/1.9/1.8/1.7 V)

A.3 Treatment of Unused Pins

A.4 Pin States in Access to Each Address Space

Table A.3 Pin States (Ordinary Memory/Little Endian)

Table A.4 Pin States (Ordinary Memory/Big Endian)

Table A.5 Pin States (Burst ROM/Little Endian)

Table A.6 Pin States (Burst ROM/Big Endian)

Table A.9 Pin States (PCMCIA/Little Endian)

Table A.10 Pin States (PCMCIA/Big Endian)

724

726 to 738

"When RTC is not used" and "When PLL2 is not used" amended (Before) (1.9/1.8V) →(After) (

2.0/1.9/1.8/1.7V) Note 2 amended Note: 2.Unused data pins should be switched to the port

function, or

pulled up.

Rev. 5.0, 09/03, page xvi of xliv

Section 1 Overview and Pin Functions

1.1 SH7709S Features .............................................................................................................1

1.2 Block Diagram .................................................................................................................. 6

1.3 Pin Description.................................................................................................................. 7

1.3.1 Pin Assignment .................................................................................................... 7

1.3.2 Pin Function ......................................................................................................... 9

Section 2 CPU

2.1 Register Configuration ...................................................................................................... 19

2.1.1 Privileged Mode and Banks.................................................................................. 19

2.1.2 General Registers ................................................................................................. 22

2.1.3 System Registers.................................................................................................. 23

2.1.4 Control Registers.................................................................................................. 23

2.2 Data Formats ..................................................................................................................... 25

2.2.1 Data Format in Registers...................................................................................... 25

2.2.2 Data Format in Memory....................................................................................... 25

2.3 Instruction Features ........................................................................................................... 26

2.3.1 Execution Environment........................................................................................ 26

2.3.2 Addressing Modes................................................................................................ 28

2.3.3 Instruction Formats............................................................................................... 32

2.4 Instruction Set.................................................................................................................... 35

2.4.1 Instruction Set Classified by Function.................................................................. 35

2.4.2 Instruction Code Map........................................................................................... 50

2.5 P rocessor States and Processor Modes.............................................................................. 53

2.5.1 Processor States.................................................................................................... 53

2.5.2 Processor Modes .................................................................................................. 54

....................................................................................................................... 19

.......................................................................... 1

Section 3 Memory Management Unit (MMU)

3.1 Overview ........................................................................................................................... 55

3.1.1 Features................................................................................................................ 55

3.1.2 Role of MMU....................................................................................................... 55

3.1.3 SH7709S MMU.................................................................................................... 58

3.1.4 Register Configuration......................................................................................... 61

3.2 Register Description.......................................................................................................... 61

3.3 TLB Functions................................................................................................................... 63

3.3.1 Configuration of the TLB..................................................................................... 63

3.3.2 TLB Indexing....................................................................................................... 65

3.3.3 TLB Address Comparison.................................................................................... 66

3.3.4 Page Management Information............................................................................ 68

............................................................ 55

Rev. 5.00, 09/03, page xvii of xliv

3.4 MMU Functions................................................................................................................69

3.4.1 MMU Hardware Management ............................................................................. 69

3.4.2 MMU Software Management............................................................................... 69

3.4.3 MMU Instruction (LDTLB)................................................................................. 70

3.4.4 Avoiding Synonym Problems............................................................................... 72

3.5 MMU Exceptions .............................................................................................................. 74

3.5.1 TLB Miss Exception ............................................................................................ 74

3.5.2 TLB Protection Violation Exception.................................................................... 75

3.5.3 TLB Invalid Exception......................................................................................... 76

3.5.4 Initial Page Write Exception ................................................................................ 77

3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow

for Address Error)................................................................................................ 79

3.6 Configuration of Memory-Mapped TLB........................................................................... 80

3.6.1 Address Array ...................................................................................................... 80

3.6.2 Data Array............................................................................................................ 81

3.6.3 Usage Examples................................................................................................... 83

3.7 Usage Note ........................................................................................................................ 83

Section 4 Exception Handling

4.1 Overview ........................................................................................................................... 85

4.1.1 Features................................................................................................................ 85

4.1.2 Register Configuration......................................................................................... 85

4.2 Exception Handling Function............................................................................................ 85

4.2.1 Exception Handling Flow..................................................................................... 85

4.2.2 Exception Vector Addresses................................................................................. 86

4.2.3 Acceptance of Exceptions.................................................................................... 88

4.2.4 Exception Codes................................................................................................... 90

4.2.5 Exception Request Masks .................................................................................... 91

4.2.6 Returning from Exception Handling .................................................................... 91

4.3 Register Descriptions......................................................................................................... 92

4.4 Exception Handling Operation .......................................................................................... 93

4.4.1 Reset..................................................................................................................... 93

4.4.2 Interrupts.............................................................................................................. 93

4.4.3 General Exceptions............................................................................................... 94

4.5 Individual Exception Operations....................................................................................... 94

4.5.1 Resets ................................................................................................................... 94

4.5.2 General Exceptions............................................................................................... 95

4.5.3 Interrupts.............................................................................................................. 99

4.6 Cautions............................................................................................................................. 100

Section 5 Cache

5.1 Overview ........................................................................................................................... 103

5.1.1 Features................................................................................................................ 103

.................................................................................................................... 103

.......................................................................................... 85

Rev. 5.00, 09/03, page xviii of xliv

5.1.2 Cache Structure.................................................................................................... 103

5.1.3 Register Configuration......................................................................................... 105

5.2 Register Description.......................................................................................................... 105

5.2.1 Cache Control Register (CCR)............................................................................. 105

5.2.2 Cache Control Register 2 (CCR2)........................................................................ 106

5.3 Cache Operation................................................................................................................ 109

5.3.1 Searching the Cache............................................................................................. 109

5.3.2 Read Access......................................................................................................... 111

5.3.3 Prefetch Operation................................................................................................ 111

5.3.4 Write Access ........................................................................................................ 111

5.3.5 Write-Back Buffer................................................................................................ 111

5.3.6 Coherency of Cache and External Memory.......................................................... 112

5.4 Me mory-Mapped Cache.................................................................................................... 112

5.4.1 Address Array ...................................................................................................... 112

5.4.2 Data Array............................................................................................................ 113

5.4.3 Examples of Usage............................................................................................... 115

Section 6 Interrupt Controller (INTC)

6.1 Overview ........................................................................................................................... 117

6.1.1 Features................................................................................................................ 117

6.1.2 Block Diagram ..................................................................................................... 118

6.1.3 Pin Configuration................................................................................................. 119

6.1.4 Register Configuration......................................................................................... 120

6.2 Interrupt Sources ............................................................................................................... 121

6.2.1 NMI Interrupt....................................................................................................... 121

6.2.2 IRQ Interrupts ...................................................................................................... 121

6.2.3 IRL Interrupts....................................................................................................... 122

6.2.4 PINT Interrupts .................................................................................................... 124

6.2.5 On-Chip Peripheral Module Interrupts................................................................. 124

6.2.6 Interrupt Exception Handling and Priority........................................................... 125

6.3 INTC Registers.................................................................................................................. 131

6.3.1 Interrupt Priority Registers A to E (IPRA–IPRE) ................................................ 131

6.3.2 Interrupt Control Register 0 (ICR0)..................................................................... 132

6.3.3 Interrupt Control Register 1 (ICR1)..................................................................... 133

6.3.4 Interrupt Control Register 2 (ICR2)..................................................................... 136

6.3.5 PINT Interrupt Enable Register (PINTER).......................................................... 137

6.3.6 Interrupt Request Register 0 (IRR0)..................................................................... 138

6.3.7 Interrupt Request Register 1 (IRR1)..................................................................... 140

6.3.8 Interrupt Request Register 2 (IRR2)..................................................................... 141

6.4 INTC Operation................................................................................................................. 143

6.4.1 Interrupt Sequence................................................................................................ 143

6.4.2 Multiple Interrupts................................................................................................ 145

6.5 Interrupt Response Time ................................................................................................... 145

........................................................................... 117

Rev. 5.00, 09/03, page xix of xliv

Section 7 User Break Controller

7.1 Overview ........................................................................................................................... 149

7.1.1 Features................................................................................................................ 149

7.1.2 Block Diagram ..................................................................................................... 150

7.1.3 Register Configuration......................................................................................... 151

7.2 Register Descriptions......................................................................................................... 152

7.2.1 Break Address Register A (BARA )...................................................................... 152

7.2.2 Break Address Mask Register A (BAMRA)........................................................ 153

7.2.3 Break Bus Cycle Register A (BBRA).................................................................. 154

7.2.4 Break Address Register B (BARB)...................................................................... 156

7.2.5 Break Address Mask Register B (BAMRB)......................................................... 157

7.2.6 Break Data Register B (BDRB) ........................................................................... 158

7.2.7 Break Data Mask Register B (BDMRB).............................................................. 159

7.2.8 Break Bus Cycle Register B (BBRB)................................................................... 160

7.2.9 Break Control Register (BRCR)........................................................................... 162

7.2.10 Execution Times Break Register (BETR)............................................................ 166

7.2.11 Branch Source Register (BRSR) .......................................................................... 167

7.2.12 Branch Destination Register (BRDR) .................................................................. 168

7.2.13 Break A S ID Register A (BASRA )....................................................................... 169

7.2.14 Break A S ID Register B (BASR B) ....................................................................... 169

7.3 Operation Description ....................................................................................................... 170

7.3.1 Flow of the User Break Operation........................................................................ 170

7.3.2 Break on Instruction Fetch Cycle......................................................................... 170

7.3.3 Break by Data Access Cycle ................................................................................ 171

7.3.4 Sequential Break .................................................................................................. 172

7.3.5 Value of Saved Program Counter......................................................................... 172

7.3.6 PC Trace............................................................................................................... 173

7.3.7 Usage Examples................................................................................................... 174

7.3.8 Notes .................................................................................................................... 179

...................................................................................... 149

Section 8 Power-Down Modes

8.1 Overview ........................................................................................................................... 181

8.1.1 Power-Down Modes............................................................................................. 181

8.1.2 Pin Configuration................................................................................................. 183

8.1.3 Register Configuration......................................................................................... 183

8.2 Register Descriptions......................................................................................................... 183

8.2.1 Standby Control Register (STBCR)..................................................................... 183

8.2.2 Standby Control Register 2 (STBCR2)................................................................ 185

8.3 Sleep Mode........................................................................................................................ 187

8.3.1 Transition to Sleep Mode..................................................................................... 187

8.3.2 Canceling Sleep Mode.......................................................................................... 187

8.3.3 Precautions when Using the Sleep Mode............................................................. 187

8.4 Standb y Mode.................................................................................................................... 188

Rev. 5.00, 09/03, page xx of xliv

......................................................................................... 181

8.4.1 Transition to Standby Mode................................................................................. 188

8.4.2 Canceling Standby Mode ..................................................................................... 189

8.4.3 Clock Pause Function........................................................................................... 190

8.5 Module Standby Function ................................................................................................. 191

8.5.1 Transition to Module Standby Function............................................................... 191

8.5.2 Clearing Module Standby Function...................................................................... 191

8.6 Timing of STATUS Pin Changes...................................................................................... 192

8.6.1 Timing for Resets ................................................................................................. 192

8.6.2 Timing for Canceling Standby ............................................................................. 194

8.6.3 Timing for Canceling Sleep Mode....................................................................... 196

8.7 Hardware Standby Mode................................................................................................... 199

8.7.1 Transition to Hardware Standby Mode ................................................................ 199

8.7.2 Canceling Hardware Standby Mode..................................................................... 199

8.7.3 Hardware Standby Mode Timing......................................................................... 200

Section 9 On-Chip Oscillation Circuits

9.1 Overview ........................................................................................................................... 203

9.1.1 Features................................................................................................................ 203

9.2 Overview of CPG .............................................................................................................. 204

9.2.1 CPG Block Diagram............................................................................................. 204

9.2.2 CPG Pin Configuration ........................................................................................ 206

9.2.3 CPG Register Configuration................................................................................. 206

9.3 Clock Operating Modes..................................................................................................... 207

9.4 Register Descriptions......................................................................................................... 211

9.4.1 Frequency Control Register (FRQCR)................................................................. 211

9.5 Changing the Frequency.................................................................................................... 213

9.5.1 Changing the Multiplication Rate ........................................................................ 213

9.5.2 Changing the Division Ratio................................................................................ 213

9.6 Overview of WDT............................................................................................................. 214

9.6.1 Block Diagram of WDT....................................................................................... 214

9.6.2 Register Configuration......................................................................................... 214

9.7 W DT Registers.................................................................................................................. 215

9.7.1 Watchdog Timer Counter (WTCNT)................................................................... 215

9.7.2 Watchdog Timer Control/Status Register (WTCSR) ........................................... 215

9.7.3 Notes on Register Access..................................................................................... 217

9.8 Using the WDT ................................................................................................................. 218

9.8.1 Canceling Standby................................................................................................ 218

9.8.2 Changing the Frequency....................................................................................... 218

9.8.3 Using Watchdog Timer Mode.............................................................................. 219

9.8.4 Using Interval Timer Mode.................................................................................. 219

9.9 Notes on Board Design...................................................................................................... 220

......................................................................... 203

Rev. 5.00, 09/03, page xxi of xliv

Section 10 Bus State Controller (BSC)

10.1 Overview ........................................................................................................................... 223

10.1.1 Features................................................................................................................ 223

10.1.2 Block Diagram..................................................................................................... 225

10.1.3 Pin Conf iguration................................................................................................. 226

10.1.4 Register Configuration......................................................................................... 228

10.1.5 Area Overview ..................................................................................................... 229

10.1.6 PCMCIA Support................................................................................................. 232

10.2 BSC Registers.................................................................................................................... 235

10.2.1 Bus Control Register 1 (BCR1)............................................................................ 235

10.2.2 Bus Control Register 2 (BCR2)............................................................................ 239

10.2.3 Wait State Control Register 1 (WCR1)................................................................ 240

10.2.4 Wait State Control Register 2 (WCR2)................................................................ 241

10.2.5 Individual Memory Control Register (MCR)....................................................... 245

10.2.6 PCMCIA Control Register (PCR)........................................................................ 248

10.2.7 Synchronous DRAM Mode Register (SDMR)..................................................... 252

10.2.8 Refresh Timer Control/Status Register (RTCSR) ................................................ 253

10.2.9 Refresh Timer Counter (RTCNT)........................................................................ 255

10.2.10 Refresh Time Constant Register (RTCOR).......................................................... 256

10.2.11 Refresh Count Register (RFCR)........................................................................... 256

10.2.12 Cautions on Accessing Refresh Control Related Registers.................................. 257

10.2.13 MCS0 Control Register (MCSCR0)..................................................................... 258

10.2.14 MCS1 Control Register (MCSCR1)..................................................................... 259

10.2.15 MCS2 Control Register (MCSCR2)..................................................................... 259

10.2.16 MCS3 Control Register (MCSCR3)..................................................................... 259

10.2.17 MCS4 Control Register (MCSCR4)..................................................................... 259

10.2.18 MCS5 Control Register (MCSCR5)..................................................................... 259

10.2.19 MCS6 Control Register (MCSCR6)..................................................................... 259

10.2.20 MCS7 Control Register (MCSCR7)..................................................................... 259

10.3 BSC Operation .................................................................................................................. 260

10.3.1 Endian/Access Size and Data Alignment............................................................. 260

10.3.2 Description of Areas............................................................................................. 265

10.3.3 Basic Interface...................................................................................................... 268

10.3.4 Synchronous DRAM Interface............................................................................. 276

10.3.5 Burst ROM Interface............................................................................................ 304

10.3.6 PCMCIA Interface ............................................................................................... 307

10.3.7 Waits betw een Access Cycles.............................................................................. 319

10.3.8 Bus Arbitration..................................................................................................... 320

10.3.9 Bus Pull-U p.......................................................................................................... 321

10.3.10 MCS[0] to MCS[7] Pin Control........................................................................... 323

......................................................................... 223

Section 11 Direct Memory Access Controller (DMAC)

11.1 Overview ........................................................................................................................... 327

Rev. 5.00, 09/03, page xxii of xliv

.......................................... 327

11.1.1 Features................................................................................................................ 327

11.1.2 Block Diagram..................................................................................................... 329

11.1.3 Pin Conf iguration................................................................................................. 330

11.1.4 Register Configuration......................................................................................... 331

11.2 Register Descriptions......................................................................................................... 333

11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)........................................... 333

11.2.2 DMA Destinat i on Address Registers 0–3 (DAR0–DAR3).................................. 334

11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 335

11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) ................................... 336

11.2.5 DMA Operation Register (DMAOR)................................................................... 343

11.3 Operation........................................................................................................................... 345

11.3.1 DMA Transfer Flow............................................................................................. 345

11.3.2 DMA Transfer Requests....................................................................................... 347

11.3.3 Channel Priority................................................................................................... 349

11.3.4 DMA Transfer Types ........................................................................................... 352

11.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing........................... 363

11.3.6 Source Address Reload Function......................................................................... 372

11.3.7 DMA Transfer Ending Conditions....................................................................... 374

11.4 Compare Match Timer (CMT).......................................................................................... 376

11.4.1 Overview.............................................................................................................. 376

11.4.2 Register Descriptions ........................................................................................... 377

11.4.3 Operation.............................................................................................................. 380

11.4.4 Compare Match.................................................................................................... 381

11.5 Examples of Use................................................................................................................ 383

11.5.1 Example of DMA Transfer between On-Chip IrDA and External Memory ........ 383

11.5.2 Example of DMA Transfer between A/D Converter and External Memory........ 384

11.5.3 Example of DMA Transfer between External Memory and SCIF Transmitter

(Indirect Address On)........................................................................................... 385

11.6 Usage Notes....................................................................................................................... 387

Section 12 Timer (TMU)

12.1 Overview ........................................................................................................................... 389

12.1.1 Features................................................................................................................ 389

12.1.2 Block Diagram..................................................................................................... 390

12.1.3 Pin Conf iguration................................................................................................. 391

12.1.4 Register Configuration......................................................................................... 391

12.2 TMU Registers .................................................................................................................. 392

12.2.1 Timer Output Control Register (TOCR) .............................................................. 392

12.2.2 Timer Start Register (TSTR)................................................................................ 392

12.2.3 Timer Control Registers (TCR)............................................................................ 393

12.2.4 Timer Constant Registers (TCOR) ....................................................................... 397

12.2.5 Timer Counters (TCNT)....................................................................................... 397

12.2.6 Input Capture Register (TCPR2).......................................................................... 399

................................................................................................... 389

Rev. 5.00, 09/03, page xxiii of xliv

12.3 TMU Operation................................................................................................................. 400

12.3.1 General Operation................................................................................................ 400

12.3.2 Input Capture Function......................................................................................... 403

12.4 Interrupts ........................................................................................................................... 404

12.4.1 Status Flag Setting Timing................................................................................... 404

12.4.2 Status Flag C learing Timing................................................................................. 405

12.4.3 Interrupt Sources and Priorities............................................................................ 405

12.5 Usage Notes....................................................................................................................... 406

12.5.1 Writing to Registers.............................................................................................. 406

12.5.2 Reading Registers................................................................................................. 406

Section 13 Realtime Clock (RTC)

13.1 Overview ........................................................................................................................... 407

13.1.1 Features................................................................................................................ 407

13.1.2 Block Diagram..................................................................................................... 408

13.1.3 Pin Conf iguration................................................................................................. 409

13.1.4 RTC Register Configuration................................................................................. 410

13.2 RTC Registers ................................................................................................................... 411

13.2.1 64-Hz Counter (R64CNT).................................................................................... 411

13.2.2 Second Counter (RSECCNT)............................................................................... 411

13.2.3 Minute Counter (RMINCNT) .............................................................................. 412

13.2.4 Hour Counter (RHRCNT).................................................................................... 412

13.2.5 Day of Week Counter (RWKCNT)...................................................................... 413

13.2.6 Date Counter (RDAYCNT).................................................................................. 414

13.2.7 Month Counter (RMONCNT).............................................................................. 414

13.2.8 Year Counter (RYRCNT) .................................................................................... 415

13.2.9 Second Alarm Register (RSECAR)...................................................................... 415

13.2.10 Minute Alarm Register (RMINAR) ..................................................................... 416

13.2.11 Hour Alarm Register (RHRAR)........................................................................... 416

13.2.12 Day of Week Alarm Register (RWKAR)............................................................. 417

13.2.13 Date Alarm Register (RDAYAR) ........................................................................ 418

13.2.14 Month Alarm Register (RMONAR)..................................................................... 418

13.2.15 RTC Control Register 1 (RCR1).......................................................................... 419

13.2.16 RTC Control Register 2 (RCR2) .......................................................................... 420

13.3 RTC Operation .................................................................................................................. 422

13.3.1 Initial Settings of Registers after Power-On......................................................... 422

13.3.2 Setting the Time................................................................................................... 422

13.3.3 Reading the Time ................................................................................................. 423

13.3.4 Alarm Fun ction .................................................................................................... 424

13.3.5 Crystal Oscillator Circuit...................................................................................... 425

13.4 Usage Notes....................................................................................................................... 426

13.4.1 Register Writing during RTC Count .................................................................... 426

13.4.2 Use of Realtime Clock (RTC) Periodic Interrupts ............................................... 426

.................................................................................. 407

Rev. 5.00, 09/03, page xxiv of xliv

13.4.3 Precautions when Using RTC Module Standby................................................... 426

Section 14 Serial Communication Interface (SCI)

14.1 Overview ........................................................................................................................... 427

14.1.1 Features................................................................................................................ 427

14.1.2 Block Diagram..................................................................................................... 428

14.1.3 Pin Conf iguration................................................................................................. 431

14.1.4 Register Configuration......................................................................................... 432

14.2 Register Descriptions......................................................................................................... 432

14.2.1 Receive Shift Register (SCRSR).......................................................................... 432

14.2.2 Receive Data Register (SCRDR).......................................................................... 433

14.2.3 Transmit Shift Register (SCTSR)......................................................................... 433

14.2.4 Transmit Data Register (SCTDR) ........................................................................ 434

14.2.5 Serial Mode Register (SCSMR)........................................................................... 434

14.2.6 Serial Control Register (SCSCR)......................................................................... 437

14.2.7 Serial Status R egister (S CSSR)............................................................................ 440

14.2.8 SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR)................. 444

14.2.9 Bit Rate Register (SCBRR).................................................................................. 446

14.3 Operation........................................................................................................................... 453

14.3.1 Overview.............................................................................................................. 453

14.3.2 Operation in Asynch ronous Mode........................................................................ 455

14.3.3 Multiprocessor Communication........................................................................... 465

14.3.4 Synchronous Operation........................................................................................ 474

14.4 SCI Interrupts.................................................................................................................... 484

14.5 Usage Notes....................................................................................................................... 485

..................................................... 427

Section 15 Smart Card Interface

15.1 Overview ........................................................................................................................... 489

15.1.1 Features................................................................................................................ 489

15.1.2 Block Diagram..................................................................................................... 490

15.1.3 Pin Conf iguration................................................................................................. 491

15.1.4 Smart Card Interface Registers............................................................................. 491

15.2 Register Descriptions......................................................................................................... 492

15.2.1 Smart Card Mode Register (SCSCMR)................................................................ 492

15.2.2 Serial Status R egister (S CSSR)............................................................................ 493

15.3 Operation........................................................................................................................... 494

15.3.1 Overview.............................................................................................................. 494

15.3.2 Pin Conn ections.................................................................................................... 495

15.3.3 Data Format.......................................................................................................... 496

15.3.4 Register Settings................................................................................................... 497

15.3.5 Clock.................................................................................................................... 498

15.3.6 Data Transmission and Reception........................................................................ 501

15.4 Usage Notes....................................................................................................................... 507

...................................................................................... 489

Rev. 5.00, 09/03, page xxv of xliv

15.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode .................... 507

15.4.2 Retransmission (Receive and Transmit Modes)................................................... 509

Section 16 Serial Communication Interface with FIFO (SCIF)

16.1 Overview ........................................................................................................................... 511

16.1.1 Features................................................................................................................ 511

16.1.2 Block Diagram..................................................................................................... 512

16.1.3 Pin Conf iguration................................................................................................. 515

16.1.4 Register Configuration......................................................................................... 516

16.2 Register Descriptions......................................................................................................... 517

16.2.1 Receive Shift Register (SCRSR).......................................................................... 517

16.2.2 Receive FIFO Data Register (SCFRDR).............................................................. 517

16.2.3 Transmit Shift Register (SCTSR)......................................................................... 517

16.2.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 518

16.2.5 Serial Mode Register (SCSMR)........................................................................... 518

16.2.6 Serial Control Register (SCSCR)......................................................................... 520

16.2.7 Serial Status R egister (S CSSR)............................................................................ 522

16.2.8 Bit Rate Register (SCBRR).................................................................................. 527

16.2.9 FIFO Control Register (SCFCR).......................................................................... 534

16.2.10 FIFO Data Count Register (SCFDR) ................................................................... 536

16.3 Operation........................................................................................................................... 537

16.3.1 Overview.............................................................................................................. 537

16.3.2 Serial Operation.................................................................................................... 538

16.4 SCIF Interrupts.................................................................................................................. 550

16.5 Usage Notes....................................................................................................................... 551

............................. 511

Section 17 IrDA

17.1 Overview ........................................................................................................................... 555

17.1.1 Features................................................................................................................ 555

17.1.2 Block Diagram..................................................................................................... 556

17.1.3 Pin Conf iguration................................................................................................. 559

17.1.4 Register Configuration......................................................................................... 560

17.2 Register Description.......................................................................................................... 561

17.2.1 Serial Mode Register (SCSMR)........................................................................... 561

17.3 Operation Description ....................................................................................................... 563

17.3.1 Overview.............................................................................................................. 563

17.3.2 Transmitting......................................................................................................... 563

17.3.3 Receiving.............................................................................................................. 564

Section 18 Pin Function Controller

18.1 Overview ........................................................................................................................... 565

18.2 Register Configuration ...................................................................................................... 569

18.3 Register Descriptions......................................................................................................... 570

Rev. 5.00, 09/03, page xxvi of xliv

.................................................................................................................... 555

................................................................................ 565

18.3.1 Port A Control Register (PACR).......................................................................... 570

18.3.2 Port B Control Register (PBCR) .......................................................................... 571

18.3.3 Port C Control Register (PCCR) .......................................................................... 572

18.3.4 Port D Control Register (PDCR).......................................................................... 573

18.3.5 Port E Control Register (PECR)........................................................................... 574

18.3.6 Port F Control R egister (PFCR)........................................................................... 575

18.3.7 Port G Control Register (PGCR).......................................................................... 576

18.3.8 Port H Control Register (PHCR).......................................................................... 577

18.3.9 Port J Control Register (PJCR) ............................................................................ 579

18.3.10 Port K Control Register (PKCR).......................................................................... 580

18.3.11 Port L Control Register (PLCR)........................................................................... 581

18.3.12 SC Port Control Register (SCPCR)...................................................................... 582

Section 19 I/O Ports

19.1 Overview ........................................................................................................................... 587

19.2 Port A ................................................................................................................................ 587

19.2.1 Register Description............................................................................................. 587

19.2.2 Port A Data Register (PADR) .............................................................................. 588

19.3 Port B ................................................................................................................................ 589

19.3.1 Register Description............................................................................................. 589

19.3.2 Port B Data Register (PBDR)............................................................................... 590

19.4 Port C ................................................................................................................................ 591

19.4.1 Register Description............................................................................................. 591

19.4.2 Port C Data Register (PCDR)............................................................................... 592

19.5 Port D ................................................................................................................................ 593

19.5.1 Register Description............................................................................................. 593

19.5.2 Port D Data Register (PDDR).............................................................................. 594

19.6 Port E................................................................................................................................. 595

19.6.1 Register Description............................................................................................. 595

19.6.2 Port E Data Register (PEDR)............................................................................... 596

19.7 Port F................................................................................................................................. 597

19.7.1 Register Description............................................................................................. 597

19.7.2 Port F Data Register (PFDR)................................................................................ 598

19.8 Port G ................................................................................................................................ 599

19.8.1 Register Description............................................................................................. 599

19.8.2 Port G Data Register (PGDR).............................................................................. 600

19.9 Port H ................................................................................................................................ 601

19.9.1 Register Description............................................................................................. 601

19.9.2 Port H Data Register (PHDR).............................................................................. 602

19.10 Port J.................................................................................................................................. 603

19.10.1 Register Description............................................................................................. 603

19.10.2 Port J Data Register (PJDR)................................................................................. 604

19.11 Port K ................................................................................................................................ 605

............................................................................................................ 587

Rev. 5.00, 09/03, page xxvii of xliv

19.11.1 Register Description............................................................................................. 605

19.11.2 Port K Data Register (PKDR).............................................................................. 606

19.12 Port L................................................................................................................................. 607

19.12.1 Register Description............................................................................................. 607

19.12.2 Port L Data Register (PLDR)............................................................................... 608

19.13 SC Port .............................................................................................................................. 609

19.13.1 Register Description............................................................................................. 609

19.13.2 SC Port Data Register (SCPDR) .......................................................................... 610

Section 20 A/D Converter

20.1 Overview ........................................................................................................................... 613

20.1.1 Features................................................................................................................ 613

20.1.2 Block Diagram..................................................................................................... 614

20.1.3 Input Pins.............................................................................................................. 615

20.1.4 Register Configuration......................................................................................... 616

20.2 Register Descriptions......................................................................................................... 617

20.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 617

20.2.2 A/D Control/Status Register (ADCSR)................................................................ 618

20.2.3 A/D Control Register (ADCR)............................................................................. 621

20.3 Bus Master Interface.......................................................................................................... 622

20.4 Operation........................................................................................................................... 623

20.4.1 Single Mode (MULTI = 0)................................................................................... 623

20.4.2 Multi Mode (MULTI = 1, SCN = 0) .................................................................... 625

20.4.3 Scan Mode (MULTI = 1, SCN = 1) ..................................................................... 627

20.4.4 Input Sampling and A/D Conversion Time.......................................................... 629

20.4.5 External Trigger Input Timing ............................................................................. 630

20.5 Interrupts ........................................................................................................................... 631

20.6 Definitions of A/D Conversion Accuracy ......................................................................... 631

20.7 Usage Notes....................................................................................................................... 632

20.7.1 Setting Analog Input Voltage............................................................................... 632

20.7.2 Processin g of Analog Input Pins .......................................................................... 632

20.7.3 Access Size and Read Data .................................................................................. 633

................................................................................................. 613

Section 21 D/A Converter

21.1 Overview ........................................................................................................................... 635

21.1.1 Features................................................................................................................ 635

21.1.2 Block Diagram..................................................................................................... 635

21.1.3 I/O Pins................................................................................................................. 636

21.1.4 Register Configuration......................................................................................... 636

21.2 Register Descriptions......................................................................................................... 637

21.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 637

21.2.2 D/A Control Register (DACR)............................................................................. 637

21.3 Operation........................................................................................................................... 639

Rev. 5.00, 09/03, page xxviii of xliv

................................................................................................. 635

Section 22 User Debugging Interface (UDI)

22.1 Overview ........................................................................................................................... 641

22.2 User Debugging Interface (UDI)....................................................................................... 641

22.2.1 Pin Description s................................................................................................... 641

22.2.2 Block Diagram..................................................................................................... 642

22.3 Register Descriptions......................................................................................................... 642

22.3.1 Bypass Register (SDBPR).................................................................................... 643

22.3.2 Instruction Register (SDIR).................................................................................. 643

22.3.3 Boundary Scan Register (SDBSR)....................................................................... 644

22.4 UDI Operation................................................................................................................... 651

22.4.1 TAP Controller..................................................................................................... 651

22.4.2 Reset Configuration.............................................................................................. 652

22.4.3 UDI Reset............................................................................................................. 653

22.4.4 UDI Interrupt........................................................................................................ 653

22.4.5 Bypass.................................................................................................................. 653

22.4.6 Using UDI to Recover from Sleep Mode............................................................. 653

22.5 Boundary Scan .................................................................................................................. 654

22.5.1 Supported Instructions.......................................................................................... 654

22.5.2 Points for Attention.............................................................................................. 655

22.6 Usage Notes....................................................................................................................... 655

22.7 Advanced User Debugger (AUD) ..................................................................................... 655

............................................................... 641

Section 23 Electrical Characteristics

23.1 Absolute Maximum Ratings.............................................................................................. 657

23.2 DC Characteristics............................................................................................................. 659

23.3 AC Characteristics............................................................................................................. 663

23.3.1 Clock Tim ing........................................................................................................ 664

23.3.2 Control Sig nal Timing.......................................................................................... 670

23.3.3 AC Bu s Timing .................................................................................................... 673

23.3.4 Basic Timing........................................................................................................ 675

23.3.5 Burst ROM Timing .............................................................................................. 678

23.3.6 Synchronous DRAM Timing ............................................................................... 681

23.3.7 PCMCIA Timing .................................................................................................. 699

23.3.8 Peripheral Module Signal Timing........................................................................ 706

23.3.9 UDI-Related Pin Timing...................................................................................... 709

23.3.10 AC Characteristics Measurement Conditions....................................................... 711

23.3.11 Delay Time Variation Due to Load Capacitance.................................................. 712

23.4 A/D Converter Characteristics........................................................................................... 713

23.5 D/A Converter Characteristics........................................................................................... 713

Appendix A Pin Functions

A.1 Pin States........................................................................................................................... 715

A.2 Pin Specifications.............................................................................................................. 719

................................................................................................ 715

.............................................................................. 657

Rev. 5.00, 09/03, page xxix of xliv

A.3 Treatment of Unused Pins................................................................................................. 724

A.4 Pin States in Access to Each Address Space ..................................................................... 725

Appendix B Memory-Mapped Control Registers

B.1 Register Address Map....................................................................................................... 739

B.2 Register Bits...................................................................................................................... 745

Appendix C Product Lineup Appendix D Package Dimensions

............................................................................................. 757

................................................................................... 758

....................................................... 739

Rev. 5.00, 09/03, page xxx of xliv

+ 777 hidden pages

Renesas SH7709S User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Cautions

General Precautions on Handling of Product

Configuration of This Manual

Preface

List of Items Revised or Added for This Version

Contents