Renesas SH7706 Series Hardware Manual

REJ09B0146-0500

The revision list can be viewed directly by
clicking the title page.

The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.

SH7706 Group

32

Hardware Manual

Renesas 32-Bit RISC Microcomputer

SuperH™ RISC engine Family/SH7700 Series

SH7706 HD6417706F

HD6417706BP

Rev. 5.00
Revision Date: May 29, 2006

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 5.00 May 29, 2006 page ii of xlviii

General Precautions on Handling of Product

1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
they are used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction m ay occur.

3. Processing before Initializatio n
Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.

Rev. 5.00 May 29, 2006 page iii of xlviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Main Revisions for This Edition
The list of revisions is a summary of points that have been revised or added to earlier versions.

This does not include all of the revised contents. For details, see th e actual locations in this
manual.

5. Contents

6. Overview

7. Description of Functional Modules

 CPU and System-Control Modules
 On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

8. List of Registers

9. Electrical Characteristics

10.Appendix

11.Index

Rev. 5.00 May 29, 2006 page iv of xlviii

Preface

The SH7706 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas
Technology original RISC CPU as its core, and the peripheral functions required to configure a
system.

Target Users: This manual was written for users who will be using this LSI in the design of

application systems. Users of this manual are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware function s and electrical

characteristics of this LSI to the above users.
Refer to the SH-3/SH-3E/SH3-DSP Progr a mming Manual for a detailed description
of the instruction set.

Notes on reading this manual:

• Product names

The following products are covered in this manual.

Product Classifications and Abbreviations
Basic Classification Product Code

SH7706 (176-pin plastic LQFP) HD6417706F133
SH7706 (208-pin plastic TFBGA) HD6417706BP133V

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU’s functions

Read the SH-3/SH-3E/SH3-DSP Programming Manual.
Rules: Register name: The following notation is used for cases when the same or a

similar function, e.g. serial communication, is implemented
on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)

Bit order: The MSB (most significant bit) is on the left and the LSB

(least significant bit) is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx

Rev. 5.00 May 29, 2006 page v of xlviii

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/

SH7706 manuals:

Document Title Document No.

SH7706 Hardware Manual This manual
SH-3/SH-3E/SH3-DSP Programming Manual ADE-602-096

Users manuals for development tools:

Document Title Document No.

SH Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s
Manual

SH Series Simulator/Debugger (for Windows) User’s Manual ADE-702-186
SH Series Simulator/Debugger (for UNIX) User’s Manual ADE-702-203
High-performance Embedded Workshop User’s Manual ADE-702-201
SH Series High-performance Embedded Workshop,

High-performance Debugging Interface Tutorial

ADE-702-246

ADE-702-230

Rev. 5.00 May 29, 2006 page vi of xlviii

Abbreviations

ACIA Asynchronous Communication Interface Adapter
ADC Analog to Digital Converter
AUD Advanced User Debugger
BSC Bus State Controller
CPG Clock Pulse Generator
CMT Compare Match Timer
DAC Digital to Analog Converter
DMA Direct Memory Access
DMAC Direct Memory Access Controller
DRAM Dynamic Random Access Memory
ETU Elementary Time Unit
FIFO First-In First-Out
H-UDI User Debugging Interface
INTC Interrupt Controller
JEIDA Japan Electronic Industry Development Association
JTAG Joint Test Action Group
LRU Least Recently Used
LSB L east Significant Bit
MMU Memory Management Unit
MSB Most Significant Bit
PCMCIA Personal Computer Memory Card International Association
PFC Pin Function Controller
PLL Phase Locked Loop
RISC Reduced Instruction Set Computer
ROM Read Only Memory
RTC Realtime Clock
SCI Serial Communication Interface
SCIF Serial Communication Interface with FIFO
SRAM Static Random Access Memory
TLB Translation Lookaside Buffer
TMU Timer Unit
UART Universal Asynchronous Receiver/Transmitter
UBC User Break Controller
WDT Watchdog Timer

Rev. 5.00 May 29, 2006 page vii of xlviii

Rev. 5.00 May 29, 2006 page viii of xlviii

Main Revisions for This Edition

Item Page Revision (See Manual for Details)

1.3 Pin Assignment
Figure 1.2 Pin

Assignment (FP-176C)

1.4 Pin Function 10 Table amended

4 Figure amended

MD3
MD4
MD5

AV

SS

AN[0]/PTJ[0]

AN[1]/PTJ[1]
AN[2]/DA[1]/PTJ[2]
AN[3]/DA[0]/PTJ[3]

Number of Pins
FP-176C TBP-208A Pin Name I/O Description

109 K15 AUDATA[0]/PTF[0] I/O AUD data / input/output port F
110 K16 AUDATA[1]/PTF[1] I/O AUD data / input port F
111 K17 AUDATA[2]/PTF[2] I/O AUD data / input/output port F

AV

CC

AV

SS

167
168
169
170
171
172
173
174
175
176

INDEX MARK

3.4.4 Avoiding
Synonym Problems

Figure 3.9 Synonym
Problem

69 Figure amended

When using a 4-kbyte page

Virtual address

31

VPN

Physical address
31

PPN

When using a 1-kbyte page

Virtual address
31

Physical address
31

VPN

PPN

12 11

12 11

0

Offset

Virtual address (11 to 4)

0

Offset

Physical address (31 to 10)

9

9

010

Offset

Virtual address (11 to 4)

010

Offset

Physical address (31 to 10)

Rev. 5.00 May 29, 2006 page ix of xlviii

Item Page Revision (See Manual for Details)

6.3.2 IRQ Interrupt 116 Description amended
When using edge-sensing for IRQ interrupts, clear the interrupt

source by having software read 1 from the corresponding bit in
IRR0, then write 0 to the bit.

It is not necessary to clear the bit
to 0 when using level-sensing. Instead, the pin corresponding to
the interrupt request must be driven high.

6.4.4 Interrupt
Request Register 0
(IRR0)

129 Description amended

To clear one of bits IRQ5R to IRQ0R to 0, first read the bit to
confirm it is set to 1, then write 0 only to the bit to be cleared
while writing 1 to all the other bits. Only 0 can be written to bits
IRQ5R to IRQ0R.

Table amended

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 R Reserved

5 IRQ5R 0 R/W IRQ5 Interrupt Request

4 IRQ4R 0 R/W IRQ4 Interrupt Request

3 IRQ3R 0 R/W IRQ3 Interrupt Request

These bits are always read as 0. The write value
should always be 0.

Indicates whether an interrupt request is input to the
IRQ5 pin. When edge detection mode is set for IRQ5,
an interrupt request is cleared by clearing the IRQ5R

It is not necessary to clear the flag when using

bit.
level-sensing, because this bit merely shows the status
of the IRQ5 pin.

0: An interrupt request is not input to IRQ5 pin
1: An interrupt request is input to IRQ5 pin

Indicates whether an interrupt request is input to the
IRQ4 pin. When edge detection mode is set for IRQ4,
an interrupt request is cleared by clearing the IRQ4R

It is not necessary to clear the flag when using

bit.
level-sensing, because this bit merely shows the status
of the IRQ4 pin.

0: An interrupt request is not input to IRQ4 pin
1: An interrupt request is input to IRQ4 pin

Indicates whether an interrupt request is input to the
IRQ3 pin. When edge detection mode is set for IRQ3,
an interrupt request is cleared by clearing the IRQ3R

It is not necessary to clear the flag when using

bit.
level-sensing, because this bit merely shows the status
of the IRQ3 pin.

0: An interrupt request is not input to IRQ3 pin
1: An interrupt request is input to IRQ3 pin

Rev. 5.00 May 29, 2006 page x of xlviii

Item Page Revision (See Manual for Details)

6.4.4 Interrupt
Request Register 0
(IRR0)

130

Table amended

Bit Bit Name Initial Value R/W Description

2 IRQ2R 0 R/W IRQ2 Interrupt Request

1 IRQ1R 0 R/W IRQ1 Interrupt Request

0 IRQ0R 0 R/W IRQ0 Interrupt Request (IRQ0R)

Indicates whether an interrupt request is input to the
IRQ2 pin. When edge detection mode is set for IRQ2,
an interrupt request is cleared by clearing the IRQ2R

It is not necessary to clear the flag when using

bit.
level-sensing, because this bit merely shows the status
of the IRQ2 pin.

0: An interrupt request is not input to IRQ2 pin
1: An interrupt request is input to IRQ2 pin

Indicates whether an interrupt request is input to the
IRQ1 pin. When edge detection mode is set for IRQ1,
an interrupt request is cleared by clearing the IRQ1R

It is not necessary to clear the flag when using

bit.
level-sensing, because this bit merely shows the status
of the IRQ1 pin.

0: An interrupt request is not input to IRQ1 pin
1: An interrupt request is input to IRQ1 pin

Indicates whether an interrupt request is input to the
IRQ0 pin. When edge detection mode is set for IRQ0,
an interrupt request is cleared by clearing the IRQ0R

It is not necessary to clear the flag when using

bit.
level-sensing, because this bit merely shows the status
of the IRQ0 pin.

0: An interrupt request is not input to IRQ0 pin
1: An interrupt request is input to IRQ0 pin

8.1 Feature 163 (Before) • PCMCIA direct-connection interface →
(After) • PCMCIA interface

8.4.4 Wait State

Control Register 2
(WCR2)

182 Description amended

Bit Bit Name Initial Value R/W Description

15

A6W2

14

A6W1

13

A6W0

12

A5W2

11

A5W1

10

A5W0

1
1
1

1
1
1

R/W

Area 6 Wait Control

R/W

Specify the number of wait states inserted into
physical space area 6

R/W

PCR. Also specify the burst pitch for burst transfer.
Refer to table 8.6 for details.

R/W

Area 5 Wait Control

R/W

Specify the number of wait states inserted into
physical space area 5

R/W

PCR. Also specify the burst pitch for burst transfer.
Refer to table 8.7 for details.

in combination with A6W3 in

in combination with A5W3 in

Table 8.6 Area 6 Wait
Control

(Normal

Memory I/F)
Table 8.7 Area 5 Wait

Control

(Normal

Memory I/F)

184 Table title amended

184 Table title amended

Rev. 5.00 May 29, 2006 page xi of xlviii

Item Page Revision (See Manual for Details)

8.4.6 PCMCIA

192 Table title amended

Control Register (PCR)
Table 8.10 Area 6

Wait Control

(PCMCIA

I/F)

8.5.4 Synchronous
DRAM Interface

222 Description added

If an external bus access request (in order to perform 2) below
conflicts with an auto-refresh request, self-refresh request, or
bus release request internal to the LSI under the following
conditions, SDRAM all-bank precharge may not be executed
properly in the first cycle of the refresh or bus release cycle. In
this case, precharging of the selected bank is executed instead
of all-bank precharge.

1. The RASD bit in the individual memory control register
(MCR) is set to 1

and

2. long-word access is performed to any 16-bit bus width area
(areas 0 to 6) or word/long-word access is performed to any 8­bit bus width area (areas 0 to 6).

The problem may be avoided by either of the following
measures.

1. Use the auto-precharge mode.

2. Use 32-bit bus width for all areas.

Figure 8.24 Auto­Refresh Operation

229 Figure amended

RTCNT value

RTCOR

H'00000000

Rev. 5.00 May 29, 2006 page xii of xlviii

Item Page Revision (See Manual for Details)

8.5.4 Synchronous

DRAM Interface
Figure 8.27

Synchronous DRAM
Mode Write Timing

233 Figure amended and note added

TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4

CKIO

A15 to A13

*

or (A14 to A12)

*

A11 (A10)

*

A12 (A11)

A10 to A2

*

(A9 to A1)

CSn

RD/WR

RASU or RASL

CASU or CASL

D31 to D0

9.3.2 DMA

Destination Address
Registers 0 to 3
(DAR_0 to DAR_3)

CKE

Note: * Items in parentheses ( ) apply to 16-bit bus width connections.

(High)

255 Description amended

To transfer data in 16 bits or in 32 bits, specify the address with
16-bit or 32-bit address boundary. When transferring data in 16­byte units, a 16-byte boundary (address 16n) must be set for
the source address value. Specifying other addresses does not
guarantee operation.

Rev. 5.00 May 29, 2006 page xiii of xlviii

Item Page Revision (See Manual for Details)

9.5.2 Register
Description

Compare Match Timer
Control/Status
Register (CMCSR)

294 Description amended

The compare match timer control/status register (CMCSR) is a
16-bit register that indicates the occurrence of compare
matches,

and establishes the clock used for

incrementation.
Table amended

Bit Bit Name Initial Value R/W Description

1
0

CKS1
CKS000

R/W

Clock select 1 and 0

R/W

These bits select the clock input to the CMCNT
from among the four clocks obtained by dividing
the peripheral clock (Pφ). When the STR
the CMSTR is set to 1, the CMCNT begins
incrementing with the clock selected by CKS1 and
CKS0.

00: P φ/4
01: P φ/8
10: P φ/16
11: P φ/64

0 bit of

9.5.3 Operation
Period Count

Operation

295 Description amended

When a clock is selected with the CKS1 and CKS0 bits of the
CMCSR register and the STR0 bit of the CMSTR is set to 1, the

CMCNT begins incrementing with the selected clock. ...

CMCNT Count Timing 296 Description amended

One of four clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) obtained by
dividing the

peripheral clock (Pφ) can be selected by the CKS1

and CKS0 bits of the CMCSR. Figure 9.28 shows the timing.

Figure 9.28 Count
Timing

Figure amended

Peripheral clock (Pφ)

CMT clock

CMCNT0 input clock

CMCNT0

N-1

Rev. 5.00 May 29, 2006 page xiv of xlviii

Item Page Revision (See Manual for Details)

9.6.1 Example of

DMA Transfer between
A/D Converter and
External Memory
(Address Reload on)

299 Table amended

Items Address reload on Address reload off

SAR_2 H'04000080 H'04000090
DAR_2 H'003FFFF0 H'003FFFF0
DMATCR_2 H'0000007C H'0000007C

Table 9.7 Values in
the DMAC after the
Fourth Transfer Ends

9.7 Cautions 301,

302

Description added

13. When the DMAC transfers data under conditions (1) or (2)
below, the CPU may fetch an unexpected instruction, resulting
in program runaway, or the DMA may transfer the wrong data.

(1) At wake-up from the sleep mode when operating with a
clock ratio for Iφ:Bφ of other than 1:1.

(2) The internal clock frequency division ratio bits (IFC[2:0]) in
the frequency control register (FRQCR) are modified.

Note that no problem occurs if the clock ratio for Iφ:Bφ is 1:1
after modification of the bits. Furthermore, no problem occurs if
the frequency multiplication ratio bits (STC[2:0]) are modified at
the same time as IFC[2:0].

These problems may be avoided by either of the following
measures.

• Do not use the DMAC when in sleep mode, or set the clock
ratio for Iφ:Bφ to 1:1 before entering sleep mode.

• Do not use the DMAC when modifying only the internal clock
frequency division ratio bits (IFC[2:0]) to produce a clock ratio
for Iφ:Bφ of other than 1:1.

Section 10 Clock
Pulse Generator
(CPG)

303 to
305,
309 to

(Before) Internal clock → (After) CPU clock

312

10.1 Feature 305 Description amended

1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, or
leaves unchanged the input clock frequency from the
or PLL circuit 2.

CKIO pin

Rev. 5.00 May 29, 2006 page xv of xlviii

Item Page Revision (See Manual for Details)

10.3 Clock Operating
Modes

Table 10.3 Available
Combination of Clock
Mode and FRQCR
Values

308,
309

Table amended and note 1 added

2

Clock
Mode FRQCR

1

*

PLL1 PLL2

Clock Rate
(I:B:P)

*

Input Frequency Range

Notes: 1. This LSI cannot operate in an FRQCR value other
than that listed in table 10.3.

2. Taking input clock as 1
Max. frequency: Iφ = 133.34 MHz, Bφ (CKIO) = 66.67 MHz,
Pφ = 33.34 MHz

10.3 Clock Operating
Modes

Cautions:

10.6 Usage Note
When Using a PLL

Oscillator Circuit:

13.3.15 RTC Control
Register 1 (RCR1)

309 Item 4 amended

• The peripheral clock frequency should not be set higher than
the frequency of the CKIO pin,

313 Description amended

… In clock mode 7, connect the EXTAL pin to V
and leave the XTAL pin open.

352 Description and table amended

RTC control register 1 (RCR1) affects carry flags and alarm

or higher than 33 MHz.

flags. It also selects whether to generate interrupts for each
flag. Because flags are sometimes set after an operand read,
do not use this register in read-modify-write processing.

RCR1 is an 8-bit read/write register. Bits CIE, AIE, and AF are
initialized by a power-on reset or manual reset. After a power­on reset or manual reset, however, the CF flag is undefined.
When using the CF flag, it must be initialized beforehand. This
register is not initialized in standby mode.

Bit Bit Name Initial Value R/W Description

7CF

— R/W Carry Flag

Status flag that indicates that a carry has occurred. CF
is set to 1 when a count-up to R64CNT or RSECCNT
occurs. A count register value read at this time cannot
be guaranteed; another read is required.

0: No count up of R64CNT or RSECCNT.

[Clearing condition]
When 0 is written to CF

1: Count up of R64CNT or RSECCNT.

[Setting condition]
When 1 is written to CF

CKIO Frequency
Range

Q or VSSQ

CC

13.4.2 Setting the
Time

356,
357

Replaced

Rev. 5.00 May 29, 2006 page xvi of xlviii

Item Page Revision (See Manual for Details)

14.3.8 SC Port

Control Register
(SCPCR)

381 Table amended

Bit Bit Name Initial Value R/W Description

11

SCP5MD1

10

SCP5MD0

9

SCP4MD1

8

SCP4MD0

7

SCP3MD1

6

SCP3MD0

5

SCP2MD1

4

SCP2MD0

R/W

1
0
1
0
1
0
0
0

See section 17.1.10, SC Port Control Register
(SCPCR).

R/W
R/W
R/W
R/W
R/W
R/W
R/W

16.1 Feature

Figure 16.1 SCIF
Block Diagram

16.3.6 Serial Control

Register 2 (SCSCR2)

442 Figure amended

SCFRDR2

RxD2

TxD2

SCK2

RTS2

CTS2

SCRSR2

451 Bit table amended

Bit Bit Name

10CKE1

CKE000

Initial
Value R/W Description

SCFTDR2

(16 stages)(16 stages)

SCTSR2

Parity generation

Parity check

R/W

00: Internal clock, SCK pin used for

R/W

ignored)
01: Internal clock, SCK2 pin used for clock output
10: External clock, SCK2 pin used for clock input
11: External clock, SCK2 pin used for clock input

Notes: 1. The output clock frequency is 16 times the bit

rate.

2. The input clock frequency is 16 times the bit rate.

SCPCR

SCPDR
SCFDR2
SCFCR2
SCSSR2
SCSCR2
SCSMR2

Transmit/

receive

control

Ex

I/O pin (input signal is

1

*

2

*

2

*

16.4.1 Serial
Operation

Serial data reception:

479 Description amended

5. When modem control is enabled, the RTS2 signal is output
when SCFRDR2 is

full. ...

Rev. 5.00 May 29, 2006 page xvii of xlviii

Item Page Revision (See Manual for Details)

Section 17 Pin
Function Controller
(PFC)

Table 17.1 List of
Multiplexed Pins

487 Table amended

Port Function

Port

(Related Module)

F PTF2 I/O (port) AUDATA[2] I/O (AUD)
F PTF1 input (port) AUDATA[1] I/O (AUD)
F PTF0 I/O (port) AUDATA[0] I/O (AUD)

Other Function
(Related Module)

17.1.6 Port F Control
Register (PFCR)

17.1.10 SC Port
Control Register
(SCPCR)

18.6 Port F
Figure 18.6 Port F

498 Bit table amended

Bit Bit Name Initial Value R/W Description

32PF1MD1

PF1MD0

1/0
0

503 Description amended

When the TE bit in SCSCR is set to 1,
ignored and the TxD function is selected.

When the RE bit in SCSCR is set to 1, the SCPCR setting is
ignored and the RxD function is selected.

When the TE bit in SCSCR2 is set to 1, the SCPCR setting is
ignored and the TxD2 function is selected.

When the RE bit in SCSCR2 is set to 1, the SCPCR setting is
ignored and the RxD2 function is selected.

517 Figure amended

PTF6 (I/O) / ASEBRKAK (output)
PTF5 (I/O) / TDO (output)

Port F

PTF4 (I/O) / AUDSYNC (output)
PTF3 (I/O) / AUDATA3 (I/O)
PTF2 (I/O) / AUDATA2 (I/O)
PTF1 (input) / AUDATA1 (I/O)
PTF0 (I/O) / AUDATA0 (I/O)

R/W

PF1 Mode 1

R/W

00: Other function (See table 17.1)

Reserved (Setting prohibited)

01:
10: Port input (Pull-up MOS: on)
11: Port input (Pull-up MOS: off)

the SCPCR setting is

18.10.2 SC Port Data
Register (SCPDR)

526 Bit table amended

Bit Bit Name Initial Value R/W Description

5 SCP5DT
4 SCP4DT 0 R/W
3 SCP3DT 0 R/W

Rev. 5.00 May 29, 2006 page xviii of xlviii

0 R Table 18.10 shows the function of SCPDR

Item Page Revision (See Manual for Details)

Section 22 Power­Down Modes

Table 22.1 Power­Down Modes

568 Table amended and note 5 added

CPU
Reg-

Mode

Module
standby
function

Transition
Conditions

Set MSTP bit of
STBCR to 1

5

*

CPG CPU

Runs Runs

*

On-Chip

ister

Memory

Held Held Specified

4

State

Note: 5. If the realtime clock (RTC) is set to module standby
mode (bit 1 in standby control register (STBCR) set to 1) before
any register in the RTC, SCI, or TMU is accessed, registers in
the serial communication interface (SCI) or timer unit (TMU)
may not be read properly. To avoid this problem, access (read
or write) any register in the RTC, SCI, or TMU once or more
before setting the RTC to module standby mode.

22.3.3 Module
Standby Function

Transition to Module
Standby Function

576 Description added

If the realtime clock (RTC) is set to module standby mode (bit 1
in standby control register (STBCR) set to 1) before any
register in the RTC, SCI, or TMU is accessed, registers in the
serial communication interface (SCI) or timer unit (TMU) may
not be read properly. To avoid this problem, access (read or
write) any register in the RTC, SCI, or TMU once or more
before setting the RTC to module standby mode.

24.3.1 Clock Timing
Figure 24.4 Power-

On Oscillation Settling
Time

615 Figure amended

CKIO,
internal clock

V

CC

V

– RTC

CC

– PLL1

V

CC

– PLL2

V

CC

VCC min

t

OSC1

On-Chip
Peripheral
Modules Pins

2

*

module
halts

External

Canceling

Memory

Procedure

Refresh 1. Clear MSTP

bit to 0

2. Power-on
reset

RESETP

Rev. 5.00 May 29, 2006 page xix of xlviii

Item Page Revision (See Manual for Details)

24.3.6 Synchronous
DRAM Timing

Figure 24.39

646 Figure amended and note added

TRp1

TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4

CKIO

Synchronous DRAM
Mode Register Write
Cycle

A11 (A10)

A12 (A11)

A10 to A2
(A9 to A1)

*

t

t

AD

AD

*

*

t

CSD3

Note: * Items in parentheses ( ) apply to 16-bit bus width
connections.

t

t

AD

AD

t

t

AD

AD

t

t

AD

AD

t

t

t

t

AD

AD

AD

CSD3

24.3.7 PCMCIA
Timing

Figure 24.45
PCMCIA I/O Bus Cycle
(TED = 2, TEH = 1,
One Wait, External
Wait)

24.3.12 Delay Time
Variation Due to Load
Capacitance

Figure 24.63 Load
Capacitance vs. Delay
Time

652 Figure amended

D15 to D0

(read)

ICIOWR

(write)

t

D15 to D0

(write)

WDD1

663 Figure amended

+3

+2

+1

Delay Time [ns]

+0

+0 +10 +20 +30 +40 +50

t

ICWSD

Load Capacitance [pF]

t

RDS1

t

ICWSD

t

WDH4

t

WDH1

50 pF stipulated

30 pF stipulated

Rev. 5.00 May 29, 2006 page xx of xlviii

Item Page Revision (See Manual for Details)

B.1 Pin Functions
Table B.1 Pin States

during Resets, Power­Down States, and Bus­Released State

669 Table amended and note 12 added

Reset Power-Down

Power-On

Manual

Reset

Reset Standby Sleep

1

*

O

1

*

IO

8

*

I

IIII

8

*

IIII

Reset Power-Down

Power-On

Manual

Reset

Reset Standby Sleep

8

*

IIZII

671

Category Pin

Clock

EXTAL I I I I I
XTAL O
CKIO IO
EXTAL2 I I I I I
XTAL2 O O O O O
CAP1, CAP2 — ————

Interrupt IRQ[3:0]/IRL[3:0]/

PTH[3:0]
IRQ4/ PTH[4] I
NMI I IIII

IRQOUT/PTE[7] H OP

Category Pin

Port

CE2B/PTD[7] H OP
CE2A/PTD[6] H OP

IOIS16/PTD[5] I I Z I I

ADTRG/PTG[5] V

*

Bus
Released

1

1

1

*

O

1

*

IO

3

*

ZK

3

*

ZH

3

*

ZH

*

O

1 *12

*

IO

3

*

OP

11

3

*

*

K

OP

11

3

*

*

K

OP

1

*

O

1

1

*

*

IO

3

3

*

*

OP

Bus
Released

3

3

*

*

ZP

3

3

*

*

ZP

B.3 Processing of
Unused Pins

H-UDI TCK/PTG[1] IV I IZ I I

TDI/PTG[0] IV I IZ I I
TMS/PTG[2] IV I IZ I I

TRST/PTG[3] IV I IZ I I
AUDSYNC/PTF[4] OV OP

TDO/PTF[5] OV OP

3

3

3

*

*

OK

3

*

OP

3

*

OK

OP

3

*

*

OP

3

3

*

*

OP
AUDCK/PTG[4] IV I IZ I I
AUDATA[3:0]/PTF[3:0] IV I IZ I I
ASEBRKAK/PTF[6] OV OP

3

3

3

*

*

OP

OP

3

*

*

OP
ASEMD0 I I Z I I

672 Notes: 12. In the standby mode, CKIO may be either high or

low level.

677 Description amended

• When EXTAL pin is not used
— EXTAL:

Connect to VCCQ or VSSQ

Rev. 5.00 May 29, 2006 page xxi of xlviii

Item Page Revision (See Manual for Details)

C. Product Lineup 692 Table amended

Model Marking Package

HD6417706F133 176-pin plastic LQFP (FP-176C/PLQP0176KD-A)
HD6417706BP133 208-pin TFBGA (TBP-208A/TTBG0208JA-A)

D. Package
Dimensions

Figure D.1 Package
Dimensions (FP-176C
PLQP0176KD-A)

Figure D.2 Package
Dimensions
(TBP-208A/
TTBG0208JA-A)

693 Figure replaced

/

694 Figure replaced

Rev. 5.00 May 29, 2006 page xxii of xlviii

Contents

Section 1 Overview............................................................................................................. 1

1.1 Feature .............................................................................................................................. 1

1.2 Block Diagram.................................................................................................................. 3

1.3 Pin Assignment ................................................................................................................. 4

1.4 Pin Function...................................................................................................................... 6

Section 2 CPU...................................................................................................................... 13

2.1 Register Description.......................................................................................................... 13

2.1.1 Privileged Mode and Banks................................................................................. 13

2.1.2 General Registers................................................................................................. 15

2.1.3 System Registers.................................................................................................. 16

2.1.4 Control Registers ................................................................................................. 17

2.2 Data Formats..................................................................................................................... 20

2.2.1 Data Format in Registers...................................................................................... 20

2.2.2 Data Format in Memory....................................................................................... 20

2.3 Instruction Features........................................................................................................... 21

2.3.1 Execution Environment ....................................................................................... 21

2.3.2 Addressing Modes ............................................................................................... 23

2.3.3 Instruction Formats.............................................................................................. 27

2.4 Instruction Set ................................................................................................................... 30

2.4.1 Instruction Set Classified by Function................................................................. 30

2.4.2 Instruction Code Map .......................................................................................... 46

2.5 Processor States and Processor Modes.............................................................................. 49

2.5.1 Processor States ................................................................................................... 49

2.5.2 Processor Modes.................................................................................................. 50

Section 3 Memory Management Unit (MMU)........................................................... 51

3.1 Role of MMU.................................................................................................................... 51

3.1.1 This LSI's MMU.................................................................................................. 53

3.2 Register Description.......................................................................................................... 56

3.2.1 Page Table Entry Register High (PTEH)............................................................. 57

3.2.2 Page Table Entry Register Low (PTEL).............................................................. 57

3.2.3 The Translation Table Base Register (TTB)........................................................ 58

3.2.4 The TLB Exception Address Register (TEA)...................................................... 58

3.2.5 MMU Control Register (MMUCR)..................................................................... 58

3.3 TLB Functions ............................................................................................................... ... 60

3.3.1 Configuration of the TLB .................................................................................... 60

3.3.2 TLB Indexing....................................................................................................... 62

Rev. 5.00 May 29, 2006 page xxiii of xlviii

3.3.3 TLB Address Comparison ................................................................................... 63

3.3.4 Page Management Information............................................................................ 65

3.4 MMU Functions................................................................................................................66

3.4.1 MMU Hardware Management............................................................................. 66

3.4.2 MMU Software Management .............................................................................. 66

3.4.3 MMU Instruction (LDTLB)................................................................................. 67

3.4.4 Avoiding Synonym Problems.............................................................................. 68

3.5 MMU Exceptions.............................................................................................................. 70

3.5.1 TLB Miss Exception............................................................................................ 70

3.5.2 TLB Protection Violation Exception ................................................................... 71

3.5.3 TLB Invalid Exception ........................................................................................ 72

3.5.4 Initial Page Write Exception................................................................................ 73

3.5.5 Processing Flow in Event of MMU Exception

(Same Processing Flow for CPU Address Error)................................................. 75

3.6 Configuration of the Memory-Mapped TLB .................................................................... 77

3.6.1 Address Array...................................................................................................... 77

3.6.2 Data Array............................................................................................................ 77

3.6.3 Usage Examples................................................................................................... 79

3.7 Usage Note........................................................................................................................ 79

3.7.1 Use of Instructions Manipulating MD and BL Bits in SR................................... 79

3.7.2 Use of TLB .......................................................................................................... 80

Section 4 Exception Processing....................................................................................... 81

4.1 Exception Processing Function......................................................................................... 81

4.1.1 Exception Processing Flow.................................................................................. 81

4.1.2 Exception Processing Vector Addresses.............................................................. 82

4.1.3 Acceptance of Exceptions.................................................................................... 83

4.1.4 Exception Codes .................................................................................................. 85

4.1.5 Exception Request and BL Bit............................................................................. 86

4.1.6 Returning from Exception Processing ................................................................. 86

4.2 Register Description.......................................................................................................... 87

4.2.1 Exception Event Register (EXPEVT).................................................................. 87

4.2.2 Interrupt Event Register (INTEVT)..................................................................... 88

4.2.3 Interrupt Event Register 2 (INTEVT2)................................................................ 88

4.2.4 TRAPA Exception Register (TRA) ..................................................................... 89

4.3 Operation .......................................................................................................................... 89

4.3.1 Reset..................................................................................................................... 89

4.3.2 Interrupts.............................................................................................................. 90

4.3.3 General Exceptions.............................................................................................. 90

4.4 Individual Exception Operations....................................................................................... 91

4.4.1 Resets................................................................................................................... 91

Rev. 5.00 May 29, 2006 page xxiv of xlviii

4.4.2 General Exceptions.............................................................................................. 92

4.4.3 Interrupts.............................................................................................................. 95

4.5 Usage Note........................................................................................................................ 97

Section 5 Cache.................................................................................................................... 99

5.1 Feature .............................................................................................................................. 99

5.1.1 Cache Structure.................................................................................................... 99

5.2 Register Description.......................................................................................................... 101

5.2.1 Cache Control Register (CCR) ............................................................................ 101

5.2.2 Cache Control Register 2 (CCR2)........................................................................ 102

5.3 Operation .......................................................................................................................... 105

5.3.1 Searching the Cache............................................................................................. 105

5.3.2 Read Access......................................................................................................... 106

5.3.3 Prefetch Operation............................................................................................... 107

5.3.4 Write Access........................................................................................................ 107

5.3.5 Write-Back Buffer ............................................................................................... 107

5.3.6 Coherency of Cache and External Memory......................................................... 108

5.4 Memory-Mapped Cache ................................................................................................... 108

5.4.1 Address Array...................................................................................................... 108

5.4.2 Data Array............................................................................................................ 109

5.4.3 Usage Examples................................................................................................... 111

Section 6 Interrupt Controller (INTC)........................................................................... 113

6.1 Feature .............................................................................................................................. 113

6.2 Input/Output Pin................................................................................................................ 115

6.3 Interrupt Sources............................................................................................................... 115

6.3.1 NMI Interrupts..................................................................................................... 115

6.3.2 IRQ Interrupt........................................................................................................ 116

6.3.3 IRL Interrupts ...................................................................................................... 117

6.3.4 On-Chip Peripheral Module Interrupts ................................................................ 118

6.3.5 Interrupt Exception Processing and Priority........................................................ 119

6.4 Register Description.......................................................................................................... 123

6.4.1 Interrupt Priority Registers A to E (IPRA to IPRE)............................................. 124

6.4.2 Interrupt Control Register 0 (ICR0)..................................................................... 125

6.4.3 Interrupt Control Register 1 (ICR1)..................................................................... 126

6.4.4 Interrupt Request Register 0 (IRR0).................................................................... 129

6.4.5 Interrupt Request Register 1 (IRR1).................................................................... 131

6.4.6 Interrupt Request Register 2 (IRR2).................................................................... 132

6.5 Operation .......................................................................................................................... 133

6.5.1 Interrupt Sequence............................................................................................... 133

6.5.2 Multiple Interrupts............................................................................................... 135

Rev. 5.00 May 29, 2006 page xxv of xlviii

6.6 Interrupt Response Time................................................................................................... 135

Section 7 User Break Controller..................................................................................... 139

7.1 Feature .............................................................................................................................. 139

7.2 Register Description.......................................................................................................... 141

7.2.1 Break Address Register A (BARA)..................................................................... 141

7.2.2 Break Address Mask Register A (BAMRA)........................................................ 142

7.2.3 Break Bus Cycle Register A (BBRA).................................................................. 142

7.2.4 Break Address Register B (BARB)...................................................................... 144

7.2.5 Break Address Mask Register B (BAMRB)........................................................ 144

7.2.6 Break Data Register B (BDRB)........................................................................... 144

7.2.7 Break Data Mask Register B (BDMRB).............................................................. 145

7.2.8 Break Bus Cycle Register B (BBRB).................................................................. 145

7.2.9 Break Control Register (BRCR).......................................................................... 147

7.2.10 Execution Times Break Register (BETR)............................................................ 150

7.2.11 Branch Source Register (BRSR).......................................................................... 151

7.2.12 Branch Destination Register (BRDR).................................................................. 152

7.2.13 Break ASID Register A (BASRA)....................................................................... 152

7.2.14 Break ASID Register B (BASRB)....................................................................... 153

7.3 Operation .......................................................................................................................... 153

7.3.1 Flow of the User Break Operation....................................................................... 153

7.3.2 Break on Instruction Fetch Cycle......................................................................... 154

7.3.3 Break by Data Access Cycle................................................................................ 154

7.3.4 Sequential Break.................................................................................................. 155

7.3.5 Value of Saved Program Counter........................................................................ 155

7.3.6 PC Trace .............................................................................................................. 156

7.3.7 Usage Examples................................................................................................... 158

7.4 Usage Note........................................................................................................................ 162

Section 8 Bus State Controller (BSC) ........................................................................... 163

8.1 Feature .............................................................................................................................. 163

8.2 Input/Output Pin................................................................................................................ 165

8.3 Area Overview.................................................................................................................. 166

8.3.1 PCMCIA Support ................................................................................................ 170

8.4 Register Description.......................................................................................................... 173

8.4.1 Bus Control Register 1 (BCR1)........................................................................... 174

8.4.2 Bus Control Register 2 (BCR2)........................................................................... 177

8.4.3 Wait State Control Register 1 (WCR1)................................................................ 179

8.4.4 Wait State Control Register 2 (WCR2)................................................................ 182

8.4.5 Individual Memory Control Register (MCR)....................................................... 186

8.4.6 PCMCIA Control Register (PCR)........................................................................ 190

Rev. 5.00 May 29, 2006 page xxvi of xlviii

8.4.7 Synchronous DRAM Mode Register (SDMR).................................................... 193

8.4.8 Refresh Timer Control/Status Register (RTCSR)................................................ 193

8.4.9 Refresh Timer Counter (RTCNT)........................................................................ 196

8.4.10 Refresh Time Constant Register (RTCOR) ......................................................... 196

8.4.11 Refresh Count Register (RFCR).......................................................................... 197

8.5 Operation .......................................................................................................................... 197

8.5.1 Endian/Access Size and Data Alignment............................................................. 197

8.5.2 Description of Areas............................................................................................ 202

8.5.3 Basic Interface ..................................................................................................... 205

8.5.4 Synchronous DRAM Interface............................................................................. 211

8.5.5 Burst ROM Interface............................................................................................ 234

8.5.6 PCMCIA Interface............................................................................................... 236

8.5.7 Waits between Access Cycles.............................................................................. 247

8.5.8 Bus Arbitration .................................................................................................... 248

8.5.9 Bus Pull-Up.......................................................................................................... 249

Section 9 Direct Memory Access Controller (DMAC)............................................ 251

9.1 Feature .............................................................................................................................. 251

9.2 Input/Output Pin................................................................................................................ 254

9.3 Register Description.......................................................................................................... 254

9.3.1 DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3)................................ 255

9.3.2 DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3)........................ 255

9.3.3 DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3)............... 256

9.3.4 DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3)......................... 256

9.3.5 DMA Operation Register (DMAOR)................................................................... 263

9.4 Operation .......................................................................................................................... 265

9.4.1 DMA Transfer Flow ............................................................................................ 265

9.4.2 DMA Transfer Requests ...................................................................................... 267

9.4.3 Channel Priority................................................................................................... 269

9.4.4 DMA Transfer Types........................................................................................... 272

9.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 284

9.4.6 Source Address Reload Function......................................................................... 288

9.4.7 DMA Transfer Ending Conditions....................................................................... 290

9.5 Compare Match Timer (CMT).......................................................................................... 292

9.5.1 Feature ................................................................................................................. 292

9.5.2 Register Description............................................................................................. 293

9.5.3 Operation ............................................................................................................. 295

9.6 Examples of Use ............................................................................................................... 298

9.6.1 Example of DMA Transfer between A/D Converter and External Memory

(Address Reload on) ............................................................................................ 298

Rev. 5.00 May 29, 2006 page xxvii of xlviii

9.6.2 Example of DMA Transfer between Ex ternal Memory and SCIF Transmitter

(Indirect Address on)........................................................................................... 299

9.7 Cautions ............................................................................................................................ 301

Section 10 Clock Pulse Generator (CPG)..................................................................... 303

10.1 Feature .............................................................................................................................. 303

10.2 Input/Output Pin................................................................................................................ 306

10.3 Clock Operating Modes .................................................................................................... 306

10.4 Register Description.......................................................................................................... 310

10.4.1 Frequency Control Register (FRQCR)................................................................. 310

10.5 Operation .......................................................................................................................... 312

10.5.1 Changing the Multiplication Rate........................................................................ 312

10.5.2 Changing the Division Ratio................................................................................ 312

10.6 Usage Note........................................................................................................................ 313

Section 11 Watchdog Timer (WDT).............................................................................. 315

11.1 Feature .............................................................................................................................. 315

11.2 Register Description.......................................................................................................... 316

11.2.1 Watchdog Timer Counter (WTCNT)................................................................... 316

11.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 316

11.2.3 Notes on Register Access..................................................................................... 318

11.3 Operation .......................................................................................................................... 319

11.3.1 Canceling Software Standbys.............................................................................. 319

11.3.2 Changing the Frequency...................................................................................... 320

11.3.3 Using Watchdog Timer Mode.............................................................................. 320

11.3.4 Using Interval Timer Mode ................................................................................. 321

Section 12 Timer Unit (TMU)......................................................................................... 323

12.1 Feature .............................................................................................................................. 323

12.2 Input/Output Pin................................................................................................................ 325

12.3 Register Description.......................................................................................................... 325

12.3.1 Timer Output Control Register (TOCR).............................................................. 326

12.3.2 Timer Start Register (TSTR)................................................................................ 327

12.3.3 Timer Control Registers 0 to 2 (TCR_0 to TCR_2)............................................. 328

12.3.4 Timer Constant Registers 0 to 2 (TCOR_0 to TCOR_2)..................................... 331

12.3.5 Timer Counters 0 to 2 (TCNT_0 to TCNT_2)..................................................... 332

12.3.6 Input Capture Register 2 (TCPR_2)..................................................................... 332

12.4 Operation .......................................................................................................................... 332

12.4.1 Counter Operation................................................................................................ 333

12.4.2 Input Capture Function........................................................................................ 336

12.5 Interrupts........................................................................................................................... 337

Rev. 5.00 May 29, 2006 page xxviii of xlviii

12.5.1 Status Flag Set Timing......................................................................................... 337

12.5.2 Status Flag Clear Timing ..................................................................................... 337

12.5.3 Interrupt Sources and Priorities............................................................................ 338

12.6 Usage Note........................................................................................................................ 338

12.6.1 Writing to Registers............................................................................................. 338

12.6.2 Reading Registers ................................................................................................ 338

Section 13 Realtime Clock (RTC).................................................................................. 339

13.1 Feature .............................................................................................................................. 339

13.2 Input/Output Pin................................................................................................................ 341

13.3 Register Description.......................................................................................................... 341

13.3.1 64-Hz Counter (R64CNT) ................................................................................... 342

13.3.2 Second Counter (RSECCNT) .............................................................................. 343

13.3.3 Minute Counter (RMINCNT).............................................................................. 343

13.3.4 Hour Counter (RHRCNT).................................................................................... 344

13.3.5 Day of the Week Counter (RWKCNT)................................................................ 344

13.3.6 Date Counter (RDAYCNT)................................................................................. 345

13.3.7 Month Counter (RMONCNT) ............................................................................. 346

13.3.8 Year Counter (RYRCNT).................................................................................... 346

13.3.9 Second Alarm Register (RSECAR)..................................................................... 347

13.3.10 Minute Alarm Register (RMINAR)..................................................................... 347

13.3.11 Hour Alarm Register (RHRAR)........................................................................... 348

13.3.12 Day of the Week Alarm Register (RWKAR)....................................................... 349

13.3.13 Date Alarm Register (RDAYAR)........................................................................ 350

13.3.14 Month Alarm Register (RMONAR).................................................................... 351

13.3.15 RTC Control Register 1 (RCR1).......................................................................... 35 2

13.3.16 RTC Control Register 2 (RCR2).......................................................................... 35 4

13.4 RTC Operation.................................................................................................................. 356

13.4.1 Initial Settings of Registers after Power-On ........................................................ 356

13.4.2 Setting the Time................................................................................................... 356

13.4.3 Reading the Time................................................................................................. 358

13.4.4 Alarm Function.................................................................................................... 359

13.4.5 Crystal Oscillator Circuit..................................................................................... 360

13.5 Usage Note........................................................................................................................ 361

13.5.1 Register Writing during RTC Count.................................................................... 361

13.5.2 Use of Realtime Clock (RTC) Periodic Interrupts............................................... 361

13.5.3 Timing for Setting ADJ Bit in RCR2................................................................... 362

Section 14 Serial Communication Interface (SCI) .................................................... 363

14.1 Feature .............................................................................................................................. 363

14.2 Input/Output Pin................................................................................................................ 367

Rev. 5.00 May 29, 2006 page xxix of xlviii

14.3 Register Description.......................................................................................................... 367

14.3.1 Receive Shift Register (SCRSR).......................................................................... 368

14.3.2 Receive Data Register (SCRDR)......................................................................... 368

14.3.3 Transmit Shift Register (SCTSR) ........................................................................ 368

14.3.4 Transmit Data Register (SCTDR)........................................................................ 368

14.3.5 Serial Mode Register (SCSMR)........................................................................... 369

14.3.6 Serial Control Register (SCSCR)......................................................................... 372

14.3.7 Serial Status Register (SCSSR)............................................................................ 376

14.3.8 SC Port Control Register (SCPCR)...................................................................... 381

14.3.9 SC Port Data Register (SCPDR).......................................................................... 382

14.3.10 Bit Rate Register (SCBRR).................................................................................. 383

14.4 Operation .......................................................................................................................... 390

14.4.1 Operation in Asynchronous Mode....................................................................... 392

14.4.2 Multiprocessor Communication........................................................................... 402

14.4.3 Clock Synchronous Operation............................................................................. 410

14.5 SCI Interrupt Sources........................................................................................................ 417

14.6 Usage Note........................................................................................................................ 418

Section 15 Smart Card Interface ..................................................................................... 421

15.1 Feature .............................................................................................................................. 421

15.2 Input/Output Pin................................................................................................................ 423

15.3 Register Description.......................................................................................................... 423

15.3.1 Smart Card Mode Register (SCSCMR)............................................................... 424

15.3.2 Serial Status Register (SCSSR)............................................................................ 425

15.4 Operation .......................................................................................................................... 427

15.4.1 Overview.............................................................................................................. 427

15.4.2 Pin Connections................................................................................................... 427

15.4.3 Data Format ......................................................................................................... 428

15.4.4 Register Settings .................................................................................................. 429

15.4.5 Clock.................................................................................................................... 431

15.4.6 Data Transmission and Reception........................................................................ 433

15.5 Usage Note........................................................................................................................ 437

Section 16 Serial Communication Interface with FIFO (SCIF)............................. 441

16.1 Feature .............................................................................................................................. 441

16.2 Input/Output Pin................................................................................................................ 445

16.3 Register Description.......................................................................................................... 445

16.3.1 Receive Shift Register 2 (SCRSR2)..................................................................... 446

16.3.2 Receive FIFO Data Register 2 (SCFRDR2) ........................................................ 446

16.3.3 Transmit Shift Register 2 (SCTSR2) ................................................................... 446

16.3.4 Transmit FIFO Data Register 2 (SCFTDR2)....................................................... 446

Rev. 5.00 May 29, 2006 page xxx of xlviii

16.3.5 Serial Mode Register 2 (SCSMR2)...................................................................... 447

16.3.6 Serial Control Register 2 (SCSCR2).................................................................... 449

16.3.7 Serial Status Register 2 (SCSSR2)....................................................................... 452

16.3.8 Bit Rate Register 2 (SCBRR2)............................................................................. 460

16.3.9 FIFO Control Register 2 (SCFCR2) .................................................................... 466

16.3.10 FIFO Data Count Set Register 2 (SCFDR2)........................................................ 468

16.3.11 SC Port Control Register (SCPCR)...................................................................... 468

16.3.12 SC Port Data Register (SCPDR).......................................................................... 468

16.4 Operation .......................................................................................................................... 469

16.4.1 Serial Operation................................................................................................... 470

16.4.2 SCIF Interrupts .................................................................................................... 480

16.5 Usage Notes ...................................................................................................................... 481

Section 17 Pin Function Controller (PFC)................................................................... 485

17.1 Register Description.......................................................................................................... 488

17.1.1 Port A Control Register (PACR).......................................................................... 489

17.1.2 Port B Control Register (PBCR).......................................................................... 490

17.1.3 Port C Control Register (PCCR).......................................................................... 492

17.1.4 Port D Control Register (PDCR).......................................................................... 493

17.1.5 Port E Control Register (PECR) .......................................................................... 495

17.1.6 Port F Control Register (PFCR)........................................................................... 497

17.1.7 Port G Control Register (PGCR).......................................................................... 499

17.1.8 Port H Control Register (PHCR).......................................................................... 500

17.1.9 Port J Control Register (PJCR)............................................................................ 502

17.1.10 SC Port Control Register (SCPCR)...................................................................... 503

Section 18 I/O Ports............................................................................................................ 507

18.1 Port A................................................................................................................................ 507

18.1.1 Register Description............................................................................................. 507

18.1.2 Port A Data Register (PADR).............................................................................. 508

18.2 Port B ................................................................................................................................ 509

18.2.1 Register Description............................................................................................. 509

18.2.2 Port B Data Register (PBDR) .............................................................................. 510

18.3 Port C ................................................................................................................................ 511

18.3.1 Register Description............................................................................................. 511

18.3.2 Port C Data Register (PCDR) .............................................................................. 512

18.4 Port D................................................................................................................................ 513

18.4.1 Register Description............................................................................................. 513

18.4.2 Port D Data Register (PDDR).............................................................................. 514

18.5 Port E ................................................................................................................................ 515

18.5.1 Register Description............................................................................................. 515

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18.5.2 Port E Data Register (PEDR)............................................................................... 516

18.6 Port F................................................................................................................................. 517

18.6.1 Register Description............................................................................................. 517

18.6.2 Port F Data Register (PFDR) ............................................................................... 518

18.7 Port G................................................................................................................................ 519

18.7.1 Register Description............................................................................................. 519

18.7.2 Port G Data Register (PGDR).............................................................................. 520

18.8 Port H................................................................................................................................ 521

18.8.1 Register Description............................................................................................. 521

18.8.2 Port H Data Register (PHDR).............................................................................. 522

18.9 Port J ................................................................................................................................. 523

18.9.1 Register Description............................................................................................. 523

18.9.2 Port J Data Register (PJDR)................................................................................. 524

18.10 SC Port.............................................................................................................................. 525

18.10.1 Register Description............................................................................................. 525

18.10.2 SC Port Data Register (SCPDR).......................................................................... 526

Section 19 A/D Converter (ADC) .................................................................................. 529

19.1 Features................................................................................................................... .......... 529

19.2 Input/Output Pin................................................................................................................ 531

19.3 Register Description.......................................................................................................... 531

19.3.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 532

19.3.2 A/D Control/Status Register (ADCSR) ............................................................... 533

19.3.3 A/D Control Register (ADCR) ............................................................................ 536

19.4 Bus Master Interface......................................................................................................... 536

19.5 Access Size of A/D Data Register..................................................................................... 538

19.5.1 Word Access........................................................................................................ 538

19.5.2 Longword Access................................................................................................. 538

19.6 Operation .......................................................................................................................... 539

19.6.1 Single Mode (MULTI = 0) .................................................................................. 539

19.6.2 Multi Mode (MULTI = 1, SCN = 0).................................................................... 540

19.6.3 Scan Mode (MULTI = 1, SCN = 1)..................................................................... 542

19.6.4 Input Sampling and A/D Conversion Time......................................................... 543

19.6.5 External Trigger Input Timing............................................................................. 545

19.7 Interrupt Requests............................................................................................................. 545

19.8 Definitions of A/D Conversion Accuracy ......................................................................... 545

19.9 Usage Note........................................................................................................................ 546

19.9.1 Setting Analog Input Voltage .............................................................................. 546

19.9.2 Processing of Analog Input Pins .......................................................................... 547

19.9.3 Access Size and Read Data.................................................................................. 548

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Section 20 D/A Converter (DAC) .................................................................................. 549

20.1 Feature .............................................................................................................................. 549

20.2 Input/Output Pin................................................................................................................ 550

20.3 Register Description.......................................................................................................... 550

20.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................ 550

20.3.2 D/A Control Register (DACR) ............................................................................ 550

20.4 Operation .......................................................................................................................... 552

Section 21 User Debugging Interface (H-UDI).......................................................... 553

21.1 Feature .............................................................................................................................. 554

21.2 Input/Output Pin................................................................................................................ 554

21.3 Register Description.......................................................................................................... 555

21.3.1 Bypass Register (SDBPR) ................................................................................... 555

21.3.2 Instruction Register (SDIR)................................................................................. 555

21.3.3 Boundary Scan Register (SDBSR)....................................................................... 556

21.4 H-UDI Operations............................................................................................................. 561

21.4.1 TAP Controller .................................................................................................... 561

21.4.2 Reset Configuration............................................................................................. 562

21.4.3 H-UDI Reset ........................................................................................................ 563

21.4.4 H-UDI Interrupt................................................................................................... 563

21.4.5 Bypass.................................................................................................................. 563

21.4.6 Using H-UDI to Recover from Sleep Mode ........................................................ 563

21.5 Boundary Scan.................................................................................................................. 564

21.5.1 Supported Instructions......................................................................................... 564

21.5.2 Notes for Boundary Scan..................................................................................... 565

21.6 Usage Note........................................................................................................................ 565

21.7 Advanced User Debugger (AUD)..................................................................................... 565

Section 22 Power-Down Modes...................................................................................... 567

22.1 Input/Output Pin................................................................................................................ 569

22.2 Register Description.......................................................................................................... 569

22.2.1 Standby Control Register (STBCR)..................................................................... 569

22.2.2 Standby Control Register 2 (STBCR2)................................................................ 571

22.3 Operation .......................................................................................................................... 573

22.3.1 Sleep Mode .......................................................................................................... 573

22.3.2 Software Standby Mode....................................................................................... 574

22.3.3 Module Standby Function.................................................................................... 576

22.3.4 Timing of STATUS Pin Changes ........................................................................ 578

22.3.5 Hardware Standby Function ................................................................................ 582

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Section 23 List of Registers.............................................................................................. 585

23.1 Register Address Map....................................................................................................... 585

23.2 Register Bits...................................................................................................................... 591

23.3 Register States in Processing Mode.................................................................................. 602

Section 24 Electrical Characteristics.............................................................................. 607

24.1 Absolute Maximum Ratings ............................................................................................. 607

24.2 DC Characteristics ............................................................................................................ 609

24.3 AC Characteristics ............................................................................................................ 612

24.3.1 Clock Timing....................................................................................................... 612

24.3.2 Control Signal Timing ......................................................................................... 619

24.3.3 AC Bus Timing.................................................................................................... 622

24.3.4 Basic Timing........................................................................................................ 624

24.3.5 Burst ROM Timing.............................................................................................. 627

24.3.6 Synchronous DRAM Timing............................................................................... 630

24.3.7 PCMCIA Timing ................................................................................................. 647

24.3.8 Peripheral Module Signal Timing........................................................................ 654

24.3.9 H-UDI, AUD Related Pin Timing ....................................................................... 658

24.3.10 A/D Converter Timing......................................................................................... 660

24.3.11 AC Characteristics Measurement Conditions...................................................... 662

24.3.12 Delay Time Variation Due to Load Capacitance................................................. 663

24.4 A/D Converter Characteristics.......................................................................................... 664

24.5 D/A Converter Characteristics.......................................................................................... 664

Appendix.................................................................................................................................. 665

A. Equivalent Circuits of I/O Buffer for Each Pin................................................................. 665

B. Pin Functions .................................................................................................................... 669

B.1 Pin Functions ........................................................................................................... 669

B.2 Pin Specifications .................................................................................................... 673

B.3 Processing of Unused Pins....................................................................................... 677

B.4 Pin States in Access to Each Address Space............................................................ 678

C. Product Lineup.................................................................................................................. 692

D. Package Dimensions......................................................................................................... 693

Index.......................................................................................................................................... 695

Rev. 5.00 May 29, 2006 page xxxiv of xlviii

Figures

Section 1 Overview

Figure 1.1 SH7706 Block Diagram....................................................................................... 3

Figure 1.2 Pin Assignment (FP-176C).................................................................................. 4

Figure 1.3 Pin Assignment (TBP-208A)............................................................................... 5

Section 2 CPU

Figure 2.1 Register Configuration......................................................................................... 14

Figure 2.2 General Registers................................................................................................. 15

Figure 2.3 System Registers.................................................................................................. 16

Figure 2.4 Control Registers ................................................................................................. 17

Figure 2.5 Data Format in Memory....................................................................................... 21

Figure 2.6 Processor State Transitions.................................................................................. 50

Section 3 Memory Management Unit (MMU)

Figure 3.1 MMU Functions................................................................................................... 52

Figure 3.2 Virtual Address Space Mapping .......................................................................... 54

Figure 3.3 Overall Configuration of the TLB ....................................................................... 60

Figure 3.4 Virtual Address and TLB Structure ..................................................................... 61

Figure 3.5 TLB Indexing (IX = 1)......................................................................................... 62

Figure 3.6 TLB Indexing (IX = 0)......................................................................................... 63

Figure 3.7 Objects of Address Comparison .......................................................................... 64

Figure 3.8 Operation of LDTLB Instruction......................................................................... 67

Figure 3.9 Synonym Problem................................................................................................ 69

Figure 3.10 MMU Exception Generation Flowchart............................................................... 74

Figure 3.11 MMU Exception Signals in Instruction Fetch ..................................................... 75

Figure 3.12 MMU Exception Signals in Data Access............................................................. 76

Figure 3.13 Specifying Address and Data for Memory-Mapped TLB Access........................ 78

Section 4 Exception Processing

Figure 4.1 Vector Addresses ................................................................................................. 82

Figure 4.2 Example of Acceptance Order of General Exceptions......................................... 84

Section 5 Cache

Figure 5.1 Cache Structure.................................................................................................... 99

Figure 5.2 Cache Search Scheme (Normal Mode)................................................................ 106

Figure 5.3 Write-Back Buffer Configuration........................................................................ 107

Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access..................... 110

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Section 6 Interrupt Controller (INTC)

Figure 6.1 INTC Block Diagram........................................................................................... 114

Figure 6.2 Example of IRL Interrupt Connection ................................................................. 117

Figure 6.3 Interrupt Operation Flowchart ............................................................................. 134

Figure 6.4 Example of Pipeline Operations when IRL Interrupt Is Accepted....................... 138

Section 7 User Break Controller

Figure 7.1 Block Diagram of User Break Controller ............................................................ 140

Section 8 Bus State Controller (BSC)

Figure 8.1 BSC Functional Block Diagram .......................................................................... 164

Figure 8.2 Corresponding to Logical Address Space and Physical Address Space.............. 167

Figure 8.3 Physical Space Allocation.................................................................................... 169

Figure 8.4 PCMCIA Space Allocation.................................................................................. 170

Figure 8.5 Basic Timing of Basic Interface........................................................................... 206

Figure 8.6 Example of 32-Bit Data-Width Static RAM Connection..................................... 207

Figure 8.7 Example of 16-Bit Data-Width Static RAM Connection..................................... 208

Figure 8.8 Example of 8-Bit Data-Width Static RAM Connection....................................... 208

Figure 8.9 Basic Interface Wait Timing (Software Wait Only) ............................................ 209

Figure 8.10 Basic Interface Wait State Timing

(Wait State Insertion by WAIT Signal WAITSEL = 1)....................................... 210

Figure 8.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)....... 212

Figure 8.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width) .......................... 213

Figure 8.13 Basic Timing for Synchronous DRAM Burst Read............................................. 216

Figure 8.14 Synchronous DRAM Burst Read Wait Specification Timing.............................. 217

Figure 8.15 Basic Timing for Synchronous DRAM Single Read........................................... 218

Figure 8.16 Basic Timing for Synchronous DRAM Burst Write............................................ 219

Figure 8.17 Basic Timing for Synchronous DRAM Single Write.......................................... 220

Figure 8.18 Burst Read Timing (No Precharge) ..................................................................... 223

Figure 8.19 Burst Read Timing (Same Row Address)............................................................ 224

Figure 8.20 Burst Read Timing (Different Row Addresses)................................................... 225

Figure 8.21 Burst Write Timing (No Precharge)..................................................................... 226

Figure 8.22 Burst Write Timing (Same Row Address)........................................................... 227

Figure 8.23 Burst Write Timing (Different Row Addresses).................................................. 228

Figure 8.24 Auto-Refresh Operation....................................................................................... 229

Figure 8.25 Synchronous DRAM Auto-Refresh Timing ........................................................ 230

Figure 8.26 Synchronous DRAM Self-Refresh Timing.......................................................... 231

Figure 8.27 Synchronous DRAM Mode Write Timing........................................................... 233

Figure 8.28 Burst ROM Wait Access Timing......................................................................... 235

Figure 8.29 Burst ROM Basic Access Timing........................................................................ 236

Figure 8.30 PCMCIA Space Allocation.................................................................................. 237

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Figure 8.31 Example of PCMCIA Interface............................................................................ 238

Figure 8.32 Basic Timing for PCMCIA Memory Card Interface ........................................... 239

Figure 8.33 Wait Timing for PCMCIA Memory Card Interface............................................. 240

Figure 8.34 Basic Timing for PCMCIA Memory Card Interface Burst Access...................... 241

Figure 8.35 Wait Timing for PCMCIA Memory Card Interface Burst Access....................... 242

Figure 8.36 Basic Timing for PCMCIA I/O Card Interface.................................................... 244

Figure 8.37 Wait Timing for PCMCIA I/O Card Interface..................................................... 245

Figure 8.38 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface............................ 246

Figure 8.39 Waits between Access Cycles.............................................................................. 248

Figure 8.40 Pins A25 to A0 Pull-Up Timing .......................................................................... 249

Figure 8.41 Pins D31 to D0 Pull-Up Timing (Read Cycle) .................................................... 250

Figure 8.42 Pins D31 to D0 Pull-Up Timing (Write Cycle).................................................... 250

Section 9 Direct Memory Access Controller (DMAC)

Figure 9.1 DMAC Block Diagram........................................................................................ 253

Figure 9.2 DMAC Transfer Flowchart.................................................................................. 266

Figure 9.3 Round-Robin Mode ............................................................................................. 270

Figure 9.4 Changes in Channel Priority in Round-Robin Mode ........................................... 271

Figure 9.5 Operation in the Direct Address Mode in the Dual Address Mode ..................... 273

Figure 9.6 Example of DMA Transfer Timing in the Direct Address Mode in the Dual

Address Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary

Memory).............................................................................................................. 274

Figure 9.7 Example of DMA Transfer Timing in the Direct Address Mode in the Dual

Address Mode (16-Byte Transfer, Transfer Source: Ordinary Memory,

Transfer Destination: Ordinary Memory)............................................................ 275

Figure 9.8 Example of DMA Transfer Timing in the Direct Address Mode in the Dual

Address Mode (16-Byte Transfer, Transfer Source: Synchronous DRAM,

Transfer Destination: Ordinary Memory)............................................................ 275

Figure 9.9 Operation in the Indirect Address mode in the Dual Address Mode

(When the External Memory Space Has a 16-Bit Width).................................... 277

Figure 9.10 Example of Transfer Timing in the Indirect Address Mode

in the Dual Address Mode ................................................................................... 278

Figure 9.11 Data Flow in the Single Address Mode............................................................... 279

Figure 9.12 Example of DMA Transfer Timing in the Single Address Mode........................ 280

Figure 9.13 Example of DMA Transfer Timing in the Single Address Mode

(16-Byte Transfer, External Memory Space (Ordinary Memory)

→ External

Device with DACK) ............................................................................................ 281

Figure 9.14 DMA Transfer Example in the Cycle-Steal Mode............................................... 282

Figure 9.15 DMA Transfer Example in the Burst Mode......................................................... 282

Figure 9.16 Bus State when Multiple Chan nels Are Operating

(Priority Level Is Round-Robin Mode)................................................................ 284

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Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)..................................... 286

Figure 9.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)..................................... 286

Figure 9.19 Cycle-Steal Mode, Level input

(CPU Access: 2 Cycles, DMA RD Access: 4 Cycles)......................................... 286

Figure 9.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) 287

Figure 9.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)...................................... 287

Figure 9.22 Burst Mode, Level Input...................................................................................... 287

Figure 9.23 Burst Mode, Edge Input....................................................................................... 288

Figure 9.24 Source Address Reload Function Diagram.......................................................... 288

Figure 9.25 Timing Chart of Source Address Reload Function.............................................. 289

Figure 9.26 CMT Block Diagram ........................................................................................... 292

Figure 9.27 Counter Operation................................................................................................ 295

Figure 9.28 Count Timing....................................................................................................... 296

Figure 9.29 CMF Set Timing.................................................................................................. 297

Figure 9.30 Timing of CMF Clear by the CPU....................................................................... 297

Section 10 Clock Pulse Generator (CPG)

Figure 10.1 Block Diagram of Clock Pulse Generator............................................................ 304

Figure 10.2 Points for Attention when Using Crystal Oscillator............................................. 313

Figure 10.3 Points for Attention when Using PLL Oscillator Circuit..................................... 314

Section 11 Watchdog Timer (WDT)

Figure 11.1 Block Diagram of the WDT................................................................................. 315

Figure 11.2 Writing to WTCNT and WTCSR........................................................................ 319

Section 12 Timer Unit (TMU)

Figure 12.1 TMU Block Diagram........................................................................................... 324

Figure 12.2 Setting the Count Operation................................................................................. 333

Figure 12.3 Auto-Reload Count Operation............................................................................. 334

Figure 12.4 Count Timing when Internal Clock Is Operating................................................. 334

Figure 12.5 Count Timing when External Clock Is Operating (Both Edges Detected)........... 335

Figure 12.6 Count Timing when On-Chip RTC Clock Is Operating ...................................... 335

Figure 12.7 Operation Timing when Using the Input Capture Function

(Using TCLK Rising Edge)................................................................................. 336

Figure 12.8 UNF Set Timing................................................................................................... 337

Figure 12.9 Status Flag Clear Timing..................................................................................... 337

Section 13 Realtime Clock (RTC)

Figure 13.1 RTC Block Diagram............................................................................................ 340

Figure 13.2(a) Setting the Time................................................................................................... 357

Figure 13.2(b) Setting the Time................................................................................................... 357

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Figure 13.3 Reading the Time................................................................................................. 358

Figure 13.4 Using the Alarm Function.................................................................................... 359

Figure 13.5 Example of Crystal Oscillator Circuit Connection .............................................. 360

Figure 13.6 Using Periodic Interrupt Function........................................................................ 361

Section 14 Serial Communication Interface (SCI)

Figure 14.1 SCI Block Diagram.............................................................................................. 364

Figure 14.2 SCPT[1]/SCK0 Pin.............................................................................................. 365

Figure 14.3 SCPT[0]/TxD0 Pin............................................................................................... 366

Figure 14.4 SCPT[0]/RxD0 Pin.............................................................................................. 366

Figure 14.5 Data Format in Asynchronous Communication................................................... 392

Figure 14.6 Output Clock and Serial Data Timing (Asynchronous Mode)............................. 394

Figure 14.7 Sample Flowchart for SCI Initialization.............................................................. 395

Figure 14.8 Sample Flowchart for Transmitting Serial Data .................................................. 396

Figure 14.9 SCI Transmit Operation in Asynchronous Mode................................................. 398

Figure 14.10 Sample Flowchart for Receiving Serial Data....................................................... 399

Figure 14.11 SCI Receive Operation ........................................................................................ 402

Figure 14.12 Communication Among Processors Using Multiprocessor Format..................... 403

Figure 14.13 Sample Flowchart for Transmitting Multiprocessor Serial Data ......................... 404

Figure 14.14 SCI Multiprocessor Transmit Operation.............................................................. 406

Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data.............................. 407

Figure 14.16 Example of SCI Receive Operation..................................................................... 409

Figure 14.17 Data Format in Clock Synchronous Communication .......................................... 410

Figure 14.18 Sample Flowchart for SCI Initialization .............................................................. 411

Figure 14.19 Sample Flowchart for Serial Transmitting........................................................... 412

Figure 14.20 Example of SCI Transmit Operation ................................................................... 413

Figure 14.21 Sample Flowchart for Serial Data Receiving....................................................... 414

Figure 14.22 Example of SCI Receive Operation..................................................................... 415

Figure 14.23 Sample Flowchart for Serial Data Transmitting/Receiving ................................. 416

Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode..................................... 419

Section 15 Smart Card Interface

Figure 15.1 Smart Card Interface Block Diagram................................................................... 422

Figure 15.2 Pin Connection Diagram for the Smart Card Interface........................................ 428

Figure 15.3 Data Format for Smart Card Interface ................................................................. 428

Figure 15.4 Waveform of Start Character............................................................................... 430

Figure 15.5 Initialization Flowchart (Example)...................................................................... 434

Figure 15.6 Transmission Flowchart....................................................................................... 435

Figure 15.7 Reception Flowchart (Example) .......................................................................... 436

Figure 15.8 Receive Data Sampling Timing in Smart Card Mode.......................................... 438

Figure 15.9 Retransmission in SCI Receive Mode.................................................................. 439

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Figure 15.10 Retransmission in SCI Transmit Mode................................................................ 440

Section 16 Serial Communication Interface with FIFO (SCIF)

Figure 16.1 SCIF Block Diagram............................................................................................ 442

Figure 16.2 SCPT[3]/SCK2 Pin.............................................................................................. 443

Figure 16.3 SCPT[2]/TxD2 Pin............................................................................................... 444

Figure 16.4 SCPT[2]/RxD2 Pin.............................................................................................. 444

Figure 16.5 Sample SCIF Initialization Flowchart.................................................................. 472

Figure 16.6 Sample Serial Transmission Flowchart................................................................ 473

Figure 16.7 Example of Transmit Operation (Example with 8-Bit Data, Parity,

One Stop Bit)....................................................................................................... 475

Figure 16.8 Example of Operation Using Modem Control (CTS2)........................................ 475

Figure 16.9 Sample Serial Reception Flowchart (1)............................................................... 476

Figure 16.10 Sample Serial Reception Flowchart (2) ............................................................... 477

Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity,

One Stop Bit)....................................................................................................... 479

Figure 16.12 Example of Operation Using Modem Control (RTS2)........................................ 479

Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode..................................... 482

Section 18 I/O Ports

Figure 18.1 Port A................................................................................................................... 507

Figure 18.2 Port B................................................................................................................... 509

Figure 18.3 Port C................................................................................................................... 511

Figure 18.4 Port D................................................................................................................... 513

Figure 18.5 Port E................................................................................................................... 515

Figure 18.6 Port F ................................................................................................................... 517

Figure 18.7 Port G................................................................................................................... 519

Figure 18.8 Port H................................................................................................................... 521

Figure 18.9 Port J.................................................................................................................... 523

Figure 18.10 SC Port................................................................................................................. 525

Section 19 A/D Converter (ADC)

Figure 19.1 A/D Converter Block Diagram............................................................................ 530

Figure 19.2 A/D Data Register Access Operation (Reading H'AA40) ................................... 537

Figure 19.3 Word Access Example......................................................................................... 538

Figure 19.4 Longword Access Example................................................................................. 538

Figure 19.5 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)......... 540

Figure 19.6 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2

Selected)............................................................................................................... 541

Figure 19.7 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2

Selected)............................................................................................................... 543

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Figure 19.8 A/D Conversion Timing...................................................................................... 544

Figure 19.9 External Trigger Input Timing............................................................................. 545

Figure 19.10 Definitions of A/D Conversion Accuracy............................................................ 546

Figure 19.11 Example of Analog Input Protection Circuit ....................................................... 547

Figure 19.12 Analog Input Pin Equivalent Circuit.................................................................... 547

Section 20 D/A Converter (DAC)

Figure 20.1 D/A Converter Block Diagram............................................................................ 549

Figure 20.2 Example of D/A Converter Operation ................................................................. 552

Section 21 User Debugging Interface (H-UDI)

Figure 21.1 H-UDI Block Diagram......................................................................................... 553

Figure 21.2 TAP Controller State Transitions......................................................................... 561

Figure 21.3 H-UDI Reset........................................................................................................ 563

Section 22 Power-Down Modes

Figure 22.1 Canceling Software Standby Mode with STBCR.STBY..................................... 575

Figure 22.2 Power-On Reset STATUS Output....................................................................... 578

Figure 22.3 Manual Reset STATUS Output ........................................................................... 578

Figure 22.4 Software Standby to Interrupt STATUS Output.................................................. 579

Figure 22.5 Software Standby to Power-On Reset STATUS Output...................................... 579

Figure 22.6 Software Standby to Manual Reset STATUS Output.......................................... 580

Figure 22.7 Sleep to Interrupt STATUS Output ..................................................................... 580

Figure 22.8 Sleep to Power-On Reset STATUS Output......................................................... 581

Figure 22.9 Sleep to Manual Reset STATUS Output ............................................................. 581

Figure 22.10 Hardware Standby Mode (When CA Goes Low in Normal Operation).............. 583

Figure 22.11 Hardware Standby Mode Timing (When CA Goes Low during WDT

Operation on Standby Mode Cancellation).......................................................... 584

Section 24 Electrical Characteristics

Power-On Sequence..................................................................................................................... 608

Figure 24.1 EXTAL Clock Input Timing................................................................................ 614

Figure 24.2 CKIO Clock Input Timing................................................................................... 614

Figure 24.3 CKIO Clock Output Timing ................................................................................ 614

Figure 24.4 Power-On Oscillation Settling Time.................................................................... 615

Figure 24.5 Oscillation Settling Time at Standby Return (Return by Reset).......................... 615

Figure 24.6 Oscillation Settling Time at Standby Return (Return by NMI)........................... 616

Figure 24.7 Oscillation Settling Time at Standby Return (Return by IRQ or IRL)................. 616

Figure 24.8 PLL Synchronization Settling Tim e by Reset o r NMI at the Returning

from Standby Mode (Return by Reset or NMI)................................................... 617

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Figure 24.9 PLL Synchronization Settling Time at th e Returning from Standby Mode

(Return by IRQ/IRL Interrupt)............................................................................. 617

Figure 24.10 PLL Synchronization Settling Time when Freque ncy Multiplication

Rate Modified...................................................................................................... 618

Figure 24.11 Reset Input Timing .............................................................................................. 620

Figure 24.12 Interrupt Signal Input Timing .............................................................................. 620

Figure 24.13 IRQOUT Timing.................................................................................................. 620

Figure 24.14 Bus Release Timing............................................................................................. 621

Figure 24.15 Pin Drive Timing at Standby ............................................................................... 621

Figure 24.16 Basic Bus Cycle (No Wait).................................................................................. 624

Figure 24.17 Basic Bus Cycle (One Wait)................................................................................ 625

Figure 24.18 Basic Bus Cycle (External Wait) ......................................................................... 626

Figure 24.19 Burst ROM Bus Cycle (No Wait)........................................................................ 627

Figure 24.20 Burst ROM Bus Cycle (Two Waits).................................................................... 628

Figure 24.21 Burst ROM Bus Cycle (External Wait) ............................................................... 629

Figure 24.22 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0).. 630
Figure 24.23 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1).. 631
Figure 24.24 Synchronous DRAM Read Bus Cycle

(Burst Read (Single Read × 4), RCD = 0, CAS Latency = 1, TPC = 1) .............. 632

Figure 24.25 Synchronous DRAM Read Bus Cycle

(Burst Read (Single Read × 4), RCD = 1, CAS Latency = 3, TPC = 0) .............. 633

Figure 24.26 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0) ........... 634

Figure 24.27 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1) ........... 635

Figure 24.28 Synchronous DRAM Write Bus Cycle

(Burst Mode (Single Write × 4), RCD = 0, TPC = 1, TRWL = 0)....................... 636

Figure 24.29 Synchronous DRAM Write Bus Cycle

(Burst Mode (Single Write × 4), RCD = 1, TPC = 0, TRWL = 0)....................... 637

Figure 24.30 Synchronous DRAM Burst Read Bus Cycle

(RAS Down, Same Row Address, CAS Latency = 1)......................................... 638

Figure 24.31 Synchronous DRAM Burst Read Bus Cycle

(RAS Down, Same Row Address, CAS Latency = 2)......................................... 639

Figure 24.32 Synchronous DRAM Burst Read Bus Cycle

(RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1).... 640

Figure 24.33 Synchronous DRAM Burst Read Bus Cycle

(RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1).... 641

Figure 24.34 Synchronous DRAM Burst Write Bus Cycle

(RAS Down, Same Row Address)....................................................................... 642

Figure 24.35 Synchronous DRAM Burst Write Bus Cycle

(RAS Down, Different Row Address, TPC = 0, RCD = 0)................................. 643

Figure 24.36 Synchronous DRAM Burst Write Bus Cycle

(RAS Down, Different Row Address, TPC = 1, RCD = 1)................................. 644

Rev. 5.00 May 29, 2006 page xlii of xlviii

Figure 24.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1)..................... 645

Figure 24.38 Synchronous DRAM Self-Refresh Cycle (TPC = 0) ........................................... 645

Figure 24.39 Synchronous DRAM Mode Register Write Cycle............................................... 646

Figure 24.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait)............................. 647

Figure 24.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait)... 648

Figure 24.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait)......... 649

Figure 24.43 PCMCIA Memory Bus Cycle

(Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3)............................ 650

Figure 24.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait) ..................................... 651

Figure 24.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) ........... 652

Figure 24.46 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing) ................ 653

Figure 24.47 TCLK Input Timing............................................................................................. 655

Figure 24.48 TCLK Clock Input Timing .................................................................................. 655

Figure 24.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on........................... 655

Figure 24.50 SCK Input Clock Timing..................................................................................... 655

Figure 24.51 SCI I/O Timing in Clock Synchronous Mode...................................................... 656

Figure 24.52 I/O Port Timing.................................................................................................... 656

Figure 24.53 DREQ Input Timing ............................................................................................ 657

Figure 24.54 DRAK Output Timing ......................................................................................... 657

Figure 24.55 TCK Input Timing ............................................................................................... 658

Figure 24.56 TRST Input Timing (Reset Hold)........................................................................ 659

Figure 24.57 H-UDI Data Transfer Timing .............................................................................. 659

Figure 24.58 ASEMD0 Input Timing ....................................................................................... 659

Figure 24.59 AUD Timing........................................................................................................ 660

Figure 24.60 External Trigger Input Timing............................................................................. 661

Figure 24.61 A/D Conversion Timing ...................................................................................... 661

Figure 24.62 Output Load Circuit............................................................................................. 662

Figure 24.63 Load Capacitance vs. Delay Time ....................................................................... 663

Appendix

Figure D.1 Package Dimensions (FP-176C).......................................................................... 693

Figure D.2 Package Dimensions (TBP-208A)....................................................................... 694

Rev. 5.00 May 29, 2006 page xliii of xlviii

Tables

Section 2 CPU

Table 2.1 Initial Register Values............................................................................................ 15

Table 2.2 Addressing Modes and Effective Addresses.......................................................... 23

Table 2.3 Instruction Formats ................................................................................................ 27

Table 2.4 Classification of Instructions .................................................................................. 30

Table 2.5 Data Transfer Instructions...................................................................................... 34

Table 2.6 Arithmetic Instructions........................................................................................... 36

Table 2.7 Logic Operation Instructions.................................................................................. 39

Table 2.8 Shift Instructions.................................................................................................... 40

Table 2.9 Branch Instructions ................................................................................................ 41

Table 2.10 System Control Instructions................................................................................... 42

Table 2.11 Instruction Code Map............................................................................................. 46

Section 3 Memory Management Unit (MMU)

Table 3.1 Access States Designated by D, C, and PR Bits..................................................... 65

Section 4 Exception Processing

Table 4.1 Exception Event Vectors........................................................................................ 82

Table 4.2 Exception Codes..................................................................................................... 85

Table 4.3 Types of Reset........................................................................................................ 92

Section 5 Cache

Table 5.1 LRU and Way Replacement................................................................................... 100

Table 5.2 Way to be Replaced when Cache Miss Occurs during PREF Instruction

Execution................................................................................................................ 103

Table 5.3 Way to be Replaced when Cache Miss Occurs during Execution of Instruction

Other than PREF Instruction.................................................................................. 104

Table 5.4 LRU and Way Replacement (When W2LOCK = 1).............................................. 104

Table 5.5 LRU and Way Replacement (When W3LOCK = 1).............................................. 104

Table 5.6 LRU and Way Replacement (When W2LOCK = 1 and W3LOCK = 1) ............... 104

Section 6 Interrupt Controller (INTC)

Table 6.1 Pin Configuration................................................................................................... 115

Table 6.2 IRL3 to IRL0 Pins and Interrupt Levels................................................................. 117

Table 6.3 Interrupt Exception Handling Sources and Priority (IRQ Mode)........................... 119

Table 6.4 Interrupt Exception Handling Sources and Priority (IRL Mode)........................... 121

Table 6.5 Interrupt Level and INTEVT Code ........................................................................ 123

Table 6.6 Interrupt Request Sources and IPRA to IPRE........................................................ 124

Rev. 5.00 May 29, 2006 page xliv of xlviii

Table 6.7 Interrupt Response Time........................................................................................ 136

Section 7 User Break Controller

Table 7.1 Data Access Cycle Addresses and Operand Size Comparison Conditions............ 154

Section 8 Bus State Controller (BSC)

Table 8.1 Pin Configuration................................................................................................... 165

Table 8.2 Physical Address Space Map ................................................................................. 168

Table 8.3 Correspondence between External Pins (MD4 and MD3) and Memory Size........ 169

Table 8.4 PCMCIA Interface Characteristics......................................................................... 170

Table 8.5 PCMCIA Support Interface.................................................................................... 171

Table 8.6 Area 6 Wait Control (Normal Memory I/F)........................................................... 184

Table 8.7 Area 5 Wait Control (Normal Memory I/F)........................................................... 184

Table 8.8 Area 4 Wait Control............................................................................................... 185

Table 8.9 Area 0 Wait Control............................................................................................... 185

Table 8.10 Area 6 Wait Control (PCMCIA I/F)....................................................................... 192

Table 8.11 32-Bit External Device/Big Endian Access and Data Alignment .......................... 198

Table 8.12 16-Bit External Device/Big Endian Access and Data Alignment .......................... 198

Table 8.13 8-Bit External Device/Big Endian Access and Data Alignment ............................ 199

Table 8.14 32-Bit External Device/Little Endian Access and Data Alignment ....................... 200

Table 8.15 16-Bit External Device/Little Endian Access and Data Alignment ....................... 200

Table 8.16 8-Bit External Device/Little Endian Access and Data Alignment ......................... 201

Table 8.17 Relationship between Bus Width, AMX, and Address Multiplex Output.............. 214

Table 8.18 Example of Correspondence between this LSI and Synchronous DRAM

Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width))..................................... 215

Section 9 Direct Memory Access Controller (DMAC)

Table 9.1 Pin Configuration................................................................................................... 254

Table 9.2 Selecting External Request Modes with the RS Bits.............................................. 267

Table 9.3 Selecting On-Chip Peripheral Module Request Modes with the RS Bit................ 268

Table 9.4 Supported DMA Transfers..................................................................................... 272

Table 9.5 Relationship of Request Modes and Bus Modes by DMA Transfer Category....... 283

Table 9.6 Transfer Conditions and Register Settings for Transfer between On-Chip A/D

Converter and External Memory............................................................................ 298

Table 9.7 Values in the DMAC after the Fourth Transfer Ends............................................. 299

Table 9.8 Transfer Conditions and Register Settings for Transfer between External

Memory and SCIF Transmitter .............................................................................. 300

Section 10 Clock Pulse Generator (CPG)

Table 10.1 Clock Pulse Generator Pins and Functions............................................................. 306

Table 10.2 Clock Operating Modes.......................................................................................... 307

Rev. 5.00 May 29, 2006 page xlv of xlviii

Table 10.3 Available Combination of Clock Mode and FRQCR Values................................. 308

Section 12 Timer Unit (TMU)

Table 12.1 Pin Configuration................................................................................................... 325

Table 12.2 TMU Interrupt Sources .......................................................................................... 338

Section 13 Realtime Clock (RTC)

Table 13.1 RTC Pin Configuration .......................................................................................... 341

Table 13.2 Recommended Oscillator Circuit Constants (Recommended Values)................... 360

Section 14 Serial Communication Interface (SCI)

Table 14.1 SCI Pins 367

Table 14.2 SCSMR Settings..................................................................................................... 383

Table 14.3 Bit Rates and SCBRR Settings in Asynchronous Mode........................................ 384

Table 14.4 Bit Rates and SCBRR Settings in Clock Synchronous Mode................................ 387

Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

(Asynchronous Mode)............................................................................................ 388

Table 14.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode)............. 389

Table 14.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)..... 389

Table 14.8 Serial Mode Register Settings and SCI Communication Formats.......................... 391

Table 14.9 SCSMR and SCSCR Settings and SCI Clock Source Selection ............................ 391

Table 14.10 Serial Communication Formats (Asynchronous Mode)......................................... 393

Table 14.11 Receive Error Conditions and SCI Operation ........................................................ 401

Table 14.12 SCI Interrupt Sources............................................................................................. 417

Table 14.13 SCSSR Status Flags and Transfer of Receive Data................................................ 418

Section 15 Smart Card Interface

Table 15.1 Pin Configuration................................................................................................... 423

Table 15.2 Register Settings for the Smart Card Interface....................................................... 429

Table 15.3 Relationship of n to CKS1 and CKS0.................................................................... 431

Table 15.4 Examples of Bit Rate B (Bit/s) f or SCBRR Settings (n = 0).................................. 431

Table 15.5 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0).................................. 432

Table 15.6 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) ...................... 432

Table 15.7 Register Set Values and SCKφ Pin......................................................................... 433

Table 15.8 Smart Card Mode Operating State and Interrupt Sources ...................................... 437

Section 16 Serial Communication Interface with FIFO (SCIF)

Table 16.1 SCIF Pins................................................................................................................ 445

Table 16.2 SCSMR2 Settings................................................................................................... 460

Table 16.3 Bit Rates and SCBRR2 Settings............................................................................. 461

Rev. 5.00 May 29, 2006 page xlvi of xlviii

Table 16.4 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

(Asynchronous Mode)............................................................................................ 465

Table 16.5 Maximum Bit Rates during External Clock Input (Asynchronous Mode)............. 465

Table 16.6 SCSMR2 Settings and SCIF Communication Formats.......................................... 469

Table 16.7 SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection....................... 470

Table 16.8 Serial Communication Formats.............................................................................. 470

Table 16.9 SCIF Interrupt Sources........................................................................................... 480

Section 17 Pin Function Controller (PFC)

Table 17.1 List of Multiplexed Pins......................................................................................... 485

Section 18 I/O Ports

Table 18.1 Read/Write Operation of the Port A Data Register (PADR).................................. 508

Table 18.2 Read/Write Operation of the Port B Data Register (PBDR) ................................. 510

Table 18.3 Read/Write Operation of the Port C Data Register (PCDR) .................................. 512

Table 18.4 Read/Write Operation of the Port D Data Register (PDDR)................................. 514

Table 18.5 Read/Write Operation of the Port E Data Register (PEDR)................................... 516

Table 18.6 Read/Write Operation of the Port F Data Register (PFDR) ................................... 518

Table 18.7 Read/Write Operation of the Port G Data Register (PGDR).................................. 520

Table 18.8 Read/Write Operation of the Port H Data Register (PHDR).................................. 522

Table 18.9 Read/Write Operation of the Port J Data Register (PJDR)..................................... 524

Table 18.10 Read/Write Operation of the SC Port Data Register (SCPDR).............................. 527

Section 19 A/D Converter (ADC)

Table 19.1 A/D Converter Pins................................................................................................ 531

Table 19.2 Analog Input Channels and A/D Data Registers.................................................... 532

Table 19.3 A/D Conversion Time (Single Mode).................................................................... 544

Table 19.4 Analog Input Pin Ratings ....................................................................................... 547

Table 19.5 Relationship between Access Size and Read Data................................................. 548

Section 20 D/A Converter (DAC)

Table 20.1 D/A Converter Pins................................................................................................ 550

Section 21 User Debugging Interface (H-UDI)

Table 21.1 Pin Configuraiton................................................................................................... 554

Table 21.2 This LSI's Pins and Boundary Scan Register Bits.................................................. 556

Table 21.3 Reset Configuration................................................................................................ 562

Section 22 Power-Down Modes

Table 22.1 Power-Down Modes............................................................................................... 568

Table 22.2 Pin Configuration................................................................................................... 569

Rev. 5.00 May 29, 2006 page xlvii of xlviii

Table 22.3 Register States in Software Standby Mode............................................................ 574

Section 24 Electrical Characteristics

Table 24.1 Absolute Maximum Ratings................................................................................... 607

Table 24.2 DC Characteristics.................................................................................................. 609

Table 24.3 Permitted Output Current Values........................................................................... 611

Table 24.4 Operating Frequency Range................................................................................... 612

Table 24.5 Clock Timing ......................................................................................................... 612

Table 24.6 Control Signal Timing............................................................................................ 619

Table 24.7 Bus Timing (Clock Modes 0/1/2/7)........................................................................ 622

Table 24.8 Peripheral Module Signal Timing .......................................................................... 654

Table 24.9 H-UDI, AUD Related Pin Timing.......................................................................... 658

Table 24.10 A/D Converter Timing ........................................................................................... 660

Table 24.11 A/D Converter Characteristics ............................................................................... 664

Table 24.12 D/A Converter Characteristics ............................................................................... 664

Appendix

Table B.1 Pin States during Resets, Power-Down States, and Bus-Released State................ 669

Table B.2 Pin Specifications................................................................................................... 673

Table B.3 Pin States (Normal Memory/Little Endian)........................................................... 678

Table B.4 Pin States (Normal Memory/Big Endian) .............................................................. 680

Table B.5 Pin States (Burst ROM/Little Endian).................................................................... 682

Table B.6 Pin States (Burst ROM/Big Endian)....................................................................... 684

Table B.7 Pin States (Synchronous DRAM/Little Endian)..................................................... 686

Table B.8 Pin States (Synchronous DRAM/Big Endian)........................................................ 687

Table B.9 Pin States (PCMCIA/Little Endian)....................................................................... 688

Table B.10 Pin States (PCMCIA/Big Endian).......................................................................... 690

Rev. 5.00 May 29, 2006 page xlviii of xlviii

Section 1 Overview

Section 1 Overview

The SH7706 is a RISC microprocessor that integrates a Renesas Technology-original RISC-type
SuperH™ architecture SH-3 CPU as its core that has peripheral functions required for system
configuration. The CPU of this LSI has upper compatibility with the SH-1 and SH-2 at object code
level. This LSI incorporates a memory management unit (MMU) that has a 128-entry 4-way set
associative translation lookaside buffer (TLB).

The LSI incorporates the following peripheral functions: an on-chip direct memory access
controller (DMAC) that enables high-speed data transfer and a bus state controller (BSC) that
enables direct connection to different types of memory. The LSI also incorporates a serial
communication interface, an A/D converter, a D/A converter, a timer, and a realtime clock that
enable system configuration at low cost.

A built-in power management function enables dynamic control of power consumption. Thus, this
LSI is optimum for portable electronic devices such as PDAs that require both high performance
and low power.

The SH7706 incorporates a user debugging interface (H-UDI) and an advanced user debugger
(AUD) to support emulator functions such as E10A. This LSI also incorporates a user break
controller (UBC) for self debugging.

Note: The SuperH is a trademark of Renesas Technology, Corp.

1.1 Feature

• Original Renesas SuperH architecture

• Object code level compatible with SH-1 , SH- 2 and SH-3

• 32-bit RISC-type instruction set

 Instruction length: 16-bit fix e d length
 Improved code efficiency
 Load-store architecture
 Delayed branch instructions
 Instruction set oriented for C language

• Five-stage pipeline

• Instruction execution time: one instruction/cycle for basic instructions

• General-register: Sixteen 32-bit general registers

• Control-register: Eight 32-bit control registers

• System-register: Four 32-bit system registers

Rev. 5.00 May 29, 2006 page 1 of 698

REJ09B0146-0500

Section 1 Overview

• 32-bit internal data bus

• Logical address space: 4 Gbytes

• Space identifier ASID: 8 bits, 256 logical address space

• Abundant Peripheral Functions
 Memory Management Unit (MMU)
 User Break Controller (UBC)
 Bus state Contro lle r (BSC)
 Direct Memory Access Controller (DMAC)
 Clock Pulse Generator (CPG)
 Watchdog Timer (WDT)
 Timer Unit (TMU)
 Realtime Clock (RTC)
 Serial Communication Interface (SCI)
 Smartcard Interface
 Serial Communication Interface with FIFO (SCIF)
 10-bit A/D converter (ADC)
 8-bit D/A converter (DAC)
 User Debugging Interface (H-UDI)
 Advanced User Debugger (AUD)

Rev. 5.00 May 29, 2006 page 2 of 698
REJ09B0146-0500

1.2 Block Diagram

Section 1 Overview

MMU

TLB

CCN

CACHE

H-UDI

INTC

CPG/WDT

I bus 1I bus 2

BRIDGE

External bus

interface

L bus

CPU

UBC

AUD

BSC

DMAC

CMT

I/O port

SCI

TMU

Peripheral bus 1

RTC

SCIF

ADC

Peripheral bus 2

DAC

Legend:
ADC
AUD
BSC
CACHE
CCN
CMT
CPG/WDT
CPU
DAC

: A/D converter
: Advanced user debugger
: Bus state controller
: Cache memory
: Cache memory controller
: Compare match timer
: Clock pulse generator/watchdog timer
: Central processing unit
: D/A converter

Figure 1.1 SH7706 Block Diagram

DMAC

: Direct memory access controller

H-UDI

: User debugging interface

INTC

: Interrupt controller

MMU

: Memory management unit

RTC

: Realtime clock

SCI

: Serial communication interface (with smart card interface)

SCIF

: Serial communication interface (with FIFO)

TLB

: Address translation buffer

TMU

: Timer unit

UBC

: User break controller

Rev. 5.00 May 29, 2006 page 3 of 698

REJ09B0146-0500

Section 1 Overview

C

1.3 Pin Assignment

- PLL2

- PLL2

SS

CC

SS

CAP2

V

MD1

V

EXTAL

XTAL

V

- PLL1

SS

V

CAP1

- PLL1

CC

V

ASEMD0

ASEBRKAK/PTF[6]

TDO/PTF[5]

TRST/PTG[3]

CC

TMS/PTG[2]

V

TCK/PTG[1]

VSSTDI/PTG[0]

AUDSYNC/PTF[4]

AUDATA[3]/PTF[3]

AUDATA[2]/PTF[2]

AUDATA[1]/PTF[1]

AUDATA[0]/PTF[0]

DRAK1/PTE[3]

DRAK0/PTE[2]

DACK1/PTE[1]

DACK0/PTE[0]

WAIT

BREQ

BACK

IOIS16/PTD[5]

CKE/PTD[4]

CASU/PTD[3]

CASL/PTD[2]

RASU/PTD[1]

Q

CC

RASL/PTD[0]

V

Q

SS

CE2B/PTD[7]

V

CE2A/PTD[6]

CS6/CE1B/PTC[7]

CS5/CE1A/PTC[6]

CS4/PTC[5]

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

Q

SS

D15

V

D17/PTA[1]

D16/PTA[0]

105

Q

CC

D14

V

V

SS

CKIO
VCCQ

V
V

V

SS

NMI

V

CC

MD0
MD2

MD3
MD4
MD5

AV

AV
AV

133
134
135
136
137

Q

138
139
140
141
142
143
144
145
146
147
148

SS

149
150

CC

151
152
153
154
155
156

Q

157
158

Q

159
160
161
162
163
164
165
166

CA

167
168
169
170

SS

171
172

INDEX MARK

173
174
175

CC

176

SS

SH-7706
FP-176C

(Top view)

12345678910111213141516171819202122232425262728293031323334353637383940414243

Q

- RTC

XTAL2

CC

V

- RTC

EXTAL2

SS

V

D31/PTB[7]

D30/PTB[6]

D29/PTB[5]

D28/PTB[4]

SS

V

D25/PTB[1]

D27/PTB[3]

D26/PTB[2]

Q

CC

V

D24/PTB[0]

D23/PTA[7]

D22/PTA[6]

D21/PTA[5]

SS

CC

V

V

D20/PTA[4]

D19/PTA[3]

D18/PTA[2]

STATUS0/PTE[4]
STATUS1/PTE[5]

TCLK/PTE[6]

IRQOUT/PTE[7]

TxD0/SCPT[0]

SCK0/SCPT[1]

TxD2/SCPT[2]
SCK2/SCPT[3]
RTS2/SCPT[4]
RxD0/SCPT[0]
RxD2/SCPT[2]

TS2/IRQ5/SCPT[5]

RESETM

IRQ0/IRL0/PTH[0]
IRQ1/IRL1/PTH[1]
IRQ2/IRL2/PTH[2]
IRQ3/IRL3/PTH[3]

IRQ4/PTH[4]

AUDCK/PTG[4]

DREQ0/PTH[5]
DREQ1/PTH[6]
ADTRG/PTG[5]

RESETP

AN[0]/PTJ[0]

AN[1]/PTJ[1]
AN[2]/DA[1]/PTJ[2]
AN[3]/DA[0]/PTJ[3]

104

D13

103

D12

102

D11

101

D10

100

D9D8D7

9998979695949392919089

Q

Q

D6

D5

D4D3D2D1D0

SS

CC

V

V

88

CS3/PTC[4]

87

CS2/PTC[3]

86

V

Q

CC

85

CS0

84

VSSQ

83

RD/WR

82

WE3/DQMUU/ICIOWR/PTC[2]

81

WE2/DQMUL/ICIORD/PTC[1]

80

WE1/DQMLU/WE

79

WE0/DQMLL

78

RD

77

BS/PTC[0]

76

A25

75

A24

74

A23

73

V

CC

72

A22

71

V

SS

70

A21

69

A20

68

A19

67

A18

66

A17

65

A16

64

A15

63

V

Q

CC

62

A14

61

VSSQ

60

A13

59

A12

58

A11

57

A10

56

A9

55

A8

54

A7

53

A6

52

A5

51

V

Q

CC

50

A4

49

VSSQ

48

A3

47

A2

46

A1

45

A0

44

1.9V V

CC

1.9V GND

3.3V V

CC

3.3V GND

Figure 1.2 Pin Assignment (FP-176C)

Rev. 5.00 May 29, 2006 page 4 of 698
REJ09B0146-0500

Section 1 Overview

ABCDEFGHJKLMNPRTU

17

16

15

14

13

12

11

10

17

16

15

14

13

12

11

SH7706

9

8

7

6

5

4

3

2

TBP-208A
(Top view)

INDEX MARK

10

9

8

7

6

5

4

3

2

1

ABCDEFGHJKLMNPRTU

Note: Section in the dotted lines are perspective view.

Figure 1.3 Pin Assignment (TBP-208A)

Rev. 5.00 May 29, 2006 page 5 of 698

1

REJ09B0146-0500

Section 1 Overview

1.4 Pin Function

Number of Pins
FP-176C TBP-208A Pin Name I/O Description

1

1C3V
2 C2 XTAL2 O On-chip RTC crystal oscillator pin
3 C1 EXTAL2 I On-chip RTC crystal oscillator pin
4D3V
5 F4 D31/PTB[7] I/O Data bus / input/output port B
6 F3 D30/PTB[6] I/O Data bus / input/output port B
7 F2 D29/PTB[5] I/O Data bus / input/output port B
8 F1 D28/PTB[4] I/O Data bus / input/output port B
9 G4 D27/PTB[3] I/O Data bus / input/output port B
10 G3 D26/PTB[2] I/O Data bus / input/output port B
11 G2 VSSQ — Input/output power supply (0 V)
12 G1 D25/PTB[1] I/O Data bus / input/output port B
13 H4 VCCQ — Input/output power supply (3.3 V)
14 H3 D24/PTB[0] I/O Data bus / input/output port B
15 H2 D23/PTA[7] I/O Data bus / input/output port A
16 H1 D22/PTA[6] I/O Data bus / input/output port A
17 J4 D21/PTA[5] I/O Data bus / input/output port A
18 J2 D20/PTA[4] I/O Data bus / input/output port A
19 J1 V
20 J3 D19/PTA[3] I/O Data bus / input/output port A
21 K1 V
22 K2 D18/PTA[2] I/O Data bus / input/output port A
23 K3 D17/PTA[1] I/O Data bus / input/output port A
24 K4 D16/PTA[0] I/O Data bus / input/output port A
25 L1 VSSQ — Input/output power supply (0 V)
26 L2 D15 I/O Data bus
27 L3 VCCQ — Input/output power supply (3.3 V)
28 L4 D14 I/O Data bus
29 M1 D13 I/O Data bus

-RTC

CC

-RTC

SS

SS

CC

*

1

*

— RTC power supply (1.9 V)

— RTC power supply (0 V)

— Internal power supply (0 V)

— Internal power supply (1.9 V)

Rev. 5.00 May 29, 2006 page 6 of 698
REJ09B0146-0500

Section 1 Overview

Number of Pins
FP-176C TBP-208A Pin Name I/O Description

30 M2 D12 I/O Data bus
31 M3 D11 I/O Data bus
32 M4 D10 I/O Data bus
33 N1 D9 I/O Data bus
34 N2 D8 I/O Data bus
35 N3 D7 I/O Data bus
36 N4 D6 I/O Data bus
37 P1 VSSQ — Input/output power supply (0 V)
38 P2 D5 I/O Data bus
39 P3 VCCQ — Input/output power supply (3.3 V)
40 R1 D4 I/O Data bus
41 R2 D3 I/O Data bus
42 P4 D2 I/O Data bus
43 T1 D1 I/O Data bus
44 T2 D0 I/O Data bus
45 U1 A0 O Address bus
46 U2 A1 O Address bus
47 R3 A2 O Address bus
48 T3 A3 O Address bus
49 U3 VSSQ — Input/output power supply (0 V)
50 R4 A4 O Address bus
51 T4 VCCQ — Input/output power supply (3.3 V)
52 U4 A5 O Address bus
53 P5 A6 O Address bus
54 R5 A7 O Address bus
55 T5 A8 O Address bus
56 U5 A9 O Address bus
57 P6 A10 O Address bus
58 R6 A11 O Address bus
59 T6 A12 O Address bus

Rev. 5.00 May 29, 2006 page 7 of 698

REJ09B0146-0500

Section 1 Overview

Number of Pins
FP-176C TBP-208A Pin Name I/O Description

60 U6 A13 O Address bus
61 P7 VSSQ — Input/output power supply (0 V)
62 R7 A14 O Address bus
63 T7 VCCQ — Input/output power supply (3.3 V)
64 U7 A15 O Address bus
65 P8 A16 O Address bus
66 R8 A17 O Address bus
67 T8 A18 O Address bus
68 U8 A19 O Address bus
69 P9 A20 O Address bus
70 T9 A21 O Address bus
71 U9 V

SS

— Internal power supply (0 V)
72 R9 A22 O Address bus
73 U10 V

CC

— Internal power supply (1.9 V)
74 T10 A23 O Address bus
75 P10 A24 O Address bus
76 T11 A25 O Address bus
77 R11 BS/PTC[0] O / I/O Bus cycle start signal /

input/output port C
78 P11 RD O Read strobe
79 U12 WE0/DQMLL O D7 to D0 select signal /

DQM (SDRAM)
80 T12 WE1/DQMLU/WE O D15 to D8 select signal / DQM

(SDRAM) / write strobe (PCMCIA)
81 R12 WE2/DQMUL/

ICIORD/PTC[1]

O / O /
O / I/O

D23 to D16 select signal /

DQM (SDRAM) /

PCMCIA input/output read /

input/output port C
82 P12 WE3/DQMUU/

ICIOWR/PTC[2]

O / O /
O / I/O

D31 to D24 select signal /

DQM (SDRAM) /

PCMCIA input/output write /

input/output port C
83 U13 RD/WR O Read/write

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Section 1 Overview

Number of Pins
FP-176C TBP-208A Pin Name I/O Description

84 R13 VSSQ — Input/output power supply (0 V)
85 P13 CS0 O Chip select 0
86 U14 VCCQ — Input/output power supply (3.3 V)
87 T14 CS2/PTC[3] O / I/O Chip select 2 / input/output port C
88 R14 CS3/PTC[4] O / I/O Chip select 3 / input/output port C
89 U17 CS4/PTC[5] O / I/O Chip select 4 / input/output port C
90 T17 CS5/CE1A/PTC[6] O / O / I/O Chip select 5 / CE1 (area 5

PCMCIA) / input/output port C

91 R15 CS6/CE1B/PTC[7] O / O / I/O Chip select 6 / CE1 (area 6

PCMCIA) / input/output port C

92 R16 CE2A/PTD[6] O / I/O Area 5 PCMCIA CE2 /

input/output port D
93 R17 VSSQ — Input/output power supply (0 V)
94 P15 CE2B/PTD[7] O / I/O Area 6 PCMCIA CE2 /

input/output port D
95 P16 VCCQ — Input/output power supply (3.3 V)
96 P17 RASL/PTD[0] O / I/O Lower 32 Mbytes address RAS

(SDRAM) / input/output port D
97 N14 RASU/PTD[1] O / I/O Upper 32 Mbytes address RAS

(SDRAM) / input/output port D
98 N15 CASL/PTD[2] O / I/O Lower 32 Mbytes address CAS

(SDRAM) / input/output port D
99 N16 CASU/PTD[3] O / I/O Upper 32 Mbytes address CAS

(SDRAM) / input/output port D
100 N17 CKE/PTD[4] O / I/O CK enable (SDRAM) /

input/output port D
101 M14 IOIS16/PTD[5] I / I/O IOIS16 (PCMCIA) / input port D
102 M15 BACK O Bus acknowledge
103 M16 BREQ I Bus request
104 M17 WAIT I Hardware wait request
105 L14 DACK0/PTE[0] O / I/O DMA acknowledge 0 /

input/output port E
106 L15 DACK1/PTE[1] O / I/O DMA acknowledge 1 /

input/output port E

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Section 1 Overview

Number of Pins
FP-176C TBP-208A Pin Name I/O Description

107 L16 DRAK0/PTE[2] O / I/O DMA request acknowledge /

input/output port E

108 L17 DRAK1/PTE[3] O / I/O DMA request acknowledge /

input/output port E
109 K15 AUDATA[0]/PTF[0] I/O AUD data / input/output port F
110 K16 AUDATA[1]/PTF[1] I/O AUD data / input port F
111 K17 AUDATA[2]/PTF[2] I/O AUD data / input/output port F
112 J14 AUDATA[3]/PTF[3] I/O AUD data / input/output port F
113 J16 AUDSYNC/PTF[4] O / I/O AUD synchronous /

input/output port F
114 J17 TDI/PTG[0] I Data input (H-UDI) / input port G
115 J15 V

SS

— Internal power supply (0 V)
116 H17 TCK/PTG[1] I Clock (H-UDI) / input port G
117 H16 V

CC

— Internal power supply (1.9 V)
118 G16 TMS/PTG[2] I Mode select (H-UDI) / input port G
119 G15 TRST/PTG[3] I Reset (H-UDI) / input port G
120 G14 TDO/PTF[5] O / I/O Data output (H-UDI) /

input/output port F

121 F16 ASEBRKAK/PTF[6] O / I/O ASE break acknowledge (H-UDI) /

input/output port F

3

122 F15 ASEMD0
123 E17 VCC-PLL1

*

2

*

I ASE mode (H-UDI)

— PLL1 power supply (1.9 V)
124 E16 CAP1 — P LL1 exter nal cap ac itan ce pin

2

125 E15 VSS-PLL1
126 E14 VSS-PLL2

*

2

*

— PLL1 power supply (0 V)

— PLL2 power supply (0 V)
127 D17 CAP2 — PLL2 external cap ac itan ce pin

2

128 D16 VCC-PLL2

*

— PLL2 power supply (1.9 V)
129 C17 MD1 I Clock mode setting
130 C16 V

SS

— Internal power supply (0 V)
131 B17 XTAL O Clock oscillator pin
132 B16 EXTAL I External clock / crystal oscillator pin

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Section 1 Overview

Number of Pins
FP-176C TBP-208A Pin Name I/O Description

133 A17 STATUS0/PTE[4] O / I/O Processor status /

input/output port E

134 A16 STATUS1/PTE[5] O / I/O Processor status /

input/output port E

135 C15 TCLK/PTE[6] I/O TMU or RTC clock input/output /

input/output port E

136 B15 IRQOUT/PTE[7] O / I/O Interrupt request notification /

input/output port E
137 A15 VSSQ — Input/output power supply (0 V)
138 C14 CKIO I/O System clock input/output
139 B14 VCCQ — Input/output power supply (3.3 V)
140 A14 TxD0/SCPT[0] O SCI transmit data 0 / SC port
141 D13 SCK0/SCPT[1] I/O SCI clock 0 / SC port
142 C13 TxD2/SCPT[2] O SCIF transmit data 2 / SC port
143 B13 SCK2/SCPT[3] I/O SCIF clock 2 / SC port
144 A13 RTS2/SCPT[4] O / I/O SCIF transmit request 2 / SC port
145 D12 RxD0/SCPT[0] I SCI receive data 0 / SC port
146 C12 RxD2/SCPT[2] I SCIF receive data 2 / SC port
147 B12 CTS2/IRQ5/SCPT[5] I SCIF transmit clear / external

interruption request / SC port
148 D11 V

SS

— Internal power supply (0 V)
149 C11 RESETM I Manual reset request
150 B11 V

CC

— Internal power supply (1.9 V)
151 A11 IRQ0/IRL0/PTH[0] I / I / I/O External interrupt request /

input/output port H

152 D10 IRQ1/IRL1/PTH[1] I / I / I/O External interrupt request /

input/output port H

153 C10 IRQ2/IRL2/PTH[2] I / I / I/O External interrupt request /

input/output port H

154 B10 IRQ3/IRL3/PTH[3] I / I / I/O External interrupt request /

input/output port H

155 A10 IRQ4/PTH[4] I / I/O External interrupt request /

input/output port H

156 D9 VSSQ — Input/output power supply (0 V)

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Section 1 Overview

Number of Pins
FP-176C TBP-208A Pin Name I/O Description

157 B9 NMI I Nonmaskable interrupt request
158 A9 VCCQ — Input/output power supply (3.3 V)
159 C9 AUDCK/PTG[4] I AUD clock / input port G
160 A8 DREQ0/PTH[5] I / I/O DMA request / input/output port H
161 B8 DREQ1/PTH[6] I / I/O DMA request / input/output port H
162 C8 ADTRG/PTG[5] I Analog trigger / input port G
163 D8 MD0 I Clock mode setting
164 B7 MD2 I Clock mode setting
165 A6 RESETP I Power-on reset request
166 B6 CA I Chip activate / hardware standby

request
167 C6 MD3 I Area 0 bus width setting
168 D6 MD4 I Area 0 bus width setting
169 A5 MD5 I Endian setting
170 B5 AV

SS

— Analog power supply (0 V)
171 C5 AN[0]/PTJ[0] I A/D converter input / input port J
172 D5 AN[1]/PTJ[1] I A/D converter input / input port J
173 A4 AN[2]/DA[1]/PTJ[2] I / O / I A/D converter input / D/A converter

output / input port J

174 B4 AN[3]/DA[0]/PTJ[3] I / O / I A/D converter input / D/A converter

output / input port J
175 B3 AV
176 B2 AV

CC

SS

— Analog power supply (3.3 V)
— Analog power supply (0 V)

Notes: Except in hardware standby mode, all VCC/VSS pins must be connected to the system power

supply. (Supply power constantly.) In hardware standby mode, power must be supplied at
least to VCC−RTC and VSS−RTC. If power is not supplied to VCC and VSS pins other than

−RTC and VSS−RTC, hold the CA pin low.

V

CC

In the TBP-208A package, the A1, A2, A3, A7, A12, B1, C4, C7, D1, D2, D4, D7, D14, D15,
E1, E2, E3, E4, F14, F17, G17, H14, H15, K14, P14, R10, T13, T15, T16, U11, U15, and
U16 pins must be connected to V

.

SS

1. Must be connected to the power supply even when the RTC is not used.

2. Must be connected to the power supply even when the on-chip PLL circuits are not
used (except in hardware standby mode).

3. Must be high level when the user system is used independently without using the
emulator or H-UDI. When this pin goes low or is open, the RESETP pin may be
masked. (See section 21, User Debugging Interface (H-UDI).)

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Section 2 CPU

Section 2 CPU

2.1 Register Description

2.1.1 Privileged Mode and Banks

Processor Modes: There are two processor modes: user mode and privileged mode. The SH7706

normally operates in user mode, and enters privileged mode when an exception occurs or an
interrupt is accepted. There are three kinds of registers—general registers, system registers, and
control registers—and the registers that can be accessed differ in the two processor modes.

General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to
R7 are banked registers which are switched by a processor mode change. In privileged mode, the
register bank bit (RB) in the status register (SR) defines which banked register set is accessed as
general registers, and which set is accessed only through the load control register (LDC) and store
control register (STC) instructions.

When the RB bit is 1, BANK1 general registers R0_BANK1 to R7_BANK1 and non-banked
general registers R8 to R15 function as the general register set, with BANK0 general registers
R0_BANK0 to R7_BANK0 accessed only by the LDC/STC instructions.

When the RB bit is 0, BANK0 general registers R0_BANK0 to R7_BANK0 and nonbanked
general registers R8 to R15 function as the general register set, with BANK1 general registers
R0_BANK1 to R7_BANK1 accessed only by the LDC/STC instructions. In user mode, the 16
registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked
registers R8 to R15 can be accessed as general registers R0 to R15, and bank 1 general registers
R0_BANK1 to R7_BANK1 cannot be accessed.

Control Registers: Control registers comprise the global base register (GBR) and status register
(SR) which can be accessed in both processor modes, and the saved status register (SSR), saved
program counter (SPC), and vector base register (VBR) which can only be accessed in privileged
mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged
mode.

System Registers: System registers comprise the multiply and accumulate registers
(MACL/MACH), the procedure register (PR), and the program counter (PC). Access to these
registers does not depend on the processor mode.

The register configuration in each mode is shown in figures 2.1.

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Section 2 CPU

Switching between user mode and privileged mode is controlled by the processor mode bit (MD)
in the status register.

31 0

R0_BANK0

R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0

R8

R9
R10
R11
R12
R13
R14
R15

1

2

*

*

2

*

2

*

2

*

2

*

2

*

2

*

2

*

SR

GBR
MACH
MACL

PR

PC

a. User mode register

configuration

31 0

R0_BANK1

R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1

R8

R9
R10
R11
R12
R13
R14
R15

SR

SSR

GBR
MACH
MACL

PR

1

3

*

*

3

*

3

*

3

*

3

*

3

*

3

*

3

*

VBR

PC

SPC

1

4

*

R0_BANK0

R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0

*

4

*

4

*

4

*

4

*

4

*

4

*

4

*

b. Privileged mode
register configuration
(RB = 1)

31 0

R0_BANK0

R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0

R8

R9
R10
R11
R12
R13
R14
R15

SR

SSR

GBR
MACH
MACL

PR

1

4

*

*

4

*

4

*

4

*

4

*

4

*

4

*

4

*

VBR

PC

SPC

1

3

*

*

R0_BANK1

R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1

3

*

3

*

3

*

3

*

3

*

3

*

3

*

c. Privileged mode
register configuration
(RB = 0)

Notes: 1.

R0 functions as an index register in the indexed register-indirect addressing mode and indexed
GBR-indirect addressing mode.

2.

Banked register

3.

Banked register
When the RB bit of the SR register is 1, the register can be accessed for general use. When the
RB bit is 0, it can only be accessed with the LDC/STC instruction.

4.

Banked register
When the RB bit of the SR register is 0, the register can be accessed for general use. When the
RB bit is 1, it can only be accessed with the LDC/STC instruction.

Figure 2.1 Register Configuration

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Section 2 CPU

Register values after a reset are shown in table 2.1.

Table 2.1 Initial Register Values

Type Registers Initial Value*

General registers R0 to R15 Undefined
Control registers

SR MD bit = 1, RB bit = 1, BL bit = 1, I3 to

I0 = 1111 (H'F), reserved bits = 0,

others undefined
GBR, SSR, SPC Undefined
VBR H'00000000
MACH, MACL, PR UndefinedSystem registers
PC H'A0000000

Note: * Initial value is set at power-on-reset or manual-reset.

2.1.2 General Registers

There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked
registers, with a different R0 to R7 register bank (R0_BANK0 to R7_BANK0 or R0_BANK1 to
R7_BANK1) being accessed according to the processor mode. For details, see figure 2.1.

The general register configuration is shown in figure 2.2.

31 0

R0

R1
R2
R3
R4
R5
R6
R7

R10
R11
R12
R13
R14
R15

R8
R9

1

2

*

*

2

*

2

*

2

*

2

*

2

*

2

*

2

*

General Registers

Initialized to undefined by a reset.

Notes:

1. R0 functions as an index register in the indexed
register-indirect addressing mode and indexed
GBR-indirect addressing mode. In some instructions,
only R0 can be used as the source register or
destination register.

2. R0 to R7 are banked registers.
In privileged mode, SR.RB specifies which banked registers are

accessed as general registers (R0_BANK0 to R7_BANK0 or
R0_BANK1 to R7_BANK1).

Figure 2.2 General Registers

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Section 2 CPU

2.1.3 System Registers

System registers can be accessed by the LDS and STS instructions. When an exception occurs, the
contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC
contents are restored to the PC by the RTE instruction used at the end of the exception handling.
There are three system registers, as follows.

• Multiply and accumulate register ( M AC)

• Procedure register (PR)

• Program counter (PC)

The system register configuration is shown in figure 2.3.

Multiply and Accumulate Register (MAC)

31 0

MACH
MACL

Procedure Register (PR)

31 0

PR

Program Counter (PC)

31 0

PC

Figure 2.3 System Registers

1. Multiply and Accumulate Register (MAC)
Multiply and Accumulate register is consist of High e r part r e gister (MACH) and Lower part

register (MACL).
Store the results of multiply-and-accumulate operations.

Initialized to undefined by a reset.

2. Procedure Register (PR)
Stores the return address for exiting a subroutine procedure.
Initialized to undefined by a reset.

3. Program Counter (PC)
Indicates the address four addresses (two instructions) ahead of the currently executing

instruction. Initialized to H'A0000000 by a reset.

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Section 2 CPU

2.1.4 Control Registers

Control registers can be accessed in privileged mode using the LDC and STC instructions. The
GBR register can also be accessed in user mode. There are five control registers, as follows:

• Status register (SR)

• Saved status register (SSR)

• Saved program counter (SPC)

• Global base register (GBR)

• Vector base register (VBR)

The control register configuration is shown in figure 2.4.

Status Register (SR)

31 0

SR

Saved Status Register (SSR)

31 0

SSR

Saved Program Counter (SPC)

31 0

SPC

Global Base Register (GBR)

31 0

GBR

Vector Base Register (VBR)

31 0

VBR

Figure 2.4 Control Registers

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Section 2 CPU

• Status Register (SR)
The information of system status are set in this register.

Bit Bit Name Initial Value R/W Description

31  0RReserved

These bits always read as 0, and the write value
should always be 0.

30 MD 1 R/W Processor operation mode bit

Indicates the processor operation mode.
0: User mode
1: Privileged mode
MD is set to 1 when an exception or interruption

is occurred.

29 RB 1 R/W Register bank bit

Determines the bank of general registers R0 to
R7 used in privileged mode.

1: R0_BANK1 to R7_BANK1 and R8 to R15 are

general registers, and R0_BANK0 to
R7_BANK0 can be accessed by LDC/STC
instructions.

0: R0_BANK0 to R7_BANK0 and R8 to R15 are

general registers, and R0_BANK1 to
R7_BANK1 can be accessed by LDC/STC
instructions.

RB is set to 1 when an exception or interruption
is occurred.

28 BL 1 R/W Block bit

0: Exceptions and interrupts are accepted.
1: Exceptions and interrupts are suppressed.

See section 4, Exception Processing, for
details.

BL is set to 1 when an exception or interruption
is occurred.

27 to 13  All 0 R Reserved

These bits always read as 0, and the write value
should always be 0.

12 C L 0 R/W Cache lock bit

0: Cache look function is disabled.
1: Cache look function is enabled.

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Section 2 CPU

Bit Bit Name Initial Value R/W Description

11, 10  All 0 R Reserved

These bits always read as 0, and the write value

should always be 0.
9
8

7
6
5
4

3, 2  All 0 R Reserved

1S  R/W S bit

0T  R/W T bit

Note: The M, Q, S and T bits can be set or cleared by special instructions in user mode. Their

M
Q

I3
I2
I1
I0

values are undefined after a reset. All other bits can be read or written in privileged mode.




1
1
1
1

R/W
R/W

R/W
R/W
R/W
R/W

M bit

Q bit

Used by the DIV0S/U and DIV1 instructions.

Interrupt mask bits

4-bit field indicating the interrupt request mask

level.

I3 to I0 do not change to the interrupt

acceptance level when an interrupt is occurred.

These bits always read as 0, and the write value

should always be 0.

Used by the MAC instruction.

Used by the MOVT, CMP/cond, TAS, TST, BT,

BF, SETT, CLRT, and DT instructions to

indicate true (1) or false (0).

Used by the ADDV/C, SUBV/C, DIV0U/S, DIV1,

NEGC, SHAR/L, SHLR/L, ROTR/L, and

ROTCR/L instructions to indicate a carry,

borrow, overflow, or underflow.

• Saved Status Register (SSR)

Stores current SR value at time of exception to indicate processor status in return to instruction
stream from exception handler.
Initialized to undefined by a reset.

• Saved Program Counter (SPC)

Stores current PC value at time of exception to indicate return address at completion of
exception handling.
Initialized to undefined by a reset.

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Section 2 CPU

• Global Base Re gister (GBR)

Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is
used for on-chip supporting module register area data transfers and logic operations.
The GBR register can also be accessed in user mode.
Initialized to undefined by a reset.

• Vector Base Register (VBR)

Stores base address of exception handling vector area.
Initialized to H'0000000 by a reset.

2.2 Data Formats

2.2.1 Data Format in Registers

Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits)
or a word (16 bits), the sign is extended to the longword, and stores into the register.

31 0

Longword

2.2.2 Data Format in Memory

Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in
8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is
sign-extended before being stored in a register.

A word operand must be accessed starting from a word boundary (even address of a 2-byte unit:
address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte
unit: address 4n). An address error will result if th is r ule is not observed. A byte operand can be
accessed from any address.

Big-endian or little-endian byte order can be selected for the data format. The endian mode should
be set with the MD5 external pin in a power-on reset. Big-endian mode is selected when the MD5
pin is low, and little-endian when high. The endian mode cannot be changed dynamically. Bit
positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit
longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least
significant bit.

Rev. 5.00 May 29, 2006 page 20 of 698
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The data format in memory is shown in figure 2.5.

Section 2 CPU

Address A
Address A + 4
Address A + 8

Address A + 1 Address A + 3

Address A

23 7

31 015

Byte0 Byte1 Byte2 Byte3

Word0

Longword Longword

Big-endian mode

Word1

Address A + 11

Address A + 10 Address A + 8

Address A + 9Address A + 2

23 7

31 015

Byte3 Byte2 Byte1 Byte0

Word1

Little-endian mode

Word0

Address A + 8
Address A + 4
Address A

Figure 2.5 Data Format in Memory

2.3 Instruction Features

2.3.1 Execution Environment

Data Length: The instruction set is implemented with fixed-length 16-bit wide instructions

executed in a pipelined sequence with single-cycle execution for most instructions. All operations
are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit word, or 32­bit longword units, with byte or word units sign-extended into 32-bit longwords. Literals are sign­extended in arithmetic operations (MOV, ADD, and CMP/EQ instructions) and zero-extended in
logical operations (TST, AND, OR, and XOR instructions).

Load/Store Architecture: The load-store architecture is used, so basic operations are executed by
the registers. Operations requiring memory access are executed in registers following register
loading, except for bit-manipulation operations such as logical AND functions, which are executed
directly in memory.

Delayed Branching: Unconditional branching is implemented as delayed branch operations.
Pipeline disruptions due to branching are minimized by the execution of the instruction following
the delayed branch instruction prior to branching. Conditional branch instructions are of two
kinds, delayed and normal.

BRA TRGET
ADD R1, R0 ; ADD is executed pr ior to branching to TRGET

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Section 2 CPU

T bit: The T bit in the status register (SR) is used to indicate the result of compar e operations, and
is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To
improve processing speed, the T bit logic state is modified only by specific operations. An
example of how the T bit may be used in a sequence of operations is shown below.

ADD #1, R0 ; T bit not modified by ADD o peration
CMP/EQ R1, R0 ; T bit set to 1 when R0 = 0
BT TRGET ; branch taken to TRGET when T bit = 1 (R0 = 0)

Literals: Byte-length literals are inserted directly into the instruction code as immediate data. To
maintain the 16-bit fixed-length instruction code, word or longword literals are stored in a table in
main memory rather than inserted directly into the instruction code. The memory table is accessed
by the MOV instruction using PC-relative addressing with displacement, as follows:

MOV.W @(disp, PC), R0

Absolute Addresses: As with word and longword literals, absolute add r esses must also be stored
in a table in main memory. The value of the absolute address is transfer red to a register and the
operand access is specified by indexed register-indirect addressing, with the absolute address
loaded (like word and longword immediate data) during instruction execution.

16-Bit and 32-Bit Displacements: In the same way, 16-bit and 32-bit displacements also must be
stored in a table in main memory. Exactly like absolute addresses, the displacement value is
transferred to a register and the operand access is specified by indexed register-indirect addressing,
loading the displacement (like word and longword immediate data) during instruction execution.

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2.3.2 Addressing Modes

Addressing modes and effective address calculation methods are shown in table 2.2.

Table 2.2 Addressing Modes and Effective Addresses

Section 2 CPU

Addressing
Mode

Register
direct

Register
indirect

Register
indirect with
post­increment

Register
indirect with
pre­decrement

Instruction
Format Effective Address Calculation Method Calculation Formula

Rn Effective address is register Rn. (Operand

is register Rn contents.)

@Rn Effective address is register Rn contents.

Rn Rn

@Rn+ Effective address is register Rn contents.

A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.

Rn

Rn + 1/2/4

1/2/4

@–Rn Effective address is register Rn contents,

decremented by a constant beforehand:
1 for a byte operand, 2 for a word operand,
4 for a longword operand.

Rn

Rn – 1/2/4

+

–

Rn

Rn – 1/2/4

—

Rn

Rn
After instruction

execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 →

Rn

Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4 →

Rn
(Instruction executed

with Rn after
calculation)

1/2/4

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Section 2 CPU

Addressing
Mode

Register
indirect with
displacement

Indexed
register
indirect

GBR indirect
with
displacement

Instruction
Format Effective Address Calculation Method Calculation Formula

@(disp:4,
Rn)

Effective address is register Rn contents
with 4-bit displacement disp added.
After disp is zero-extended, it is multiplied
by 1 (byte), 2 (word), or 4 (longword),
according to the operand size.

Rn

disp

(zero-extended)

1/2/4

+

×

Rn

+ disp × 1/2/4

@(R0, Rn) Effective address is sum of register Rn and

Byte: Rn + disp
Word: Rn + disp × 2
Longword: Rn + disp ×

4

Rn + R0

R0 contents.

Rn

+

Rn + R0

R0

@(disp:8,
GBR)

Effective address is register GBR contents
with 8-bit displacement disp added.
After disp is zero-extended, it is multiplied
by 1 (byte), 2 (word), or 4 (longword),
according to the operand size.

Byte: GBR + disp
Word: GBR + disp × 2
Longword: GBR + disp

× 4

GBR
disp

(zero-extended)

1/2/4

Indexed
GBR
indirect

@(R0,
GBR)

Effective address is sum of register GBR
and R0 contents.

GBR

R0

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REJ09B0146-0500

+

×

GBR

+ disp × 1/2/4

GBR + R0

+

GBR + R0

Section 2 CPU

Addressing
Mode

PC-relative
with
displacement

Instruction
Format Effective Address Calculation Method Calculation Formula

@(disp:8,
PC)

Effective address is register PC contents
with 8-bit displacement disp added.
After disp is zero-extended, it is multiplied
by 2 (word), or 4 (longword), according to
the operand size. With a longword operand,

Word: PC + disp × 2
Longword:

PC & H'FFFF FFFC +
disp × 4

the lower 2 bits of PC are masked.

PC

(for longword)

&

H'FFFFFFFC

+

disp

(zero-extended)

x

2/4

disp:8 Effective address is register PC contents

PC + disp × 2

or

PC&H'FFFFFFFC

+ disp × 4

PC + disp × 2PC-relative
with 8-bit displacement disp added after
being sign-extended and multiplied by 2.

PC

disp

(sign-extended)

+

PC + disp × 2

×

2

disp:12 Effective address is register PC contents

with 12-bit displacement disp added after
being sign-extended and multiplied by 2.

PC
disp

(sign-extended)

2

+

PC + disp × 2

×

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PC + disp × 2

REJ09B0146-0500

Section 2 CPU

Addressing
Mode

PC-relative Rn Effective address is sum of register PC and

Instruction
Format Effective Address Calculation Method Calculation Formula

PC + Rn

Rn contents.

PC

Immediate

+

R0

#imm:8 8-bit immediate data imm of TST, AND, OR,

PC + R0

—

or XOR instruction is zero-extended.

#imm:8 8-bit immediate data imm of MOV, ADD,

—

or CMP/EQ instruction is sign-extended.

#imm:8 8-bit immediate data imm of TRAPA

—
instruction is zero-extend ed and mult iplied
by 4.

Note: For the addressing modes below that use a displacement (disp), the assembler descriptions

in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the
operand size. This is done to clarify the operation of the LSI. Refer to the relevant
assembler notation rules for the actual assembler descriptions.

@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, Rn) ; GBR indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12 ; PC-relative

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Section 2 CPU

2.3.3 Instruction Formats

Table 2.3 explains the meaning of instruction formats and source and destination operands. The
meaning of the operands depends on the operation code. The following symbols are used.

xxxx: Operation code
mmmm: Source register
nnnn: Destination register
iiii: I mmediate data
dddd: Displacement

Table 2.3 Instruction Formats

Instruction Format

0 format

n format

m
format

15 0

xxxx xxxx xxxxxxxx

15 0

xxxx xxxx xxxxnnnn

15 0

xxxx xxxx

mmmm

xxxx

Source
Operand

——NOP

— nnnn: regi ster

Control register or
system register

Control register or
system register

mmmm: register
direct

mmmm: register
indirect with post­increment

mmmm: register
indirect

mmmm: PC­relative using Rm

Destination
Operand

direct
nnnn: register

direct
nnnn: register

indirect with
pre-decrement

Control register
or system
register

Control register
or system
register

— JMP

— BRAF

Instruction
Example

MOVT
Rn

STS
MACH,Rn

STC.L
SR,@–Rn

LDC
Rm,SR

LDC.L
@Rm+,SR

@Rm

Rm

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Section 2 CPU

Instruction Format

nm
format

md
format

nd4
format

15 0

xxxx xxxx

15 0

xxxx dddd

15 0

xxxx

nnnn

xxxx

xxxx

mmmm

mmmm

nnnn

dddd

Source
Operand

mmmm: register
direct

mmmm: register
indirect

mmmm: register

Destination
Operand

nnnn: register
direct

nnnn: register
indirect

MACH,MACL MAC.W
indirect with post­increment
(multiply-and­accumulate
operation)

nnnn: * register
indirect with post­increment
(multiply-and­accumulate
operation)

mmmm: register
indirect with post-

nnnn: register

direct
increment

mmmm: register
direct

nnnn: register

indirect with

pre-decrement
mmmm: register

direct
mmmmdddd:

register indirect

nnnn: indexed

register indirect

R0 (register

direct)
with displacement

R0 (register direct) nnnndddd:

register indirect

with

displacement

Instruction
Example

ADD
Rm,Rn

MOV.L
Rm,@Rn

@Rm+,@Rn+

MOV.L
@Rm+,Rn

MOV.L
Rm,@–Rn

MOV.L
Rm,@(R0,Rn)

MOV.B
@(disp,Rm),R0

MOV.B
R0,@(disp,Rn)

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Section 2 CPU

Instruction Format

nmd
format

15 0

xxxx dddd

nnnn

mmmm

Source
Operand

mmmm: register
direct

Destination
Operand

nnnndddd:
register indirect
with
displacement

mmmmdddd:
register indirect

nnnn: register
direct

with displacement

d format

15 0

xxxx

xxxx

dddd

dddd

dddddddd: GBR
indirect with

R0 (register
direct)

displacement
R0 (register direct) dddddddd: GBR

indirect with
displacement

dddddddd:
PC-relative with

R0 (register
direct)

displacement
dddddddd:

— BF label

PC-relative

d12
format

nd8
format

15 0

xxxx

15 0

xxxx

dddd

nnnn

dddd dddd

dddd

dddd

dddddddddddd:
PC-relative

dddddddd:
PC-relative with

— BRA label

nnnn: register
direct

displacement

i format

15 0

xxxx

xxxx

i i i i

iiiiiiii: immediate Indexed GBR

i i i i

indirect

iiiiiiii: immediate R0 (register

direct)

iiiiiiii: immediate — TRAPA #imm

ni format

15 0

xxxx

nnnn

i i i i

i i i i

iiiiiiii: immediate nnnn: register

direct

Note: * In a multiply-and-accumulate instruction, nnnn is the source register.

Instruction
Example

MOV.L
Rm,@(disp,Rn)

MOV.L
@(disp,Rm),Rn

MOV.L
@(disp,GBR),R0

MOV.L
R0,@(disp,GBR)

MOVA
@(disp,PC),R0

(label = disp +
PC)

MOV.L
@(disp,PC),Rn

AND.B
#imm,
@(R0,GBR)

AND
#imm,R0

ADD
#imm,Rn

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Section 2 CPU

2.4 Instruction Set

2.4.1 Instruction Set Clas sif ied by Function

The SH7706 instruction set includes 68 basic instruction types, as listed in table 2.4.

Table 2.4 Classification of Instructions

Classification Types

Data transfer 5

21 ADD Binary additionArithmetic

operations

Operation
Code Function

MOV Data transfer
MOVA Effective address transfer
MOVT T bit transfer
SWAP Swap of upper and lower bytes
XTRCT Extraction of middle of linked registers

ADDC Binary addition with carry
ADDV Binary addition with overflow check
CMP/cond Comparison
DIV1 Division
DIV0S Initialization of signed division
DIV0U Initialization of unsigned division
DMULS Signed double-precision multiplication
DMULU Unsigned double-prec is ion mul tip lic ati on
DT Decrement and test
EXTS Sign extension
EXTU Zero extension
MAC Multiply-and-accumulate operat io n,

double-precision multiply-and-accumulate
operation

No. of
Instructions

39

33

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Section 2 CPU

Operation

Classification Types

Arithmetic
operations

Logic
operations

Shift 12 ROTL One-bit left rotation

21

6

Code Function

MUL Double-precision multiplication

(32 × 32 bits)
MULS Signed multiplication (16 × 16 bits)
MULU Unsigned multiplication (16 × 16 bits)
NEG Negation
NEGC Negation with borrow
SUB Binary subtraction
SUBC Binary subtraction with borrow
SUBV Binary subtraction with underflow check
AND Logical AND
NOT Bit inversion
OR Logical OR
TAS Memory test and bit set
TST Logical AND and T bit set
XOR Exclusive OR

ROTR One-bit right rotation
ROTCL One-bit left rotation with T bit
ROTCR One-bit right rotation with T bit
SHAL One-bit arithmet ic left sh ift
SHAR One-bit arithmetic right shift
SHLL One-bit logical left shift
SHLLn n-bit logical left shift
SHLR One-bit logical right shift
SHLRn n-bit logical right shift
SHAD Dynamic arithmetic shift
SHLD Dynamic logical shift

No. of
Instructions

33

14

16

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Section 2 CPU

Operation

Classification Types

Branch 9

System
control

Total: 68 188

15

Code Function

BF Conditional branch, delayed conditional

branch (T = 0)

BT Conditional branch, delayed conditional

branch (T = 1)
BRA Unconditional branch
BRAF Unconditional branch
BSR Branch to subroutine procedure
BSRF Branch to subroutine procedure
JMP Unconditional branch
JSR Branch to subroutine procedure
RTS Return from subroutine procedure
CLRMAC MAC register clear
CLRT Clear T bit
CLRS Clear S bit
LDC Load to control register
LDS Load to system register
LDTLB Load PTE to TLB
NOP No operation
PREF Prefetch data to cache
RTE Return from exception handling
SETS Set S bit
SETT Set T bit
SLEEP Shift to power-down mode
STC Store from control register
STS Store from system register
TRAPA Trap exception handling

No. of
Instructions

11

75

The instruction codes are listed from tables 2.5 to 2.10. Those tables are described according to the
following items.

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Section 2 CPU

Item Format Explanation

Instruction
mnemonic

Instruction
code

Operation
summary

Privileged
mode

Execution
cycles

T bit Value of T bit after instruction is executed

Note: * Scaling (×1, ×2, ×4) is performed according to the instruction operand size.

OP.Sz SRC,DEST OP: Operation code

Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement

MSB ↔ LSB mmmm: Source register

nnnn: Destination register

0000: R0
0001: R1

...........

1111: R15
iiii: Immediate data
dddd: Displacement*

→, ←
(xx)
M/Q/T
&
|
^
~
<<n, >>n

Direction of transfer
Memory operand
Flag bits in SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit shift

Indicates whether privileged mode applies

Value when no wait states are inserted
The execution cycles listed in the table are minimums. The

actual number of cycles may be increased in cases such as
the followings:

1. When contention occurs between instruction fetches and

data access

2. When the destination register of the load instruction

(memory → register) and the register used by the next
instruction are the same

—: No change

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Section 2 CPU

Table 2.5 lists the data transfer instruction s

Table 2.5 Data Transfer Instructions

Privileged

Instruction Operation Code

MOV #imm,Rn imm → Sign extension

→ Rn

MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign

extension → Rn

MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn 1101nnnndddddddd — 1 —
MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 — 1 —
MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 — 1 —
MOV.W Rm,@Rn Rm → (Rn) 0010nnnnmmmm0001 — 1 —
MOV.L Rm,@Rn Rm → (Rn) 0010nnnnmmmm0010 — 1 —
MOV.B @Rm,Rn (Rm) → Sign extension

→ Rn

MOV.W @Rm,Rn (Rm) → Sig n extension

→ Rn

MOV.L @Rm,Rn (Rm) → Rn 0110nnnnmmmm0010 — 1 —
MOV.B Rm,@–Rn Rn–1 → Rn, Rm → (Rn) 0010nnnnmmmm0100 — 1 —
MOV.W Rm,@–Rn Rn–2 → Rn, Rm → (Rn) 0010nnnnmmmm0101 — 1 —
MOV.L Rm,@–Rn Rn–4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 — 1 —
MOV.B @Rm+,Rn (Rm) → Sign extension

→ Rn, Rm + 1 → Rm

MOV.W @Rm+,Rn (Rm) → Sign extension

→ Rn, Rm + 2 → Rm

MOV.L @Rm+,Rn (Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110 — 1 —
MOV.B R0,@(disp,Rn) R0 → (disp + Rn) 10000000nnnndddd — 1 —
MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn) 10000001nnnndddd — 1 —
MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd — 1 —
MOV.B @(disp,Rm),R0 (disp + Rm) → Sign

extension → R0

MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → Sig n

extension → R0

MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd — 1 —
MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 — 1 —

1110nnnniiiiiiii — 1 —

1001nnnndddddddd — 1 —

0110nnnnmmmm0000 — 1 —

0110nnnnmmmm0001 — 1 —

0110nnnnmmmm0100 — 1 —

0110nnnnmmmm0101 — 1 —

10000100mmmmdddd — 1 —

10000101mmmmdddd — 1 —

Mode Cycles T Bi t

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Section 2 CPU

Privileged

Instruction Operation Code

MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 — 1 —
MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 — 1 —
MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign

extension → Rn

MOV.W @(R0,Rm),Rn (R0 + Rm) → Sign

extension → Rn

MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 — 1 —
MOV.B R0,@(disp,GBR) R0 → (disp + GBR) 11000000dddddddd — 1 —
MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd — 1 —
MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd — 1 —
MOV.B @(disp,GBR),R0 (disp + GBR) → Sign

extension → R0

MOV.W @(disp,GBR),R0 (disp × 2 + GBR) →

Sign extension → R0

MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd — 1 —
MOVA @(disp,PC),R0 disp × 4 + PC → R0 11000111dddddddd — 1 —
MOVT Rn T → Rn 0000nnnn00101001 — 1 —
SWAP.B Rm,Rn Rm → Swap the bottom

two bytes → REG

SWAP.W Rm,Rn Rm → Swap two

consecutive words → Rn

XTRCT Rm,Rn Rm: Middle 32 bits of

Rn → Rn

0000nnnnmmmm1100 — 1 —

0000nnnnmmmm1101 — 1 —

11000100dddddddd — 1 —

11000101dddddddd — 1 —

0110nnnnmmmm1000 — 1 —

0110nnnnmmmm1001 — 1 —

0010nnnnmmmm1101 — 1 —

Mode Cycles T Bi t

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Section 2 CPU

Table 2.6 lists the arithmetic instructions.

Table 2.6 Arithmetic Instructions

Privileged

Instruction Operation Code

ADD Rm,Rn Rn + Rm → Rn 0011nnnnmmmm1100 — 1 —
ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii — 1 —
ADDC Rm,Rn Rn + Rm + T → Rn,

Carry → T

ADDV Rm,Rn Rn + Rm → Rn,

Overflow → T

CMP/EQ #imm,R0 If R0 = imm, 1 → T 10001000iiiiiiii — 1 Comparison

CMP/EQ Rm,Rn If Rn = Rm, 1 → T 0011nnnnmmmm0000 — 1 Comparison

CMP/HS Rm,Rn If Rn ≥ Rm with

unsigned data, 1 → T

CMP/GE Rm,Rn If Rn ≥ Rm with signed

data, 1 → T

CMP/HI Rm,Rn If Rn > Rm with

unsigned data, 1 → T

CMP/GT Rm,Rn If Rn > Rm with signed

data, 1 → T

CMP/PZ Rn If Rn ≥ 0, 1 → T 0100nnnn00010001 — 1 Comparison

CMP/PL Rn If Rn > 0, 1 → T 0100nnnn00010101 — 1 Comparison

CMP/STR Rm,Rn If Rn and Rm have an

equivalent byte, 1 → T

DIV1 Rm,Rn Single-step divisi on

(Rn/Rm)

DIV0S Rm,Rn MSB of Rn → Q, MSB

of Rm → M, M ^ Q → T

DIV0U 0 → M/Q/T 0000000000011001 — 10

0011nnnnmmmm1110 — 1 Carry

0011nnnnmmmm1111 — 1Overflow

0011nnnnmmmm0010 — 1 Comparison

0011nnnnmmmm0011 — 1 Comparison

0011nnnnmmmm0110 — 1 Comparison

0011nnnnmmmm0111 — 1 Comparison

0010nnnnmmmm1100 — 1 Comparison

0011nnnnmmmm0100 — 1 Calculation

0010nnnnmmmm0111 — 1 Calculation

Mode Cycles T Bit

result

result

result

result

result

result

result

result

result

result

result

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Section 2 CPU

Privileged

Instruction Operation Code

DMULS.L Rm,Rn Signed operation of

Rn × Rm → MACH,
MACL 32 × 32 → 64 bits

DMULU.L Rm,Rn Unsigned operation of

Rn × Rm → MACH,
MACL 32 × 32 → 64 bits

DT Rn Rn – 1 → Rn, if Rn =

0, 1 → T, else 0 → T

EXTS.B Rm,Rn A byte in Rm is sign-

extended → Rn

EXTS.W Rm,Rn A word in Rm is sign-

extended → Rn

EXTU.B Rm,Rn A byte in Rm is zero-

extended → Rn

EXTU.W Rm,Rn A word in Rm is zero-

extended → Rn

MAC.L @Rm+,@Rn+ Signed operation of (Rn)

× (Rm) + MAC → MAC,
Rn + 4 → Rn,
Rm + 4 → Rm
32 × 32 + 64 → 64 bits

MAC.W @Rm+,@Rn+ Signed operation of (Rn)

× (Rm) + MAC → MAC,
Rn + 2 → Rn,
Rm + 2 → Rm
16 × 16 + 64 → 64 bits

MUL.L Rm,Rn Rn × Rm → MACL

32 × 32 → 32 bits

MULS.W Rm,Rn Signed operation of Rn

× Rm → MACL
16 × 16 → 32 bits

MULU.W Rm,Rn Unsigned operation of

Rn × Rm → MACL
16 × 16 → 32 bits

NEG Rm,Rn 0–Rm → Rn 0110nnnnmmmm1011 — 1 —
NEGC Rm,Rn 0–Rm–T → Rn,

Borrow → T

0011nnnnmmmm1101 — 2 to (5)* —

0011nnnnmmmm0101 — 2 to (5)* —

0100nnnn00010000 — 1 Comparison

0110nnnnmmmm1110 — 1 —

0110nnnnmmmm1111 — 1 —

0110nnnnmmmm1100 — 1 —

0110nnnnmmmm1101 — 1 —

0000nnnnmmmm1111 — 2 to (5)* —

0100nnnnmmmm1111 — 2 to (5)* —

0000nnnnmmmm0111 — 2 to (5)* —

0010nnnnmmmm1111 — 1 to (3)* —

0010nnnnmmmm1110 — 1 to (3)* —

0110nnnnmmmm1010 — 1 Borrow

Mode Cycles T Bit

result

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Section 2 CPU

Privileged

Instruction Operation Code

SUB Rm,Rn Rn–Rm → Rn 0011nnnnmmmm1000 — 1 —
SUBC Rm,Rn Rn–Rm–T → Rn,

Borrow → T

SUBV Rm,Rn Rn–Rm → Rn,

Underflow → T

0011nnnnmmmm1010 — 1 Borrow

0011nnnnmmmm1011 — 1 Underflow

Mode Cycles T Bit

Note: * The normal number of execution cycles is shown. The value in parentheses is the

number of cycles required in case of contention with the preceding or following
instruction.

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Section 2 CPU

Table 2.7 lists the logic operation instructions.

Table 2.7 Logic Operation Instructions

Privileged

Instruction Operation Code

AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 — 1 —
AND #imm,R0 R0 & imm → R0 11001001iiiiiiii — 1 —
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm →

(R0 + GBR)

NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 — 1 —
OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 — 1 —
OR #imm,R0 R0 | imm → R0 11001011iiiiiiii — 1 —
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm →

(R0 + GBR)

TAS.B @Rn* If (Rn) is 0, 1 → T;

1 → MSB of (Rn)*

TST Rm,Rn Rn & Rm; if the result

is 0, 1 → T

TST #imm,R0 R0 & imm; if the result

is 0, 1 → T

TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;

if the result is 0, 1 → T

XOR Rm,Rn Rn ^ Rm → Rn 0010nnnnmmmm1010 — 1 —
XOR #imm,R0 R0 ^ imm → R0 11001010iiiiiiii — 1 —
XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm →

(R0 + GBR)

11001101iiiiiiii — 3 —

11001111iiiiiiii — 3 —

0100nnnn00011011 — 4Test

0010nnnnmmmm1000 — 1Test

11001000iiiiiiii — 1Test

11001100iiiiiiii — 3Test

11001110iiiiiiii — 3 —

Note: * The on-chip DMAC's bus cycle is not inserted between the read and write cycles of the

TAS instruction. The bus authority is not released by the BREQ.

Mode Cycles T Bit

result

result

result

result

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Table 2.8 lists the shift instructions.

Table 2.8 Shift Instructions

Privileged

Instruction Operation Code

ROTL Rn T ← Rn ← MSB 0100nnnn00000100 — 1MSB
ROTR Rn LSB → Rn → T 0100nnnn00000101 — 1LSB
ROTCL Rn T ← Rn ← T 0100nnnn00100100 — 1MSB
ROTCR Rn T → Rn → T 0100nnnn00100101 — 1LSB
SHAD Rm,Rn Rn ≥ 0: Rn << Rm → Rn

Rn < 0: Rn >> Rm →
[MSB → Rn]

SHAL Rn T ← Rn ← 0 0100nnnn00100000 — 1MSB
SHAR Rn MSB → Rn → T 0100nnnn00100001 — 1LSB
SHLD Rm,Rn Rn ≥ 0: Rn << Rm → Rn

Rn < 0: Rn >> Rm →
[0 → Rn]

SHLL Rn T ← Rn ← 0 0100nnnn00000000 — 1MSB
SHLR Rn 0 → Rn → T 0100nnnn00000001 — 1LSB
SHLL2 Rn Rn << 2 → Rn 0100nnnn00001000 — 1 —
SHLR2 Rn Rn >> 2 → Rn 0100nnnn00001001 — 1 —
SHLL8 Rn Rn << 8 → Rn 0100nnnn00011000 — 1 —
SHLR8 Rn Rn >> 8 → Rn 0100nnnn00011001 — 1 —
SHLL16 Rn Rn << 16 → Rn 0100nnnn00101000 — 1 —
SHLR16 Rn Rn >> 16 → Rn 0100nnnn00101001 — 1 —

0100nnnnmmmm1100 — 1 —

0100nnnnmmmm1101 — 1 —

Mode Cycles T Bit

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Table 2.9 lists the branch instructions.

Table 2.9 Branch Instructions

Privileged

Instruction Operation Code

BF label If T = 0, disp × 2 + PC → PC;

if T = 1, nop (where label is
disp + PC)

BF/S label Delayed branch, if T = 0,

disp × 2 + PC → PC;
if T = 1, nop

BT label Delayed branch, if T = 1,

disp × 2 + PC → PC;
if T = 0, nop

BT/S label If T = 1, disp × 2 + PC → PC;

if T = 0, nop

BRA label Delayed branch,

disp × 2 + PC → PC

BRAF Rm Delayed branch,

Rm + PC → PC

BSR label Delayed branch, PC → PR,

disp × 2 + PC → PC

BSRF Rm Delayed branch, PC → PR,

Rm + PC → PC

JMP @Rm Delay ed branch, Rm → PC 0100mmmm00101011 — 2 —
JSR @Rm Delay ed branch, PC → PR,

Rm → PC

RTS Delayed branch, PR → PC 0000000000001011 — 2 —

10001011dddddddd — 3/1* —

10001111dddddddd — 2/1* —

10001001dddddddd — 3/1* —

10001101dddddddd — 2/1* —

1010dddddddddddd — 2 —

0000mmmm00100011 — 2 —

1011dddddddddddd — 2 —

0000mmmm00000011 — 2 —

0100mmmm00001011 — 2 —

Note: * One state when there is no branch.

Mode Cycles T Bi t

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Table 2.10 lists the system control instructions.

Table 2.10 System Control Instructions

Privileged

Instruction Operation Code

CLRMAC 0 → MACH, MACL 0000000000101000 — 1 —
CLRS 0 → S 0000000001001000 — 1 —
CLRT 0 → T 0000000000001000 — 10
LDC Rm,SR Rm → SR 0100mmmm00001110 √ 5LSB
LDC Rm,GBR Rm → GBR 0100mmmm00011110 — 3 —
LDC Rm,VBR Rm → VBR 0100mmmm00101110 √ 3 —
LDC Rm,SSR Rm → SSR 0100mmmm00111110 √ 3 —
LDC Rm,SPC Rm → SPC 0100mmmm01001110 √ 3 —
LDC Rm,R0_BANK Rm → R0_BANK 0100mmmm10001110 √ 3 —
LDC Rm,R1_BANK Rm → R1_BANK 0100mmmm10011110 √ 3 —
LDC Rm,R2_BANK Rm → R2_BANK 0100mmmm10101110 √ 3 —
LDC Rm,R3_BANK Rm → R3_BANK 0100mmmm10111110 √ 3 —
LDC Rm,R4_BANK Rm → R4_BANK 0100mmmm11001110 √ 3 —
LDC Rm,R5_BANK Rm → R5_BANK 0100mmmm11011110 √ 3 —
LDC Rm,R6_BANK Rm → R6_BANK 0100mmmm11101110 √ 3 —
LDC Rm,R7_BANK Rm → R7_BANK 0100mmmm11111110 √ 3 —
LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 √ 7LSB
LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 — 5 —
LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 √ 5 —
LDC.L @Rm+,SSR (Rm) → SSR, Rm + 4 → Rm 0100mmmm00110111 √ 5 —
LDC.L @Rm+,SPC (Rm) → SPC, Rm + 4 → Rm 0100mmmm01000111 √ 5 —
LDC.L @Rm+,

R0_BANK

LDC.L @Rm+,

R1_BANK

LDC.L @Rm+,

R2_BANK

LDC.L @Rm+,

R3_BANK

(Rm) → R0_BANK,
Rm + 4 → Rm

(Rm) → R1_BANK,
Rm + 4 → Rm

(Rm) → R2_BANK,
Rm + 4 → Rm

(Rm) → R3_BANK,
Rm + 4 → Rm

0100mmmm10000111 √ 5 —

0100mmmm10010111 √ 5 —

0100mmmm10100111 √ 5 —

0100mmmm10110111 √ 5 —

Mode Cycles T Bit

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Privileged

Instruction Operation Code

LDC.L @Rm+,

R4_BANK

LDC.L @Rm+,

R5_BANK

LDC.L @Rm+,

R6_BANK

LDC.L @Rm+,

R7_BANK

(Rm) → R4_BANK,
Rm + 4 → Rm

(Rm) → R5_BANK,
Rm + 4 → Rm

(Rm) → R6_BANK,
Rm + 4 → Rm

(Rm) → R7_BANK,
Rm + 4 → Rm

0100mmmm11000111 √ 5 —

0100mmmm11010111 √ 5 —

0100mmmm11100111 √ 5 —

0100mmmm11110111 √ 5 —

LDS Rm,MACH Rm → MACH 0100mmmm00001010 — 1 —
LDS Rm,MACL Rm → MACL 0100mmmm00011010 — 1 —
LDS Rm,PR Rm → PR 0100mmmm00101010 — 1 —
LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 — 1 —
LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 — 1 —
LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 — 1 —
LDTLB PTEH/PTEL → TLB 0000000000111000 √ 1 —
NOP No operation 0000000000001001 — 1 —
PREF @Rm (Rm) → cache 0000mmmm10000011 — 2 —
RTE Delayed branch,

0000000000101011 √ 4 —

SSR/SPC → SR/PC

SETS 1 → S 0000000001011000 — 1 —
SETT 1 → T 0000000000011000 — 11
SLEEP Sleep 0000000000011011 √ 4* —
STC SR,Rn SR → Rn 0000nnnn00000010 √ 1 —
STC GBR,Rn GBR → Rn 0000nnnn00010010 — 1 —
STC VBR,Rn VBR → Rn 0000nnnn00100010 √ 1 —
STC SSR,Rn SSR → Rn 0000nnnn00110010 √ 1 —
STC SPC,Rn SPC → Rn 0000nnnn01000010 √ 1 —
STC R0_BANK,Rn R0_BANK→ Rn 0000nnnn10000010 √ 1 —
STC R1_BANK,Rn R1_BANK→ Rn 0000nnnn10010010 √ 1 —
STC R2_BANK,Rn R2_BANK→ Rn 0000nnnn10100010 √ 1 —
STC R3_BANK,Rn R3_BANK→ Rn 0000nnnn10110010 √ 1 —

Mode

Cycles T Bit

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Privileged

Instruction Operation Code

STC R4_BANK,Rn R4_BANK→ Rn 0000nnnn11000010 √ 1 —
STC R5_BANK,Rn R5_BANK→ Rn 0000nnnn11010010 √ 1 —
STC R6_BANK,Rn R6_BANK→ Rn 0000nnnn11100010 √ 1 —
STC R7_BANK,Rn R7_BANK→ Rn 0000nnnn11110010 √ 1 —
STC.L SR,@–Rn Rn–4 → Rn, SR → (Rn) 0100nnnn00000011 √ 2 —
STC.L GBR,@–Rn Rn–4 → Rn, GBR → (Rn) 0100nnnn00010011 — 2 —
STC.L VBR,@–Rn Rn–4 → Rn, VBR → (Rn) 0100nnnn00100011 √ 2 —
STC.L SSR,@–Rn Rn–4 → Rn, SSR → (Rn) 0100nnnn00110011 √ 2 —
STC.L SPC,@–Rn Rn–4 → Rn, SPC → (Rn) 0100nnnn01000011 √ 2 —
STC.L R0_BANK,

Rn–4 → Rn, R0_BANK → (Rn) 0100nnnn10000011 √ 2 —

@–Rn

STC.L R1_BANK,

Rn–4 → Rn, R1_BANK → (Rn) 0100nnnn10010011 √ 2 —

@–Rn

STC.L R2_BANK,

Rn–4 → Rn, R2_BANK → (Rn) 0100nnnn10100011 √ 2 —

@–Rn

STC.L R3_BANK,

Rn–4 → Rn, R3_BANK → (Rn) 0100nnnn10110011 √ 2 —

@–Rn

STC.L R4_BANK,

Rn–4 → Rn, R4_BANK → (Rn) 0100nnnn11000011 √ 2 —

@–Rn

STC.L R5_BANK,

Rn–4 → Rn, R5_BANK → (Rn) 0100nnnn11010011 √ 2 —

@–Rn

STC.L R6_BANK,

Rn–4 → Rn, R6_BANK → (Rn) 0100nnnn11100011 √ 2 —

@–Rn

STC.L R7_BANK,

Rn–4 → Rn, R7_BANK → (Rn) 0100nnnn11110011 √ 2 —

@–Rn
STS MACH,Rn MACH → Rn 0000nnnn00001010 — 1 —
STS MACL,Rn MACL → Rn 0000nnnn00011010 — 1 —
STS PR,Rn PR → Rn 0000nnnn00101010 — 1 —
STS.L MACH,@–Rn Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 — 1 —
STS.L MACL,@–Rn Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 — 1 —
STS.L PR,@–Rn Rn–4 → Rn, PR → (Rn) 0100nnnn00100010 — 1 —
TRAPA #imm PC → SPC, SR → SSR,

11000011iiiiiiii — 8 —

imm → TRA

Mode

Cycles T Bit

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Section 2 CPU

Notes: The table shows the minimum number of execution cycles. The actual number of

instruction execution cycles will increase in cases such as the followings:

a. When there is contention between an instruction fetch and data access
b. When the destination register in a load (memory-to-register) instruction is also used

by the next instruction

With the addressing modes using displacement (disp) listed below, the assembler
descriptions in this manual show the value before scaling (×1, ×2, or ×4) is performed. This
is done to clarify the operation of the chip. For the actual assembler descriptions, refer to
the individual assembler notation rules.

@ (disp:4, Rn) ; Register-indirect with displacement
@ (disp:8, Rn) ; GBR-indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12 ; PC-relative

* The number of cycles until the sleep state is entered.

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Section 2 CPU

2.4.2 Instruction Code Map

Table 2.11 shows the instruction code map.

Table 2.11 Instruction Code Map

Instruction Code

MSB LSB

0000 Rn Fx 0000
0000 Rn Fx 0001
0000 Rn 00MD 0010 STC SR,Rn STC GBR,Rn STC VBR,Rn STC SSR,Rn
0000 Rn 01MD 0010 STC SPC,Rn
0000 Rn 10MD 0010 STC R0_BANK,Rn STC R1_BANK,Rn STC R2_BANK,Rn STC R3_BANK,Rn
0000 Rn 11MD 0010 STC R4_BANK,Rn STC R5_BANK,Rn STC R6_BANK,Rn STC R7_BANK,Rn
0000 Rm 00MD 0011 BSRF Rm BRAF Rm
0000 Rm 10MD 0011 PREF @Rm
0000 Rn Rm 01MD MOV.B Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MUL.L Rm,Rn
0000 0000 00MD 1000 CLRT SETT CLRMAC LDTLB
0000 0000 01MD 1000 CLRS SETS
0000 0000 Fx 1001 NOP DIV0U
0000 0000 Fx 1010
0000 0000 Fx 1011 RTS SLEEP RTE
0000 Rn Fx 1000
0000 Rn Fx 1001 MOVT Rn
0000 Rn Fx 1010 STS MACH,Rn STS MACL,Rn STS PR,Rn
0000 Rn Fx 1011
0000 Rn Rm 11MD MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MAC.L @Rm+,@Rn+
0001 Rn Rm disp MOV.L Rm,@(disp:4,Rn)
0010 Rn Rm 00MD MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn
0010 Rn Rm 01MD MOV.B Rm,@-Rn MOV.W Rm,@-Rn MOV.L Rm,@-Rn DIV0S Rm,Rn
0010 Rn Rm 10MD TST Rm,Rn AND Rm,Rn XOR Rm,Rn OR Rm,Rn
0010 Rn Rm 11MD CMP/STR Rm,Rn XTRCT Rm,Rn MULU.W Rm,Rn MULSW Rm,Rn
0011 Rn Rm 00MD CMP/EQ Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn
0011 Rn Rm 01MD DIV1 Rm,Rn DMULU.L Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn
0011 Rn Rm 10MD SUB Rm,Rn SUBC Rm,Rn SUBV Rm,Rn
0011 Rn Rm 11MD ADD Rm,Rn DMULS.L Rm,Rn ADDC Rm,Rn ADDV Rm,Rn

Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111

MD: 00 MD: 01 MD: 10 MD: 11

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Section 2 CPU

Instruction Code

MSB LSB

0100 Rn Fx 0000 SHLL Rn DT Rn SHAL Rn
0100 Rn Fx 0001 SHLR Rn CMP/PZ Rn SHAR Rn
0100 Rn Fx 0010 STS.L MACH,@-Rn STS.L MACL,@-Rn STS.L PR,@-Rn
0100 Rn 00MD 0011 STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn STC.L SSR,@-Rn
0100 Rn 01MD 0011 STC.L SPC,@-Rn
0100 Rn 10MD 0011 STC.L R0_BANK,@-Rn STC.L R1_BANK,@-Rn STC.L R2_BANK,@-Rn STC.L R3_BANK,@-

0100 Rn 11MD 0011 STC.L R4_BANK,@-Rn STC.L R5_BANK,@-Rn STC.L R6_BANK,@-Rn STC.L R7_BANK,@-

0100 Rn Fx 0100 ROTL Rn ROTCL Rn
0100 Rn Fx 0101 ROTR Rn CMP/PL Rn ROTCR Rn
0100 Rm Fx 0110 LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR
0100 Rm 00MD 0111 LDC.L @ Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR
0100 Rm 01MD 0111 LDC.L @Rm+,SPC
0100 Rm 10MD 0111 LDC.L @Rm+,R0_BANK LDC.L @Rm+,R1_BANK LDC.L @Rm+,R2_BANK LDC.L

0100 Rm 11MD 0111 LDC.L @Rm+,R4_BANK LDC.L @Rm+,R5_BANK LDC.L @Rm+,R6_BANK LDC.L

0100 Rn Fx 1000 SHLL2 Rn SHLL8 Rn SHLL16 Rn
0100 Rn Fx 1001 SHLR2 Rn SHLR8 Rn SHLR16 Rn
0100 Rm Fx 1010 LDS Rm,MACH LDS Rm,MACL LDS Rm,PR
0100 Rm/RnFx 1011 JSR @Rm TAS.B @Rn JMP @Rm

Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111

MD: 00 MD: 01 MD: 10 MD: 11

Rn

Rn

@Rm+,R3_B

ANK

@Rm+,R7_B

ANK

0100 Rn Rm 1100 SHAD Rm,Rn
0100 Rn Rm 1101 SHLD Rm,Rn
0100 Rm 00MD 1110 LDC Rm,SR LDC Rm,GBR LDC Rm,VBR LDC Rm,SSR
0100 Rm 01MD 1110 LDC Rm,SPC
0100 Rm 10MD 1110 LDC Rm,R0_BANK LDC Rm,R1_BANK LDC Rm,R2_BANK LDC Rm,R3_BANK
0100 Rm 11MD 1110 LDC Rm,R4_BANK LDC Rm,R5_BANK LDC Rm,R6_BANK LDC Rm,R7_BANK
0100 Rn Rm 1111 MAC.W @Rm+,@Rn+
0101 Rn Rm disp MOV.L @(disp:4,Rm),Rn
0110 Rn Rm 00MD MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV Rm,Rn
0110 Rn Rm 01MD MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn NOT Rm,Rn

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Section 2 CPU

Instruction Code

MSB LSB

0110 Rn Rm 10MD SWAP.B Rm,Rn SWAP.W Rm,Rn NEGC Rm,Rn NEG Rm,Rn
0110 Rn Rm 11MD EXTU.B Rm,Rn EXTU.W Rm,Rn EXTS.B Rm,Rn EXTS.W Rm,Rn
0111 Rn imm ADD #imm:8,Rn
1000 00MD Rn disp MOV.B

1000 01MD Rm disp MOV.B

1000 10MD imm/disp CMP/EQ #imm:8,R0 BT label:8 BF label:8
1000 11MD imm/disp BT/S label:8 BF/S label:8
1001 Rn disp MOV.W @(DISP:8,PC),RN
1010 disp BRA label:12
1011 disp BSR label:12
1100 00MD imm/disp MOV.B

1100 01MD disp MOV.B

1100 10MD imm TST #imm:8,R0 AND #imm:8,R0 XOR #imm:8,R0 OR #imm:8,R0
1100 11MD imm TST.B

Rn disp MOV.L @(disp:8,PC),Rn

1101
1110 Rn imm MOV #imm:8,Rn
1111 ************

Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111

MD: 00 MD: 01 MD: 10 MD: 11

R0,@(disp:4,Rn)

@(disp:4,Rm),R0

R0,@(disp:8,GBR)

@(disp:8,GBR),R0

#imm:8,@(R0,GBR)

MOV.W
R0,@(disp:4,Rn)

MOV.W
@(disp:4,Rm),R0

MOV.W
R0,@(disp:8,GBR)

MOV.W
@(disp:8,GBR),R0

AND.B
#imm:8,@(R0,GBR)

MOV.L
R0,@(disp:8,GBR)

MOV.L
@(disp:8,GBR),R0

XOR.B
#imm:8,@(R0,GBR)

TRAPA #imm:8

MOVA
@(disp:8,PC),R0

OR.B
#imm:8,@(R0,GBR)

Note: See the SH-3/SH-3E/SH3-DSP Programming Manual for details.

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Section 2 CPU

2.5 Processor States and Processor Modes

2.5.1 Processor States

The SH7706 has five processor states: the reset state, exception-handling state, bus-released state,
program execution state, and power-down state.

Reset State: In this state the CPU is reset. The CPU enters the power-on reset state if the RESETP
pin is low, or the manual reset state if the RESETM pin is low. See section 4, Exception
Processing, for more information on resets.

In the power-on reset state, the internal states of the CPU and the on-chip supporting module
registers are initialized. In the manual reset state, th e internal states of the CPU and registers of on­chip supporting modules other than the bus state controller (BSC) are initialized. For details, refer
to section 23.3, Register States in Processing Mode.

Exception-Handling State: This is a transient state during which the CPU's processor state flow
is altered by a reset, general exception, or interrupt exception handling.

In the case of a reset, the CPU branches to address H'A0000000 and starts executing the user­coded exception handling program.

In the case of a general exception or interrupt, the program counter (PC) contents are saved in the
saved program counter (SPC) and the status register (SR) contents are saved in the saved status
register (SSR). The CPU branches to the start address of the user-coded exception service routine
found from the sum of the contents of the vector base address and the vector offset. See section 4,
Exception Processing, for more information on resets, general exceptions, and interrupts.

Program Execution State: In this state the CPU executes program instructions in sequence.

Power-Down State: In the power-down state, CPU operation halts and power consumption is

reduced. There are three modes in the power-down state: sleep mode, software standby mode and
hardware standby mode. The software standby mode and hardware standby mode are expressed by
a generlc name, standby mode. See section 22, Power-Down Modes, for more information.

Bus-Released State: In this state the CPU has released the bus to a device that requested it.

Transitions between the states are shown in figure 2.6.

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Section 2 CPU

From any state when
RESETP = 0

Interrupt

Bus-released state

Bus
request

Sleep mode

Power-on reset

Bus request

Bus
request
clearance

From any state but hardware standby
mode or bus-released state when RESETM = 0

RESETP = 0

state

RESETP = 1 RESETM = 1

Exception-handling state

Exception

Bus request clearance

Bus request

interrupt

Bus request

clearance

SLEEP
instruction
with STBY
bit cleared

Program execution state

End of exception
transition
processing

Manual reset

state

Reset state

Interrupt

SLEEP
instruction
with STBY
bit set

Software standby mode

CA = 1, RESETP=0

Note: * The hardware standby mode is entered when the CA pin goes low level from any state.

Hardware standby mode

*

Power-down state

Figure 2.6 Processor State Transitions

2.5.2 Processor Modes

There are two processor modes: privileged mode and user mode. The processor mode is
determined by the processor mode bit (MD) in the status register (SR). User mode is selected
when the MD bit is 0, and privileged mode when the MD bit is 1. When the reset state or
exception state is entered, the MD bit is set to 1. When ex ceptio n handling ends, the MD bit is
cleared to 0 and user mode is entered. There are certain registers and bits which can only be
accessed in privileged mode.

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Section 3 Memory Management Unit (MMU)

Section 3 Memory Management Unit (MMU)

This LSI has an on-chip memory management unit (MMU) that implements address translation.
This LSI's features a resident translation look-aside buffer (TLB) that caches information for user­created address translation tables located in external memory. It enables high-speed translation of
virtual addresses into physical addresses. Address translation uses the paging system and supports
two page sizes (1 kbyte and 4 kbytes). The access right to virtual address space can be set for
privileged and user modes to provide memory protection.

3.1 Role of MMU

The MMU is a feature designed to make efficient use of physical memory. As shown in figure 3.1,
if a process is smaller in size than the physical memory, the entire process can be mapped onto
physical memory. However, if the process increases in size to the extent that it no longer fits into
physical memory, it becomes necessary to partition the process and to map those parts requiring
execution onto memory as occasion demands (figure 3.1(1)). Having the process itself consider
this mapping onto physical memory would impose a large burden on the process. To lighten this
burden, the idea of virtual memory was born as a means of performing en bloc mapping onto
physical memory (figure 3.1(2)). In a virtual memory system, substantially more virtual memory
than physical memory is provided, and the process is mapped onto this virtual memory. Thus a
process only has to consider operation in virtual memory. Mapping from virtual memory to
physical memory is handled by the MMU. The MMU is normally controlled by the operating
system, switching physical memory to allow the virtual memory required by a process to be
mapped onto physical memory in a smooth fashion. Switching of physical memory is carried out
via secondary storage, etc.

The virtual memory system that came into being in this way is particularly effective in a time­sharing system (TSS) in which a number of processes are running simultaneously (figure 3.1(3)).
If processes running in a TSS had to take mapping onto virtual memory into consideration while
running, it would not be possible to increase efficiency. Virtual memory is thus used to reduce this
load on the individual processes and so improve efficiency (figure 3.1(4)). In the virtual memory
system, virtual memory is allocated to each process. The task of the MMU is to perform efficient
mapping of these virtual memory areas onto physical memory. It also has a memory protection
feature that prevents one process from inadvertently accessing another process's physical memory.

When address translation from virtual memory to physical memory is performed using the MMU,
it may occur that the relevant translation information is not recorded in the MMU, with the result
that one process may inadvertently access the virtual memory allocated to another process. In this
case, the MMU will generate an exception, change the physical memory mapping, and record the
new address translation inform ation.

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Section 3 Memory Management Unit (MMU)

Although the functions of the MMU could also be implemented by software alone, the need for
translation to be performed by software each time a process accesses physical memory would
result in poor efficiency. For this reason, a buffer for address translation (translation look-aside
buffer: TLB) is provided in hardware to hold frequently used address translation information. The
TLB can be described as a cache for storing address translation information. Unlike cache
memory, however, if address translation fails, that is, if an exception is generated, switching of
address translation information is normally performed by software. This makes it possible for
memory management to be performed flexibly by software.

The MMU has two methods of mapping from virtual memory to physical memory: a paging
method using fixed-length address translation, and a segment method using variable-length
address translation. With the pag ing method, the unit of translation is a fixed-size address sp ace
(usually of 1 to 64 kbytes) called a page.

In the following text, this LSI's address space in virtual memory is referred to as virtual address
space, and address space in physical memory as physical memory space.

Virtual

Process 1

Physical
memory

Process 1

Physical
memory

Process 1

memory

MMU

Physical
memory

Process 1

Process 2

Process 3

Figure 3.1 MMU Functions

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Physical
memory

(3)

(1)

Process 1

Process 2

Process 3

Virtual
memory

MMU

Physical
memory

(2)

(4)