Page 1
SH7705 Group
32
SuperH
Hardware Manual
Renesas 32-Bit RISC Microcomputer
RISC engine Family/SH7700 Series
Rev.2.00
2003.9.19
Page 2
Page 3
Renesas 32-Bit RISC Microcomputer
SuperH RISC engine Family/SH7700 Series
SH7705 Group
Hardware Manual
REJ09B0082-0200O
Page 4
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibilitythat trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
convey any license under anyintellectual property r ights, or any other rights, belonging to
Renesas TechnologyCorp.or a third party.
2. Renesas Technolog y Corp. assumes no responsibility for any damage, or infr ingement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs,
algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of these
materials, and are subject to chan ge by Ren esas Technology Corp. without notice due to
product improvements or other reasons. It is therefore recommended that customers contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for
the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various
means, including the Renesas Technology Corp. Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, progr ams, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products.
Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss
resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at stake.
Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product
distributor when considering the use of a product contained herein for any specific purposes,
such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or
undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported into a
country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 2.00, 09/03, page iv of xlvi
Page 5
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment ofUnused Input Pins
Note: Fix all unused input pins tohigh or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough curr ent flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefin ed or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 2.00, 09/03, page v of xlvi
Page 6
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The con figuration of the functional description of each module differs according to the
module. However, the generic style in cludes the following items:
i) Feature
ii) In put/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each
section includes notes in relation to the descriptions given, and usage notes are given, as required,
as the final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10.Index
Rev. 2.00, 09/03, page vi of xlvi
Page 7
Preface
The SH7705 single-chip RISC (Reduced Instruction Set Computer) microprocessor includes a
Renesas Technology original RISC CPU as its core, and the peripheral function s required to
configure a system.
Target users: This manual was written for users who will be using the SH7705 Micro-Computer
Unit (MCU) in the design of application systems. Users of this manual are expected
to understand the fundamentals of electrical circuits, logical circuits, and
microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the SH7705 MCU to the above users.
Refer to the SH-3/SH-3E/SH3-DSP Programming Manual for a detailed description
of the instruction set.
Notes on reading this manual:
• Product names
The following products are covered in this manual.
Product Classifications and Abbreviations
Basic Classification Product Code
SH7705 HD6417705
• In order to understand the overall functions ofthe chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understandthe details of the CPU's functions
Read the SH-3/SH-3E/SH3-DSP Programming Manual.
Rev. 2.00, 09/03, page vii of xlvi
Page 8
Rules: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication, is implemented
on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB (most significant bit) is on the left and the LSB
(least significant bit) is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx
Signal notation: An overbar is added to a low-active signal:
xxxx
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.ren esas.com/eng/
SH7705 manuals:
Manual Title ADE No.
SH7705 Hardware Manual This manual
SH-3/SH-3E/SH3-DSP Programming Manual ADE-602-096
Users manuals for development tools:
Manual Title ADE No.
SH Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's
Manual
ADE-702-246
SH Series Simulator/Debugger (for Windows) User's Manual ADE-702-186
SH Series Simulator/Debugger (for UNIX) User's Manual ADE-702-203
Embedded Workshop Use r's Manual ADE-702-201
SH Series Embedded Workshop, Debugging Interface Tutorial ADE-702-230
Rev. 2.00, 09/03, page viii of xlvi
Page 9
Abbreviations
ADC Analog to Digital Co nverter
ALU Arithmetic Logic Unit
ASE Adaptive System Evaluator
ASID Address Space Identifier
AUD Advanced User Debugger
BCD Binary Coded Decimal
bps bit per second
BSC Bus State Controller
CCN Cache Memory Controller
CMT Compare Match Timer
CPG Clock Pulse Generator
CPU Central Processing Unit
DMAC Direct Memory Access Controller
etu Elemen tary Time Unit
FIFO First-In First-Out
Hi-Z High Impedance
UDI User Debugging Interface
INTC Interrupt Controller
IrDA Infrared Data Association
JTAG Joint Test Action Group
LQFP Low Profile QFP
LRU Least Recently Used
LSB Least Significant Bit
MMU Memory Management Unit
MPX Multiplex
MSB Most Significant Bit
PC Program Counter
PFC Pin Function Controller
PLL Phase Locked Loop
PWM Pulse Width Modulation
RAM Random Access Memory
RISC Reduced Instruction Set Computer
ROM Read Only Memory
RTC Realtime Clock
SCIF Serial Communication Interface with FIFO
Rev. 2.00, 09/03, page ix of xlvi
Page 10
SDRAM Synchronous DRAM
TAP Test Access Port
T.B.D To Be Determined
TLB Translation Lookaside Buffer
TMU Timer Unit
TPU Timer Pulse Unit
UART Universal Asynchronous Receiver/Transmitter
UBC User Break Controller
USB Universal Serial Bus
WDT Watchdog Timer
Rev. 2.00, 09/03, page x of xlvi
Page 11
Main Revisions and Additions in this Edition
Item Page Revisions (See Manual for Details)
1.1 SH7705 Features
Table 1.1 SH7705
Features
1.3 Pin Assignment
Table 1.2 Pin Functions
4 Features of USB function module (USB) amended
•ConformstoUSB
2.0 full-speed specification
Note *6, *7 added13, 15,
16
Pin No.
FP208C
139 G15 TDI
140 G14 TCK
141 F17 TMS
142 F16
143 F15 TDO/PTF5 O / I/O Test data output (UDI) /
144 F14
145 E17
195 C6
TBP208A Pin Name I/O Description
7
*
/PTG0 I / I/O Test data input (UDI) /
input/output port G
7
*
/PTG1 I / I/O
7
*
/PTG2 I / I/O Testmode select(UDI) /
7
*1*
TRST
ASEBRKAK
PTF6
ASEMD0
PTF7
RESETP
/PTG3 I / I/O Test reset (UDI) / input/output
/
O/I/O
7
*2*
/
I / I/O ASE mode (UDI) / input/output
6
*
I Power-on reset request
Test clock (UDI) / input/output
port G
input/output port G
port G
input/output port F
ASE break acknowledge
(UDI) / input/output port F
port F
4.4.1 Address Array
Address-ArrayWrite
(Associative Operation)
4.4.3 Usage Examples
Invalidating a Specific Entry
Invalidating an Add ress
Specification
5.2.5 Exception Source
Acceptance Timing and
Priority
Table 5.1 Exception E vent
Vectors
Notes: 6. Pull-up MOS connected.
7. The pull-up MOS turns on if the pin function controller
(PFC) is used to select other functions (UDI).
105 Description amended
⋅⋅⋅⋅⋅
This operation is used to invalidate the address
specification for a cache.
107 Description largely revised
108 Description added
117 Note *3 amended
Note: 3. If an interrupt is accepted, the
register (EXPEVT) is not changed. ⋅⋅⋅⋅⋅
exception event
Rev. 2.00, 09/03, page xi of xlvi
Page 12
Item Page Revisions (See Manual for Details)
6.1 Features
Figure 6.1 Block Diagram
of INTC
6.4.6 Interrupt Exception
Handling and Priority
Table6.4 Interrupt
Exception Handling Sources
and Priority (IRQ Mode)
126 CMT deleted
NMI
IRQ5−IRQ0
PINT15−PINT0
DMAC
SCIF
ADC
USB
TMU
Legend:
DMAC : Direct memory access controller
SCIF : Serial communication interface (with FIFO)
ADC : A/D converter
USB : USB interface
TMU : Timer pulse unit
TPU : 16-bit timer pulse unit
Input/output
6
control
16
(Interrupt request)
140 IPR (bit numbers) amended for interrupt source TMU2
IPRA(
7to4)
7.4.2 CSn Space Bus
Control Register (CSnBCR)
(n=0,2,3,4,5A,5B,6A,
6B)
Control/Status Register
(RTCSR)
7.4.6 Refresh Timer
Counter (RTCNT)
160 Bits 14 to 12 description added
Note: SDRAM can be specified only in area 2 and area 3.
SDRAM is connected to only one area, SDRAM should be
specified for area 3. In this case area 2 should be specified
as normal space.
161 Note 5 added
Note: 5.
The SDRAM bank active mode can only be used
for the CS3 space. (Refer to the explanation of the BACTV
bit in the SDRAM control register.)
177 Bits 31 to 18 description amended7.4.5 Refresh Timer
Bit
Bit
Name
31 to 8 0R
Initial
Value R/W Description
179 Bits 31 to 18 description amended
Bit
Bit
Name
Initial
Value R/W Description
If
Res erved
Rev. 2.00, 09/03, page xii of xlvi
31 to 8 0RReserved
Page 13
Item Page Revisions (See Manual for Details)
7.13 Others
Reset
8.3.4 DMA Channel
Control Registers (CHCR)
8.4.3 Channel Priority
Round-Robin Mode
237 In standby, sleep, and manual rese t, control registers of the
bus state controller are not initialized. At manual reset, the
current bus cycle being e xecuted is comple ted and then the
access wait state is entered.
Since the RTCNT continues
counting up during manual reset signal assertion, a refresh
request occurs to initiate the refresh cycle.
Note that arbitration requests using
BREQ
are not accepted
during manual reset signal assertion.
244 Bits 15, 14 description amended
00: Fixed de stination address
(setting prohibited in 16-byte transfer)
245 Bits 13, 12 description amended
00: Fixe d source address
(setting prohibited in 16-byte transfer)
258 ⋅⋅⋅⋅⋅ The priority of round-robin mode is CH0 > CH1 > CH2 >
CH3 immediately after a reset.
When the round-robin mode is specified, cycle-steal mode
and burst mode should not bemixed among the bus modes
for multiple channels.
8.4.4 DMA Transfer Types
Address Modes
Figure 8.6 Example of
DMA Transfer Timing in
Dual Mode (Source:
Ordinary Memory,
Destination: Ordinary
Memory)
Bus Mode and channel
Priority Order
262 Figure amended
CKIO
A25 to A0
CSn
D31 to D0
RD
WEn
DACKn
(Active-Low)
Transfer source
address
Data read cycle
(1st cycle)
266 Description largely revised
Transfer destination
address
Data write cycle
(2nd cycle)
8.5 Precautions 270 Newly added
Rev. 2.00, 09/03, page xiii of xlvi
Page 14
Item Page Revisions (See Manual for Details)
9.1 Features
Figure 9.1 Block Diagram
of Clock Pulse Generator
10.2.2 Watchdog Timer
Control/Status Register
(WTCSR)
11.6.1 Transition to
Module Standby Function
16.5 SCIF Interrupt
Sources and DMAC
Table 16.4 SCIF Interrupt
Sources
272 Figure amended
Bus interface
Peripheral bus
289 Note added
Note: If manual reset is selected using the RSTS bit, a
frequency division ratio of 1/16, 1/32, 1/64, 1/256, 1/1,024,
or 1/4,096 is selected using bits CKS2 to CKS0, and a
watchdog timer coun ter overflow occurs, resulting in a
manual reset, the LSI will generate two manual resets in
succession. This will not affect its operation but will cause
change in the state of the STATUS pin.
301 Description amended
This function can be used to reduce the power consumption
in the normal mode
427 Table amended
Interrupt
Source Description DMAC Activation
ERI Interrupt initiated by receive error flag
(ER) or break flag (BRK)
RXI
TXI Interrupt initiated by transmit FIFO data
Interrupt initiated by receiveFIFO data
full flag (RDF) or receive data ready
(DR)
empty flag (TDFE) or transmit data stop
flag (TSF)
and sleep mode.
Not possible
1
Possible
Possible
*
2
*
18.1 Features 437 Description amended
• The UDC (USB device controller) conforming to USB
and transceiver process USB protocol automatically.
19.2.7 Port F Control
Register (PFCR)
19.2.9 Port G Control
Register (PGCR)
489 Note *2 added to Bits 15 and 14
2. Pull-up MOS on.
Note
491 Note *2 added to Bits 7 to 0
2. Pull-up MOS on.
Note
Rev. 2.00, 09/03, page xiv of xlvi
2.0
Page 15
Item Page Revisions (See Manual for Details)
22.2.10 Execution Times
Break Register (BETR)
552 Note added
Note: If the channel B brake condition set to during instruction fetch cycles and any of the
instructions below perform breaks, BETR is not decremented when the first break occurs.
The decremented values are listed below.
Instruction
RTE
DMULS.L Rm,Rn
DMULU.L Rm,Rn
MAC.L @Rm+,@Rn+
MAC.W @Rm+,@Rn+
MUL.L Rm,Rn
AND.B #imm,@(R0,GBR)
OR.B #imm,@(R0,GBR)
TAS.B @Rn
TST.B #imm,@(R0,GBR)
XOR.B #imm,@(R0,GBR)
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC Rm,SSR
LDC Rm,SPC
LDC Rm,R0_BANK
LDC Rm,R1_BANK
LDC Rm,R2_BANK
LDC Rm,R3_BANK
LDC Rm,R4_BANK
LDC Rm,R5_BANK
LDC Rm,R6_BANK
LDC Rm,R7_BANK
Value
Decremented
4
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
Instruction
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDC.L @Rm+,SSR
LDC.L @Rm+,SPC
LDC.L @Rm+,R0_BANK
LDC.L @Rm+,R1_BANK
LDC.L @Rm+,R2_BANK
LDC.L @Rm+,R3_BANK
LDC.L @Rm+,R4_BANK
LDC.L @Rm+,R5_BANK
LDC.L @Rm+,R6_BANK
LDC.L @Rm+,R7_BANK
LDC.L @Rn+,MOD
LDC.L @Rn+,RS
LDC.L @Rn+,RE
LDC Rn,MOD
LDC Rn,RS
LDC Rn,RE
BSR label
BSRF Rm
JSR @Rm
Value
Decremented
6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
23.2 Input/Output Pins 569 Note * added
Note: * The pull-up MOS turns on if the pin function
controller (PFC) is used to select other functions (UDI).
23.3.3 Boundary Scan
Register (SDBSR)
570 Description amended
SDBSR is a 38
5-bit shift register, located on the PAD, for
controlling the input/output pins of this LSI.
23.5.2 Points for Attention 582 Item 7 added under “23.5.2 Points for Attention”
7. The CKIO cock should operate during boundary scan.
The MD[2:0] pin should be set to the clock mode used
during normal operation, and EXTAL and CKIO should be
set within the frequency range specified in the Clock Pulse
Generator (CPG) section.
As during normal operation, the boundary scan test should
be performed after allowing sufficient settling time for the
crystal oscillator, PLL1, and PLL2.
24.1 Register Addresses
(by functional module, in
592
Access size of EP1 data register and EP2 data register
amended to 8/
32
order of the corresponding
section numbers)
Rev. 2.00, 09/03, page xv of xlvi
Page 16
Item Page Revisions (See Manual for Details)
25.3.1 Clock Timing
Figure 25.5 Power-On
OscillationSettling Tim e
25.3.2 Control Signal
Timing
Table 25.6 Control Signal
Timing
Figure 25.15 Pin Drive
Timing at Standby
633 Figure amended
CKIO,
internal clock
V
RESETP
TRST
CC
VCC min
636 Conditions amended
(Conditions: V
V
=VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, AVCC=3.0to
CC
3.6 V, V
Q=VSS=VSS-RTC = VSS-USB = VSS-PLL1 = VSS-
SS
PLL2 = AV
Q=VCC-RTC= VCC-USB = 3.0 to 3.6 V,
CC
=0V,Ta= –20 to 75°C, Clock mode
SS
0/1/2/4/5/6/7)
Note *1 amended
Note: 1.
RESETP,RESETM
asynchronous. ⋅⋅⋅⋅⋅⋅
638 Figure amended
Normal mode Normal modeStandby mode
t
OSC1
Stable oscillation
t
RESPW
t
RESPS
, NMI, and IRQ5 to IRQ0 are
25.3.4 Basic Timing
Figure 25.16 Basic Bus
Cycle (No Wait)
Figure 25.17 Basic Bus
Cycle(One Software Wait)
CKIO
STATUS 0
STATUS 1
640 Note *2 added
2
*
WEn
Write
D31 to D0
Notes: 1. DACKn is a waveform when active-low is specified.
2. Output timing is the same when reading byte-selection SRAM.
641 Note *2 added
2
*
WEn
Write
D31 to D0
t
WDD1
t
t
WDD1
WED
t
WED
t
WED
t
STD
t
AH
t
WDH1
t
WDH4
t
WED
t
t
WDH1
t
WDH4
AH
Rev. 2.00, 09/03, page xvi of xlvi
Notes: 1. DACKn is a waveform when active-low is specified.
2. Output timing is the same when reading byte-selection SRAM.
Page 17
Item Page Revisions (See Manual for Details)
25.3.4 Basic Timing
Figure 25.18 Basic Bus
Cycle(OneExternalWait)
Figure 25.19 Basic Bus
Cycle(One Software Wait,
External Wait Enabled
(WM Bit = 0), No Idle Cycle
Setting)
25.3.11 SCIF Module
Signal Timing
Table 25.13 SCIF Module
Signal Timing
642 Note *2 added
2
*
WEn
Write
D31 to D0
Notes:
1. DACKn is a waveform when active-low is specified.
2. Output timing is the same when reading byte-selection SRAM.
643 Note *2 added
2
*
WEn
Write
D15 to D0
Notes: 1. DACKn is a waveform when active-low is specified.
2. Output timing is the same when reading byte-selection SRAM.
t
WDD1
671 Item amended
Transmission data delay time
RTS
delay time (clock synchronization)
t
WED
t
WDD1
t
WED
t
t
AH
WED
t
WDH1
t
WED
t
WED
t
WDD1
t
AH
t
WDH1
t
t
AH
WED
t
WDH1
(clock synchronization)
A. I/O Port States in Each
Processing State
TableA.1 I/O Port States
in Each Processing State
679 Note *11 added
Category Pin
System
control
RESETP
RESETM
Power-Down
Reset
Power-
on
Reset
11
*
I
Manual
Reset
*
I
States
Bus
Sleep
11
*
I
Mastership
Released I/O
11
*
I
Software
Standby
11
11
*
I
Handling
of Unused
Pins
IMustbe
used
I I I I I I Pull-up
Rev. 2.00, 09/03, page xvii of xlvi
Page 18
Item Page Revisions (See Manual for Details)
A. I/O Port States in Each
Processing State
TableA.1 I/O Port States
in Each Processing State
682,
684
Note *13 added
Power-Down
Reset
Power-
on
Category Pin
Port NF/PTD[5] I I Z I I I/I Pull-up
PTE[7] V P K P P IO Open
NF/PTJ[7] L O O O O O/O Open
NF/PTJ
[6:0]
Reset
H
Manual
Reset
13
*
O O O O O/O Open
States
Software
Standby
Sleep
Bus
Mastership
Released I/O
Handling
of Unused
Pins
Note: 13. The values of PTJ6, PTJ1, and PTJ0 differ during
power-on reset and after the power-on reset state is
released. They conform to the port J data register value
after being switched to port status by the pin function
controller (PFC).
During Power-On
Reset PTD5/NF = 1 PTD5/NF = 0
After Power-On Reset Release
PTJ6/NF 1 0 1
PTJ1/NF 1 1 0
PTJ0/NF 1 0 1
Rev. 2.00, 09/03, page xviii of xlvi
Page 19
Contents
Section 1 Overview ....................................................................................... 1
1.1 SH7705 Features..........................................................................................................1
1.2 Block Diagram.............................................................................................................6
1.3 Pin Assignment............................................................................................................7
1.4 Pin Functions............................................................................................................... 17
Section 2 CPU............................................................................................... 25
2.1 Processing States and Processing Modes.......................................................................25
2.1.1 Processing States............................................................................................. 25
2.1.2 Processing Modes............................................................................................ 26
2.2 MemoryMap...............................................................................................................27
2.2.1 Logical Address Space.....................................................................................27
2.2.2 External MemorySpace...................................................................................28
2.3 Register Descriptions...................................................................................................29
2.3.1 General Register s ............................................................................................32
2.3.2 System Registers .............................................................................................33
2.3.3 Program Coun ter.............................................................................................34
2.3.4 Contr ol Registers.............................................................................................35
2.4 Data Formats...............................................................................................................37
2.4.1 Register Data Format.......................................................................................37
2.4.2 Memory Data Formats.....................................................................................38
2.5 Features of CPU Cor e Instructions ...............................................................................40
2.5.1 Instruction Execution Method.......................................................................... 40
2.5.2 CPU Instruction Addressing Modes.................................................................42
2.5.3 CPU Instruction For mats .................................................................................45
2.6 Instruction Set..............................................................................................................48
2.6.1 CPU Instruction Set Based on Functions..........................................................48
2.6.2 Oper ation Code Map ....................................................................................... 62
Section 3 Memory Manag ement Unit (MMU) ............................................... 65
3.1 Role of MMU..............................................................................................................65
3.1.1 MMUof This LSI............................................................................................67
3.2 Register Descriptions...................................................................................................72
3.2.1 Page Table EntryRegister High (PTEH)..........................................................72
3.2.2 Page Table EntryRegister Low (PTEL)........................................................... 73
3.2.3 Translation Table Base Register (TTB)............................................................73
3.2.4 MMUControl Register (MMUCR).................................................................. 73
3.3 TLB Functions.............................................................................................................75
3.3.1 Configuration of the TLB ................................................................................75
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3.3.2 TLB Indexing .................................................................................................. 77
3.3.3 TLB Address Comparison...............................................................................78
3.3.4 Page Management Information ........................................................................ 80
3.4 MMUFunctions ..........................................................................................................81
3.4.1 MMU Hardware Management.........................................................................81
3.4.2 MMUSoftware Management .......................................................................... 81
3.4.3 MMUInstruction (LDTLB)............................................................................. 82
3.4.4 Avoiding Syn onym Problems..........................................................................83
3.5 MMUExceptions ........................................................................................................ 85
3.5.1 TLB Miss Exception ....................................................................................... 85
3.5.2 TLB Protection Violation Exception................................................................ 86
3.5.3 TLB Invalid Exception....................................................................................87
3.5.4 Initial Page Write Exception............................................................................88
3.6 Memory-Mapped TLB................................................................................................. 90
3.6.1 Address Array ................................................................................................. 90
3.6.2 Data Array ...................................................................................................... 90
3.6.3 Usage Examples..............................................................................................92
3.7 Usage Note.................................................................................................................. 92
Section 4 Cache..............................................................................................93
4.1 Features....................................................................................................................... 93
4.1.1 Cache Structure............................................................................................... 93
4.2 Register Descriptions................................................................................................... 95
4.2.1 Cache Control Register 1 (CCR1).................................................................... 96
4.2.2 Cache Control Register 2 (CCR2).................................................................... 97
4.2.3 Cache Control Register 3 (CCR3).................................................................... 100
4.3 Oper ation .................................................................................................................... 101
4.3.1 Searchin g the Cache........................................................................................ 101
4.3.2 Read Access.................................................................................................... 102
4.3.3 Prefetch Operation ..........................................................................................102
4.3.4 Write Access ................................................................................................... 102
4.3.5 Write-Back Buffer........................................................................................... 103
4.3.6 Coher ency of Cache and External Memory......................................................103
4.4 Memory-Mapped Cache............................................................................................... 104
4.4.1 Address Array ................................................................................................. 104
4.4.2 Data Array ...................................................................................................... 105
4.4.3 Usage Examples..............................................................................................107
4.5 Usage Note.................................................................................................................. 108
Section 5 Exception Handling........................................................................109
5.1 Register Descriptions................................................................................................... 109
5.1.1 TRAPA Exception Register (TRA).................................................................. 110
5.1.2 Exception Event Register (EXPEVT) .............................................................. 111
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5.1.3 Interrupt Event Register (INTEVT) .................................................................. 111
5.1.4 Interrupt Event Register 2 (INTEVT2).............................................................112
5.1.5 Exception Address Register (TEA) .................................................................. 112
5.2 Exception Handling Fun ction.......................................................................................113
5.2.1 Exception Handling Flow ................................................................................113
5.2.2 Exception Vector Addresses ............................................................................114
5.2.3 Exception Codes..............................................................................................114
5.2.4 Exception Request and BL Bit (Multiple Exception Prevention) ....................... 114
5.2.5 Exception Source Acceptance Timing and Priority...........................................115
5.3 Individual Exception Operations .................................................................................. 118
5.3.1 Resets..............................................................................................................118
5.3.2 General Exceptions..........................................................................................118
5.3.3 General Exceptions (MMU Exceptions)........................................................... 121
5.4 Usage Notes.................................................................................................................124
Section 6 Interrupt Controller (INTC)............................................................ 125
6.1 Features.......................................................................................................................125
6.2 Input/Output Pins.........................................................................................................127
6.3 Register Descriptions...................................................................................................127
6.3.1 Interrupt PriorityLevel Setting Registers A to H (IPRA to IPRH).....................128
6.3.2 Interrupt Contr ol Register 0 (ICR0)..................................................................129
6.3.3 Interrupt Contr ol Register 1 (ICR1)..................................................................130
6.3.4 Interrupt Contr ol Register 2 (ICR2)..................................................................132
6.3.5 PINT Interrupt Enable Register (PINTER).......................................................132
6.3.6 Interrupt Request Register 0 (IRR0).................................................................133
6.3.7 Interrupt Request Register 1 (IRR1).................................................................134
6.3.8 Interrupt Request Register 2 (IRR2).................................................................135
6.4 Interrupt Sources..........................................................................................................136
6.4.1 NMI Interrupt..................................................................................................136
6.4.2 IRQ Interrupts.................................................................................................136
6.4.3 IRL Interrupts..................................................................................................137
6.4.4 PINT Interrupt.................................................................................................138
6.4.5 On-Chip Peripheral Module Interrupts.............................................................138
6.4.6 Interrupt Exception Handling and Priority........................................................139
6.5 Oper ation..................................................................................................................... 144
6.5.1 Interrupt Sequence...........................................................................................144
6.5.2 Multiple Interrupts...........................................................................................147
6.6 Usage Note..................................................................................................................147
Section 7 Bus State Controller (BSC)............................................................ 149
7.1 Overview..................................................................................................................... 149
7.1.1 Features...........................................................................................................149
7.1.2 Block Diagram................................................................................................150
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7.2 Pin Configuration ........................................................................................................151
7.3 Area Overview............................................................................................................. 152
7.3.1 Address Map................................................................................................... 152
7.3.2 Memory Bus Width......................................................................................... 154
7.3.3 Shadow Space................................................................................................. 155
7.4 Register Descriptions................................................................................................... 155
7.4.1 Common Control Register (CMNCR).............................................................. 156
7.4.2 CSn Space Bus Control Register (CSn BCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) .... 158
7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B). 161
7.4.4 SDRAM Control Register (SDCR) .................................................................. 174
7.4.5 Refr esh Timer Control/Status Register (RTCSR) ............................................. 177
7.4.6 Refresh Timer Counter (RTCNT).................................................................... 179
7.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 179
7.4.8 Reset Wait Counter (RWTCNT) ...................................................................... 180
7.5 Endian/Access Size and Data Alignment...................................................................... 180
7.6 Normal Space Interface................................................................................................ 187
7.6.1 Basic Timing................................................................................................... 187
7.6.2 Access Wait Control........................................................................................ 192
7.6.3
CSn
Assert Period Expansion .......................................................................... 194
7.7 Address/Data Multiplex I/O Interface........................................................................... 195
7.8 SDRAM Interface........................................................................................................ 198
7.8.1 SDRAM Direct Connection............................................................................. 198
7.8.2 Address Multiplexing...................................................................................... 200
7.8.3 Burst Read ......................................................................................................212
7.8.4 Single Read..................................................................................................... 214
7.8.5 Burst Write ..................................................................................................... 215
7.8.6 Single Write.................................................................................................... 217
7.8.7 Bank Active....................................................................................................218
7.8.8 Refreshing.......................................................................................................225
7.8.9 Low-Frequency Mod e .....................................................................................228
7.8.10 Power-On Sequence........................................................................................229
7.9 Burst ROM Interface....................................................................................................231
7.10 Byte-Selection SRAM Interface...................................................................................233
7.11 Wait between Access Cycles........................................................................................235
7.12 Bus Arbitration............................................................................................................235
7.13 Oth ers.......................................................................................................................... 237
Section 8 Direct Memory Access Contro ller (DMAC)....................................239
8.1 Features....................................................................................................................... 239
8.2 Input/Output Pins.........................................................................................................241
8.3 Register Descriptions................................................................................................... 241
8.3.1 DMA Source Address Registers (SAR)............................................................ 242
8.3.2 DMA Destin ation Address Registers (DAR).................................................... 242
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8.3.3 DMA Transfer Count Registers (DMATCR)....................................................243
8.3.4 DMA Channel Control Registers (CHCR)........................................................243
8.3.5 DMA Operation Register (DMAOR)...............................................................248
8.3.6 DMA ExtendedResource Selectors 0, 1 (DMARS0, DMARS1)....................... 250
8.4 Oper ation..................................................................................................................... 252
8.4.1 Transfer Flow.................................................................................................. 252
8.4.2 DMA Transfer Requests..................................................................................254
8.4.3 Channel Priority..............................................................................................257
8.4.4 DMA Transfer Types.......................................................................................260
8.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing.........................267
8.5 Precautions..................................................................................................................270
8.5.1 Precautions when Mixing Cycle-Steal Mode Channels and Burst Mode
Channels.........................................................................................................270
Section 9 Clock Pu lse Generat o r (CPG)......................................................... 271
9.1 Features.......................................................................................................................271
9.2 Input/Output Pins.........................................................................................................274
9.3 Clock Operating Modes................................................................................................275
9.4 Register Descriptions...................................................................................................279
9.4.1 Frequency Control Register (FRQCR)..............................................................279
9.4.2 USBClock Frequency Control Register (UCLKCR)........................................281
9.4.3 Usage Notes....................................................................................................281
9.5 Changing Frequen cy....................................................................................................282
9.5.1 Changing Multiplication Rate..........................................................................282
9.5.2 Changing Division Ratio..................................................................................282
9.5.3 Modification of Clock Operating Mode............................................................282
9.6 Usage Notes.................................................................................................................283
Section 10 Watchdog Timer (WDT).............................................................. 285
10.1 Features................................................................................................................... .... 285
10.2 Register Descriptions...................................................................................................286
10.2.1 Watchdog Timer Counter (WTCNT)................................................................286
10.2.2 Watchdog Timer Contr ol/Status Register (WTCSR).........................................287
10.2.3 Notes on Register Access.................................................................................289
10.3 Oper ation.....................................................................................................................290
10.3.1 Canceling Software Standbys...........................................................................290
10.3.2 Changin g Frequency........................................................................................291
10.3.3 Using Watchdog Timer Mode..........................................................................291
10.3.4 Using Interval Timer Mode..............................................................................291
Section 11 Power-Down Modes..................................................................... 293
11.1 Features................................................................................................................... .... 293
11.2 Input/Output Pin s.........................................................................................................295
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11.3 Register Descriptions................................................................................................... 295
11.3.1 Standby Control Register (STBCR)................................................................. 296
11.3.2 Standby Control Register 2 (STBCR2)............................................................. 297
11.3.3 Standby Control Register 3 (STBCR3)............................................................. 298
11.4 Sleep Mode..................................................................................................................299
11.4.1 Transition to Sleep Mode................................................................................. 299
11.4.2 Canceling Sleep Mode..................................................................................... 299
11.5 Software Standby Mode............................................................................................... 300
11.5.1 Transition to Software Standby Mode..............................................................300
11.5.2 Canceling Software Standby Mode..................................................................300
11.6 Module Standby Function............................................................................................ 301
11.6.1 Transition to Module Standby Function ...........................................................301
11.6.2 Canceling Module StandbyFunction ...............................................................302
11.7 Hardware Standby Mod e.............................................................................................. 302
11.7.1 Transition to Hardware Standby Mode............................................................. 302
11.7.2 Canceling Hardware Standby Mode................................................................. 302
11.8 Timing of STATUS Pin Changes.................................................................................303
Section 12 Timer Unit (TMU)........................................................................309
12.1 Features....................................................................................................................... 309
12.2 Input/Output Pin .......................................................................................................... 311
12.3 Register Descriptions................................................................................................... 311
12.3.1 Timer Start Register (TSTR)............................................................................ 312
12.3.2 Timer Control Registers (TCR)........................................................................ 313
12.3.3 Timer Con stant Registers (TCOR)................................................................... 317
12.3.4 Timer Counters (TCNT) .................................................................................. 317
12.3.5 Input Capture Register_2 (TCPR_2)................................................................317
12.4 Oper ation .................................................................................................................... 318
12.4.1 Counter Operation........................................................................................... 318
12.4.2 Input Capture Function .................................................................................... 320
12.5 Interrupts..................................................................................................................... 321
12.5.1 Status Flag Set Timin g .................................................................................... 321
12.5.2 Status Flag Clear Timin g.................................................................................321
12.5.3 Interrupt Sources and Priorities........................................................................ 322
12.6 Usage Notes.................................................................................................................322
12.6.1 Writing to Registers ........................................................................................ 322
12.6.2 Reading Registers............................................................................................ 322
Section 13 Compare Match Timer (CMT)......................................................323
13.1 Features....................................................................................................................... 323
13.2 Register Descriptions................................................................................................... 324
13.2.1 Compare Match Timer Start Register (CMSTR)............................................... 324
13.2. 2 Compare Match Timer Control/Status Register (CMCSR)................................ 325
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13.2.3 Compare Match Counter (CMCNT).................................................................326
13.2.4 Compare Match Constant Register (CMCOR)..................................................326
13.3 Oper ation.....................................................................................................................326
13.3.1 Period Count Operation ...................................................................................326
13.3.2 CMCNT Count Timing.................................................................................... 327
13.3.3 Compare Match Flag Set Timin g .....................................................................327
Section 14 16-Bit Timer Pulse U nit (TPU) .................................................... 329
14.1 Features................................................................................................................... .... 329
14.2 Input/Output Pin s.........................................................................................................332
14.3 Register Descriptions...................................................................................................332
14.3.1 Timer Control Registers (TCR)........................................................................ 334
14.3.2 Timer Mode Registers (TMDR).......................................................................337
14.3.3 Timer I/O Contr ol Registers (TIOR) ................................................................338
14.3.4 Timer Interrupt Enable Registers (TIER)..........................................................339
14.3.5 Timer Status Registers (TSR)...........................................................................340
14.3.6 Timer Counters (TCNT)..................................................................................341
14.3.7 Timer Gen eral Registers (TGR)....................................................................... 341
14.3.8 Timer Start Register (TSTR)............................................................................341
14.4 Oper ation.....................................................................................................................342
14.4.1 Overview.........................................................................................................342
14.4.2 Basic Functions...............................................................................................343
14.4.3 Buffer Operation .............................................................................................346
14.4.4 PWM Modes...................................................................................................348
Section 15 Realtime Clock (RTC).................................................................. 351
15.1 Features................................................................................................................... .... 351
15.2 Input/Output Pin s.........................................................................................................353
15.3 Register Descriptions...................................................................................................353
15.3.1 64-Hz Counter (R64CNT) ...............................................................................354
15.3.2 Second Counter (RSECCNT)...........................................................................354
15.3.3 Minute Counter (RMINCNT)..........................................................................355
15.3.4 Hour Counter (RHRCNT)................................................................................355
15.3.5 Day of Week Counter (RWKCNT) ..................................................................356
15.3.6 Date Counter (RDAYCNT) .............................................................................357
15.3.7 Month Counter (RMONCNT)..........................................................................357
15.3.8 Year Counter (RYRCNT)................................................................................ 358
15.3.9 Second Alarm Register (RSECAR)..................................................................358
15.3.10 Minute Alarm Register (RMINAR)..................................................................359
15.3.11 Hour Alarm Register (RHRAR).......................................................................360
15.3.12 Day of Week Alarm Register (RWKAR)..........................................................361
15.3.13 Date Alarm Register (RDAYAR)..................................................................... 362
15.3.14 Month Alarm Register (RMONAR).................................................................363
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15.3.15 Year Alarm Register (RYRAR)....................................................................... 364
15.3.16 RTC Control Register 1 (RCR1)...................................................................... 365
15.3.17 RTC Control Register 2 (RCR2)...................................................................... 366
15.3.18 RTC Control Register 3 (RCR3)...................................................................... 368
15.4 Oper ation .................................................................................................................... 369
15.4.1 Initial Settings of Registers after Power-On ..................................................... 369
15.4.2 Setting Time.................................................................................................... 369
15.4.3 Reading the Time............................................................................................ 370
15.4.4 Alarm Function............................................................................................... 371
15.4.5 Crystal Oscillator Circuit................................................................................. 372
15.5 Notes for Usage........................................................................................................... 373
15.5.1 Register Writing during RTC Count ................................................................ 373
15.5.2 Use of Realtime Clock (RTC) Periodic Interrupts.............................................373
15.5.3 Standby Mode after Register Setting................................................................ 373
Section 16 Serial Communication Interface with FIFO (SCIF).......................375
16.1 Features....................................................................................................................... 375
16.2 Input/Output Pin s......................................................................................................... 378
16.3 Register Descriptions................................................................................................... 379
16.3.1 Receive Shift Register (SCRSR)...................................................................... 380
16.3.2 Receive FIFO Data Register (SCFRDR).......................................................... 380
16.3.3 Transmit Shift Register (SCTSR) ..................................................................... 380
16.3.4 Transmit FIFO Data Register (SCFTDR).........................................................381
16.3.5 Serial Mode Register (SCSMR)....................................................................... 381
16.3.6 Serial Control Register (SCSCR).....................................................................385
16.3.7 FIFO Error Count Register (SCFER) ...............................................................389
16.3.8 Serial Status Register (SCSSR)........................................................................ 390
16.3.9 Bit Rate Register (SCBRR)..............................................................................395
16.3.10 FIFO Con trol Register (SCFCR)...................................................................... 398
16.3.11 FIFO Data Count Register (SCFDR)................................................................ 401
16.3.12 Transmit Data Stop Register (SCTDSR) .......................................................... 401
16.4 Oper ation .................................................................................................................... 402
16.4.1 Overview ........................................................................................................ 402
16.4.2 Asynchr onous Mode........................................................................................402
16.4.3 Serial Operation in Asynchron ous Mode.......................................................... 404
16.4.4 Clock Synchronous Mode................................................................................ 415
16.4.5 Serial Operation in Clock Synchronous Mode..................................................416
16.5 SCIF Interrupt Sources and DMAC .............................................................................. 426
16.6 Notes on Usage............................................................................................................ 428
Section 17 Infrared Data Associat ion Module (IrDA).....................................431
17.1 Features....................................................................................................................... 431
17.2 Input/Output Pin s......................................................................................................... 432
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17.3 Register Description.....................................................................................................432
17.3.1 IrDA Mode Register (SCSMR_Ir)....................................................................432
17.4 Oper ation.....................................................................................................................434
17.4.1 Overview.........................................................................................................434
17.4.2 Transmitting....................................................................................................434
17.4.3 Receiving........................................................................................................435
17.4.4 Data Format Specification...............................................................................435
Section 18 USB Funct ion Module.................................................................. 437
18.1 Features................................................................................................................... .... 437
18.2 Input/Output Pin s.........................................................................................................439
18.3 Register Descriptions...................................................................................................440
18.3.1 Interrupt Flag Register 0 (IFR0).......................................................................441
18.3.2 Interrupt Flag Register 1 (IFR1).......................................................................442
18.3.3 Interrupt Select Register 0 (ISR0)....................................................................443
18.3.4 Interrupt Select Register 1 (ISR1)....................................................................443
18.3.5 Interrupt Enable Register 0 (IER0)...................................................................444
18.3.6 Interrupt Enable Register 1 (IER1)...................................................................444
18.3.7 EP0i Data Register (EPDR0i) .......................................................................... 445
18.3.8 EP0o Data Register (EPDR0o).........................................................................445
18.3.9 EP0s Data Register (EPDR0s) .........................................................................445
18.3.10 EP1 Data Register (EPDR1) ............................................................................446
18.3.11 EP2 Data Register (EPDR2) ............................................................................446
18.3.12 EP3 Data Register (EPDR3) ............................................................................446
18.3.13 EP0o Receive Data SizeRegister (EPSZ0o)..................................................... 447
18.3.14 EP1 Receive Data Size Register (EPSZ1).........................................................447
18.3.15 Trigger Register (TRG) ...................................................................................448
18.3.16 Data StatusRegister (DASTS)......................................................................... 449
18.3.17 FIFO Clear Register (FCLR)............................................................................449
18.3.18 DMA Tran sfer Setting Register (DMAR).........................................................450
18.3.19 Endpoin t Stall Register (EPSTL) .....................................................................453
18.3.20 Transceiver Control Register (XVERCR).........................................................453
18.4 Oper ation.....................................................................................................................454
18.4.1 Cable Connection............................................................................................ 454
18.4.2 Cable Disconnection........................................................................................455
18.4.3 Control Transfer..............................................................................................455
18.4.4 EP1 Bulk-Out Transfer (Dual FIFOs)............................................................... 461
18.4.5 EP2 Bulk-In Transfer (Dual FIFOs).................................................................462
18.4.6 EP3 Interrupt-In Transfer.................................................................................463
18.5 Processing of USB Standard Commands and Class/Vendor Comman ds........................464
18.5.1 Processing of Commands Transmitted byControl Transfer ..............................464
18.6 Stall Operations...........................................................................................................465
18.6.1 Overview.........................................................................................................465
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18.6.2 Forcible Stall by Application........................................................................... 465
18.6.3 Automatic Stall byUSB Function Module....................................................... 467
18.7 DMA Transfer.............................................................................................................468
18.7.1 Overview ........................................................................................................ 468
18.7.2 DMA Transfer for Endpoint 1.......................................................................... 468
18.7.3 DMA Transfer for Endpoint 2.......................................................................... 469
18.8 Example of USB External Circuitry..............................................................................470
18.9 Usage Notes.................................................................................................................473
18.9.1 Receivin g Setup Data...................................................................................... 473
18.9.2 Clearingthe FIFO ........................................................................................... 473
18.9.3 Overreading and Overwritin g the Data Registers.............................................. 473
18.9.4 Assigning Interrupt Sources to EP0..................................................................474
18.9.5 Clearingthe FIFO when DMATran sfer Is Enabled.......................................... 474
18.9.6 Notes on TR Interrupt...................................................................................... 474
Section 19 Pin Function Controller.................................................................475
19.1 Overview..................................................................................................................... 475
19.2 Register Descriptions................................................................................................... 479
19.2.1 Port A Control Register (PACR) ...................................................................... 480
19.2.2 Port B Control Register (PBCR)...................................................................... 481
19.2.3 Port C Control Register (PCCR)...................................................................... 483
19.2.4 Port D Control Register (PDCR) ...................................................................... 485
19.2.5 Port E Con trol Register (PECR) ....................................................................... 487
19.2.6 Port E Con trol Register 2 (PECR2) .................................................................. 488
19.2.7 Port F Control Register (PFCR).......................................................................489
19.2.8 Port F Control Register 2 (PFCR2) ..................................................................490
19.2.9 Port G Control Register (PGCR) ...................................................................... 491
19.2.10 Port H Control Register (PHCR)...................................................................... 493
19.2.11 Port J Con trol Register (PJCR) ........................................................................494
19.2.12 Port K Control Register (PKCR)...................................................................... 496
19.2.13 Port L Control Register (PLCR)....................................................................... 498
19.2.14 Port M Control Register (PMCR).....................................................................499
19.2.15 Port N Control Register (PNCR)...................................................................... 500
19.2.16 Port N Control Register 2 (PNCR2)................................................................. 502
19.2.17 Port SC Control Register (SCPCR).................................................................. 503
Section 20 I/O Ports.......................................................................................507
20.1 Por t A.......................................................................................................................... 507
20.1.1 Register Description........................................................................................ 507
20.1.2 Port A Data Register (PADR)..........................................................................508
20.2 Por t B .......................................................................................................................... 508
20.2.1 Register Description........................................................................................ 509
20.2.2 Port B Data Register (PBDR)...........................................................................509
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20.3 Por t C..........................................................................................................................510
20.3.1 Register Description........................................................................................ 510
20.3.2 Port C Data Register (PCDR)...........................................................................510
20.4 Por t D ...................................................................................................................... .... 511
20.4.1 Register Description........................................................................................ 511
20.4.2 Port D Data Register (PDDR) ..........................................................................511
20.5 Por t E ..........................................................................................................................513
20.5.1 Register Description........................................................................................ 513
20.5.2 Port E Data Register (PEDR)...........................................................................513
20.6 Por t F ..........................................................................................................................514
20.6.1 Register Description........................................................................................ 514
20.6.2 Port F Data Register (PFDR) ........................................................................... 514
20.7 Por t G .......................................................................................................................... 515
20.7.1 Register Description........................................................................................ 515
20.7.2 Port G Data Register (PGDR) ..........................................................................516
20.8 Por t H .......................................................................................................................... 516
20.8.1 Register Description........................................................................................ 517
20.8.2 Port H Data Register (PHDR)..........................................................................517
20.9 Por t J...........................................................................................................................518
20.9.1 Register Description........................................................................................ 518
20.9.2 Port J Data Register (PJDR).............................................................................518
20.10 Port K .......................................................................................................................... 519
20.10.1 Register Description........................................................................................519
20.10.2 Port K Data Register (PKDR)..........................................................................519
20.11 Port L..........................................................................................................................520
20.11.1 Register Description........................................................................................520
20.11.2 Port L Data Register (PLDR)........................................................................... 521
20.12 Port M.........................................................................................................................521
20.12.1 Register Description........................................................................................522
20.12.2 Port M Data Register (PMDR).........................................................................522
20.13 Port N .......................................................................................................................... 523
20.13.1 Register Description........................................................................................523
20.13.2 Port N Data Register (PNDR)..........................................................................523
20.14 SC Port........................................................................................................................524
20.14.1 Register Description........................................................................................525
20.14.2 Port SC Data Register (SCPDR) ......................................................................525
Section 21 A/D Converter.............................................................................. 527
21.1 Features................................................................................................................... .... 527
21.2 Input/Output Pin s.........................................................................................................529
21.3 Register Descriptions...................................................................................................529
21.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ...........................................530
21.3.2 A/D Control/Status Registers (ADCSR)........................................................... 530
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21.4 Oper ation .................................................................................................................... 533
21.4.1 Single Mode.................................................................................................... 533
21.4.2 Multi Mode..................................................................................................... 533
21.4.3 Scan Mode...................................................................................................... 534
21.4.4 Input Sampling and A/D Conversion Time.......................................................534
21.5 Interrupts and DMACTransfer Request ....................................................................... 536
21.6 Definitions of A/D Conver sion Accuracy.....................................................................536
21.7 Usage Notes.................................................................................................................538
21.7.1 Allowable Signal-Source Impedance................................................................538
21.7.2 Influence to Absolute Accuracy ....................................................................... 538
21.7.3 Setting Analog Input Voltage...........................................................................538
21.7.4 Notes on Board Design.................................................................................... 539
21.7.5 Notes on Countermeasur es to Noise................................................................. 539
Section 22 User Break Contro ller...................................................................541
22.1 Features....................................................................................................................... 541
22.2 Register Descriptions................................................................................................... 543
22.2.1 Break Addr ess Register A (BARA).................................................................. 543
22.2.2 Break Addr ess Mask Register A (BAMRA)..................................................... 544
22.2.3 Break Bus Cycle Register A (BBRA)...............................................................544
22.2.4 Break Addr ess Register B (BARB).................................................................. 545
22.2.5 Break Addr ess Mask Register B (BAMRB) ..................................................... 546
22.2.6 Break Data Register B (BDRB) ....................................................................... 546
22.2.7 Break Data Mask Register B (BDMRB)........................................................... 547
22.2.8 Break Bus Cycle Register B (BBRB)............................................................... 547
22.2.9 Break Control Register (BRCR)....................................................................... 549
22.2.10 Execution Times Break Register (BETR)......................................................... 552
22.2.11 Branch Source Register (BRSR)......................................................................553
22.2.12 Branch Destination Register (BRD R)............................................................... 554
22.2.13 Break ASID Register A (BASRA) ................................................................... 554
22.2.14 Break ASID Register B (BASRB)....................................................................555
22.3 Oper ation .................................................................................................................... 555
22.3.1 Flow of the User Break Operation....................................................................555
22.3.2 Break on In struction Fetch Cycle..................................................................... 557
22.3.3 Break on Data Access Cycle............................................................................558
22.3.4 Sequential Break.............................................................................................559
22.3.5 Value of Saved Program Counter..................................................................... 559
22.3.6 PC Trace......................................................................................................... 561
22.3.7 Usage Examples.............................................................................................. 562
22.3.8 Notes............................................................................................................... 566
Section 23 User Debugging Interface (UDI)...................................................567
23.1 Features....................................................................................................................... 567
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Page 31
23.2 Input/Output Pin s.........................................................................................................568
23.3 Register Descriptions...................................................................................................569
23.3.1 Bypass Register (SDBPR)................................................................................569
23.3.2 Instruction Register (SDIR) .............................................................................569
23.3.3 BoundaryScan Register (SDBSR)...................................................................570
23.3.4 ID Register (SDID)..........................................................................................577
23.4 Oper ation.....................................................................................................................578
23.4.1 TAP Controller................................................................................................578
23.4.2 Reset Configuration.........................................................................................579
23.4.3 TDO Output Timin g........................................................................................579
23.4.4 UDI Reset .......................................................................................................580
23.4.5 UDI Interrupt ..................................................................................................580
23.5 Boundary Scan............................................................................................................. 581
23.5.1 Supported Instructions..................................................................................... 581
23.5.2 Points for Attention.........................................................................................582
23.6 Usage Notes.................................................................................................................583
23.7 Advanced User Debugger (AUD)................................................................................. 583
Section 24 List of Registers ........................................................................... 585
24.1 Register Addresses
(by functional module, in order of the corresponding section numbers).........................586
24.2 Register Bits............................................................................................................... . 595
24.3 Register States in Each Operating Mode.......................................................................614
Section 25 Electrical Characteristics.............................................................. 623
25.1 Absolute Maximum Ratings.........................................................................................623
25.2 DC Character istics....................................................................................................... 625
25.3 AC Character istics....................................................................................................... 630
25.3.1 Clock Timing ..................................................................................................631
25.3.2 Control Signal Timing.....................................................................................636
25.3.3 AC Bus Timing...............................................................................................638
25.3.4 Basic Timing...................................................................................................640
25.3.5 Burst ROM Timing .........................................................................................645
25.3.6 Synchron ous DRAM Timin g ...........................................................................646
25.3.7 DMAC Signal Timin g .....................................................................................668
25.3.8 TMU Sign al Timing........................................................................................669
25.3.9 RTC Signal Timing .........................................................................................670
25.3.10 16-Bit Timer Pulse Unit (TPU) Signal Timing.................................................670
25.3.11 SCIF Module Signal Timing............................................................................ 671
25.3.12 USB Module Signal Timin g.............................................................................672
25.3.13 USB Tran sceiver Timing.................................................................................673
25.3.14 Port Input/Output Timing ................................................................................ 674
25.3.15 UDI Related Pin Timing..................................................................................675
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Page 32
25.3.16 AC Characteristics Measur ement Conditions ................................................... 677
25.4 A/D Converter Characteristics...................................................................................... 678
Appendix .....................................................................................................679
A. I/O Port States in Each Processing State....................................................................... 679
B. Package Dimensions....................................................................................................685
Index .....................................................................................................687
Rev. 2.00, 09/03, page xxxii of xlvi
Page 33
Figures
Section 1 Overview
Figure 1.1 Block Diagram of SH7705........................................................................................6
Figure 1.2 Pin Assign ment (FP-208C) .......................................................................................7
Figure 1.3 Pin Assignment (TBP-208A).....................................................................................8
Section 2 CPU
Figure 2.1 Processin g State Transitions ....................................................................................26
Figure 2.2 Logical Address to External MemorySpace Mapping .............................................29
Figure 2.3 Register Configuration in Each Processing Mode ....................................................31
Figure 2.4 General Registers....................................................................................................33
Figure 2.5 System Registers and Progr am Counter...................................................................34
Figure 2.6 Control Register Configuration ...............................................................................37
Figure 2.7 Data Format on Memory(Big Endian Mode)...........................................................38
Figure 2.8 Data Format on Memory(Little Endian Mode)........................................................39
Section 3 Memory Management Unit (MMU)
Figure 3.1 MMUFunction s .....................................................................................................66
Figure 3.2 Virtual Address Space (MMUCR.AT = 1)...............................................................68
Figure 3.3 Virtual Address Space (MMUCR.AT = 0)...............................................................69
Figure 3.4 P4 Area ..................................................................................................................69
Figure 3.5 External Memory Space..........................................................................................70
Figure 3.6 Overall Configuration of th e TLB ...........................................................................75
Figure 3.7 Virtual Addr ess and TLB Structure.........................................................................76
Figure 3.8 TLB Indexing (IX = 1)............................................................................................77
Figure 3.9 TLB Indexing (IX = 0)............................................................................................78
Figure 3.10 Objects of Address Compar ison ............................................................................79
Figure 3.11 Operation of LDTLB In struction...........................................................................82
Figure 3.12 Syn onym Problem (32-kbyte Cache)..................................................................... 84
Figure 3.13 MMU Exception Generation Flowchart.................................................................89
Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access............................91
Section 4 Cache
Figure 4.1 Cache Structur e (32-kbyte Mode)............................................................................94
Figure 4.2 Cache Search Scheme...........................................................................................101
Figure 4.3 Write-Back Buffer Configuration..........................................................................103
Figure 4.4 Specifying Address and Data for Memory-Mapped Cache Access
(32-kbyte Mode)....................................................................................................106
Section 5 Exception Handling
Figure 5.1 Register Bit Configuration ....................................................................................110
Section 6 Interrupt Controller (INTC)
Figure 6.1 Block Diagram of INTC........................................................................................126
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Figure 6.2 Example of IRL Interrupt Connection ................................................................... 137
Figure 6.3 Interr upt Operation Flowchart............................................................................... 146
Section 7 Bus State Controller (BSC)
Figure 7.1 BSC Functional Block Diagram............................................................................150
Figure 7.2 Address Space......................................................................................................154
Figure 7.3 Continuous Access for Normal Space (No Wait, WM Bit in CSnWCR = 1,
16-Bit Bus Width, Longword Access, No Wait State between Cycles) ...................188
Figure 7.4 Continuous Access for Normal Space (No Wait, One Wait State between Cycles) . 189
Figure 7.5 Example of 32-Bit Data-Width SRAM Connection ...............................................190
Figure 7.6 Example of 16-Bit Data-Width SRAM Connection ...............................................191
Figure 7.7 Example of 8-Bit Data-Width SRAM Connection ................................................. 191
Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only)................................192
Figure 7.9 Wait State Timing for Normal Space Access
Figure 7.10
(Wait State Insertion by
CSn
Assert Period Expan sion.............................................................................. 194
WAIT
Signal).................................................................. 193
Figure 7.11 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait)...195
Figure 7.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait)...... 196
Figure 7.13 Access Timing for MPX Space (Address Cycle Access Wait 1,
Data Cycle Wait 1, External Wait 1)...................................................................197
Figur e 7.14 Example of 64-MBit Synchron ous DRAM Connection (32-Bit Data Bus)............ 199
Figure 7.15 Example of 64-MBit Synchronous DRAM (16-Bit Data Bus)..............................200
Figur e 7.16 Synchronous DRAM Burst Read Wait Specification Timing (Auto Precharge) .... 213
Figure 7.17 Basic Timing for Single Read (Auto Precharge).................................................. 214
Figure 7.18 Basic Timing for Synchronous DRAM Burst Write (Auto Precharge).................. 216
Figure 7.19 Basic Timing for Sin gle Write(Auto Precharge) ................................................. 217
Figure 7.20 Burst Read Timing (No Auto Precharge).............................................................219
Figure 7.21 Burst Read Timing (Bank Active, Same Row Address) ....................................... 220
Figure 7.22 Burst Read Timing (Bank Active, Different Row Addresses)............................... 221
Figure 7.23 Single Write Timing (No Auto Precharge)...........................................................222
Figure 7.24 Single Write Timing (Bank Active, Same Row Address).....................................223
Figure 7.25 Single Write Timing (Bank Active, Different RowAddresses).............................224
Figure 7.26 Auto-Refresh Timing..........................................................................................226
Figure 7.27 Self-Refresh Timing ...........................................................................................227
Figure 7.28 Low-FrequencyMode Access Timing.................................................................228
Figure 7.29 Synchronous DRAM Mode Write Timing (Based on JEDEC).............................231
Figure 7.30 Burst ROM Access (Bus Width 8 Bits, Access Size 32 Bits (Number of Burst 4),
Access Wait for the 1st Time 2, Access Wait for 2nd Time and after 1)............... 232
Figure 7.31 Byte-Selection SRAM Basic Access Timin g .......................................................233
Figur e 7.32 Example of Conn ection with 32-Bit Data-Width Byte-Selection SRAM .............. 234
Figur e 7.33 Example of Conn ection with 16-Bit Data-Width Byte-Selection SRAM .............. 234
Figure 7.34 Bus Arbitration...................................................................................................237
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Section 8 Direct Memory Access Controller (DMAC)
Figure 8.1 Block Diagram of DMAC.....................................................................................240
Figure 8.2 DMAC Transfer Flowchart ...................................................................................253
Figure 8.3 Round-Robin Mode..............................................................................................258
Figure 8.4 Channel Priority in Round-Robin Mode................................................................259
Figure 8.5 Data Flow of Dual Address Mode .........................................................................261
Figure 8.6 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)..................................262
Figure 8.7 Data Flow in Single Address Mode.......................................................................263
Figure 8.8 Example of DMA Transfer Timing in Single Address Mode..................................263
Figure 8.9 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection).........................................................264
Figure 8.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ LowLevel Detection).......................................................265
Figure 8.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ LowLevel Detection).......................................................265
Figure 8.12 Bus State when Multiple Channels are Operating.................................................267
Figur e 8.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection.............267
Figur e 8.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection............268
Figur e 8.15 Example of DREQ Input Detection in Burst Mode Edge Detection......................268
Figur e 8.16 Example of DREQ Input Detection in Burst Mode Level Detection .....................269
Figur e 8.17 Example of DMA Tran sfer End Signal (in Cycle Steal Level Detection)..............269
Figure 8.18 BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)................................270
Section 9 Clock Pulse Generator (CPG)
Figure 9.1 Block Diagram of Clock Pulse Generator..............................................................272
Figure 9.2 Points for Attention when Using Crystal Reson ator ...............................................283
Figure 9.3 Points for Attention when Using PLL Oscillator Circuit ........................................284
Section 10 Watchdog Timer (WDT)
Figure 10.1 Block Diagram of WDT......................................................................................286
Figure 10.2 Writing to WTCNT and WTCSR ........................................................................290
Section 11 Power-Down Modes
Figure 11.1 Canceling Stan dby Mode with STBY Bit in STBCR............................................301
Figure 11.2 Power-On Reset STATUS Output.......................................................................303
Figure 11.3 Manual Reset STATUS Output...........................................................................303
Figure 11.4 Canceling Software Standby by Interrupt STATUS Output..................................304
Figure 11.5 Canceling Software Standby by Power-On Reset STATUS Output......................304
Figure 11.6 Canceling Software Standby by Manual Reset STATUS Output..........................305
Figure 11.7 Canceling Sleep by Interrupt STATUS Output ....................................................305
Figure 11.8 Canceling Sleep by Power-On Reset STATUS Output.........................................306
Figure 11.9 Canceling Sleep by Manual Reset STATUS Output.............................................306
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Figure 11.10 Hardware StandbyMode (When CA Goes Low in Normal Operation)...............307
Figure 11.11 Hardware Standby Mode Timing (When CA Goes Low during
WDT Operation while Standby Mode Is Canceled)............................................307
Section 12 Timer Unit (TMU)
Figure 12.1 TMU Block Diagram..........................................................................................310
Figure 12.2 Setting Count Operation......................................................................................318
Figure 12.3 Auto-Reload Coun t Operation.............................................................................319
Figure 12.4 Count Timing when In ternal Clock Is Operating..................................................319
Figur e 12.5 Count Timing wh en External Clock Is Operating (Both Edges Detected).............320
Figure 12.6 Operation Timing when Using Input Capture Function
(Using TCLK Risin g Edge)................................................................................. 320
Figure 12.7 UNF Set Timing.................................................................................................321
Figure 12.8 Status Flag Clear Timing .................................................................................... 321
Section 13 Compare Match Timer (CMT)
Figure 13.1 CMT Block Diagram .......................................................................................... 323
Figure 13.2 Counter Operation .............................................................................................. 326
Figure 13.3 Count Timing ..................................................................................................... 327
Figure 13.4 CMF Set Timin g................................................................................................. 327
Section 14 16-Bit Timer Pulse Unit (TPU)
Figure 14.1 Block Diagram of TPU.......................................................................................331
Figure 14.2 Example of Counter Operation Setting Procedure................................................343
Figure 14.3 Free-Running Counter Operation ........................................................................ 344
Figure 14.4 Periodic Counter Operation................................................................................. 344
Figur e 14.5 Example of Setting Procedure for Waveform Output by Compare Match............. 345
Figure 14.6 Example of 0 Output/1 Output Operation............................................................345
Figure 14.7 Example of Toggle Output Operation..................................................................346
Figure 14.8 Compar e Match Buffer Operation ....................................................................... 346
Figure 14.9 Example ofBuffer Operation Setting Procedure..................................................347
Figure 14.10 Example of Buffer Oper ation............................................................................348
Figure 14.11 Example of PWM Mode Setting Procedure .......................................................349
Figure 14.12 Example of PWM Mode Operation (1).............................................................. 350
Figure 14.13 Examples of PWM Mode Operation (2)............................................................ 350
Section 15 Realtime Clock (RTC)
Figure 15.1 RTC Block Diagram...........................................................................................352
Figure 15.2 Setting Time....................................................................................................... 369
Figure 15.3 Reading the Time................................................................................................370
Figure 15.4 Using the Alarm Function...................................................................................371
Figure 15.5 Example of Crystal Oscillator Circuit Conn ection ............................................... 372
Figure 15.6 Using Periodic Interrupt Function ....................................................................... 373
Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.1 Block Diagram of SCIF ......................................................................................377
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Figure 16.2 Sample SCIF Initialization Flowchart..................................................................406
Figure 16.3 Sample Serial Transmission Flowchart................................................................407
Figure 16.4 Example of Transmit Operation
(Example with 8-Bit Data, Parity, One Stop Bit)..................................................409
Figure 16.5 Example of Transmit Data Stop Fun ction............................................................409
Figure 16.6 Transmit Data Stop Fun ction Flowchart ..............................................................410
Figure 16.7 Sample Serial Reception Flowchar t (1)................................................................411
Figure 16.8 Sample Serial Reception Flowchar t (2)................................................................412
Figure 16.9 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)..................................................414
Figure 16.10
Figure 16.11
CTS
Control Operation .....................................................................................414
RTS
Control Operation .....................................................................................415
Figure 16.12 Data Format in Clock Synchronous Communication..........................................416
Figure 16.13 Sample SCIF Initialization Flowchart (1) (Transmission) ...................................418
Figure 16.13 Sample SCIF Initialization Flowchart (2) (Reception) ........................................419
Figure 16.13 Sample SCIF Initialization Flowchart (3)
(Simultaneous Transmission and Reception) ......................................................420
Figure 16.14 Sample Serial Transmission Flowchart (1)
(Fir st Transmission after Initialization) ..............................................................421
Figure 16.14 Sample Serial Transmission Flowchart (2)
(Second and Subsequent Transmission) .............................................................421
Figure 16.15 Sample Serial Reception Flowchart (1) (First Reception after Initialization).......422
Figure 16.15 Sample Serial Reception Flowchart (2) (Second and Subsequent Reception)......423
Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (1)
(Fir st Transfer after Initialization)......................................................................424
Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (2)
(Second and Subsequent Transfer).....................................................................425
Section17 InfraredDataAssociationModule(IrDA)
Figure 17.1 Block Diagram of IrDA.......................................................................................431
Figure 17.2 Transmit/Receive Operation................................................................................435
Section 18 USB Function Module
Figure 18.1 Block Diagram of USB.......................................................................................438
Figure 18.2 Cable Connection Operation ...............................................................................454
Figure 18.3 Cable Disconnection Operation...........................................................................455
Figure 18.4 Transfer Stages in Con trol Transfer.....................................................................455
Figure 18.5 Setup Stage Operation.........................................................................................456
Figure 18.6 Data Stage (Control-In) Operation .......................................................................457
Figure 18.7 Data Stage (Control-Out) Operation....................................................................458
Figure 18.8 Status Stage (Control-In) Operation.....................................................................459
Figure 18.9 Status Stage (Control-Out) Operation..................................................................460
Figure 18.10 EP1 Bulk-Out Transfer Operation .....................................................................461
Figure 18.11 EP2 Bulk-In Transfer Operation........................................................................462
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Figure 18.12 Operation of EP3 Interrupt-In Tran sfer.............................................................. 463
Figure 18.13 Forcible Stall by Application ............................................................................. 466
Figure 18.14 Automatic Stall by USB Function Module......................................................... 467
Figure 18.15 RDFN Bit Oper ation for EP1 ............................................................................ 468
Figure 18.16 PKTE Bit Operation for EP2............................................................................. 469
Figur e 18.17 Example of US B Function Module External Circuitry (Internal Transceiver).....471
Figur e 18.18 Example of USB Function ModuleExternal Circuitry (External Transceiver)....472
Figure 18.19 TR Interrupt Flag Set Timing............................................................................ 474
Section 20 I/O Ports
Figure 20.1 Port A................................................................................................................ . 507
Figure 20.2 Port B................................................................................................................. 508
Figure 20.3 Port C................................................................................................................. 510
Figure 20.4 Port D................................................................................................................ . 511
Figure 20.5 Port E.................................................................................................................513
Figure 20.6 Port F .................................................................................................................514
Figure 20.7 Port G................................................................................................................ . 515
Figure 20.8 Port H................................................................................................................ . 516
Figure 20.9 Port J..................................................................................................................518
Figure 20.10 Port K ............................................................................................................... 519
Figure 20.11 Port L...............................................................................................................520
Figure 20.12 Port M..............................................................................................................521
Figure 20.13 Port N ............................................................................................................... 523
Figure 20.14 SC Port............................................................................................................. 524
Section 21 A/D Converter
Figure 21.1 Block Diagram of A/D Conver ter........................................................................ 528
Figure 21.2 A/D Conversion Timing......................................................................................535
Figure 21.3 Definition s of A/D Conversion Accuracy ........................................................... 537
Figure 21.4 Defin itions of A/D Conversion Accuracy............................................................ 537
Figure 21.5 Analog Input Circuit Example.............................................................................538
Figure 21.6 Example of Analog Input Protection Circuit........................................................539
Figure 21.7 Analog Input Pin Equivalent Circuit.................................................................... 540
Section 22 User Break Controller
Figure 22.1 Block Diagram of User Break Controller.............................................................542
Section 23 User Debugging Interface (UDI)
Figure 23.1 Block Diagram of UDI........................................................................................567
Figure 23.2 TAP Controller StateTransitions ........................................................................ 578
Figure 23.3 UDI Data Transfer Timing .................................................................................. 580
Figure 23.4 UDI Reset...........................................................................................................580
Section 25 Electrical Characteristics
Figure 25.1 Power On/Off Sequence......................................................................................624
Figure 25.2 EXTAL Clock Input Timing...............................................................................632
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Page 39
Figure 25.3 CKIO Clock Input Timing ..................................................................................632
Figure 25.4 CKIO Clock Output Timing................................................................................632
Figure 25.5 Power-On Oscillation Settlin g Time....................................................................633
Figure 25.6 Oscillation Settling Time at Standby Return (Return by Reset) ............................633
Figure 25.7 Oscillation Settling Time at Standby Return (Return by NMI) .............................633
Figure 25.8 Oscillation Settling Time at Standby Return
(Return by IRQ5 to IRQ0, PINT15 to PINT0, and
IRL3toIRL0
).........................634
Figure 25.9 PLL Synchronization Settlin g Time by Reset or NMI..........................................634
Figure 25.10 PLL Synchronization Settlin g Time byIRQ/IRL, PINT Interrupts.....................635
Figure 25.11 PLL Syn chronization Settlin g Time when FrequencyMultiplication
Ratio Modified.................................................................................................635
Figure 25.12 Reset Input Timing ...........................................................................................637
Figure 25.13 Interrupt Signal Input Timing ............................................................................637
Figure 25.14 Bus Release Timing..........................................................................................637
Figure 25.15 Pin Drive Timin g at Stan dby.............................................................................638
Figure 25.16 Basic Bus Cycle (No Wait) ...............................................................................640
Figure 25.17 Basic Bus Cycle (One Software Wait)...............................................................641
Figure 25.18 Basic Bus Cycle (One External Wait)................................................................642
Figure 25.19 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM Bit = 0),
No Idle Cycle Settin g) ......................................................................................643
Figure 25.20 Address/Data Multiplex I/O Bus Cycle
(Three Address Cycles, One Software Wait, One External Wait)........................644
Figure 25.21 Burst ROM Read Cycle
(One Access Wait, One External Wait, One Burst Wait, Two Bursts) .................645
Figure 25.22 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency = 2, TRCD = 1Cycle,TRP= 1 Cycle)...............646
Figure 25.23 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency = 2, TRCD = 2Cycle,TRP= 2 Cycle)...............647
Figure 25.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4),
(Auto Precharge, CAS Latency = 2, TRCD = 1Cycle,TRP= 2 Cycle)...............648
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4),
(Auto Precharge, CAS Latency = 2, TRCD = 2Cycle,TRP= 1 Cycle)...............649
Figure 25.26 Synchronous DRAM Single Write Bus Cycle
(AutoPrecharge, TRWL = 2 Cycle)...................................................................650
Figure 25.27 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, TRCD = 3 Cycle, TRWL = 2 Cycle) .......................................651
Figure 25.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4),
(Auto Precharge, TRCD = 1 Cycle, TRWL = 2 Cycle) .......................................652
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4),
(Auto Precharge, TRCD = 2 Cycle, TRWL = 2 Cycle) .......................................653
Figure 25.30 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Ban k Active Mode: ACTV + READ Commands, CAS Latency= 2,
TRCD = 1 Cycle)..............................................................................................654
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Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: READ Command, Same RowAddress,
CAS Latency= 2, TRCD = 1 Cycle).................................................................655
Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: PRE + ACTV + READ Commands,
Different Row Addr ess, CAS Latency = 2, TRCD = 1 Cycle)............................656
Figure 25.33 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: ACTV + WRITE Commands, TRCD = 1 Cycle,
TRWL = 1 Cycle)............................................................................................. 657
Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: WRITE Command, Same Row Address,
TRCD = 1 Cycle, TRWL = 1 Cycle).................................................................658
Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: PRE + ACTV + WRITE Commands,
Different Row Addr ess, TRCD= 1 Cycle, TRWL = 1 Cycle)............................ 659
Figure 25.36 Syn chronous DRAM Auto-Refresh Timing (TRP = 2 Cycle).............................660
Figure 25.37 Syn chronous DRAM Self-Refresh Timing (TRP = 2 Cycle) .............................. 661
Figur e 25.38 Synchronous DRAM Mode Register WriteTiming (TRP = 2 Cycle).................. 662
Figure 25.39 Access Timing in Low-Frequency Mode (Auto Precharge)................................ 664
Figure 25.40 Synchronous DRAM Auto-Refresh Timing
(TRP = 2 Cycle, Low-Frequen cy Mod e) ............................................................ 665
Figure 25.41 Synchronous DRAM Self-Refresh Timing
(TRP = 2 Cycle, Low-Frequen cy Mod e) ............................................................ 666
Figure 25.42 Synchronous DRAM Mode Register Write Timing
(TRP = 2 Cycle, Low-Frequen cy Mod e) ............................................................ 667
Figure 25.43 DREQ Input Timin g .........................................................................................668
Figure 25.44 DACK, TEND Output Timing .......................................................................... 668
Figure 25.45 TCLK Input Timing.......................................................................................... 669
Figure 25.46 TCLK Clock In put Timing................................................................................669
Figur e 25.47 Oscillation Settling Time when RTC Crystal Oscillator Is Turned On................670
Figure 25.48 TPU Output Timin g..........................................................................................670
Figure 25.49 SCK Input Clock Timing..................................................................................671
Figure 25.50 SCIF Input/Output Timing in Clock Synchr onous Mode.................................... 672
Figure 25.51 USB Clock Timing...........................................................................................672
Figur e 25.52 Oscillation Settling Time when USB Crystal Oscillator Is Turned On................673
Figure 25.53 I/O Port Timing ................................................................................................ 674
Figure 25.54 TCK Input Timing............................................................................................675
Figure 25.55
TRST
Input Timing (Reset Hold)...................................................................... 676
Figure 25.56 UDI Data Transfer Timing................................................................................676
Figure 25.57
ASEMD0
Input Timing.....................................................................................676
Figure 25.58 Output Load Circuit.......................................................................................... 677
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Page 41
Appendix
Figure B.1 Package Dimen sions (FP-208C)...........................................................................685
Figure B.2 Package Dimensions (TBP-208A) ........................................................................686
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Page 42
Tables
Section 1 Overview
Table 1.1 SH7705 Features......................................................................................................2
Table 1.2 Pin Functions...........................................................................................................9
Table 1.3 Pin Functions......................................................................................................... 17
Section 2 CPU
Table 2.1 Logical Address Space...........................................................................................28
Table 2.2 Register Initial Values............................................................................................30
Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions ...........................42
Table 2.4 CPU Instruction Formats ........................................................................................ 45
Table 2.5 CPU Instruction Types...........................................................................................48
Table 2.6 Data Tran sfer Instruction s ...................................................................................... 52
Table 2.7 Arithmetic Operation Instruction s...........................................................................54
Table 2.8 Logic Operation Instructions..................................................................................56
Table 2.9 Shift In structions....................................................................................................57
Table 2.10 Branch Instr uction s ............................................................................................58
Table 2.11 System Contr ol Instructions................................................................................59
Table 2.12 Operation Code Map.......................................................................................... 62
Section 3 Memory Management Unit (MMU)
Table 3.1 Access States Design ated by D, C, and PR Bits....................................................... 80
Section 4 Cache
Table 4.1 Number of Entries and Size/Wayin Each Cache Size .............................................93
Table 4.2 LRU and WayReplacement (when Cache Locking Mechanism Is Disabled)...........95
Table 4.3 Way Replacemen t when a PREF In struction Misses the Cache................................99
Table 4.4 Way Replacement when Instructions other than
the PREF In struction Miss the Cache......................................................................99
Table 4.5 LRU an d Way Replacement (when W2LOCK = 1 and W3LOCK = 0)....................99
Table 4.6 LRU an d Way Replacement (when W2LOCK = 0 and W3LOCK = 1)....................99
Table 4.7 LRU an d Way Replacement (when W2LOCK = 1 and W3LOCK = 1)..................100
Table 4.8 Address Format Based on Size of Cach e to be Assigned to Memory......................106
Section 5 Exception Handling
Table 5.1 Exception Event Vector s ...................................................................................... 116
Section 6 Interrupt Controller (INTC)
Table 6.1 Pin Con figuration.................................................................................................127
Table 6.2 Interrupt Sources and IPRA to IPRH.....................................................................128
Table 6.3
Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)............................ 140
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IRL3toIRL0
Pins and Interrupt Levels ................................................................ 138
Page 43
Section 7 Bus State Controller (BSC)
Table 7.1 Pin Con figuration.................................................................................................151
Table 7.2 Physical Address Space Map................................................................................152
Table 7.3 Correspondence between External Pins (MD3 and MD4) and Memory Size..........154
Table 7.4 32-Bit External Device/Big Endian Access and Data Alignment............................181
Table 7.5 16-Bit External Device/Big Endian Access and Data Alignment............................182
Table 7.6 8-Bit External Device/Big Endian Access and Data Alignment .............................183
Table 7.7 32-Bit External Device/Little Endian Access and Data Alignment.........................184
Table 7.8 16-Bit External Device/Little Endian Access and Data Alignment.........................185
Table 7.9 8-Bit External Device/Little Endian Access and Data Alignment...........................186
Table 7.10 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (1)-1..................................................................201
Table 7.11 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (2)-1..................................................................203
Table 7.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (3).....................................................................205
Table 7.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (4)-1..................................................................206
Table 7.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (5)-1..................................................................208
Table 7.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0],
and Address Multiplex Output (6)-1..................................................................210
Table 7.16 Relationship between Access Size and Number of Bursts..................................212
Table 7.17 Access Address in SDRAM Mode Register Write.............................................229
Table 7.18 Relationship between Bus Width, Access Size, and Number of Bursts...............232
Section 8 Direct Memory Access Controller (DMAC)
Table 8.1 Pin Con figuration.................................................................................................241
Table 8.2 Transfer Request Sources.....................................................................................251
Table 8.3 Selecting External Request Modes with RS Bits....................................................254
Table 8.4 Selectin g External Request Detection with DL, DS Bits........................................255
Table 8.5 Selectin g External Request Detection with DO Bit ................................................255
Table 8.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits.........256
Table 8.7 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits.........256
Table 8.8 Supported DMA Transfers....................................................................................260
Table 8.9 Relation ship of Request Modes an d Bus Modes by DMA Transfer Category.........266
Section 9 Clock Pulse Generator (CPG)
Table 9.1 Clock Pulse Generator Pins and Fun ctions............................................................274
Table 9.2 Clock Operatin g Modes........................................................................................275
Table 9.3 Possi ble Combination of Clock Modes and FRQCR Values..................................276
Section 11 Power-Down Modes
Table 11.1 States of Power -Down Modes...........................................................................294
Rev. 2.00, 09/03, page xliii of xlvi
Page 44
Table 11.2 Pin Configuration.............................................................................................295
Section 12 Timer Unit (TMU)
Table 12.1 Pin Configuration.............................................................................................311
Table 12.2 TMU Interrupt Sources.....................................................................................322
Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.1 TPU Functions.................................................................................................330
Table 14.2 Pin Configuration.............................................................................................332
Table 14.3 TPU Clock Sources .......................................................................................... 335
Table 14.4 TPSC2 to TPSC0 (1)........................................................................................335
Table 14.4 TPSC2 to TPSC0 (2)........................................................................................335
Table 14.4 TPSC2 to TPSC0 (3)........................................................................................336
Table 14.4 TPSC2 to TPSC0 (4)........................................................................................336
Table 14.5 IOA2 to IOA0.................................................................................................. 338
Table 14.6 Register Combination s in Buffer Operation....................................................... 346
Section 15 Realtime Clock (RTC)
Table 15.1 Pin Configuration.............................................................................................353
Table 15.2 Recommended Oscillator Circuit Constants (Recommen ded Values).................372
Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.1 Pin Configuration.............................................................................................378
Table 16.2 SCSMR Settings for Serial Transfer Format Selection.......................................403
Table 16.3 Serial Transfer Formats....................................................................................404
Table 16.4 SCIF Interrupt Sources..................................................................................... 427
Section17 InfraredDataAssociationModule(IrDA)
Table 17.1 Pin Configuration.............................................................................................432
Section 18 USB Function Module
Table 18.1 Pin Configuration.............................................................................................439
Table 18.2 Command Decoding on Application Side.......................................................... 464
Section 19 Pin Function Controller
Table 19.1 Multiplex Pins.................................................................................................. 475
Section 20 I/O Ports
Table 20.1 Port A Data Register (PADR) Read/Write Operations.......................................508
Table 20.2 Port B Data Register (PBDR) Read/Write Operations .......................................509
Table 20.3 Port C Data Register (PCDR) Read/Write Operations .......................................511
Table 20.4 Port D Data Register (PDDR) Read/Write Operations.......................................512
Table 20.5 Port E Data Register (PEDR) Read/Write Operations........................................ 514
Table 20.6 Port F Data Register (PFDR) Read/Write Operations ........................................ 515
Table 20.7 Port G Data Register (PGDR) Read/Write Operations.......................................516
Table 20.8 Port H Data Register (PHDR) Read/Write Operations....................................... 517
Table 20.9 Port J Data Register (PJDR) Read/Write Operations..........................................519
Rev. 2.00, 09/03, page xliv of xlvi
Page 45
Table 20.10 Port K Data Register (PKDR) Read/Wr ite Operations.......................................520
Table 20.11 Port L Data Register (PLDR) Read/Write Operation .........................................521
Table 20.12 Port M Data Register (PMDR) Read/Write Operations......................................522
Table 20.13 Port N Data Register (PNDR) Read/Wr ite Operations.......................................524
Table 20.14 SC Por t Data Register (SCPDR) Read/Write Operations ...................................525
Section 21 A/D Converter
Table 21.1 Pin Configuration .............................................................................................529
Table 21.2 Analog Input Channels and A/D Data Register s ................................................530
Table 21.3 A/D Conversion Time (Single Mode)................................................................535
Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode) ........................................535
Table 21.5 A/D Converter Interrupt Source........................................................................536
Table 21.6 Analog In put Pin Ratings..................................................................................540
Section 22 User Break Controller
Table 22.1 Data Access Cycle Addresses and Operand Size Comparison Conditions ..........558
Section 23 User Debugging Interface (UDI)
Table 23.1 Pin Configuration .............................................................................................568
Table 23.2 UDI Commands ...............................................................................................570
Table 23.3 SH7705 Pins and Boundary Scan Register Bits.................................................571
Table 23.4 Reset Configuration..........................................................................................579
Section 25 Electrical Characteristics
Table 25.1 Absolute Maximum Ratings .............................................................................623
Table 25.2 DC Characteristics (1) [Common Items] ...........................................................625
Table 25.2 DC Characteristics (2-a) [Excluding USB- Related Pins]....................................627
Table 25.2 DC Characteristics (2-b) [USB-Related Pins*]..................................................628
Table 25.2 DC Characteristics (2-c) [USB Transceiver-Related Pins*
1
]..............................629
Table 25.3 PermittedOutput Curren t Values......................................................................629
Table 25.4 Maximum Operating Frequencies .....................................................................630
Table 25.5 Clock Timing ...................................................................................................631
Table 25.6 Control Signal Timing......................................................................................636
Table 25.7 Bus Timin g (1).................................................................................................638
Table 25.8 Bus Timin g (2).................................................................................................663
Table 25.9 DMAC Signal Timing ......................................................................................668
Table 25.10 TMU Signal Timing.........................................................................................669
Table 25.11 RTC Signal Timing ..........................................................................................670
Table 25.12 16-Bit Timer Pulse Unit (TPU) Signal Timing ..................................................670
Table 25.13 SCIF Module Signal Timing.............................................................................671
Table 25.14 USB Module Clock Timing..............................................................................672
Table 25.15 USB Transceiver Timing..................................................................................673
Table 25.16 Port Input/Output Timing .................................................................................674
Table 25.17 UDI Related Pin Timing...................................................................................675
Table 25.18 A/D Con verter Characteristics ..........................................................................678
Rev. 2.00, 09/03, page xlv of xlvi
Page 46
Appendix
Table A.1 I/O Port States in Each Processing State............................................................679
Rev. 2.00, 09/03, page xlvi of xlvi
Page 47
Section 1 Overview
1.1 SH7705 Features
This LSI is a microprocessor that integrates a 32-bit RISC-type SuperH architecture CPU as its
core, together with 32-kbyte cache memory as well as peripheral functions required for system
configuration such as an interrupt controller.
High-speed data transfers can be formed by an on-chip direct memory access controller (DMAC),
and an external memory access support function enables direct connection to different kinds of
memory. This LSI also includes powerful peripheral functions that are essential to system
configuration , such as USB (Function) functionality and a serial interface with a large FIFO.
A powerful built-in power-management function keeps power consumption low, even during
high-speed operation. This LSI is ideal for use in electronic devices such as those for applications
that require both high speeds and low power consumption.
The features of th is LSI are listed in table 1.1.
Rev. 2.00, 09/03, page 1 of 690
Page 48
Table 1.1 SH7705 Features
Item Features
CPU
Memory
management
unit (MMU)
• Original Renesas SuperH archite cture
• Compatible with SH-1, SH-2 and SH-3 at object code level
• 32-bit internal data bus
• General-registers
Sixteen 32-bit general registe rs (eigh t 32-bi t shadow registers)
Five 32-bit control registers
Four 32-bit system registers
• RISC-type instruction set
Instruction length: 16-bit fixed length and improved code efficie ncy
Load/store architecture
Delayed branch instruct ions
Instruction set based on C language
• Instruction execution time: one instruction/cycle for basic instructions
• Logical address space: 4 Gbytes
• Five-stage pipeline
• 4 Gbytes of address space, 256 address space identifiers (ASID: 8 bits)
• Page unit sharing
• Supports multiple page sizes: 1 kbyte or 4 kbytes
Cache memory
Interrupt
controller (INTC)
• 128-entry, 4-way set associative TLB
• Supports software selection of replacement method and random-
replacement algorithms
• Contents of TLB are directly accessible by addressmapping
• 32-kbyte cache, mixture of instructions and da ta
• 512 entries, 4-way set associative, 16-byte block length
• Write-back, write-through, LRU replacement algorithm
• 1-stage write-back buffer
• Seven external interrupt pins (NMI, IRQ5 to IRQ0)
• On-chip peripheral interrupt: Priority level is independently selected for each
module
Rev. 2.00, 09/03, page 2 of 690
Page 49
Item Features
Bus state
controller (BSC)
• Physical address space is divided into eight areas: area 0, areas 2 to 4;
each a maximum of 64 Mbytes, and areas 5A, 5B, 6A, 6B; each amaximum
of 32 Mbytes
• The following features are settable for each area
Bus size (8, 16, or 32 bits). The supported bus size differs for each area.
Number of access wait cycles (Numbers of wait-state cycles during reading
and writing are independently selectable for some are as.)
Setting of idle wait cycles (for the same area or different area)
Specifying the memory type to be connected to each area enables direct
connection to SRAM , byte selection SRAM, SDRAM, and burst ROM. Some
areas support address/data multiplex I/O (MPX).
Outputs chip select signal (
corresponding area (Programs are used to select the
CS0,CS2toCS4,CS5A/B,CS6A/B
CS
assert/negate
)for
timing.)
• SDRAM refresh function
Supports auto-refresh and self-refresh modes
• SDRAM burst access function
Direct memory
access controller
(DMAC)
Clock pulse
generator (CPG)
Watchdog timer
(WDT)
Different SDRAM can be connected to area 2 or area 3 (size/latency)
• Usable as either big or little endian machine
• Four channels. Two of these channels support external requests.
• Burst mode and cycle steal mode
• Outputs transfer end signal in channel with DREQ (one channel)
• Supports intermittent mode (supports 16 or 64 cycles)
• Clock mode: Input clock can be selected from external input (EXTAL o r
CKIO) or crystal resonator
• Three types of clocks gene rate d
CPU clock: max. 133.34 MHz/100 MHz
Bus clock: max. 66.67 MHz
Peripheral clock: max. 33.34 MHz
• Seven types of clock mode (selection of multiplicat ion ratio of PLL1 and
PLL2, and selection external clock or crys tal resonator)
• One-channe l watchdog timer
Power-down
mode
• Supports power-down mode
Sleep mode
Software standby mode and hardware standby mode
Module standby mode
Rev. 2.00, 09/03, page 3 of 690
Page 50
Item Features
Timer unit (TMU)
Compare match
timer (CMT)
16-bit timer pulse
unit (TPU)
Realtime clock
(RTC)
Serial
communication
interface
(SCIF_0,SCIF_2)
• Three-channel auto-reload-type 32-bit timer
• Input capture function (only channel 2)
• Five types of counter input clocks can be selected (Pφ/4, Pφ/16, Pφ/64,
Pφ/256, TCLK input)
• 16-bit counter
• Four types of clocks can be sele cted (Pφ/4, Pφ/8, Pφ/16, Pφ/64)
• Four PWM output (TO0, TO1, TO2, and TO3)
• Supports PWM function
• Clock and calendar functions (BCD format)
• 30-second adjust function
• Alarm/periodic/carry interrupt
• Automatic leap year adjustment
• Clock synchronous/asynchronous mode
• 64-byte transmit/receive FIFOs
• High-speed UART
USB function
module (USB)
I/O port
A/D converter
User break
controller (UBC)
• UART supports FIFO stop and FIFO trigger
• Supports
RTS/CTS
• Supports IrDA 1.0 (only channel 0)
• Conforms to USB 2.0 full-speed specification
• Supports modes with an on-chip and external USB transceiver
• Supports control transfer (endpoint 0), bulk transfer (endpoint 1, 2), and
interrupt transfer (endpoint 3)
• The USB standard commands are supp orted, and class and bender
commands are handled by firmware
• On-chip FIF O buffer for endpoints (128 bytes/endpoint 1, 2)
• Module input clock : 48 MHz
• Bitwise select ion of input/output for input/output port
• 10 bits ± 4 LSB, four channels
• Input range: 0 to AVcc (max. 3.6 V)
• Address, data value, access type, and data size are available for setting as
break conditions
• Supports the sequential break function
• Two break channels
Rev. 2.00, 09/03, page 4 of 690
Page 51
Item Features
User debugging
interface (UDI)
Power-supply
voltage
Product lineup
• Supports the E10A emulator
• JTAG-standard pin assignment
• Real-time branch trace (AUD)
• I/O: 3.3 ± 0.3 V, internal: 1.5 ± 0.1 V
Power Supply Voltage
Product
Name I/O
SH7705 3.3 ± 0.3 V 1.5 ± 0.1 V
On-chip
Modules
Operating
Frequency Product Code Package
133 MHz HD6417705F133
100 MHz HD6417705F100
133 MHz HD6417705BP133
100 MHz HD6417705BP100
208-pin
plastic
LQFP (FP208C)
208-pin
TFBGA
(TBP-208A)
Rev. 2.00, 09/03, page 5 of 690
Page 52
1.2 Block Diagram
Figure 1.1 shows an internal block diagram of the SH7705.
CACHE
CPG/WDT
Legend:
CACHE:
CCN:
MMU:
TLB:
INTC:
CPG/WDT:
CPU:
UBC:
AUD:
BSC:
DMAC:
CCN
MMU
I bus
TLB
INTC
External bus
interface
Cache memory
Cache memory controller
Memory management unit
Translation look-aside buffer
Interrupt controller
Clock pulse generator/watchdog timer
Central processing unit
User break controller
Advanced user debugger
Bus state controller
Direct memory access controller
L bus
I/O port
TMU:
TPU:
RTC:
CMT:
SCIF:
IrDA:
USB:
ADC:
UDI:
PFC:
SH3
CPU
UBC
AUD
Peripheral bus
BSC
DMAC
TMU
TPU
RTC
CMT
SCIF0/IrDA
SCIF2
USB
ADC
UDI
(PFC)
Timer unit
16-bit timer pulse unit
Realtime clock
Compare match timer
Serial communication interface with FIFO
Infrared data association module
Universal serial bus
A/D converter
User debugging interface
Pin function controller
Figure 1.1 Block Diagram of SH7705
Rev. 2.00, 09/03, page 6 of 690
Page 53
1.3 Pin Assignment
-PLL2
MD5
CC
V
-PLL2
-PLL1
SS
SS
V
V
-PLL1
CC
V
Q
SS
EXTAL
XTAL
V
MD2
MD1
MD0
ASEMD0/PTF7
ASEBRKAK/PTF6
TDO/PTF5
TRST/PTG3
TMS/PTG2
TCK/PTG1
Q
CC
TDI/PTG0
V
PTM3
PTM2
PTM1
PTM0
Q
SS
CC
NF*/PTM4
VSSNF*/PTJ7
NF*/PTJ6
NF*/PTJ5
NF*/PTJ4
NF*/PTJ3
NF*/PTJ2
NF*/PTJ1
NF*/PTJ0
AUDATA3/PTF3/TO3
AUDATA2/PTF2/TO2
AUDATA1/PTF1/TO1
V
V
AUDATA0/PTF0/TO0
Q
Q
CC
AUDSYNC/PTF4
TEND0/PTE3
DACK1/PTE1
DACK0/PTE0
V
WAIT/PTG7
V
SS
BREQ/PTG6
BACK/PTG5
PTD5/NF*
CKE/PTD4
CASU/PTD3
Q
SS
V
STATUS0/PTE4/RTS0
STATUS1/PTE5/CTS0
TxD0/SCPT0/IrTX
RxD0/SCPT0/IrRX
IRQ0/IRL0/PTH0
IRQ1/IRL1/PTH1
IRQ2/IRL2/PTH2
IRQ3/IRL3/PTH3
V
SS
CKIO
V
PTN0/SUSPND
PTN3/TXDMNS
CC
PTN1/TXENL
PTN2/XVDATA
PTN4/TXDPLS
PTN5/DMNS
PTN6/DPLS
PTN7
TCLK/PTE6
PTE7
SCK0/SCPT1
TxD2/SCPT2
SCK2/SCPT3
RTS2/SCPT4
V
CC
RxD2/SCPT2
V
SS
CTS2/SCPT5
V
RESETM
V
IRQ4/PTH4
IRQ5/PTE2
AUDCK/PTG4
NMI
DREQ0/PTH5
DREQ1/PTH6
RESETP
MD3
MD4
AV
AN0/PTL0
AN1/PTL1
AN2/PTL2
AN3/PTL3
AV
VSSQ
EXTAL_USB
XTAL_USB
V
CC
CA
119
118
117
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
157
158
Q
159
160
Q
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
Q
178
179
Q
180
181
182
SS
183
184
CC
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
SS
200
201
202
INDEX
203
204
CC
205
206
207
Q
208
SH7705
FP-208C
(Top view)
121
120
116
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051
111
115
114
113
112
110
109
108
107
106
105
104
CASL/PTD2
103
RASU/PTD1
102
RASL/PTD0
101
CS6B/PTD7
100
CS6A/PTC7
99
CS5B/PTD6
98
CS5A/PTC6
97
CS4/PTC5
96
CS3/PTC4
95
CS2/PTC3
94
CS0
93
RD/WR
92
WE3/DQMUU/AH/PTC2
91
WE2/DQMUL/PTC1
90
WE1/DQMLU
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
Q
V
CC
WE0/DQMLL
Q
V
SS
RD
BS/PTC0
A25/PTK7
A24/PTK6
A23/PTK5
A22/PTK4
V
CC
A21/PTK3
V
SS
A20/PTK2
A19/PTK1
A18
A17
A16
A15
Q
V
CC
A14
Q
V
SS
A13
A12
A11
A10
A9
A8
A7
A6
A5
Q
V
CC
A4
Q
V
SS
A3
A2
A1
A0/PTK0
52
Q
V
SS
D+
-USB
CC
V
D-
-RTC
-USB
SS
V
V
MD6
-RTC
XTAL2
SS
CC
EXTAL2
V
Q
Q
SS
CC
V
V
SS
V
Q
CC
V
Q
D15
SS
V
D11
D14
D13
D12
CC
V
D10
D9
D8
D7
D6
Q
Q
D5
D4
SS
CC
V
V
D3
D2
D1
Q
D0
SS
V
VBUS/PTM6
D19/PTA3/PINT3
D18/PTA2/PINT2
D17/PTA1/PINT1
D27/PTB3/PINT11
D31/PTB7/PINT15
D30/PTB6/PINT14
D26/PTB2/PINT10
D29/PTB5/PINT13
D28/PTB4/PINT12
D23/PTA7/PINT7
D22/PTA6/PINT6
D21/PTA5/PINT5
D20/PTA4/PINT4
D25/PTB1/PINT9
D24/PTB0/PINT8
D16/PTA0/PINT0
Note: * The initial functions of NF (No Function) pins are not assigned after power-on reset. Specifies the functions with Pin Function Controller (PFC).
Figure 1.2 Pin Assignment (FP-208C)
Rev. 2.00, 09/03, page 7 of 690
Page 54
ABCDEFGHJ KLMNPRTU
17
16
15
14
13
12
11
10
17
16
15
14
13
12
11
SH7705
9
8
7
6
5
TBP-208A
(Top view)
INDEX MARK
10
9
8
7
6
5
4
3
2
1
ABCDEFGHJ KLMNPRTU
Note: The terminal area surrounded by the dotted line is the perspective view.
Figure 1.3 Pin Assignment (TBP-208A)
4
3
2
1
Rev. 2.00, 09/03, page 8 of 690
Page 55
Table 1.2 Pin Functions
Pin No.
FP208C
TBP208A Pin Name I/O Description
1 A1 VssQ I/O power supply (0 V)
2 B1 Vcc-USB USB power supply (3.3 V)
3 C3 D+ I/O USB data line
4 C2 D- I/O USB data line
5 C1 Vss-USB USB power supply (0 V)
6 D3 Vcc-RTC
5
*
RTC power supply (3.3 V)
5
*
7 D2 XTAL2 O Crystal oscillator pin for on-chip RTC
8 D1 EXTAL2 I Crystal oscillator pin for on-chip RTC
9 E4 Vss-RTC
5
*
RTC power supply (0 V)
5
*
10 E3 VBUS/PTM6 I / I/O USB power supply detection / input/output port M
11 E2 MD6 I connect to I/O power supp ly (0V)
12 E1 D31/PTB7/PINT15 I/O / I/O / I Data bus / input/output port B / PINT interrupt
13 F4 D30/PTB6/PINT14 I/O / I/O / I Data bus / input/output port B / PINT interrupt
14 F3 D29/PTB5/PINT13 I/O / I/O / I Data bus / input/output port B / PINT interrupt
15 F2 D28/PTB4/PINT12 I/O / I/O / I Data bus / input/output port B / PINT interrupt
16 F1 D27/PTB3/PINT11 I/O / I/O / I Data bus / input/output port B / PINT interrupt
17 G4 VssQ I/O power supply (0 V)
18 G3 D26/PTB2/PINT10 I/O / I/O / I Data bus / input/output por t B / PINT inte rrupt
19 G2 VccQ I/O power supply (3.3 V)
20 G1 D25/PTB1/PINT9 I/O / I/O / I Data bus / input /output port B / PINT interrupt
21 H4 D 24/PTB0/PINT8 I/O / I/O / I Data bus / input/output port B / PINT interrupt
22 H3 D 23/PTA7/PINT7 I/O / I/O / I Data bus / input/output port A / PINT interrupt
23 H2 D 22/PTA6/PINT6 I/O / I/O / I Data bus / input/output port A / PINT interrupt
24 H1 D 21/PTA5/PINT5 I/O / I/O / I Data bus / input/output port A / PINT interrupt
25 J4 D20/PTA4/PINT4 I/O / I/O / I Data bus / input/output port A / PINT interrupt
26 J2 Vss Internal power supply (0 V)
27 J1 D19/PTA3/PINT3 I/O / I/O / I Data bus / input/output port A / PINT interrupt
28 J3 Vcc Internal power supply (1.5 V)
29 K1 D18/PTA2/PINT2 I/O / I/O / I Data bus / input/output port A / PINT interrupt
30 K2 D17/PTA1/PINT1 I/O / I/O / I Data bus / input/output port A / PINT interrupt
31 K3 D16/PTA0/PINT0 I/O / I/O / I Data bus / input/output port A / PINT interrupt
Rev. 2.00, 09/03, page 9 of 690
Page 56
Pin No.
FP208C
TBP208A Pin Name I/O Description
32 K4 VssQ I/O power supply (0 V)
33 L1 D15 I/O Data bus
34 L2 VccQ I/O power supply (3.3 V)
35 L3 D14 I/O Data bus
36 L4 D13 I/O Data bus
37 M1 D12 I/O Data bus
38 M2 D11 I/O Data bus
39 M3 D10 I/O Data bus
40 M4 D9 I/O Data bus
41 N1 D8 I/O Data bus
42 N2 D7 I/O Data bus
43 N3 D6 I/O Data bus
44 N4 VssQ I/O power supply (0 V)
45 P1 D5 I/O Data bus
46 P2 VccQ I/O power supply (3.3 V)
47 P3 D4 I/O Data bus
48 R1 D3 I/O Data bus
49 R2 D2 I/O Data bus
50 P4 D1 I/O Data bus
51 T1 D0 I/O Data bus
52 T2 VssQ I/O power supply (0 V)
53 U1 A0/PTK0 O / I/O Address bus / input/output port K
54 U2 A1 O Address bus
55 R3 A2 O Address bus
56 T3 A3 O Address bus
57 U3 VssQ I/O power supply (0 V)
58 R4 A4 O Address bus
59 T4 VccQ I/O power supply (3.3 V)
60 U4 A5 O Address bus
61 P5 A6 O Address bus
62 R5 A7 O Address bus
63 T5 A8 O Address bus
Rev. 2.00, 09/03, page 10 of 690
Page 57
Pin No.
FP208C
TBP208A Pin Name I/O Description
64 U5 A9 O Address bus
65 P6 A10 O Address bus
66 R6 A11 O Address bus
67 T6 A12 O Addre ss bus
68 U6 A13 O Address bus
69 P7 VssQ I/O power supply (0 V)
70 R7 A14 O Address bus
71 T7 VccQ I/O power supply (3.3 V)
72 U7 A15 O Address bus
73 P8 A16 O Address bus
74 R8 A17 O Address bus
75 T8 A18 O Addre ss bus
76 U8 A19/PTK1 O / I/O Address bus / input/output port K
77 P9 A20/PTK2 O / I/O Address bus / input/output port K
78 T9 Vss Internal power supply (0 V)
79 U9 A21/PTK3 O / I/O Address bus / input/output port K
80 R9 Vcc Internal power supply (1.5 V)
81 U10 A22/PTK4 O / I/O Address bus / input/output port K
82 T10 A23/PTK5 O / I/O Address bus / input/output po rt K
83 R10 A24/PTK6 O / I/O Address bus / input/output port K
84 P10 A25/PTK7 O / I/O Address bus / input/output port K
85 U11
86 T11
BS
/PTC0 O / I/O Bus cycle start signal / input/outpu t por t C
RD
O Read strobe
87 R11 VssQ I/O power supply (0 V)
88 P11
WE0
/DQMLL O / O D7 to D0 select signal / DQM(SDRAM)
89 U12 VccQ I/O power supply (3.3 V)
90 T12
91 R12
WE1
/DQMLU O / O D15 to D8 select signal / DQM(SDRAM)
WE2
/DQMUL/PTC1 O / O / I/O
D23 to D16 select signal / DQM (SDRAM) /
input/output port C
92 P12
WE3
/DQMUU/AH/
PTC2
93 U13 RD/
94 T13
WR
CS0
O/O/O/
I/O
D31 to D24 select signal / DQM (SDRAM) /
address hold / input/output port C
O Re ad/write
O Chip select 0
Rev. 2.00, 09/03, page 11 of 690
Page 58
Pin No.
FP208C
95 R13
96 P13
97 U14
98 T14
99 R14
100 U15
101 T15
102 P14
TBP208A Pin Name I/O Description
CS2
/PTC3 O / I/O Chip select 2 / input/output port C
CS3
/PTC4 O / I/O Chip select 3 / input/output port C
CS4
/PTC5 O / I/O Chip select 4 / input/output port C
3
CS5A
CS5B
CS6A
CS6B
RASL
*
/PTC6 O / I/O Chip select 5A / input/output port C
3
*
/PTD6 O / I/O Chip select 5B / input/output port D
3
*
/PTC7 O / I/O Chip select 6A / input/output port C
3
*
/PTD7 O / I/O Chip select 6B / input/output port D
/PTD0 O / I/O Lower 32 Mbytes address RAS (SDRAM) /
input/output port D
3
103 U16
RASU
*
/PTD1 O / I/O
Upper 32 Mbytes address RAS (SDRAM) /
input/output port D
104 T16
CASL
/PTD2 O / I/O
Lower 32 Mbytes address CAS (SDRAM) /
input/output port D
105 U17 VssQ I/O power supply (0 V)
3
106 T17
CASU
*
/PTD3 O / I/O
Upper 32 Mbytes address CAS (SDRAM) /
input/output port D
107 R15 CKE/PTD4 O / I/O CK enable (SDRAM) / input/output port D
108 R16 PTD5/NF
109 R17
110 P15
BACK
BREQ
/PTG5 O / I/O Bus acknowledge / input/output port G
/PTG6 I / I/O Bus request / input/output port G
4
*
I Input port D / NF
4
*
111 P16 VssQ I/O power supply (0 V)
112 P17
WAIT
/PTG7 I / I/O Hardware wait request / input/output port G
113 N14 VccQ I/O power supply (3.3 V)
114 N15 DACK0/PTE0 O / I/O DM A acknowledge 0 / input/output port E
115 N16 DACK1/PTE1 O / I/O DM A acknowledge 1 / input/output port E
116 N17 TEND0/PTE3 O / I/O
DMA transfer end notification / input/output
port E
117 M14 AUDSYN C/PTF4 O / I/O AUD synchronous / input/output port F
118 M15 AUDATA0/PTF0/TO0 O / I/O / O
AUD data output / input/output port F / timer
output
119 M16 AUDATA1/PTF1 /TO1 O / I/O / O AUD data output / input/output port F / timer
output
120 M17 AUDATA2/PTF2 /TO2 O / I/O / O AUD data output / input/output port F / timer
Rev. 2.00, 09/03, page 12 of 690
output
Page 59
Pin No.
FP208C
121 L14 AUDA TA 3/PTF3/TO3 O / I/O / O
TBP208A Pin Name I/O Description
AUD data output / input/output port F / timer
output
122 L15 NF
123 L16 NF
124 L17 NF
125 K14 N F
126 K15 N F
127 K16 N F
128 K17 N F
129 J14 NF
4
*
/PTJ0 O NF
4
*
/PTJ1 O NF
4
*
/PTJ2 O NF
4
*
/PTJ3 O NF
4
*
/PTJ4 O NF
4
*
/PTJ5 O NF
4
*
/PTJ6 O NF
4
*
/PTJ7 O NF
4
*
/output port J
4
*
/output port J
4
*
/output port J
4
*
/output port J
4
*
/output port J
4
*
/output port J
4
*
/output port J
4
*
/output port J
130 J16 Vss Internal power supply (0 V)
131 J17 NF
4
*
/PTM4 I NF
4
*
/ input port M
132 J15 Vcc Internal power supply (1.5 V)
133 H17 VssQ I/O power supply (0 V)
134 H16 PTM0 I/O Input/output port M
135 H15 PTM1 I/O Input/output port M
136 H14 PTM2 I/O Input/output port M
137 G17 PTM3 I/O Input/output port M
138 G16 VccQ I/O power supply (3.3 V)
7
139 G15 TDI
140 G14 TCK
141 F17 TMS
142 F16
*
/PTG0 I / I/O Test data input (UDI) / input/output port G
7
*
/PTG1 I / I/O Test clock (UDI) / input/output port G
7
*
/PTG2 I / I/O Test mode select (UDI) / input/output port G
7
TRST
*1*
/PTG3 I/I/O Testreset(UDI)/input/outputportG
143 F15 TDO/PTF5 O / I/O Test data output (UDI) / input/output port F
144 F14
ASEBRKAK
/PTF6 O / I/O ASE break acknowledge (UDI) / input/output
port F
7
145 E17
ASEMD0
*2*
/PTF7 I / I/O ASE mode (UDI) / input/output port F
146 E16 MD0 I Clock mode setting
147 E15 MD1 I Clock mode setting
148 E14 MD2 I Clock mode setting
149 D17 Vcc-PLL1 PLL1 power supply (1.5 V)
150 D16 Vss-PLL1 PLL1 power supply (0 V)
Rev. 2.00, 09/03, page 13 of 690
Page 60
Pin No.
FP208C
TBP208A Pin Name I/O Description
151 D15 Vss-PLL2 PLL2 power supply (0 V)
152 C17 Vcc-PLL2 PLL2 power supply (1.5 V)
153 C16 MD5 I Endian setting
154 D14 XTAL O Crystal oscillator pin
155 B17 EXTAL I External clock / crystal oscillator pin
156 B16 VssQ I/O power supply (0 V)
157 A17
158 A16
STATUS0/PTE4/
RTS0
STATUS1/PTE5/
CTS0
O/I/O/O
O/I/O/I
Processor status / input/output port E / SCIF0
transmit reque st
Processor status / input/output port E / SCIF0
transmit clear
159 C15 VssQ I/O power supply (0 V)
160 B15 CKIO I/O System clock input/output
161 A15 VccQ I/O power supply (3.3 V)
162 C14 PTN0/SUSPND I/O / O input/output port N / USB suspend
163 B14 PTN1/TXENL I/O / O input/output port N / USB output enable
164 A14 PTN2/XVDATA I/O / I input/output port N / USB differential receive
input
165 D13 PTN3/TXDMNS I/O / O input/output port N / USB D– transmit output
166 C13 PTN4/TXDPLS I/O / O input/output port N / USB D+ transmit output
167 B13 PTN 5/DM NS I/O / I
input/output port N / D– input from USB
receiver
168 A13 PTN6/DPLS I/O / I input/output port N / D+ input from USB
receiver
169 D12 PTN7 I/O input/output port N
170 C12 TCLK/PTE6 I / I/O TMU clock input / input/output port E
171 B12 PTE 7 I/O Input/output port E
172 A12 TxD0/SCPT0/IrTX O / O / O SCIF0 transmit data / SC port / IrDA TX port
173 D11 SCK0/SCPT1 I/O / I/O SCIF0 clock / SC port
174 C11 TxD2/SCPT2 O / O SCIF2 transmit data / SC port
175 B11 SCK2/SCPT3 I/O / I/O SCIF2 clock / SC port
176 A11
RTS2
/SCPT4 O / I/O SCIF2 transmit request / SC port
177 D10 RxD0/SCPT0/IrRX I/I/I SCIF0receivedata/SCport/IrDARXport
178 C10 VccQ I/O power supply (3.3 V)
179 B10 RxD2/SCPT2 I / I SCIF2 receive data / SC port
Rev. 2.00, 09/03, page 14 of 690
Page 61
Pin No.
FP208C
TBP208A Pin Name I/O Description
180 A10 VssQ I/O power supply (0 V)
181 D9
CTS2
/SCPT5 I / I/O SCIF2 transmit clear / SC port
182 B9 Vss I/O power supply (0 V)
183 A9
RESETM
I Manual reset request
184 C9 Vcc Internal power supply (1.5 V)
185 A8 IRQ0/
186 B8 IRQ1/
187 C8 IRQ2/
188 D8 IRQ3/
IRL0
/PTH0 I/I/I/O Externalinterruptrequest/input/output port H
IRL1
/PTH1 I/I/I/O Externalinterruptrequest/input/output port H
IRL2
/PTH2 I/I/I/O Externalinterruptrequest/input/output port H
IRL3
/PTH3 I/I/I/O Externalinterruptrequest/input/output port H
189 A7 IRQ4/PTH4 I / I/O External interrupt reque st / input/output port H
190 B7 IRQ5/PTE2 I / I/O External interrupt request / input/output port E
191 C7 AUDCK/PTG4 O / I/O AUD clock / input/output port G
192 D7 NMI I Nonmaskable interrupt request
193 A6 DREQ0/PTH5 I / I/O DMA request / input/output port H
194 B6 DREQ1/PTH6 I / I/O DMA request / input/output port H
6
195 C6
RESETP
*
I Power-on reset request
196 D6 CA I Hardware standby request
197 A5 MD3 I Area 0 bus width setting
198 B5 MD4 I Area 0 bus width setting
199 C5 AVss Analog power supply (0 V)
200 D5 AN0/PTL0 I / I A/D converter input / input port L
201 A4 AN1/PTL1 I / I A/D converter input / input port L
202 B4 AN2/PTL2 I / I A/D converter input / input port L
203 C4 AN3/PTL3 I / I A/D converter input / input port L
204 A3 AVcc Analog power supply (3.3 V)
205 B3 VssQ I/O power supply (0 V)
206 D4 EXTAL_USB I USB clock
207 A2 XTAL_USB O USB clock
208 B2 VccQ I/O power supply (3.3 V)
Notes: The unused pins should be handled according to table A.1, I/O Port States in Each
Processing State, in Appendix.
1. The
TRST
pin must be driven low for a specified period when power supply is turned on
regardless of whether the UDI function is used or not. As the same as the
the
TRST
pin should be driven low at the power-on set state and driven high after the
power-on reset state is released.
RESETP
pin,
Rev. 2.00, 09/03, page 15 of 690
Page 62
2. The input level of the
ASEMD0
pin must be high if the E10A emulator is not used. For
details, refer to section 23.4.2 , Reset Configuration.
3. These pins are initialized to the general input port setting in which the pull-up MOS is off
at a power-on rese t. When these pins are connected to memory and so on, their levels
must be fixed externally.
4. The initial functions of NF (No Function) pins are not assigned after power-on reset.
Specifies the functions with Pin Function Cont roller (PFC).
5. In hardware standby mode, supply power to all power supply pins including the RTC
power supply pins.
6. Pull-up MOS connecte d .
7. The pull-up MOS turns on if the pin function controller (PFC) is used to select other
functions (UDI).
Rev. 2.00, 09/03, page 16 of 690
Page 63
1.4 Pin Functions
Table 1.3 lists the pin functions.
Table 1.3 Pin Functions
Classification Symbol I/O Name Function
Power supply
Clock
Vcc Power supply
Vss Ground
VccQ Power supply Power supply for I/O pins. Connect
VssQ Ground Ground pin. Connect all VssQ pins
Vcc-PLL1 PLL1 power
supply
Power supply for the internal
modules and ports for the system.
Connect all Vcc pins to the system
power supply. There will be no
operation if any pins are open.
Ground pin. Connect all Vss pins to
the system power supply (0 V).
Therewillbenooperationifany
pins are open.
all VccQ pins to the system power
supply. There will be no operation
if any pins are open.
to the system power supply(0 V).
Therewillbenooperationifany
pins are open.
Power supply for the on-chip PLL1
oscillator.
Vss-PLL1 PLL1 ground
Vcc-PLL2 PLL2 power
supply
Vss-PLL2 PLL2 ground Ground pin for the on-chip PLL2
EXTAL I External clock
XTAL O Crystal
CKIO I/O System clock Supplies the system clock to
Ground pin for the on-chip PLL1
oscillator.
Power supply for the on-chip PLL2
oscillator.
oscillator.
For connection to a crystal
resonator. An external clock signal
mayalsobeinputtotheEXTAL
pin.
For connection to a crystal
resonator.
external device s.
Rev. 2.00, 09/03, page 17 of 690
Page 64
Classification Symbol I/O Name Function
Operating mode
control
System control
MD6 to MD0 I Mode set Sets the operating mode. Do not
change values on these pins
during operation.
MD2 to MD0 set the clock mode,
MD3 and MD4 set the bus-width
mode of area 0 and MD5 sets the
endian. MD6 pin should be
connected to VssQ.
RESETP
I Power-on reset
Whenlow, the system enters the
power-on reset state.
RESETM
I Manual reset When low, the system enters the
manual reset state.
STATUS1,
O Status output Indicates the operating state.
STATUS0
BREQ
I Bus request
Low when an external device
requests the release of the bus
mastership.
BACK
O Bus request
acknowledge
Indicates that the bus mastership
has been release d to an external
device. Reception of the
BACK
signal informs the device which
has output the
BREQ
signal that it
has acquired the bus.
CA I Chip active
High in normal operation, and low
in hardware standby mode.
Interrupts
NMI I Non-maskable
interrupt
Non-maskable interrupt request
pin. Fix to high level when not in
use.
IRQ5to IRQ0 I
Interrupt
requests 5 to 0
Maskable interrupt request pin.
Selectable as level input or edge
input. The rising edge or falling
edge is selectable as the dete ction
edge. The low leve l or high level is
selectable as the dete ction level.
IRL3toIRL0
PINT15 to
PINT0
I
Interrupt
requests 3 to 0
I Interrupt
requests15to0
Maskable interrupt request pin.
Input a coded interrupt level.
PINTinterrupt request pin.
Address bus A25 to A0 O Address bus Outputs addresses.
Data bus D31 to D0 I/O Data bus 32-bit bidirectional data bus.
Rev. 2.00, 09/03, page 18 of 690
Page 65
Classification Symbol I/O Name Function
Bus control
CS0
,
CS2toCS4
CS5A,CS5B
CS6A,CS6B
RD
RD/
WR
BS
WE3
WE2
WE1
WE0
O Chip select 0,
,
,
2to4,5A,5B,
6A, 6B
Chip-select signal for external
memory or devices.
,
ORead
Indicates reading of data from
external device s.
O Read/write Read/write signal.
O Bus start Bus-cycle start.
O Highest-byte
write
Indicatesthatbits31to24ofthe
data in the external memory or
device are being written.
O Second-highest-
byte write
Indicatesthatbits23to16ofthe
data in the external memory or
device are being written.
O
Second-lowestbyte write
Indicatesthatbits15to8ofthe
data in the external memory or
device are being written.
O
Lowest-byte
write
Indicates that bits 7 to 0 of the data
in the external memory or device
are being written.
CKE O CK enable Clock enable. (SDRAM)
DQMUU O DQ mask UU Selects D31 to D24. (SDRAM)
DQMUL O DQ mask UL Selects D23 to D16. (SDRAM)
DQMLU O DQ mask LU Selects D15 to D8. (SDRAM)
DQMLL O DQ mask LL Selects D7 to D0. (SDRAM)
RASU
RASL
CASU
O Row address U Specifies a row address. (SDRAM)
O Row address L Specifies a row address. (SDRAM)
O Column addressUSpecifies a column address.
(SDRAM)
CASL
O
Column addressLSpecifies a column address.
(SDRAM)
AH
WAIT
O Address hold Address hold signal.
IWait
Inserts a wait cycleinto the bus
cycles during access to the
external space.
Rev. 2.00, 09/03, page 19 of 690
Page 66
Classification Symbol I/O Name Function
Direct memory
access controller
(DMAC)
DREQ0,
DREQ1
DACK0,
DACK1
I DMA-transfer
request
O
DMA-transfer
strobe
TEND0 O DMA-transfer
end
Timer unit (TMU) TCLK I Clock input
16-bit timer pulse
TO3 to TO0 O Timer output Output compare/PWM output pin.
unit (TPU)
Serial
communication
TxD0, TxD2 O Transmit data Transmit data pin.
RxD0, RxD2 I Receive data Receive data pin.
interface with
FIFO
(SCIF0, SCIF2)
SCK0, SCK2 I/O Serial clock Clock input/output pin.
RTS0,RTS2
O Transmit
request
CTS0,CTS2
I Transmit enable Modem control pin.
Input pin for external requests for
DMA transfer.
Output strobe to external I/O, in
response to external requests for
DMA transfer.
Transfer end output for DMAC
channel 0.
External clock input pin/input
capture control input pin.
Modem control pin.
Realtime clock
(RTC)
A/D converter
(ADC)
IrTX O IrDA TX port IrDA transmit data output.IrDA
IrRX I IrDA RX port IrDA receive data input.
EXTAL2 I RTC clock RTC crystal oscillator pin. (32.768
kHz)
XTAL2 O RTC clock
RTC crystal oscillator pin. (32.768
kHz)
Vcc-RTC RTC power
Power supply pin for the RTC.
supply
Vss-RTC RTC ground Ground pin for the RTC.
AN3 to AN0 I Analog input pin Analog input pin.
AVcc
A/D analog
power supply
Power supply for the A/D
converter. W hen theA/D converter
is not in use, connect this pin to the
port power supply (VccQ) .
AVss
A/D analog
ground
Ground pin for the A/D converter.
Connect this pin to the system
power supply (Vss).
Rev. 2.00, 09/03, page 20 of 690
Page 67
Classification Symbol I/O Name Function
USB
EXTAL_USB I USB clock USB clock input pin. (48-MHz
input)
XTAL_USB O USB clock USB clock pin.
XVDATA I Data input
Receive data input pin from the
differential receiver.
VBUS I
USB power
USB-cable connection-monitor pin.
supply detection
TXDPLS O D+ output D+ transmit output pin for the
driver.
TXDMNS O D− output
D− transmit output pin for the
driver.
DPLS I D+ input D+ signal input pin from the
receiver to the driver.
DMNS I D− input
D− signal input pin from the
receiver to the driver.
TXENL O Output enable Output enable pin for the driver.
SUSPND O Suspend
Suspend-state ou tput pin for the
transceiver.
Vcc-USB USB analog
power supply
USB power supply pin. When the
USB is not in use, connect this pin
to the port power supply (VccQ).
Vss-USB USB analog
ground
USB ground pin. Connect this pin
to the system power supply(Vss).
D− I/O D− I/O On-chip USB transceiver D−.
D+ I/O D+ I/O On-chip USB transceiver D+.
Rev. 2.00, 09/03, page 21 of 690
Page 68
Classification Symbol I/O Name Function
I/O port
PTA7 to PTA0 I/O General
purpose port
PTB7 to PTB0 I/O
General
purpose port
PTC7 to PTC0 I/O General
purpose port
PTD7 to PTD0 I/O
General
purpose port
PTE7 to PTE0 I/O General
purpose port
PTF7 to PTF0 I/O
General
purpose port
PTG7to PTG0 I/O General
purpose port
PTH6 to PTH0 I/O General
purpose port
PTJ7 to PTJ0 O
General
purpose port
8-bit general-purpose I/O port pins .
8-bit general-purpose I/O port pins .
8-bit general-purpose I/O port pins .
8-bit general-purpose I/O port pins .
8-bit general-purpose I/O port pins .
8-bit general-purpose I/O port pins .
8-bit general-purpose I/O port pins .
7-bit general-purpose I/O port pins .
8-bit general-purpose output port
pins.
PTK7 to PTK0 I/O General
purpose port
PTL3 to PTL0 I
General
purpose port
PTM6, PTM4 to
PTM0
PTN7 to PTN0 I/O
I/O General
purpose port
General
purpose port
SCPT5 to
I/O Serial port 6-bit serial port pins.
SCPT0
8-bit general-purpose I/O port pins .
4-bit general-purpose input port
pins.
6-bit general-purpose I/O port pins .
8-bit general-purpose I/O port pins .
Rev. 2.00, 09/03, page 22 of 690
Page 69
Classification Symbol I/O Name Function
User debugging
interface
(UDI)
Advanced user
debugger
(AUD)
E10A interface
TCK I Test clock Test-clock input pin.
TMS I Test mode
Inputs the test-mode select signal.
select
TDI I Test data input
Serial input pin for instructions and
data.
TDO O
TRST
AUDATA3 to
I Test reset Initial-signal input pin.
O AUD data
AUDATA0
Test data
output
Serial output pin for instructions
and data.
Destination-address output pin in
branch-trace mode.
AUDCK O AUD clock Synchronous clock output pin in
branch-trace mode.
AUDSYNC O
ASEBRKAK
O Break mode
AUD
synchronous
signal
acknowledge
Data start-position acknowledge-
signal output pin in branch-trace
mode.
Indicates that the E10A emulator
has entered its break mode.
ASEMD0
For the connection with the E10A,
see the SH7705 E10A E mulator
User’s Manual (tentative title).
I ASE mode Sets ASE mode.
Rev. 2.00, 09/03, page 23 of 690
Page 70
Rev. 2.00, 09/03, page 24 of 690
Page 71
Section 2 CPU
2.1 Processing States and Processing Modes
2.1.1 Processing States
This LSI supports four types of processing states: a reset state, an exception handling state, a
program execution state, and a low-power consumption state, according to the CPU processing
states.
Reset State: In the reset state, the CPU is reset. The LSI supports two types of resets: power-on
reset and manual reset. For details on resets, refer to section 5, Exception Handling.
In power-on reset, the registers and internal statuses of all LSI on-chip modules are initialized. In
manualreset, the register contents of a part of the LSI on-chip modules, such as the bus state
controller (BSC), are retained. For details, r efer to section 24, List of Registers. The CPUinternal
statuses and registers are initialized both in power-on reset and manual reset. After initialization,
the program branches to address H'A0000000 to pass control to the reset processing program to be
executed.
Exception Handling State: In the exception handling state, the CPU processing flow is changed
temporarily by a general exception or interrupt exception processing. The program counter (PC)
and status register (SR) are saved in the save program counter (SPC) and save status register
(SSR), respectively. The program branches to an address obtained by adding a vector offset to the
vector base register (VBR) and passes control to the exception processing program defined by the
user to be executed. For details on reset,refer to section 5, Exception Handling.
Program Execution State: The CPU executes pr ograms sequentially.
Low-Power Consumption State: The CPU stops operation to reduce power consumption. The
low-power consumption state can be enter ed by executing the SLEEP instruction. For details on
the low-power consumption state, refer to section 11, Power-Down Modes.
Figure 2.1 sh ows a statustransition diagram.
CPUS3D0S_000020020300
Rev. 2.00, 09/03, page 25 of 690
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2.1.2 Processing Modes
This LSI supports two processing modes: user mode and privileged mode. These processing
modes can be determined by the processing mode bit (MD) of the status register (SR). If the MD
bit is cleared to 0, the user mode is selected. If the MD bit is set to 1, the privileged mode is
selected. The CPU enters the privileged mode by a transition to reset state or exception handling
state. In the privileged mode, any registers and resources in address spaces can be accessed.
Clearing the MD bit of the SRto0 puts theCPUin the user mode. In the user mode, some of the
registers, including SR, and some of the address spaces cannot be accessed by the user program
and system control instructions cannot be executed. This function effectively protects the system
resources from the user program. To change the processing mode from user to privileged mode, a
transition to exception handling state is required.*
Note: * To call a service routine used in privileged mode from user mode, the LSI supports an
unconditional trap instruction (TRAPA). When a transition from user mode to
privileged mode occurs, the contents of the SR and PC are saved. A program execution
in user mode can be resumed by restoringthe contents of the SR and PC. Toreturn
from an exception processing program, the LSI supports an RTE instruction.
(From any states)
Power-on reset
Manual reset
Multiple
exceptions
Exception handling state
Reset processing
Reset state
Exception
handling
routine starts
routine starts
An exception
is accepted
An exception
is accepted
Figure 2.1 Processing State Transitions
Program execution state
SLEEP instruction
Low-power
consumption state
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2.2 Memory Map
2.2.1 Logical Address Space
The LSI supports 32-bit logical addresses and accesses system resources using the 4-Gbytes of
logical address space. User programs and data are accessed from the logical address space. The
logical address space is divided into several areas as shown in table 2.1.
P0/U0 Area: This area is called the P0 area when the CPU is in privileged mode and the U0 area
when in user mode. For the P0 and U0 areas, access using the cache is enabled. The P0 and U0
areas are handled as address translatable areas.
If the cache is enabled, access to the P0 or U0 area is cached. If a P0 or U0 address is specified
while the address translation unit is enabled, the P0 or U0 address is translated into a physical
address based on translation information defined by the user.
If the CPU is in user mode, only the U0 area can be accessed. If P1, P2, P3, or P4 is accessed in
user mode, a transition to an address error exception occurs.
P1 Area: The P1 area is defined as a cacheable but non-address translatable area. Normally,
programs executed at high speed in privileged mode, such as exception processing handlers, which
are at the core of the operating system (S), are assigned to the P1 area.
P2 Area: The P2 area is defined as a non-cacheable but non-address translatable area. A reset
processing program to be called from the reset state is described at the start address (H'A0000000)
of the P2 area. Normally, programs such as system initialization routines and OS initiation
programs are assigned to the P2 area. To access a part of an on-chip module control register, its
corresponding program should be assigned to the P2 area.
P3 Area: The P3 area is defined as a cacheable and address translatable area. This area is used if
an address translation is required for a privileged program.
P4 Area: The P4 area is defined as a control area which is non-cacheable and non-address
translatable. This area can be accessed only in privileged mode. A part of this LSI's on-chip
module control register is assigned to this area.
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Table 2.1 Logical Address Space
Address
Range Name Mode Description
H’00000000 to
H’7FFFFFFF
H’80000000 to
H’9FFFFFFF
H’A0000000 to
H’BFFFFFFF
H’C0000000 to
H’DFFFFFFF
H’E0000000 to
H’FFFFFFFF
P0/U0 Privileged/user mode
P1 Privileged mode 0.5-Gbyte physical space, cacheable
P2 Privileged mode 0.5-Gbyte physical space, non-cacheable
P3 Privileged mode 0.5-Gbyte physical space, cacheable,
P4 Privileged mode 0.5-Gbyte control space , non-cacheable
2-Gbyte physical space, cacheable, address
translatable
In user mode, only this address space can
be accessed.
address translatable
2.2.2 External Memory Space
The LSI uses 29 bits of the 32-bit logical address to access external memory. In this case, 0.5Gbyte of external memory space can be accessed. The external memory space is managed in area
units. Different types of memory can be connected to each area, as shown in figure 2.2. For
details, please r efer to section 7, Bus State Controller (BSC). In addition, area 1 in the external
memory space is used as an on-chip I/O space where most of this LSI's on-chip module control
registers are mapped. *
1
Normally, the upper three bits of the 32-bit logical address are masked and the lower 29 bits are
used for external memory addresses.*
2
For example, address H'00000100 in the P0 area, address
H'80000100 in the P1 area, address H'A0000100 in the P2 area, and address H'C0000100 in the P3
area of the logical address space are mapped into address H'00000100 of area 0 in the external
memory space. The P4 area in the logical address space is not mapped into the external memory
address. If an address in the P4 area is accessed, an external memory cannot be accessed.
Notes: 1. To access an on-chip module control register mapped into area 1 in the external
memory space, access the address from the P2 area which is not cached in the logical
address space.
2. If the addresstranslation unit is enabled, arbitrary mapping in page units can be
specified. For details, refer to section 3, Memory Management Unit (MMU).
Rev. 2.00, 09/03, page 28 of 690
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External memory space
H'0000 0000 H'0000 0000
P0 area
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
U0 area
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
P1 area
P2 area
Address error
P3 area
P4 area
Privileged mode User mode
H'8000 0000
H'FFFF FFFF
Figure 2.2 Logical Address to External Memory Space Mapping
2.3 Register Descriptions
This LSI provides thirty-three 32-bit registers: 24 generalregisters, five control registers, three
system registers, and one program counter.
General Registers: This LSI incorporates 24 general registers: R0_BANK0 to R7_BANK0,
R0_BANK1 to R7_BANK1 and R8 to R15. R0 to R7 are banked. The process mode and the
register bank (RB) bit in the status register (SR) define which set of banked registers (R0_BANK0
to R7_BANK0 or R0_BANK1 to R7_BANK1) are accessed as general registers.
SystemRegisters: This LSI incorporates the multiply and accumulateregisters (MACH/MACL)
and procedure register (PR) as system registers. These registers can be accessed regardless of the
processing mode.
Program Counter: The program counter stores the value obtained by adding 4 to the current
instruction address.
Control Registers: This LSI incorporates the statusregister (SR), global base register (GBR),
save status register (SSR), save program counter (SPC), and vector base register (VBR) as control
register. Only the GBR can be accessed in user mode. Control registers other than the GBR can be
accessed only in privileged mode.
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Table 2.2 shows the register values after reset. Figure 2.3 shows the register configurations in each
process mode.
Table 2.2 Register Initial Values
Register Type Registers Initial Values
General registers R0_BANK0 to R7_BANK0,
Undefined
R0_BANK1 to R7_BANK1,
R8 to R15
System registers MACH, MACL, PR Undefined
Program counter PC H’A0000000
Control registers
SR
MD bit = 1, RB bit = 1, BL bit = 1, I3 to I0
bits = H’F (1111), reserved b its = all 0, othe r
bits = undefined
GBR, SSR, SPC Undefined
VBR H’00000000
Note:* Initialized by a power-on or manual reset.
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31
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
R8
R9
R10
R11
R12
R13
R14
R15
*1 *2
*2
*2
*2
*2
*2
*2
*2
31
0
R0_BANK1
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
*1 *3
*3
*3
*3
*3
*3
*3
*3
R8
R9
R10
R11
R12
R13
R14
R15
31
0
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
*1 *4
*4
*4
*4
*4
*4
*4
*4
0
R8
R9
R10
R11
R12
R13
R14
R15
SR
GBR
MACH
MACL
PR
PC
(a) User mode register
configuration
SR
SSR
GBR
MACH
MACL
PR
VBR
PC
SPC
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
*1 *4
*4
*4
*4
*4
*4
*4
*4
(b) Privileged mode register
configuration (RB = 1)
SR
SSR
GBR
MACH
MACL
PR
VBR
PC
SPC
R0_BANK1
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
*1 *3
*3
*3
*3
*3
*3
*3
*3
(c) Privileged mode register
configuration (RB = 0)
Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode
and indexed GBR indirect addressing mode.
2. Bank register
3. Bank register
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
4. Bank register
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
Figure 2.3 Register Configuration in Each Processing Mode
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2.3.1 General Registers
There are twenty-four 32-bit general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to
R7_BANK1, and R8 to R15. R0 to R7 are banked. The process mode and the register bank (RB)
bit in the status register (SR) define which set of banked registers (R0_BANK0 to R7_BANK0 or
R0_BANK1 to R7_BANK1) are accessed as general registers. R0 to R7 registers in the selected
bank are accessed as R0 to R7. R0 to R7 in the non-selected bank is accessed as R0_BANK to
R7_BANK by the control register load instruction (LDC) and control register store instruction
(STC).
In user mode, bank 0 is selected regardless of he RB bit value. Sixteen registers: R0_BANK0 to
R7_BANK0 and R8 to R15 are accessed as general registers R0 to R15. The R0_BANK1 to
R7_BANK1 registers in bank 1 cannot be accessed.
In privileged mode that is entered by a transition to exception handling state, the RB bit is set to 1
to select bank 1. In privileged mode, sixteen registers: R0_BANK1 to R7_BANK1 and R8 to R15
are accessed as general registers R0 to R15. A bank is switched automatically when an exception
handling state is entered, register s R0 to R7 need not be saved by the exception handling routine.
The R0_BANK0 to R7_BANK0 registers in bank 0 can be accessed as R0_BANK to R7_BANK
by th e LDC and STC instructions.
In privileged mode, bank 0 can also be used as general registers byclearing the RB bit to 0. In this
case, sixteen registers: R0_BANK0 to R7_BANK0 and R8 to R15 are accessed as general
registers R0 to R15. The R0_BANK1 to R7_BANK1 registers in bank 1 can be accessed as
R0_BANK to R7_BANK by the LDC and STC instructions.
The gen eral registers R0 to R15 are used as equivalent registers for almost all instructions. In
some instruction s, the R0 register is automaticallyused or only the R0 register can be used as
source or destination registers.
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31
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
*1 *2
*2
*2
*2
*2
*2
*2
*2
0
General Registers: Undefined after reset
Notes: 1. R0 functions as an index register in the indexed
register-indirect addressing mode and indexed
GBR-indirect addressing mode. In some
instructions, only R0 can be used as the source
or destination register.
2. R0−R7 are banked registers. In user mode,
BANK0 is used. In privileged mode, either
R0_BANK0 to R7_BANK0 or R0_BANK1 to
R7_BANK1 is selected by the RB bit of the SR
register.
Figure 2.4 General Registers
2.3.2 System Registers
The system registers: multiplyand accumulate registers (MACH/MACL) and procedure register
(PR) as system registers can be accessed by the LDS and STS instructions.
Multiply and Accumulate Registers (MACH/MACL): The multiplyand accumulate registers
(MACH/MACL) store the results of multiplication and accumulation instructions or multiplication
instructions. The MACH/MACL register s also store addition values for the multiplication and
accumulations. After reset, these registers are undefined. The MACH and MACL registers store
upper 32 bits and lower 32 bits, respectively.
Procedure Register (PR): The procedure register (PR) stores the return address for a subroutin e
call using the BSR, BSRF, or JSR instruction. The return address stored in the PR register is
restored to the program counter (PC) by the RTS (return from the subroutine) instruction. After
reset, this register is undefined.
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2.3.3 Program Counter
The program counter (PC) stores the value obtained by adding 4 to the current instruction address.
There is no instruction to read the PC directly. Before an exception handling state is entered, the
PC is saved in the save program counter (SPC). Before a subroutine call is executed, the PC is
saved in the procedur e register (PR). Inaddition, the PC can be used for PC relative addressing
mode.
Figure 2.5 sh ows the system register and program counter configurations.
Multiply and accumulate high and low registers (MACH/MACL)
31 0
MACH
MACL
Procedure register (PR)
31 0
PR
Program counter (PC)
31 0
PC
Figure 2.5 System Registers and Program Counter
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2.3.4 Control Registers
The control registers (SR, GBR, SSR, SPC, and VBR) can be accessed by the LDC or STC
instruction in privileged mode. The GBR register can be accessed in the user mode.
The control registers are described below.
Status Register (SR): The status register (SR) indicates the system status as shown below. The
SR register can be accessed only in privileged mode.
Initial
Bit Bit Name
31 0RReserved
30 MD 1 R /W Processing Mode
Value R/W Description
This bit is always read as 0. The write value should always be
0.
Indicates the CPU processing mode.
0: User mode
1: Privileged mode
The MD bit is set to 1 in reset or exception handling state.
29 RB 1 R/W Register Bank
The general registers R0 to R7 are banked registers. The RB
bit selects a bank used in the privileged mode.
0: Selects bank 0 registers. In this case , R0_BANK0 to
R7_BANK0 and R8 to R15 are used as general registers.
R0_BANK1 to R7_BANK1 can be accessed by the LDC or
STR instruction.
1: Selects bank 1 registers. In this case , R0_BANK1 to
R7_BANK1 and R8 to R15 are used as general registers.
R0_BANK0 to R7_BANK0 can be accessed by the LDC or
STR instruction.
The RB bit is set to 1 in reset or exception handling state.
28 BL 1 R/W Block
Specifies whether an exception, interrupt, or user break is
enabled or not.
27 to 10 0RReserved
0: Enables an exception, interrupt, or user break.
1: Disables an exception, interrupt, or user break.
The BL bit is set to 1 in reset or exception handling state.
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 35 of 690
Page 82
Bit Bit Name
Initial
Value R/W Description
9
8
7 to 4 I3 to I0 1 R/W Interrupt Mask
3, 2 0RReserved
1S R/W Saturation Mode
M
Q
R/W
R/W
MBit
QBit
These bits are used by the DIV0S, DIV0U , and D IV1
instructions. Thesebits can be changed even in user mode by
using the DIV0S, DIV0U, and DIV1 instructions. These bits
are undefined at reset. Thesebits do not change in an
exception handling state.
Indicates the interrupt mask level. These bits do not change
even if an interrupt occurs. At reset, these bits are initialized
to B’1111. These bits are not affected in an exception
handling state.
These bits are always read as 0. The write value should
always be 0.
Specifies the saturation mode for multiply instructions or
multiply and accumulate instructions. This bit can be specified
by the SETS and CLRS instructions in user mode.
At reset, this bit is undefined. This bit is not affected in an
exception handling state.
0T R/W T Bit
Indicates true or falsefor compare instructions or carry or
borrow occurrence for an operation instruction with carry or
borrow. This bit can be specified by the SETT and CLRT
instructions in user mode.
At reset, this bit is undefined. This bit is not affected in an
exception handling state.
Note: The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits
can be read or written in privileged mode.
Save Status Register (SSR): The save status register (SSR) can be accessed only in privileged
mode. Before enteringtheexception, the contents of the SR register is stored in theSSR register.
At reset, the SSR initial value is undefin ed.
Save Program Counter (SPC): The save program counter (SPC) can be accessed only in
privileged mode. Before entering the exception, the contents of the PC are stor ed in the SPC. At
reset, the SPC initial value is undefin ed.
Global Base Register (GBR): The global base register (GBR) is referenced as a base r egister in
GBR indirect addressing mode. At reset, the GBR initial value is undefined.
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Page 83
Vector Base Register (VBR): The global base register (GBR) can be accessed only in privileged
mode. If a transition from reset state to exception handling state occurs, this register is referenced
as a base address. For details, refer to section 5, Exception Handling. At r eset, the VBR is
initialized as H'00000000.
Figure 2.6 shows the control register configuration.
Save status register (SSR)
31 0
SSR
Save program counter (SPC)
31
SPC
Global base register (GBR)
31 0
GBR
Vector base register (VBR)
31
VBR
0
0
Status register (SR)
31 0
0
MD RB BL
0
TS00I0I1I2I3QM0
Figure 2.6 Control Register Configuration
2.4 Data Formats
2.4.1 Register Data Format
Register operands are always longwords (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31 0
Longword
Rev. 2.00, 09/03, page 37 of 690
Page 84
2.4.2 Memory Data Formats
Memory data formats are classified into byte, word, and longword. Memory can be accessed in
byte, word, and longword. When the memory operand is only a byte (8 bits) or a word (16 bits), it
is sign-extended into a longword when loaded into a register.
An address error will occur if word data starting from an address other than 2n or longword data
starting from an address other than 4n is accessed. In such cases, the data accessed cannot be
guaranteed.
When a word or longword operand is accessed, the byte positions on the memory correspon ding to
the word or longword data on the register is determined to the specified endian mode (big endian
or little endian).
Figure 2.7 shows a byte correspondence in big endian mode. In big endian mode, the MSB byte in
the register corresponds to the lowest address in the memory, and the LSB the in the register
correspon ds to the highest address. For example, if the contents of the general register R0 is stored
at an address indicated by the general register R1 in longword, the MSB byte of the R0 is stored at
the address indicated bythe R1 and the LSB byte of the R1 register is stored at the address
indicated by the (R1 +3).
The on-chip device registers assigned to memory are accessed in big endian mode. Note that the
available access size (byte, word, or long word) differs in each register.
Note: The CPU instruction codes of this LSI must be stored in word units. In big endian mode,
the instruction code must be stored from upper byte to lower byte in this order from the
word boundary of the memory.
Byte position
31
in R0
Byte position
in memory
@(R1+0) @(R1+1) @(R1+2) @(R1+3) @(R1+0) @(R1+1) @(R1+2) @(R1+3) @(R1+0) @(R1+1) @(R1+2) @(R1+3)
23 15 7 0
[7:0]
[7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
(a) Byte access
Example: MOV.B R0, @R1
(R1 = Address 4n)
(b) Word access
Example: MOV.W R0, @R1
(R1 = Address 4n)
[15:8]
[7:0]
[31:24] [23:16] [15:8] [7:0]
(c) Longword access
Example: MOV.L R0, @R1
(R1 = Address 4n)
Figure 2.7 Data Format on Memory (Big Endian Mode)
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The little endian mode can also be specified as data format. Either big-endian or little-endian mode
can be selected according to the MD5 pin at reset. When MD5 is low at reset, the processor
oper ates in big-endian mode. When MD5 ishigh at reset, the processor operates in little-endian
mode. The endian mode cannot be modified dynamically.
In little endian mode, the MSB byte in the register corresponds to the highest address in the
memory, and the LSB the in the register corresponds to the lowest address (figure 2.8). For
example, if the contents of th e general register R0 is stored at an address indicated by the general
register R1 in longword, the MSB byte of the R0 is stored at theaddress indicated bythe (R1+3)
and the LSB byte of the R1 register is stored at the address indicated by the R1.
If the little endian mode is selected, the on-chip device registers assigned to memory are accessed
in big endian mode. Note that the available access size (byte, word, or long word) differs in each
register.
Note: The CPU instruction codes of this LSI must be stored in word units. In little endian mode,
the instruction code must be stored from lower byte to upper byte in this order from the
word boundary of the memory.
Byte position
in R0
Byte position
in memory
31
@(R1+3) @(R1+2) @(R1+1) @(R1+0) @(R1+3) @(R1+2) @(R1+1) @(R1+0) @(R1+3) @(R1+2) @(R1+1) @(R1+0)
23 15 7 0
[7:0]
[7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
(a) Byte access
Example: MOV.B R0, @R1
(R1 = Address 4n)
[15:8] [7:0]
(b) Word access
Example: MOV.W R0, @R1
(R1 = Address 4n)
[31:24] [23:16] [15:8] [7:0]
(c) Longword access
Example: MOV.L R0, @R1
(R1 = Address 4n)
Figure 2.8 Data Format on Memory (Little Endian Mode)
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2.5 Features of CPU Core Instructions
2.5.1 Instruction Execution Method
Instruction Length: Allinstructionshaveafixedlengthof16bitsandareexecutedinthe
sequential pipeline. In the sequential pipeline, almost all instructions can be executed in one cycle.
All data items are handles in longword (32 bits). Memory can be accessed in byte, word, or
longword. In this case, Memory byte or word data is sign-extended and operated on as longword
data. Immediate data is sign-extended to longword size for arithmetic operations (MOV, ADD,
and CMP/EQ instructions) or zero-extended to longword size for logical operations (TST, AND,
OR, and XOR instructions).
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly on memory.
Delayed Branching: Unconditional branch instructions are executed as delayed branches. With a
delayed branch instruction, the branch is made after execution of the instruction (called the slot
instruction) immediately following the delayed branch instruction. This minimizes disruption of
the pipeline when a branch is made.
This LSI supports two types of conditional branch instructions: delayed branch instruction or
normal branch instruction.
Example: BRA TARGET
ADD R1, R0 ; ADD is executed before branching to the TARGET
TBit:The result of a comparison is indicated by the T bit in the status register (SR), and a
condition al branch is performed according to whether the result is True or False. Processing speed
has been improved by keeping the number of instructions that modify the T bit to a minimum.
Example: ADD #1, R0 ; The T bit cannot be modified by the ADD instruction
CMP/EQ #0, R0 ;TheTbitissetto1ifR0is0.
BT Target ; Branch to TARGET if the T bit is set to 1 (R0=0).
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Literal Constant: Byte literal con stant is placed inside the instruction code as immediate data.
Since the instruction length is fixed to 16 bits, word and longword literal constant is not placed
inside the instr uction code, but in a table in memory. The table in memory is referenced with a
MOV instruction using PC-relative addressing mode with displacement.
Example: MOV.W @(disp, PC)
Absolute Addresses: When data is referenced by absolute address, the absolute address value is
placed in a table in memory beforehand as well as word or longword literal constant. Using the
method whereby immediatedata is loaded wh en an instruction is executed, this value is
transferred to a register and the data is referenced using register indirect addressing mode.
16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit displacement, the
displacement valueis placed in a table in memory beforehand. Usin g the method whereby word or
longword immediate data is loaded when an instruction is executed, this value is transferred to a
register and the data is referenced using indexed register indirect addressing mode.
Rev. 2.00, 09/03, page 41 of 690
Page 88
2.5.2 CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation meth ods for
instructions executed by the CPU core.
Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Register
direct
Register
indirect
Register
indirect with
post-increment
Register
indirect with
pre-decrement
Instruction
Format Effective Address Calculation Method
Rn Effective address is register Rn.
(Operand is register Rn contents.)
@Rn Effective addressis regis ter Rn contents.
Rn Rn
@Rn+ Effective address is registe r Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn Rn
@–Rn
Rn + 1/2/4
1/2/4
Effective addressis regis ter Rn contents,
+
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn - 1/2/4
-
1/2/4
Rn - 1/2/4
Calculation
Formula
—
Rn
Rn
After instruction
execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 →
Rn
Byte: Rn – 1 → Rn
Word: Rn– 2 → Rn
Longword: Rn – 4 →
Rn
(Instruction executed
with Rn after
calculation)
Register
indirect with
displacement
@(disp:4,
Rn)
Effective addressis regis ter Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multi plied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
(zero-extended)
Rev. 2.00, 09/03, page 42 of 690
Rn
disp
1/2/4
Byte: Rn + disp
Word: Rn + disp×
2
Longword: Rn +
disp × 4
+
×
Rn
+ disp × 1/2/4
Page 89
Addressing
Mode
Instruction
Format Effective Address Calculat ion Method
Calculation
Formula
Indexed
register indirect
GBR indirect
with
displacement
Indexed GBR
indirect
@(R0, Rn) Effective address is sum of register Rn and R0
contents.
Rn
Rn + R0
@(disp:8,
GBR)
+
R0
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multi plied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
GBR
+ disp
GBR
×
1/2/4
@(R0,
GBR)
disp
(Zero-extended)
1/2/4
+
×
Effective addre ssis sum of register GBR and
R0 contents.
Rn + R0
Byte: GBR + disp
Word: GBR+ disp
× 2
Longword: GBR +
disp × 4
GBR + R0
PC-relative with
displacement
@(disp:8,
PC)
GBR
+
R0
GBR + R0
Effective address is PC with 8-bit displacement
disp added. After disp is zero-extended, it is
multiplied by 2 (word) or 4 (longword), according
to the operand size. With a longword operand,
the lower 2 bitsof PC aremasked.
PC
*
&
H'FFFFFFFC
disp
(zero-extended)
2/4
PC + disp
+
H'FFFFFFFC
×
*: With longword operand
or
PC &
+ disp
×
2
×
4
Word: PC+disp× 2
Longword:
PC&H'FFFFFFFC
+disp× 4
Rev. 2.00, 09/03, page 43 of 690
Page 90
Addressing
Mode
Instruction
Format Effective Address Calculation Method
Calculation
Formula
PC-relative disp:8 Effective address is PC with 8-bit displacement
disp added after being sign-extended and
multiplied by 2.
PC
disp:12
disp
(sign-extended)
2
Effective addressis PC with 12-bit displacement
+
×
PC + disp × 2
disp added after being sign-extended and
multiplied by 2
PC
disp
(sign-extended)
2
+
×
PC + disp × 2
Rn Effective address is sum of PC and Rn.
PC + disp × 2
PC + disp × 2
PC + Rn
PC
Immediate
+
Rn
#imm:8 8-bit immediate dataimm of TST, AND, OR,
PC + Rn
—
or XOR instruction is zero-extended.
#imm:8
8-bit immediate data imm of MOV, ADD, or
—
CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA instruction
—
is zero-extended and multiplied by 4.
Note: For addressing modes with displacement (disp) as shown below, the assembler description
in this manual indicates the value before it is scaled(x 1, x2, or x4) accordingto the
operand size to clarify the LSI operation . For details on assembler description, refer to the
description rules in each asse mbler.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, Rn) ; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp ; PC relative
Rev. 2.00, 09/03, page 44 of 690
Page 91
2.5.3 CPU Instruction Formats
Table 2.4 shows the instruction formats, and the meaning of the source and destination operands,
for instructions executed by the CPU core. The meaning of the operands depends on the
instruction code. The following symbols are used in the table.
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Table 2.4 CPU Instruction Formats
Instruction Format
0 type
15 0
xxxx xxxx xxxx xxxx
n type
15 0
xxxx nnnn xxxx xxxx
m type
15 0
xxxx
mmmm
xxxx xxxx
Source
Operand
Destination
Operand Sample Instruction
——NOP
—
nnnn: register
MOVT Rn
direct
Control register or
system register
Control register or
system register
nnnn: register
direct
nnnn: predecrement register
STS MACH,Rn
STC.L SR,@-Rn
indirect
mmmm: register
direct
mmmm: postincrement register
Control register or
system register
Control register or
system register
LDC Rm,SR
LDC.L @Rm+,SR
indirect
mmmm: register
—JMP@Rm
indirect
PC-relative usingRm—BRAFRm
Rev. 2.00, 09/03, page 45 of 690
Page 92
Instruction Format
Source
Operand
Destination
Operand Sample Instruction
nm type
15 0
xxxx nnnn
mmmm
xxxx
mmmm: register
direct
mmmm: register
indirect
mmmm: postincrement register
indirect (multiplyand-accumulate
operation)
nnnn:*postincrement register
indirect (multiplyand-accumulate
operation)
mmmm: postincrement register
indirect
nnnn: register
ADD R m,Rn
direct
nnnn: register
MOV.L Rm,@Rn
indirect
MACH, MACL MAC.W @Rm+,@Rn+
nnnn: register
MOV.L @Rm+,Rn
direct
md type
15 0
xxxx xxxx
mmmm
dddd
nd4 type
15 0
xxxx xxxx nnnn dddd
nmd type
15 0
xxxx nnnn
mmmm
dddd
mmmm: register
direct
mmmm: register
direct
mmmmdddd:
register indirect
with displacement
R0 (register direct)
mmmm: register
direct
mmmmdddd:
register indirect
with displacement
nnnn: pre-
MOV.L Rm,@-Rn
decrement register
indirect
nnnn: indexed
MOV.L Rm,@(R0,Rn)
register indirect
R0 (register direct) MOV.B@(disp,Rm),R0
nnnndddd:
MOV.B R0,@(d isp,Rn)
register indirect
with displacement
nnnndddd:
MOV.L Rm,@(disp,Rn)
register indirect
with displacement
nnnn: register
MOV.L @(disp,Rm),Rn
direct
Rev. 2.00, 09/03, page 46 of 690
Page 93
Instruction Format
Source
Operand
Destination
Operand Sample Instruction
d type
15 0
xxxx xxxx dddd dddd
d12 type
15 0
xxxx dddd dddd dddd
nd8 type
15 0
xxxx nnnn dddd dddd
dddddddd: GBR
indirect with
displacement
R0 (register direct)
dddddddd:
PC-relative with
displacement
dddddddd:
PC-relative
dddddddddddd:
PC-relative
dddddddd: PCrelative with
displacement
R0 (register direct) MOV.L @(disp,GBR),R0
dddddddd: GBR
MOV.L R0,@(disp,GBR)
indirect with
displacement
R0 (register direct) MOVA @(disp,PC),R0
— BF label
—
BRA label
(label=disp+PC)
nnnn: register
MOV.L @(disp,PC),Rn
direct
i type
15 0
xxxx xxxx i i i i i i i i
iiiiiiii: immediate Indexed GBR
indirect
AND.B #imm,@(R0,GBR)
iiiiiiii: immediate R0 (register direct) AND #imm,R0
iiiiiiii: immed iate — TRAPA #imm
ni type
15 0
xxxx nnnn i i i i i i i i
iiiiiiii: immediate
nnnn: register
direct
ADD #imm,Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 2.00, 09/03, page 47 of 690
Page 94
2.6 Instruction Set
2.6.1 CPU Instruction Set Based on Functions
The CPU instruction set consists of 68 basic instruction types divided into six functional groups,
as shown in table 2.5. Tables 2.6 to 2.11 show the instruction notation, machine code, execution
time, and function.
Table 2.5 CPU Instruction Types
Type
Datatransfer
instructions
Arithmetic
operation
instructions
Kinds of
Instruction Op Code Function
5
21 ADD Binary addition 33
MOV Data transfer
Immediate data transfer
Peripheral module data transfer
Structure datatransfer
MOVA Effective address transfer
MOVT T bit transfer
SWAP Upper/lower swap
XTRCT Extraction of middle of linked registers
ADDC Binary addi tion with carry
ADDV Binary addition with overflow check
CMP/cond Comparison
DIV1 Division
Number of
Instructions
39
DIV0S Signed divisioninitialization
DIV0U Unsigned div ision initialization
DMULS Signed double-precision multiplication
DMULU Unsigned double-precisionmultiplication
DT Decrement and test
EXTS Sign extension
EXTU Zero extension
MAC
MUL Double-precisionmultiplication
Rev. 2.00, 09/03, page 48 of 690
Multiply-and-accu mulate, double-
precision multiply-and-accumulate
(32 × 32 bits)
Page 95
Type
Kinds of
Instruction Op Code Function
Number of
Instructions
Arithmetic
operation
instructions
Logic
operation
instructions
Shift
instructions
21 MULS Signed multiplication (16 × 16 bits) 33
MULU U nsigned multiplication(16 × 16 bits)
NEG Sign inversion
NEGC Sign inversionwith borrow
SUB Binary subtraction
SUBC Binary subtraction with carry
SUBV Binary subtraction with underflow
6 AND Logical AND 14
NOT Bit inversion
OR Logical OR
TAS Memory test and bit setting
TST Logical AND and T bit setting
XOR Exclusivelogical OR
12 ROTL 1-bit left shift 16
ROTR 1-bit right shift
ROTCL 1-bit left shift with T bit
ROTCR 1-bit right shift with T bit
SHAL Arithmetic 1-bit left shift
SHAR Arithmetic 1-bit right shift
SHLL Logical 1-bit left shift
SHLLn Logical n-bit left shift
SHLR Logical 1-bit right shift
SHLRn Logical n-bit right shift
SHAD Arithmetic dynamic shift
SHLD Logical dynamic shift
Rev. 2.00, 09/03, page 49 of 690
Page 96
Type
Kinds of
Instruction Op Code Function
Number of
Instructions
Branch
instructions
System
control
instructions
9 BF Conditional branch, delayed condi tional
11
branch (T = 0)
BT
Conditional branch, de layed conditional
branch (T = 1)
BRA Unconditional branch
BRAF Unconditional branch
BSR Branch to subroutine procedure
BSRF Branch to subroutine procedure
JMP Unconditional branch
JSR Branch to subroutine procedure
RTS Return from subroutine procedure
15 CLRT T bit clear 75
CLRMAC MAC register clear
CLRS S bit clear
LDC Load into control register
LDS Load into system register
LDTLB PTEH/PTEL load into TLB
NOP No operation
PREF Data prefetch to cache
RTE Return from exception handling
SETS S bit setting
SETT T bit setting
SLEEP Transition to power-downmode
STC Store from control register
STS Storefrom system register
TRAPA Trap exception handling
Total: 68 188
Rev. 2.00, 09/03, page 50 of 690
Page 97
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Execution
Instruction Instruction Code Operation Privilege
States
TBit
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement
Indicated in MSB ↔
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
.........
1111: R15
iiii: Immediate data
dddd: Displacement
Indicates summary of
operation.
Explanation of Symbols
→, ←: Transfer direction
(xx): Memory operand
M/Q/T: Flag bits in SR
&: Logical AND of each bit
|: Logical OR of each bit
^: Exclusive logical OR of
2
*
each bit
~: Logical NOT of each bit
<<n: n-bitleft shift
>>n: n-bit right shift
Indicates a
privileged
instruction.
Value when
no wait
states are
inserted
1
*
Value of T
bit after
instruction is
executed
Explanation
of Symbols
—: No
change
Notes: 1. The table shows the minimum number of exe cution states. In practice, the number of
instruction execution states wi ll be increased in cases such as the following:
a. When there is a conflict be tween an instruction fetch and a data access
b. When the dest ination register of a load instruction (memory → register) is also
used by the following instruc tion
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
Rev. 2.00, 09/03, page 51 of 690
Page 98
Table 2.6 Data Transfer Instructions
Instruction Instruction Code Operation
Privileged
Mode Cycles T Bit
MOV #imm,Rn
MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp x 2+PC)→Sign extension
MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp x 4+PC)→Rn – 1 –
MOV Rm,Rn 0110nnnnmmmm0011 Rm→Rn – 1 –
MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm→(Rn) – 1 –
MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm→(Rn) – 1 –
MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm→(Rn) – 1 –
MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm)→Sign extension→Rn – 1 –
MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm)→Sign extension→Rn – 1 –
MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm)→Rn – 1 –
MOV.B Rm,@–Rn 0010nnnnmmmm0100 Rn–1→Rn, Rm→(Rn) – 1 –
MOV.W Rm,@–Rn 0010nnnnmmmm0101 Rn–2→Rn, Rm→(Rn) – 1 –
MOV.L Rm,@–Rn 0010nnnnmmmm0110 Rn–4→Rn, Rm→(Rn) – 1 –
MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm)→Sign extension→Rn,
1110nnnniiiiiiii Imm → Sign extension → Rn – 1 –
–1–
→ Rn
–1–
Rm+1→Rm
MOV.W @Rm+,Rn 0110nnnnmmmm0101
MOV.L @Rm+,Rn 0110nnnnmmmm0110 (Rm)→Rn, Rm+4→Rm – 1 –
MOV.B R0,@(disp,Rn) 10000000nnnndddd R0→(disp+Rn) – 1 –
MOV.W R0,@(disp,Rn) 10000001nnnndddd R0→(disp x 2+Rn) – 1 –
MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm→(disp x 4+Rn) – 1 –
MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp+Rm)→Sign extension→R0 – 1 –
MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp x 2+Rm)→Sign
MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp x 4+Rm)→Rn – 1 –
MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm→(R0+Rn) – 1 –
MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm→(R0+Rn) – 1 –
MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm→(R0+Rn) – 1 –
(Rm)→Sign extension→Rn,
Rm+2→Rm
extension→R0
–1–
–1–
Rev. 2.00, 09/03, page 52 of 690
Page 99
Instruction Instruction Code Operation
Privileged
Mode Cycles T Bit
MOV.B @(R0,Rm),Rn
0000nnnnmmmm1100 (R0+Rm)→Sign extension→Rn – 1 –
MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0+Rm)→Sign extension→Rn – 1 –
MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0+Rm)→Rn – 1 –
MOV.B R0,@(disp,GBR) 11000000dddddddd R0→(disp+GBR) – 1 –
MOV.W R0,@(disp,GBR) 11000001dddddddd R0→(disp x 2+GBR) – 1 –
MOV.L R0,@(disp,GBR) 11000010dddddddd R0→(disp x 4+GBR) – 1 –
MOV.B @(disp,GBR),R0 11000100dddddddd
(disp+GBR)→Sign
–1–
extension→R0
MOV.W @(disp,GBR),R0 11000101dddddddd (disp x 2+GBR)→Sign
–1–
extension→R0
MOV.L @(disp,GBR),R0 11000110dddddddd (disp x 4+GBR)→R0 – 1 –
MOVA @(disp,PC),R0 11000111dddddddd disp x 4+PC→R0 – 1 –
MOVT Rn 0000nnnn00101001 T→Rn – 1 –
SWAP.B Rm,Rn 0110nnnnmmmm1000 Rm→Swap lowest two
–1–
bytes→Rn
SWAP.W Rm,Rn 0110nnnnmmmm1001
Rm→Swap two consecutive
–1–
words→Rn
XTRCT Rm,Rn 0010nnnnmmmm1101 Rm: Middle 32 bits of Rn →Rn – 1 –
Rev. 2.00, 09/03, page 53 of 690
Page 100
Table 2.7 Arithmetic Operation Instructions
Instruction Instruction Code Operation
Privileged
Mode Cycles T Bit
ADD Rm,Rn
0011nnnnmmmm1100 Rn+Rm→Rn – 1 –
ADD #imm,Rn 0111nnnniiiiiiii Rn+imm→Rn – 1 –
ADDC Rm,Rn 0011nnnnmmmm1110 Rn+Rm+T→Rn, Carry→T– 1Carry
ADDV Rm,Rn 0011nnnnmmmm1111 Rn+Rm→Rn, Overflow→T– 1Overflow
CMP/EQ #imm,R0 10001000iiiiiiii If R0 = imm, 1 → T–1Comparison
result
CMP/EQ Rm,Rn 0011nnnnmmmm0000 If Rn = Rm, 1→ T–1
CMP/HS Rm,Rn 0011nnnnmmmm0010 If Rn ≥ R m with unsigned data, 1
–1Comparison
→ T
Comparison
result
result
CMP/GE Rm,Rn 0011nnnnmmmm0011 If Rn ≥ R m with signed data, 1 →T–1Comparison
result
CMP/HI Rm,Rn 0011nnnnmmmm0110
If Rn > Rm with unsigned data, 1
→ T
–1
Comparison
result
CMP/GT Rm,Rn 0011nnnnmmmm0111 If Rn > Rm with signed data, 1 →T–1Comparison
result
CMP/PL Rn 0100nnnn00010101 If Rn ≥ 0, 1 → T–1
Comparison
result
CMP/PZ Rn 0100nnnn00010001 If Rn > 0, 1 → T–1Comparison
result
CMP/STR Rm,Rn 0010nnnnmmmm1100
If Rn and Rm have an equivalent
byte, 1 → T
DIV1 Rm,Rn 0011nnnnmmmm0100 Single-step division (Rn/Rm) – 1
DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn → Q, MSB of Rm →
M, M ^ Q → T
–1
Comparison
result
Calculation
result
–1Calculation
result
DIV0U 0000000000011001 0 → M/Q/T – 1 0
DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn × Rm →
MACH, MACL 32 × 32 → 64 bits
DMULU.L Rm,Rn 0011nnnnmmmm0101
Unsigned operation of Rn × Rm
→ MACH, MACL 32 × 32 → 64
–2(to
5)
–
2(to
5)
–
*
–
*
bits
DT Rn 0100nnnn00010000 Rn – 1 → Rn,ifRn= 0, 1 → T,
else 0 → T
–1Comparison
result
Rev. 2.00, 09/03, page 54 of 690
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