RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RCR2.ADJ30, RCR2.AADJE, RCR2.AADJP
Note 2. This bit is reserved in binary counter mode. The write value should be 0.
Note 3. After writing to this bit, confirm that its value has actually changed before proceeding with further processing.
Refer to section 24.5.5, Notes When Writing to and Reading from Registers for notes on accessing registers.
RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RCR2.ADJ30, RCR2.AADJE, RCR2.AADJP
Note 2. This bit is reserved in binary counter mode. The write value should be 0.
Note 3. After writing to this bit, confirm that its value has actually changed before proceeding with further processing.
Refer to section 24.5.5, Notes on Writing to and Reading from Registers, regarding changes to the values of the AADJE,
AADJP, and HR24 bits.
Page 3 of 8
RENESAS TECHNICAL UPDATE TN-RX*-A0238B/E
Date: Mar. 2, 2021
• Page 651 of 1491
Description of the CNTMD bit in section 24.2.18, RTC Control Register 2 (RCR2) is corrected as follows.
Before correction
CNTMD Bit (Count Mode Select)
This bit specifies whether the RTC count mode is operated in calendar count mode or in binary count mode.
When setting the count mode, execute an RTC software reset and start again from the initial settings.
This bit is updated synchronously with the count source, and its value is fixed before the RTC software reset is
completed.
For details on initial settings, refer to section 24.3.1, Outline of Initial Settings of Registers after Power On.
After correction
CNTMD Bit (Count Mode Select)
This bit specifies whether the RTC count mode is operated in calendar count mode or in binary count mode.
After setting the count mode, execute an RTC software reset and start again from the initial settings.
The CNTMD bit is updated in synchronization with the count source, so when the value of the CNTMD bit has been
changed, check that the value of the bit has actually been updated before applying the RTC software reset. The count
mode changes to that which was specified beforehand in the CNTMD bit after the RTC software reset is applied.
For details on initial settings, refer to section 24.3.1, Outline of Initial Settings of Registers after Power On.
Page 4 of 8
Note 1. This step is not necessary if the count mode has been set concurrently with setting the START bit to 0.
A value corresponding to the count mode setting must be written to the RCR2.CNTMD bit.
START = 0
Set the START bit to 0
No
Yes
Wait for the RCR2.START bit to become 0
Select count mode
Supply 6 clocks of the count source
Set the RCR3 register
Wait for the RCR2.RESET bit to become 0
RESET = 0
No
Yes
Set the sub-clock oscillator
Execute RTC software reset
RCR2.CNTMD bit setting
*1
Write 1 to the RCR2.RESET bit
RENESAS TECHNICAL UPDATE TN-RX*-A0238B/E
Date: Mar. 2, 2021
• Page 655 of 1491
The setting procedure described in Figure 24.3, Clock and Count Mode Setting Procedure is corrected as follows.
Before correction
Figure 24.3Clock and Count Mode Setting Procedure
Page 5 of 8
Note 1. This step is not necessary if the count mode has been set concurrently with setting the START bit to 0.
A value corresponding to the count mode setting must be written to the RCR2.CNTMD bit.
START = 0?
Set the START bit to 0
No
Yes
Wait for the RCR2.START bit to become 0
Select count mode
Supply 6 clocks of the count source
Set the RCR3 register
Wait for the RCR2.RESET bit to become 0
RESET = 0?
No
Yes
Set the sub-clock oscillator
Execute RTC software reset
RCR2.CNTMD bit setting
*1
Write 1 to the RCR2.RESET bit
Wait until the RCR2.CNTMD bit has the newly set
value
CNTMD = the set value?
No
Yes
RENESAS TECHNICAL UPDATE TN-RX*-A0238B/E
After correction
Date: Mar. 2, 2021
Figure 24.3Clock and Count Mode Setting Procedure
Page 6 of 8
START = 0
Set the START bit to 0
No
Yes
Wait for the RCR2.START bit to become 0
Supply 6 clocks of the count source
Set the sub-clock oscillator
RCR2.CNTMD bit setting
*1
Wait for the RCR2.RESET bit to become 0
RESET = 0
No
Yes
Execute RTC software reset
Disable the interrupt request
Write 0 to the RCR1.AIE, CIE, and PIE bits
Select count mode
Note1. This step is not necessary if the count mode has been set concurrently with setting the START bit to 0.
Set the RCR3 register
Write 1 to the RCR2.RESET bit
RENESAS TECHNICAL UPDATE TN-RX*-A0238B/E
Date: Mar. 2, 2021
• Page 666 of 1491
The initialization procedure described in Figure 24.12 of section 24.5.7 Initialization Procedure When the Realtime
Clock is Not to be Used is corrected as follows.
Before correction
Figure 24.12Initialization Procedure
Page 7 of 8
RCR2 = 00h?
Set the RCR2 register to 00h
No
Yes
Wait for the RCR2 register to become 00h
Supply 6 clocks of the count source
Set the sub-clock oscillator
Wait for the RCR2.RESET bit to become 0
RESET = 0?
No
Yes
Execute RTC software reset
Disable the interrupt request
Write 0 to the RCR1.AIE, CIE, and PIE bits
Set the RCR3 register
Write 1 to the RCR2.RESET bit
RENESAS TECHNICAL UPDATE TN-RX*-A0238B/E
After correction
Date: Mar. 2, 2021
Figure 24.12Initialization Procedure
Page Number, Section/Figure/Table Number
Item
Table for RTC Control Register 2
(RCR2)
Descriptions of the CNTMD bit
Figure of the clock and count
mode setting procedure
Figure of the initialization
procedure when the realtime clock
is not to be used
Page 650
24.2.18
Page 651
24.2.18
Page 655
Figure 24.3
Page 666
Figure 24.12
Page Number, Section/Figure/Table Number
RX113 GroupRX130 Group
Page642
24.2.18
Page 643
24.2.18
Page 647
Figure 24.3
Page 658
Figure 24.12
Page 8 of 8
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