Renesas RTK00V2X720MTORS7J User Manual
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp.
RTK00V2X720MTORS7J
User’s Manual: Hardware
Rev.1.1 Aug. 2017
GAC-B-17-0004
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Introduction
RTK00V2X720MTORS7J(Tortuga) is an evaluation board for RTK00V2X7200MPIN7J (V2X wireless module).
Tortuga can be used as standalone without the need of Host board, and be evaluated RF performance of V2X wireless
module. Tortuga also be used in conjunction with the Host board.
V2X wireless module has optimized function to realize IEEE802.11p PHY layer function. This product conforms not
only to 802.11p standard but 1609.4 and ETSI standard. This module provides cost effective, low power and small form
factor solution for communication unit manufacture.
Overview
Tortuga is an evaluation board for V2X wireless module(including Renesas’ ASSP and suitable component). V2X
wireless module has optimized function to realize ETSI EN 302 571/ ETSI EN 302 663 PHY/MAC layer function. This
product provides cost effective, low power and small form factor solution to communication unit manufacture.
V2X wireless module includes radio transceiver, PA, LNA , antenna switch, Filters and peripherals.
Feature
- Support Standard: ETSI EN 302 571/ ETSI EN 302 663 / IEEE802.11p™ -2010<15.July.2010> PHY/MAC protocol
with Firmware
- Operational Frequency band: 5.9GHz
- Using 32bit CPU core, Operating Frequency: up to 160MHz
- Internal memory: RAM/128kByte, ROM/32kByte, EEPROM/512Byte
- Mini PCIE Connector
- SDIO interface for host CPU
- UART interfaces
- USB interfaces
- Integrate Function for ETSI EN 302 571/ ETSI EN 302 663
OFDM Modulator/ Demodulator with Maximum Ratio Converting diversity
MAC hardware accelerator
- Power Supply: 12V from AC Adapter or 5.0V from Host board
- Peak Power Consumption (at 12 V)
TYP:
- Listen mode : TBD (diversity on)/TBD(diversity off)
- Rx mode : TBD (diversity on)/TBD(diversity off)
- Tx mode : TBD (@24dBm)
- Operating Temperature
Ta = -40 to +85 degree
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Contents
1. DIMENSION AND LAYOUT ..................................................................................................................4
1.1 BOARD LAYOUT INFORMATION 4
2. BOARD DESCRIPTION ........................................................................................................................6
2.1 BLOCK DIAGRAM 6
2.2 MINI PCIE PIN INFORMATION 7
2.3 POWER SUPPLY 8
2.4 USAGE FOR STANDALONE OPERATION 8
3. FUNCTION DETAILS ...........................................................................................................................9
3.1 ABSOLUTE MAXIMUM RATING 9
3.2 ELECTRICAL CHARACTERISTICS 9
3.3 RF CHARACTERISTIC 10
3.3.1 Receive characteristic
10
3.3.2 Transmit characteristic
11
3.4 MODE TRANSFER DEFINITION AND SUB BOARD CONTROL 12
3.5 POWER UP/DOWN, RESET, WDT SEQUENCE 14
3.5.1 Power On / Off Sequence
14
3.5.2 Reset sequence
15
3.5.3 WDT Reset timing
15
3.6 LOGIC INTERFACE AC CHARACTERISTICS 16
3.6.1 UART sequence
16
3.6.2 SDIO sequence
16
3.6.3 1PPS sequence
18
4. APPENDIX – VALIDATION CONFIGURATION INFORMATION ....................................................... 18
5. REGULATORY WARNING STATEMENTS ......................................................................................... 18
6. EU DECLARATION OF CONFORMITY (DOC) ................................................................................... 20
7. MANUFACTURER INFORMATION .................................................................................................... 21
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1. Dimension and Layout
1.1 Board layout information
Figure1. Board top view information
Unit: mm
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Figure2. Board bottom view information
Unit: mm
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2. Board description
2.1 BLOCK Diagram
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2.2 Mini PCIE pin information
Pin
Pin Name
I/O
Functional
Description
1
RESERVE
I/O - No connection(only connected to test pin)
2
RESERVE
I/O - No connection
3
RESERVE
I/O - No connection(only connected to test pin)
4
GND - GND
GND
5
5.0V - Voltage Supply
5V voltage supply
6
5.0V - Voltage Supply
5V voltage supply
7
RESET
I
CMOS Schmitt Trigger Input
(with Pull-Up)
System reset input (Low Active)
8
1PPS
I
CMOS Schmitt Trigger I
(with Pull-Down)
If you don’t use, select open.
9
GND - GND
GND
10
RESERVE
I/O - No connection(only connected to test pin)
11
UART0_TXD
O
CMOS Output
UART0 Tx signal [TXD]
12
ANT_M
I
CMOS Schmitt Trigger I
(with Pull-Up)
RX Diversity Enable selects.
- High : Diversity
- Low : Single_ANT B
If you don’t use, select open.
13
UART0_RXD
I
CMOS Schmitt Trigger Input
UART0 Rx signal [RXD]
14
RESERVE
I/O - No connection(only connected to test pin)
15
GND - GND
GND
16
STATE
O
CMOS Output
Status indication signal
17
RESERVE
I/O - No connection(only connected to test pin)
18
GND - GND
GND
19
RESERVE
I/O - No connection(only connected to test pin)
20
RESERVE
I/O - No connection(only connected to test pin)
21
GND - GND
GND
22
RESERVE
I/O - No connection(only connected to test pin)
23
RESERVE
I/O - No connection(only connected to test pin)
24
5.0V - Voltage Supply
5V voltage supply
25
RESERVE
I/O - No connection(only connected to test pin)
26
GND - GND
GND
27
GND - GND
GND
28
5.0V - Voltage Supply
5V voltage supply
29
GND - GND
GND
30
RESERVE
I/O - No connection(only connected to test pin)
31
RESERVE
I/O - No connection(only connected to test pin)
32
RESERVE
I/O - No connection(only connected to test pin)
33
RESERVE
I/O - No connection(only connected to test pin)
34
GND - GND
GND
35
GND - GND
GND
36
RESERVE
I/O - No connection(only connected to test pin)
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Pin
Pin Name
I/O
Functional
Description
37
SDIO_CLK
I
CMOS Schmitt Trigger Input
(with Pull-Up)
SDIO clock [CLK]
38
RESERVE
I/O - No connection(only connected to test pin)
39
RESERVE
I/O - No connection(only connected to test pin)
40
GND - GND
GND
41
GND - GND
GND(Pull Down
42
RESERVE
I/O - No connection(only connected to test pin)
43
SDIO_DAT3
I/O
CMOS I/O with Pull-Up
SDIO data [DAT3]
44
RESERVE
I/O - No connection(only connected to test pin)
45
SDIO_DAT2
I/O
CMOS I/O with Pull-Up
SDIO data [DAT2]
46
RESERVE
I/O - No connection(only connected to test pin)
47
SDIO_DAT1
I/O
CMOS I/O with Pull-Up
SDIO data [DAT1]
48
5.0V - Voltage Supply
5V voltage supply
49
SDIO_DAT0
I/O
CMOS I/O with Pull-Up
SDIO data [DAT0]
50
GND - GND
GND
51
SDIO_CMD
I/O
CMOS I/O with Pull-Up
SDIO command [CMD]
52
RESERVE
I/O - No connection
2.3 Power Supply
Tortuga are powered from the HOST board if used in conjunction with the HOST board.
For standalone operation Tortuga are powered from the AC adapter(12V/2A).
2.4 Usage for standalone operation
Please refer to the “UW2b Tortuga test TP quick manual“ for usage of standalone operation.
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