Renesas RL78/G23 Application Note

Application Note

RL78/G23

Voltage Detector

Introduction

This application note describes how to use the two voltage detectors (LVD) mounted on the RL78/G23 to

detect two voltage values.

Set voltage detector 0 (LVD0) to reset mode and voltage detector 1 (LVD1) to interrupt mode. When the power supply voltage becomes lower than the voltage detected by voltage detector 1 (LVD1), the clock frequency for the CPU and peripheral hardware changes to the frequency of the subsystem clock to reduce power consumption.

Target Device

RL78/G23

When applying the sample program covered in this application note to another microcomputer, modify the program according to the specifications for the target microcomputer and conduct an extensive evaluation of the modified program.

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RL78/G23 Voltage Detector

Contents

1. Specifications ............................................................................................................................. 3

1.1 Overview of Specifications ....................................................................................................................... 3

1.2 Outline of Operation ................................................................................................................................. 4

2. Operation Confirmation Conditions ............................................................................................ 6

3. Hardware Descriptions ............................................................................................................... 7

3.1 Example of Hardware Configuration ........................................................................................................ 7

3.2 List of Pins to be Used ............................................................................................................................. 7

4. Software Explanation ................................................................................................................. 8

4.1 Setting of Option Byte .............................................................................................................................. 8

4.2 List pf Constants ...................................................................................................................................... 8

4.3 List of Variables ....................................................................................................................................... 9

4.4 List of Functions ....................................................................................................................................... 9

4.5 Specification of Functions ........................................................................................................................ 9

4.6 Flowcharts .............................................................................................................................................. 10

4.6.1 Main Processing .................................................................................................................................. 10

4.6.2 Voltage Detector (LVD1) Interrupt Processing .................................................................................... 11

4.6.3 External Interrupt (INTP0) Processing ................................................................................................. 13

5. Sample Code ........................................................................................................................... 14

6. Reference Documents ............................................................................................................. 14

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RL78/G23 Voltage Detector

Peripheral Function

Use

Voltage detector (LVD0, LVD1)

Monitor the power supply voltage (VDD).

External interrupt

Used as a pin edge detection interrupt (INTP0) by switch input.

(INTP0).

Port output

Controls the LEDs (LED1 to LED3) connected to P03, P02, and P43 pins.

Power s upply voltage

(VDD)

LVD0

LVD1

PDR

INTL VI

LVD0 re set signal

POR rese t signa l

Res et

Operat ing Res et Operat ing

Res et

Operat ing Res et

CP U s ta tu s

Oper ating f requ ency

32 MHz

Inactive

32 MHz

Inactive

32 MHz

Inactive

32 MHz

Inactive

32. 768 kHz

(After INTLVI

processing)

32. 768 kHz

RAM st atus

RA M d ata ret ained

Not

determined

RA M d ata ret ained

Not

determined

Not

determined

LVD1EN

32. 768

kHz

(After INTLVI

processing)

1. Specifications

1.1 Overview of Specifications

In this application note, three LEDs are used. When the CPU is operating, one LED keeps flashing. Each time

the switch is pressed, the flashing LED changes to another LED.

Set voltage detector 0 (LVD0) to reset mode and voltage detector 1 (LVD1) to interrupt mode.

When the power supply voltage (V

) equals or exceeds the voltage detected by LVD0 (V

operates at 32 MHz and flashes an LED. When V operation clock (f When V

equals or exceeds V

) changes to 32.768 kHz. As a result, the flashing interval of the LED becomes longer.

CLK

LVD1

again, f

changes to 32 MHz. In this case, the flashing interval of the LED

CLK

falls below the voltage detected by LVD1 (V

), the CPU

LVD0

LVD1

), the CPU

becomes shorter.

When V than V in the RAM is retained. When V

equals or exceeds the voltage detected by the power-on reset (POR) circuit (V

, LVD0 generates an internal reset signal and the LED goes off. In this voltage range, the data stored

LVD0

equals or exceeds V

again, the LED that used to flash before the reset

LVD0

) and is lower

PDR

resumes flashing.

When V

falls below the voltage detected by the POR circuit (V

reset signal and the LED goes off. In this case, the data stored in the RAM is not retained. When V exceeds V

again, LED1 starts flashing.

LVD0

), the POR circuit generates an internal

PDR

equals or

Table 1-1 lists the peripheral functions to be used and their uses, and Figure 1-1 gives an overview of the voltage detector (LVD) operation.

Table 1-1 Peripheral Functions Used and Their Uses

Receives switch input interrupts on the edge-detecting interrupt input pin

Figure 1-1 Overview of the Voltage Detector (LVD) Operation

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RL78/G23 Voltage Detector

LED On/Off Status

LED1

LED2

LED3

(1)

OFF

(2)

ON (flashing)

OFF

(3)

OFF

ON (flashing)

OFF

(4)

OFF

ON (flashing)

1.2 Outline of Operation

Set LVD0 to reset mode and LVD1 to interrupt mode.

changes depending on VDD. You can determine whether f

CLK

is changed by checking the flashing interval

CLK

of the LED.

When V

LVD1

LVD0

≦ VDD: f

≦ V

= 32 MHz, shorter LED flashing interval

CLK

< V

LVD1

: f

= 32.768 kHz, longer LED flashing interval

CLK

The LEDs cycle as follows each time the switch is pressed.

LED1 → LED2 → LED3 → LED1 →・・・

Table 1-2 LED On/Off Status

Operation

Operations (2) to (4) cycle each time the switch is pressed.

When LVD0 generates a reset signal, the data stored in the RAM (the number of switch inputs) is retained. When the CPU resumes operation, the LED that used to flash before the reset is selected.

When the POR circuit generates a reset signal, the data stored in the RAM (the number of switch inputs) is not retained. When the CPU resumes operation, LED1 is selected.

(1) Initialize the voltage detector (LVD).

 At power-on or after a reset release, the option bytes are automatically referenced and LVD0 is set to reset

mode.

 Set the LVD0 detection voltage to 1.875 V (rising) and to 1.835 V (falling).

 Set LVD1 to interrupt mode.

 Set the LVD1 detection voltage to 2.400 V (rising) and to 2.350 V (falling).

(2) Set the I/O ports.

 P03, P02, and P43 pins: Set as output ports (to be used for LED control).

 P137 / INTP0 pin: Set as an input port (to be used for switch input).

(3) Initialize external interrupt processing.

 Set the falling edge as the valid edge for the INTP0 pin and enable switch input.

 Enable INTP0 interrupts.

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RL78/G23 Voltage Detector

;--------------------------------------------------

Comment out

__no_init uint8_t g_SwCount; /* Counter for KEY pushed */

(4) Flash the LED corresponding to the input count of the switch.

 When the switch is pressed, the falling edge of the P137 / INTP0 pin is detected and interrupt processing

is performed.

 To prevent chattering, the voltage applied to the P137 pin is checked approximately every 5 ms. When the

switch is determined to be pressed, the switch input count is updated and the LED corresponding to the switch input count flashes (see Table 1-2).

(5) f

changes based on the voltage detected by LVD1.

CLK

 When V

LVD1

LVD0

≦ VDD: f

≦ V

= 32 MHz

CLK

< V

LVD1

: f

= 32.768 kHz

CLK

When LVD0 generates a reset signal, the data stored in the RAM (switch input count) is retained. However, if you use the startup routine prepared in CS+ or e2studio without modifying it, the data in the internal RAM is initialized before the main functions. To prevent this, comment out the initialization program for the internal RAM data.

; initializing BSS ;------------------------------------------------- ; clear external variables which doesn't have initial value (near) ; MOVW HL,#LOWW(STARTOF(.bss)) ; MOVW AX,#LOWW(STARTOF(.bss) + SIZEOF(.bss)) ; BR $.L2_BSS ;.L1_BSS: ; MOV [HL+0],#0 ; INCW HL ;.L2_BSS: ; CMPW AX,HL ; BNZ $.L1_BSS

If you use the startup routine prepared in IAR Embedded Workbench without modifying it, the data in the internal RAM is initialized before the main functions. To prevent this, add __no_init when you declare variables, and place the data in the area for holding variable values.

Caution For details about the cautions on using the device, see the RL78/G23 User’s Manual: Hardware.

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RL78/G23 Voltage Detector

Item

Description

MCU used

RL78/G23 (R7F100GLG)

Operating frequency

• High-speed on-chip oscillator clock (fIH): 32 MHz

• Subsystem clock (XT1 clock (fXT)): 32.768 kHz

Operating voltage

5.0 V (can be operated at 2.0 V to 5.5 V)

At falling edge TYP. 2.35 V (2.30 V to 2.40 V)

Integrated development environment (CS+)

CS+ for CC V8.05.00f from Renesas Electronics Corp. C compiler (CS+)

CC-RL V1.09.00 from Renesas Electronics Corp.

Integrated development environment (e2studio)

e2studio V2021-01 from Renesas Electronics Corp. C compiler (e2studio)

CC-RL V1.09.00 from Renesas Electronics Corp.

Integrated development environment (IAR)

IAR Embedded Workbench for Renesas RL78 V4.20.1 from IAR Systems Corp.

C compiler (IAR)

IAR C/C++ Compiler for Renesas RL78 V4.20.1.2260 from IAR Systems Corp.

Board used

RL78/G23 Fast Prototyping Board

2. Operation Confirmation Conditions

The operation of the sample code provided with this application note has been tested under the following conditions.

Table 2-1

Operation Confirmation Conditions

LVD0 detection voltage: Reset mode

At rising edge TYP. 1.90 V (1.84 V to 1.95 V)

At falling edge TYP. 1.86 V (1.80 V to 1.91 V)

LVD1 detection voltage: Interrupt mode

At rising edge TYP. 2.40 V (2.35 V to 2.45 V)

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+ 11 hidden pages

Renesas RL78/G23 Application Note

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Specifications

1.1 Overview of Specifications

1.2 Outline of Operation

2. Operation Confirmation Conditions