Renesas RL78/G1H User Manual

User’s Manual

RL78/G1H

16

User’s Manual: Hardware

16-Bit Single-Chip Microcontrollers

All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information publish ed by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).

www.renesas.com

Dec 2016Rev. 1.20

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
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and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.

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incurred by you resulting from errors in or omissions from the information included herein.

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(2012.4)

NOTES FOR CMOS DEVICES

(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a

reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. T ake care to prevent chattering noise
from entering the device when the input level is fixed, and also in the tra nsition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).

(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be c ause of malfunction. If

an input pin is unconnected, it is possible that an internal input level may be generate d due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-do wn circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.

(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause

destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be gr oun ded usin g a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.

(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS

device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.

(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal

operation and external interface, as a rule, switch on the e xternal power suppl y after switching on th e internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse po wer on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degr adation of internal elements
due to the passage of an abnormal current. The correct po wer on/off sequence must be judged separately
for each device and according to related specifications governing the device.

(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply

while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.

How to Use This Manual

Readers This manual is intended for user engineers who wish to understand the functions of the

RL78/G1H and design and develop application systems and programs for these devices.

Purpose This manual is intended to give users an understanding of the functions described in the

Organization below.

Organization The RL78/G1H manual is separated into two parts: this manual and the software edition

(common to the RL78 family).

How to Read This Manual

RL78/G1H

User’s Manual

Hardware

(This Manual)

• Pin functions

• Internal block functions

• Interrupts

• Other on-chip peripheral functions

• Electrical specifications

It is assumed that the readers of this manual have general knowledge of electrical engineering,

logic circuits, and microcontrollers.

• To gain a general understanding of functions:

→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major revised

points. The revised points can be easily searched by copying an “<R>” in the PDF file and

specifying it in the “Find what:” field.

• How to interpret the register format:

→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved word

• CPU functions

• Instruction set

• Explanation of each instruction

RL78 Family

User’s Manual

Software

in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the

compiler.

• To know details of the RL78/G1H Microcontroller instructions:

→ Refer to the separate document RL78 Family User's Manual Software (R01US0015E).

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representations: ×××

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numerical representations: Binary..................×××× or ××××B

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No.

RL78/G1H User’s Manual Hardware This manual

RL78 Family User’s Manual Software R01US0015E

Documents Related to Flash Memory Programming (User’s Manual)

Document Name Document No.

PG-FP5 Flash Memory Programmer User’s Manual ―

RL78, 78K, V850, RX100, RX200, RX600 (Except RX64x), R8C, SH R20UT2923E

Common R20UT2922E

Setup Manual R20UT0930E

(overscore over pin and signal name)

Decimal...............××××

Hexadecimal .......××××H

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

Other Documents

Document Name Document No.

Renesas MPUs & MCUs RL78 Family R01CP0003E

Semiconductor Package Mount Manual R50ZZ0003E

Semiconductor Reliability Handbook R51ZZ0001E

Caution The related documents listed above are subject to change without no tice. Be sure to use the latest

version of each document when designing.

All trademarks and registered trademarks are the property of their respective owners.

EEPROM is a trademark of Renesas Electronics Corporation.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United

States and Japan.

Caution: This product uses SuperFlash



technology licensed from Silicon Storage Technology, Inc.

CONTENTS

1. OUTLINE ........................................................................................................................................ 1

1.1 Features ................................................................................................................................... 1

1.2 Ordering Information ................................................................................................................. 4

1.3 Pin Configuration (Top View) .................................................................................................... 6

1.4 Pin Identification ....................................................................................................................... 7

1.5 Block Diagram .......................................................................................................................... 8

1.6 Outline of Functions .................................................................................................................. 9

2. CONNECTION BETWEEN MCU AND RF TRANSCEIVER .......................................................... 11

2.1 Connection Pins of MCU and RF Transceiver ......................................................................... 11

2.2 Communication Interface Between MCU and RF Transceiver ............................................... 12

2.3 Initial Settings of Unused Internal Pins of MCU ...................................................................... 13

2.4 Base Operation Clock of RF Unit ........................................................................................... 14

2.5 Power Configuration ............................................................................................................... 15

2.6 Peripheral Circuits’Connection Diagram ................................................................................. 16

3. PIN FUNCTIONS .......................................................................................................................... 19

3.1 Port Functions ........................................................................................................................ 19

3.2 Functions other than port pins ................................................................................................ 22

3.3 Connection of Unused Pins .................................................................................................... 23

3.4 Pin Block Diagrams ................................................................................................................ 24

4. CPU ARCHITECTURE ................................................................................................................. 36

4.1 Memory Space ........................................................................................................................ 36

4.1.1 Internal program memory space ......................................................................................... 44

4.1.2 Mirror area .......................................................................................................................... 45

4.1.3 Internal data memory space ............................................................................................... 46

4.1.4 Special function register (SFR) area ................................................................................... 46

4.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area .......... 46

4.1.6 Data memory addressing ................................................................................................... 47

4.2 Processor Registers ............................................................................................................... 48

4.2.1 Control registers ................................................................................................................. 48

4.2.2 General-purpose registers .................................................................................................. 51

4.2.3 ES and CS registers ........................................................................................................... 52

4.2.4 Special function registers (SFRs) ....................................................................................... 53

4.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ............. 59

5. PORT FUNCTIONS ...................................................................................................................... 67

5.1 Port Functions ........................................................................................................................ 67

5.2 Port Configuration ................................................................................................................... 68

5.2.1 Port 0 .................................................................................................................................. 69

5.2.2 Port 1 .................................................................................................................................. 69

5.2.3 Port 2 .................................................................................................................................. 69

5.2.4 Port 3 .................................................................................................................................. 70

5.2.5 Port 4 .................................................................................................................................. 70

Index - 1

5.2.6 Port 6 .................................................................................................................................. 70

5.2.7 Port 7 .................................................................................................................................. 70

5.2.8 Port 8 .................................................................................................................................. 70

5.2.9 Port 10 ................................................................................................................................ 71

5.2.10 Port 12 ................................................................................................................................ 71

5.2.11 Port 13 ................................................................................................................................ 71

5.2.12 Port 14 ................................................................................................................................ 72

5.2.13 Port 15 ................................................................................................................................ 72

5.2.14 GPIO port ........................................................................................................................... 72

5.3 Registers Controlling Port Function ........................................................................................ 73

5.3.1 Port mode registers (PMxx) ................................................................................................ 76

5.3.2 Port registers (Pxx) ............................................................................................................. 78

5.3.3 Pull-up resistor option registers (PUxx) .............................................................................. 80

5.3.4 Port input mode registers (PIMxx) ...................................................................................... 81

5.3.5 Port output mode registers (POMxx) .................................................................................. 82

5.3.6 Port mode control registers (PMCxx) ................................................................................. 83

5.3.7 A/D port configuration register (ADPC) .............................................................................. 84

5.4 Port Function Operations ........................................................................................................ 85

5.4.1 Writing to I/O port ............................................................................................................... 85

5.4.2 Reading from I/O port ......................................................................................................... 85

5.4.3 Operations on I/O port ........................................................................................................ 85

5.4.4 Handling different potential (1.8 V, 2.5 V, 3 V) by using I/O buffers .................................... 86

5.5 Register Settings When Using Alternate Function .................................................................. 87

5.5.1 Basic concept when using alternate function ..................................................................... 87

5.5.2 Register settings for alternate function whose output function is not used ......................... 88

5.5.3 Register setting examples for used port and alternate functions ........................................ 89

5.6 Cautions When Using Port Function ...................................................................................... 95

5.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) ................................... 95

5.6.2 Notes on specifying the pin settings ................................................................................... 96

6. CLOCK GENERATOR .................................................................................................................. 97

6.1 Functions of Clock Generator ................................................................................................. 97

6.2 Configuration of Clock Generator ........................................................................................... 99

6.3 Registers Controlling Clock Generator ................................................................................. 101

6.3.1 Clock operation mode control register (CMC) .................................................................. 101

6.3.2 System clock control register (CKC) ................................................................................. 104

6.3.3 Clock operation status control register (CSC) .................................................................. 105

6.3.4 Oscillation stabilization time counter status register (OSTC) ............................................ 106

6.3.5 Oscillation stabilization time select register (OSTS) ......................................................... 108

6.3.6 Peripheral enable registers 0, 1 (PER0, PER1) ................................................................ 110

6.3.7 Subsystem clock supply mode control register (OSMC) ................................................... 114

6.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) ................................ 115

6.3.9 High-speed on-chip oscillator trimming register (HIOTRM) ............................................... 116

6.4 System Clock Oscillator ......................................................................................................... 117

6.4.1 X1 oscillator ....................................................................................................................... 117

6.4.2 XT1 oscillator ..................................................................................................................... 117

6.4.3 High-speed on-chip oscillator ........................................................................................... 121

6.4.4 Low-speed on-chip oscillator ............................................................................................ 121

6.5 Clock Generator Operation ................................................................................................... 122

Index - 2

6.6 Controlling Clock .................................................................................................................. 124

6.6.1 Example of setting high-speed on-chip oscillator ............................................................. 124

6.6.2 Example of setting X1 oscillation clock ............................................................................. 126

6.6.3 Example of setting XT1 oscillation clock .......................................................................... 128

6.6.4 CPU clock status transition diagram ................................................................................. 129

6.6.5 Condition before changing CPU clock and processing after changing CPU clock ........... 135

6.6.6 Time required for switchover of CPU clock and main system clock ................................. 137

6.6.7 Conditions before clock oscillation is stopped .................................................................. 138

7. TIMER ARRAY UNIT .................................................................................................................. 139

7.1 Functions of Timer Array Unit ............................................................................................... 140

7.1.1 Independent channel operation function .......................................................................... 140

7.1.2 Simultaneous channel operation function ......................................................................... 141

7.1.3 8-bit timer operation function (channels 1 and 3 only) ...................................................... 141

7.2 Configuration of Timer Array Unit ......................................................................................... 142

7.2.1 Timer count register mn (TCRmn) .................................................................................... 146

7.2.2 Timer data register mn (TDRmn) ...................................................................................... 148

7.3 Registers Controlling Timer Array Unit ................................................................................. 149

7.3.1 Peripheral enable register 0 (PER0) ................................................................................. 150

7.3.2 Timer clock select register m (TPSm) ............................................................................... 151

7.3.3 Timer mode register mn (TMRmn) ................................................................................... 154

7.3.4 Timer status register mn (TSRmn) ................................................................................... 159

7.3.5 Timer channel enable status register m (TEm) ................................................................. 160

7.3.6 Timer channel start register m (TSm) ............................................................................... 161

7.3.7 Timer channel stop register m (TTm) ............................................................................... 163

7.3.8 Timer input select register 0 (TIS0) .................................................................................. 164

7.3.9 Timer output enable register m (TOEm) ........................................................................... 165

7.3.10 Timer output register m (TOm) ......................................................................................... 166

7.3.11 Timer output level register m (TOLm) ............................................................................... 167

7.3.12 Timer output mode register m (TOMm) ............................................................................ 168

7.3.13 Noise filter enable register 1 (NFEN1) .............................................................................. 169

7.3.14 Registers controlling port functions of pins to be used for timer I/O ................................. 171

7.4 Basic Rules of Timer Array Unit ............................................................................................ 172

7.4.1 Basic rules of simultaneous channel operation function ................................................... 172

7.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) ............................... 174

7.5 Operation of Counter ............................................................................................................ 175

7.5.1 Count clock (f

TCLK) ........................................................................................................... 175

7.5.2 Start timing of counter ....................................................................................................... 177

7.5.3 Operation of counter ......................................................................................................... 178

7.6 Channel Output (TOmn pin) Control ..................................................................................... 183

7.6.1 TOmn pin output circuit configuration ............................................................................... 183

7.6.2 TOmn Pin Output Setting ................................................................................................. 184

7.6.3 Cautions on Channel Output Operation ........................................................................... 185

7.6.4 Collective manipulation of TOmn bit ................................................................................. 190

7.6.5 Timer Interrupt and TOmn Pin Output at Operation Start ................................................. 191

7.7 Timer Input (TImn) Control ................................................................................................... 192

7.7.1 TImn input circuit configuration ......................................................................................... 192

7.7.2 Noise filter ......................................................................................................................... 192

7.7.3 Cautions on channel input operation ................................................................................ 193

Index - 3

7.8 Independent Channel Operation Function of Timer Array Unit ............................................. 194

7.8.1 Operation as interval timer/square wave output ............................................................... 194

7.8.2 Operation as external event counter ................................................................................ 199

7.8.3 Operation as input pulse interval measurement ............................................................... 203

7.8.4 Operation as input signal high-/low-level width measurement ......................................... 207

7.8.5 Operation as delay counter ............................................................................................... 211

7.9 Simultaneous Channel Operation Function of Timer Array Unit ........................................... 215

7.9.1 Operation as PWM function .............................................................................................. 215

7.10 Cautions When Using Timer Array Unit ................................................................................ 222

7.10.1 Cautions When Using Timer output .................................................................................. 222

8. TIMER RJ ................................................................................................................................... 223

8.1 Functions of Timer RJ ........................................................................................................... 223

8.2 Configuration of Timer RJ ..................................................................................................... 224

8.3 Registers Controlling Timer RJ ............................................................................................. 225

8.3.1 Peripheral enable register 1 (PER1) ................................................................................. 226

8.3.2 Subsystem clock supply mode control register (OSMC) .................................................. 227

8.3.3 Timer RJ counter register 0 (TRJ0) .................................................................................. 228

8.3.4 Timer RJ control register 0 (TRJCR0) .............................................................................. 229

8.3.5 Timer RJ mode register 0 (TRJMR0) ................................................................................ 230

8.4 Timer RJ Operation .............................................................................................................. 231

8.4.1 Reload Register and Counter Rewrite Operation ............................................................. 231

8.4.2 Timer Mode ....................................................................................................................... 232

8.4.3 Coordination with Event Link Controller (ELC) ................................................................. 233

8.5 Cautions for Timer RJ ........................................................................................................... 234

8.5.1 Count Operation Start and Stop Control ........................................................................... 234

8.5.2 Access to Flags (TUNDF bit in TRJCR0 Register) ........................................................... 234

8.5.3 Access to Counter Register .............................................................................................. 234

8.5.4 When Changing Mode ..................................................................................................... 234

8.5.5 When Timer RJ Operating Clock is Stopped .................................................................... 235

8.5.6 When Count is Forcibly Stopped by TSTOP Bit ............................................................... 235

8.5.7 When Selecting f

IL as Count Source ................................................................................ 235

9. REAL-TIME CLOCK ................................................................................................................... 236

9.1 Functions of Real-time Clock ................................................................................................ 236

9.2 Configuration of Real-time Clock .......................................................................................... 236

9.3 Registers Controlling Real-time Clock .................................................................................. 238

9.3.1 Peripheral enable register 0 (PER0) ................................................................................. 239

9.3.2 Subsystem clock supply mode control register (OSMC) .................................................. 240

9.3.3 Real-time clock control register 0 (RTCC0) ...................................................................... 241

9.3.4 Real-time clock control register 1 (RTCC1) ...................................................................... 242

9.3.5 Second count register (SEC) ............................................................................................ 244

9.3.6 Minute count register (MIN) .............................................................................................. 244

9.3.7 Hour count register (HOUR) ............................................................................................. 245

9.3.8 Day count register (DAY) .................................................................................................. 247

9.3.9 Week count register (WEEK) ............................................................................................ 248

9.3.10 Month count register (MONTH) ........................................................................................ 249

9.3.11 Year count register (YEAR) .............................................................................................. 249

9.3.12 Watch error correction register (SUBCUD) ....................................................................... 250

Index - 4

9.3.13 Alarm minute register (ALARMWM) ................................................................................. 251

9.3.14 Alarm hour register (ALARMWH) ..................................................................................... 251

9.3.15 Alarm week register (ALARMWW) ................................................................................... 251

9.4 Real-time Clock Operation ................................................................................................... 253

9.4.1 Starting operation of real-time clock ................................................................................. 253

9.4.2 Shifting to HALT/STOP mode after starting operation ...................................................... 254

9.4.3 Reading/writing real-time clock ......................................................................................... 255

9.4.4 Setting alarm of real-time clock ........................................................................................ 257

9.4.5 Example of watch error correction of real-time clock ........................................................ 258

10. 12-BIT INTERVAL TIMER ........................................................................................................... 261

10.1 Functions of 12-bit Interval Timer ......................................................................................... 261

10.2 Configuration of 12-bit Interval Timer ................................................................................... 261

10.3 Registers Controlling 12-bit Interval Timer ........................................................................... 262

10.3.1 Peripheral enable register 0 (PER0) ................................................................................. 262

10.3.2 Subsystem clock supply mode control register (OSMC) .................................................. 263

10.3.3 12-bit interval timer control register (ITMC) ...................................................................... 264

10.4 12-bit Interval Timer Operation ............................................................................................. 265

10.4.1 12-bit interval timer operation timing ................................................................................ 265

10.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/

STOP mode ...................................................................................................................... 266

11. CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ............................................................... 267

11.1 Functions of Clock Output/Buzzer Output Controller ............................................................ 267

11.2 Configuration of Clock Output/Buzzer Output Controller ...................................................... 269

11.3 Registers Controlling Clock Output/Buzzer Output Controller .............................................. 269

11.3.1 Clock output select registers n (CKSn) ............................................................................. 269

11.3.2 Registers controlling port functions of pins to be used for clock or buzzer output ............ 271

11.4 Operations of Clock Output/Buzzer Output Controller .......................................................... 272

11.4.1 Operation as output pin .................................................................................................... 272

11.5 Cautions of clock output/buzzer output controller ................................................................. 272

12. WATCHDOG TIMER ................................................................................................................... 273

12.1 Functions of Watchdog Timer ............................................................................................... 273

12.2 Configuration of Watchdog Timer ......................................................................................... 274

12.3 Register Controlling Watchdog Timer ................................................................................... 275

12.3.1 Watchdog timer enable register (WDTE) .......................................................................... 275

12.4 Operation of Watchdog Timer ............................................................................................... 276

12.4.1 Controlling operation of watchdog timer ........................................................................... 276

12.4.2 Setting overflow time of watchdog timer .......................................................................... 277

12.4.3 Setting window open period of watchdog timer ................................................................ 278

12.4.4 Setting watchdog timer interval interrupt .......................................................................... 279

13. A/D CONVERTER ...................................................................................................................... 280

13.1 Function of A/D Converter .................................................................................................... 280

13.2 Configuration of A/D Converter ............................................................................................ 283

13.3 Registers Controlling A/D Converter ..................................................................................... 285

13.3.1 Peripheral enable register 0 (PER0) ................................................................................. 286

13.3.2 A/D converter mode register 0 (ADM0) ............................................................................ 287

Index - 5

13.3.3 A/D converter mode register 1 (ADM1) ............................................................................ 295

13.3.4 A/D converter mode register 2 (ADM2) ............................................................................ 296

13.3.5 10-bit A/D conversion result register (ADCR) ................................................................... 298

13.3.6 8-bit A/D conversion result register (ADCRH) .................................................................. 298

13.3.7 Analog input channel specification register (ADS) ........................................................... 299

13.3.8 Conversion result comparison upper limit setting register (ADUL) ................................... 300

13.3.9 Conversion result comparison lower limit setting register (ADLL) .................................... 300

13.3.10 A/D test register (ADTES) ................................................................................................ 301

13.3.11 Registers controlling port function of analog input pins .................................................... 302

13.4 A/D Converter Conversion Operations ................................................................................. 303

13.5 Input Voltage and Conversion Results .................................................................................. 305

13.6 A/D Converter Operation Modes .......................................................................................... 306

13.6.1 Software trigger mode (select mode, sequential conversion mode) ................................. 306

13.6.2 Software trigger mode (select mode, one-shot conversion mode) ................................... 307

13.6.3 Hardware trigger no-wait mode (select mode, sequential conversion mode) ................... 308

13.6.4 Hardware trigger no-wait mode (select mode, one-shot conversion mode) ..................... 309

13.6.5 Hardware trigger wait mode (select mode, sequential conversion mode) ........................ 310

13.6.6 Hardware trigger wait mode (select mode, one-shot conversion mode) ........................... 311

13.7 A/D Converter Setup Flowchart ............................................................................................ 312

13.7.1 Setting up software trigger mode ...................................................................................... 312

13.7.2 Setting up hardware trigger no-wait mode ........................................................................ 313

13.7.3 Setting up hardware trigger wait mode ............................................................................. 314

13.7.4 Setting up test mode ......................................................................................................... 315

13.8 SNOOZE Mode Function ...................................................................................................... 316

13.9 Cautions for A/D Converter .................................................................................................. 319

14. SERIAL ARRAY UNIT ................................................................................................................ 323

14.1 Functions of Serial Array Unit ............................................................................................... 324

14.1.1 3-wire serial I/O (CSIp) ..................................................................................................... 324

14.1.2 UART (UARTq) ................................................................................................................. 325

14.2 Configuration of Serial Array Unit ......................................................................................... 326

14.2.1 Shift register ..................................................................................................................... 329

14.2.2 Lower 8 bits of the serial data register mn (SDRmn) ........................................................ 329

14.3 Registers Controlling Serial Array Unit ................................................................................. 331

14.3.1 Peripheral enable register 0 (PER0) ................................................................................. 332

14.3.2 Serial clock select register m (SPSm) .............................................................................. 333

14.3.3 Serial mode register mn (SMRmn) ................................................................................... 335

14.3.4 Serial communication operation setting register mn (SCRmn) ......................................... 336

14.3.5 Serial data register mn (SDRmn) ..................................................................................... 339

14.3.6 Serial flag clear trigger register mn (SIRmn) .................................................................... 340

14.3.7 Serial status register mn (SSRmn) ................................................................................... 341

14.3.8 Serial channel start register m (SSm) ............................................................................... 343

14.3.9 Serial channel stop register m (STm) ............................................................................... 344

14.3.10 Serial channel enable status register m (SEm) ................................................................ 345

14.3.11 Serial output enable register m (SOEm) ........................................................................... 346

14.3.12 Serial output register m (SOm) ......................................................................................... 347

14.3.13 Serial output level register m (SOLm) .............................................................................. 348

14.3.14 Noise filter enable register 0 (NFEN0) .............................................................................. 350

14.3.15 Registers controlling port functions of serial input/output pins ......................................... 351

Index - 6

14.4 Operation Stop Mode ............................................................................................................ 352

14.4.1 Stopping the operation by units ........................................................................................ 352

14.4.2 Stopping the operation by channels ................................................................................. 353

14.5 Operation of 3-Wire Serial I/O (CSIp) Communication ......................................................... 354

14.5.1 Master transmission ......................................................................................................... 356

14.5.2 Master reception ............................................................................................................... 364

14.5.3 Master transmission/reception .......................................................................................... 372

14.5.4 Slave transmission ........................................................................................................... 380

14.5.5 Slave reception ................................................................................................................. 388

14.5.6 Slave transmission/reception ............................................................................................ 394

14.5.7 Calculating transfer clock frequency ................................................................................. 402

14.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSIp)

communication ................................................................................................................. 404

14.6 Operation of UART (UARTq) Communication ...................................................................... 405

14.6.1 UART transmission ........................................................................................................... 406

14.6.2 UART reception ................................................................................................................ 415

14.6.3 Calculating baud rate ........................................................................................................ 422

14.6.4 Procedure for processing errors that occurred during UART (UARTq) communication ... 426

15. SERIAL INTERFACE IICA .......................................................................................................... 427

15.1 Functions of Serial Interface IICA ......................................................................................... 427

15.2 Configuration of Serial Interface IICA ................................................................................... 430

15.3 Registers Controlling Serial Interface IICA ........................................................................... 433

15.3.1 Peripheral enable register 0 (PER0) ................................................................................. 434

15.3.2 IICA control register n0 (IICCTLn0) .................................................................................. 434

15.3.3 IICA status register n (IICSn) ............................................................................................ 439

15.3.4 IICA flag register n (IICFn) ................................................................................................ 441

15.3.5 IICA control register n1 (IICCTLn1) .................................................................................. 443

15.3.6 IICA low-level width setting register n (IICWLn) ............................................................... 445

15.3.7 IICA high-level width setting register n (IICWHn) ............................................................. 445

15.3.8 Register to control port function of serial I/O pin ............................................................. 446

15.4 I

2

C Bus Mode Functions ....................................................................................................... 447

15.4.1 Pin configuration ............................................................................................................... 447

15.4.2 Setting transfer clock by using IICWLn and IICWHn registers ......................................... 448

15.5 I

2

C Bus Definitions and Control Methods ............................................................................. 450

15.5.1 Start conditions ................................................................................................................. 450

15.5.2 Addresses ......................................................................................................................... 451

15.5.3 Transfer direction specification ......................................................................................... 451

15.5.4 Acknowledge (ACK) ......................................................................................................... 452

15.5.5 Stop condition ................................................................................................................... 453

15.5.6 Wait ................................................................................................................................... 454

15.5.7 Canceling wait ................................................................................................................. 456

15.5.8 Interrupt request (INTIICAn) generation timing and wait control ...................................... 457

15.5.9 Address match detection method ..................................................................................... 458

15.5.10 Error detection .................................................................................................................. 458

15.5.11 Extension code ................................................................................................................ 459

15.5.12 Arbitration ......................................................................................................................... 460

15.5.13 Wakeup function ............................................................................................................... 462

15.5.14 Communication reservation .............................................................................................. 465

Index - 7

15.5.15 Cautions ........................................................................................................................... 469

15.5.16 Communication operations ............................................................................................... 470

15.5.17 Timing of I

2

C interrupt request (INTIICAn) occurrence ..................................................... 478

15.6 Timing Charts ....................................................................................................................... 499

16. DATA TRANSFER CONTROLLER (DTC) .................................................................................. 514

16.1 Functions of DTC .................................................................................................................. 514

16.2 Configuration of DTC ............................................................................................................ 516

16.3 Registers Controlling DTC .................................................................................................... 517

16.3.1 Allocation of DTC Control Data Area and DTC Vector Table Area ................................... 518

16.3.2 Control Data Allocation ..................................................................................................... 519

16.3.3 Vector Table ...................................................................................................................... 520

16.3.4 Peripheral enable register 1 (PER1) ................................................................................. 522

16.3.5 DTC control register j (DTCCRj) (j = 0 to 23) .................................................................... 523

16.3.6 DTC block size register j (DTBLSj) (j = 0 to 23) ................................................................ 524

16.3.7 DTC transfer count register j (DTCCTj) (j = 0 to 23) ......................................................... 524

16.3.8 DTC transfer count reload register j (DTRLDj) (j = 0 to 23) .............................................. 525

16.3.9 DTC source address register j (DTSARj) (j = 0 to 23) ...................................................... 525

16.3.10 DTC destination address register j (DTDARj) (j = 0 to 23) ............................................... 525

16.3.11 DTC activation enable register i (DTCENi) (i = 0 to 4) ...................................................... 526

16.3.12 DTC base address register (DTCBAR) ............................................................................ 529

16.4 DTC Operation ..................................................................................................................... 529

16.4.1 Activation Sources ............................................................................................................ 530

16.4.2 Normal Mode .................................................................................................................... 531

16.4.3 Repeat Mode .................................................................................................................... 532

16.4.4 Chain Transfers ................................................................................................................ 534

16.5 Cautions for DTC .................................................................................................................. 535

16.5.1 Setting DTC Control Data and Vector Table ..................................................................... 535

16.5.2 Allocation of DTC Control Data Area and DTC Vector Table Area ................................... 535

16.5.3 DTC Pending Instruction .................................................................................................. 536

16.5.4 Operation when Accessing Data Flash Memory Space .................................................... 536

16.5.5 Number of DTC Execution Clock Cycles .......................................................................... 537

16.5.6 DTC Response Time ........................................................................................................ 538

16.5.7 DTC Activation Sources ................................................................................................... 538

16.5.8 Operation in Standby Mode Status ................................................................................... 539

17. EVENT LINK CONTROLLER (ELC) ........................................................................................... 540

17.1 Functions of ELC .................................................................................................................. 540

17.2 Configuration of ELC ............................................................................................................ 540

17.3 Registers Controlling ELC .................................................................................................... 541

17.3.1 Event output destination select register n (ELSELRn) (n = 00, 03, 04, 07, 13, 16 to 23) . 541

17.4 ELC Operation ...................................................................................................................... 543

18. RF TRANSCEIVER .................................................................................................................... 544

18.1 RF Transceiver Overview ..................................................................................................... 545

18.2 Pin Functions ........................................................................................................................ 546

18.2.1 Digital pin .......................................................................................................................... 546

18.2.2 Analog pin ......................................................................................................................... 547

18.2.3 Description of RF pin functions ......................................................................................... 547

Index - 8

18.3 Configuration of RF Transceiver ........................................................................................... 548

18.3.1 Digital block ...................................................................................................................... 548

18.3.2 Analog block ..................................................................................................................... 549

18.3.3 Oscillator block ................................................................................................................. 550

18.3.4 Power supply block ........................................................................................................... 550

18.4 Baseband Function ............................................................................................................... 551

18.4.1 Configuration .................................................................................................................... 551

18.4.2 Frame configuration .......................................................................................................... 552

18.4.3 Baseband Interrupt ........................................................................................................... 556

18.4.4 Baseband Function Controlling Register .......................................................................... 557

18.5 Serial Interface Only for Internal Communication ................................................................. 651

18.5.1 Overview ........................................................................................................................... 651

18.5.2 Communication specification ............................................................................................ 652

18.5.3 Communication Format .................................................................................................... 653

18.6 RF Mode ............................................................................................................................... 655

18.6.1 RF operating mode ........................................................................................................... 655

18.6.2 RF standby mode ............................................................................................................. 655

18.6.3 State transition .................................................................................................................. 656

18.6.4 Mode transition ................................................................................................................. 657

18.6.5 Pin state in each RF mode ............................................................................................... 662

18.6.6 Function state in each RF mode ....................................................................................... 662

18.7 Example of Procedure for Setting ......................................................................................... 663

18.7.1 Example of procedure for each operation ........................................................................ 663

18.7.2 Example of procedure for function setting ........................................................................ 666

18.7.3 Setting for each data rate ................................................................................................. 694

18.8 Notice For Using Baseband Function ................................................................................... 704

18.8.1 Notice About Transmission ............................................................................................... 704

18.8.2 Cautions on First and Second Address Filter Match Monitor Bits .................................... 704

19. INTERRUPT FUNCTIONS ......................................................................................................... 705

19.1 Interrupt Function Types ....................................................................................................... 705

19.2 Interrupt Sources and Configuration ..................................................................................... 705

19.3 Registers Controlling Interrupt Functions ............................................................................. 709

19.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) ............................... 712

19.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) ..................... 714

19.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,

PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) ........................................................... 716

19.3.4 External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling

edge enable registers (EGN0, EGN1) .............................................................................. 718

19.3.5 Program status word (PSW) ............................................................................................. 720

19.4 Interrupt Servicing Operations .............................................................................................. 721

19.4.1 Maskable interrupt request acknowledgment ................................................................... 721

19.4.2 Software interrupt request acknowledgment .................................................................... 724

19.4.3 Multiple interrupt servicing ................................................................................................ 724

19.4.4 Interrupt servicing during division instruction .................................................................... 728

19.4.5 Interrupt request hold ....................................................................................................... 730

20. STANDBY FUNCTION ............................................................................................................... 731

20.1 Standby Function .................................................................................................................. 731

Index - 9

20.2 Registers controlling standby function .................................................................................. 732

20.3 Standby Function Operation ................................................................................................. 733

20.3.1 HALT mode ....................................................................................................................... 733

20.3.2 STOP mode ...................................................................................................................... 738

20.3.3 SNOOZE mode ................................................................................................................ 743

21. RESET FUNCTION .................................................................................................................... 746

21.1 Timing of Reset Operation .................................................................................................... 748

21.2 Register for Confirming Reset Source .................................................................................. 752

21.2.1 Reset control flag register (RESF) .................................................................................... 752

22. POWER-ON-RESET CIRCUIT ................................................................................................... 755

22.1 Functions of Power-on-reset Circuit ..................................................................................... 755

22.2 Configuration of Power-on-reset Circuit ................................................................................ 756

22.3 Operation of Power-on-reset Circuit ..................................................................................... 756

23. VOLTAGE DETECTOR ............................................................................................................... 760

23.1 Functions of Voltage Detector ............................................................................................... 760

23.2 Configuration of Voltage Detector ......................................................................................... 761

23.3 Registers Controlling Voltage Detector ................................................................................. 761

23.3.1 Voltage detection register (LVIM) ...................................................................................... 762

23.3.2 Voltage detection level register (LVIS) .............................................................................. 763

23.4 Operation of Voltage Detector .............................................................................................. 764

23.4.1 When used as reset mode ................................................................................................ 764

23.4.2 When used as interrupt mode .......................................................................................... 766

23.4.3 When used as interrupt and reset mode .......................................................................... 768

23.5 Cautions for Voltage Detector ............................................................................................... 773

24. SAFETY FUNCTIONS ................................................................................................................ 775

24.1 Overview of Safety Functions ............................................................................................... 775

24.2 Registers Used by Safety Functions .................................................................................... 776

24.3 Operation of Safety Functions .............................................................................................. 776

24.3.1 Flash memory CRC operation function (high-speed CRC) .............................................. 776

24.3.2 CRC operation function (general-purpose CRC) .............................................................. 780

24.3.3 RAM parity error detection function ................................................................................. 783

24.3.4 RAM guard function .......................................................................................................... 785

24.3.5 SFR guard function ........................................................................................................... 786

24.3.6 Invalid memory access detection function ........................................................................ 787

24.3.7 Frequency detection function ........................................................................................... 789

24.3.8 A/D test function ............................................................................................................... 791

24.3.9 Digital output signal level detection function for I/O pins .................................................. 795

25. REGULATOR .............................................................................................................................. 796

25.1 Regulator Overview .............................................................................................................. 796

26. OPTION BYTE ............................................................................................................................ 797

26.1 Functions of Option Bytes .................................................................................................

26.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H) ............................................ 797

... 797

Index - 10

26.1.2 On-chip debug option byte (000C3H/ 010C3H) ................................................................ 798

26.2 Format of User Option Byte .................................................................................................. 799

26.3 Format of On-chip Debug Option Byte ................................................................................. 805

27. FLASH MEMORY ....................................................................................................................... 806

27.1 Serial Programming Using Flash Memory Programmer ....................................................... 807

27.1.1 Programming Environment ............................................................................................... 808

27.1.2 Communication Mode ....................................................................................................... 808

27.2 Connection of Pins on Board ................................................................................................ 810

27.2.1 P40/TOOL0 pin ................................................................................................................. 810

27.2.2 RESET

27.2.3 Port pins ............................................................................................................................ 811

27.2.4 REGC pin .......................................................................................................................... 811

27.2.5 X1 and X2 pins .................................................................................................................. 811

27.2.6 Power supply ..................................................................................................................... 811

27.3 Programming Method ........................................................................................................... 812

27.3.1 Serial programming procedure ......................................................................................... 812

27.3.2 Flash memory programming mode ................................................................................... 813

27.3.3 Selecting communication mode ........................................................................................ 815

27.3.4 Communication commands .............................................................................................. 816

27.4 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) .............. 817

27.5 Self-Programming ................................................................................................................. 818

27.5.1 Self-programming procedure ............................................................................................ 819

27.5.2 Boot swap function ........................................................................................................... 820

27.5.3 Flash shield window function ............................................................................................ 822

27.6 Security Settings ................................................................................................................... 823

27.7 Data Flash ............................................................................................................................ 825

27.7.1 Data flash overview .......................................................................................................... 825

27.7.2 Register controlling data flash memory ............................................................................ 826

27.7.3 Procedure for accessing data flash memory .................................................................... 827

pin ........................................................................................................................ 810

28. ON-CHIP DEBUG FUNCTION ................................................................................................... 828

28.1 Connecting E1 On-chip Debugging Emulator ....................................................................... 828

28.2 On-Chip Debug Security ID .................................................................................................. 829

28.3 Securing of User Resources ................................................................................................. 829

29. BCD CORRECTION CIRCUIT ................................................................................................... 831

29.1 BCD Correction Circuit Function ........................................................................................... 831

29.2 Registers Used by BCD Correction Circuit ........................................................................... 831

29.2.1 BCD correction result register (BCDADJ) ......................................................................... 831

29.3 BCD Correction Circuit Operation ......................................................................................... 832

30. INSTRUCTION SET ................................................................................................................... 834

30.1 Conventions Used in Operation List ..................................................................................... 835

30.1.1 Operand identifiers and specification methods ................................................................. 835

30.1.2 Description of operation column ....................................................................................... 836

30.1.3 Description of flag operation column ................................................................................ 837

30.1.4 PREFIX instruction ........................................................................................................... 837

30.2 Operation List ....................................................................................................................... 838

Index - 11

31. ELECTRICAL SPECIFICATIONS ............................................................................................... 856

31.1 Absolute Maximum Ratings .................................................................................................. 857

31.2 Oscillator Characteristics ...................................................................................................... 859

31.2.1 X1, XT1 characteristics ..................................................................................................... 859

31.2.2 On-chip oscillator characteristics ...................................................................................... 859

31.3 DC Characteristics ................................................................................................................ 860

31.3.1 Pin characteristics ............................................................................................................ 860

31.3.2 Supply current characteristics .......................................................................................... 865

31.4 AC Characteristics ................................................................................................................ 870

31.5 Peripheral Functions Characteristics .................................................................................... 875

31.5.1 Serial array unit ................................................................................................................ 875

31.5.2 Serial interface IICA .......................................................................................................... 891

31.6 Analog Characteristics .......................................................................................................... 894

31.6.1 A/D converter characteristics ............................................................................................ 894

31.6.2 POR characteristics ......................................................................................................... 895

31.6.3 LVD characteristics .......................................................................................................... 896

31.6.4 Power supply voltage rising slope characteristics ............................................................ 897

31.7 RF Transceiver Characteristics ............................................................................................ 898

31.7.1 Recommended operating conditions ................................................................................ 898

31.7.2 XIN Frequency Deviation .................................................................................................. 898

31.7.3 DC characteristics ............................................................................................................ 900

31.7.4 Power supply current ........................................................................................................ 900

31.7.5 Transceiver reception characteristics ............................................................................... 901

31.7.6 Transceiver transmission characteristics .......................................................................... 902

31.7.7 IEEE802.15.4g frequency/data rate table ......................................................................... 903

31.7.8 AC Characteristics ............................................................................................................ 904

31.8 RAM Data Retention Characteristics .................................................................................... 907

31.9 Flash Memory Programming Characteristics ........................................................................ 907

31.10 Dedicated Flash Memory Programmer Communication (UART) .......................................... 907

31.11 Timing for Switching Flash Memory Programming Modes ................................................... 908

32. PACKAGE DRAWING ................................................................................................................ 909

APPENDIX A REVISION HISTORY .................................................................................................. 910

A.1 Major Revisions in This Edition ............................................................................................ 910

A.2 Revision History of Preceding Editions ................................................................................. 912

Index - 12

RL78/G1H

RENESAS MCU

R01UH0575EJ0120

Dec 22, 2016

CHAPTER 1 OUTLINE

RL78/G1H is a microcontroller equipped with the low-power-consumption RF transceiver compatible with the SubGHz­band wireless communication. The wireless communication in the SubGHz band is best for the smart meter
communication part, HEMS controller, wireless sensor network, etc.

1.1 Features

Ultra-low power consumption technology

• Standby function of MCU: HALT mode, STOP mode, SNOOZE mode

• Standby function of RF unit: DLE mode, SLEEP mode

• RF operation transmission current: 21 mA (TYP.) (RF; 100 kbps, 2FSK, +10 dBm, 3.0 V/
at STOP mode of MCU)

: 36 mA (TYP.) (RF; 100 kbps, 2FSK, +13 dBm, 3.0 V/

at STOP mode of MCU)

• RF operation reception current: 6.9 mA (TYP.) (RF; 100 kbps, 2FSK, 3.0 V/at STOP mode of MCU)

• RF operation SLEEP mode (POWER_DOWN mode) current:

0.1 μA (TYP.) (3.0 V/at STOP mode of MCU)

Rev. 1.20

RL78 CPU core

• CISC architecture with 3-stage pipeline

• Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz operation with high­speed on-chip oscillator) to ultra-low speed (30.5 μs: @ 32.768 kHz operation with subsystem clock)

• Address space: 1 MB

• General-purpose registers: (8-bit register × 8) × 4 banks

• On-chip RAM: 24 to 48 KB

On-chip RF transceiver

• IEEE802.15.4g standard specification SubGHz-band transceiver

• RF frequency range: 863 to 928 MHz

• Modulation method: 2FSK/GFSK, 4FSK/GFSK

• Data rate: 2FSK/GFSK 10 to 300 kbps, 4FSK/GFSK 200/400 kbps

• Forward error correction (FEC) function

Code flash memory

• Code flash memory: 256 to 512 KB

• Block size: 1 KB

• Prohibition of block erase and rewriting (security function)

• On-chip debug function

• Self-programming (with boot swap function/flash shield window function)

R01UH0575EJ0120 Rev. 1.20 Page 1 of 920
Dec 22, 2016

RL78/G1H CHAPTER 1 OUTLINE

Data flash memory

• Data flash memory: 8 KB

• Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data
flash memory.

• Number of rewrites: 1,000,000 times (TYP.)

• Voltage of rewrites: V

High-speed on-chip oscillator

• Select from 32 MHz (TYP.), 24 MHz (TYP.), 16 MHz (TYP.), 12 MHz (TYP.), 8 MHz (TYP.), 6 MHz (TYP.), 4 MHz
(TYP.), 3 MHz (TYP.), 2 MHz (TYP.), and 1 MHz (TYP.)

Operating ambient temperature

•T

A = -40 to +85°C (A: Consumer applications, D: Industrial applications)

Power management and reset function

• On-chip power-on-reset (POR) circuit

• On-chip voltage detector (LVD) (Select interrupt and reset from 10 levels)

DD = 1.8 to 3.6 V

Data transfer controller (DTC)

• Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode

• Activation sources: Activated by interrupt sources.

• Chain transfer function

Event link controller (ELC)

• Event signals of 13 types can be linked to the specified peripheral function.

Serial interface

• CSI: 4 channels (1 channel of 4 channels is used for the internal communication between MCU and RF

transceiver.)

• UART: 2 channels

2

•I

C: 2 channels

Timer

• 16-bit timer: 9 channels

• 12-bit interval timer: 1 channel

• Real-time clock: 1 channel (calendar for 99 years, alarm function, and clock correction function)

• Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator)

A/D converter

• 10-bit resolution A/D converter (V

DD = 1.8 to 3.6 V)

• Analog input: 6 channels

I/O port

• I/O port: 41

• Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor

• Different potential interface: Can connect to a 1.8/2.5 V device

• On-chip clock output/buzzer output controller

R01UH0575EJ0120 Rev. 1.20 Page 2 of 920
Dec 22, 2016

RL78/G1H CHAPTER 1 OUTLINE

Cipher

• AES cipher processing (128-bit key length)

• Random number generator (true random number, complies with AIS31 standard)

Others

• On-chip BCD (binary-coded decimal) correction circuit

ROM, RAM capacities

Flash ROM Data flash RAM RL78/G1H

256 KB 8 KB 24 KB R5F11FLJ

384 KB 8 KB 32 KB R5F11FLK

512 KB 8 KB

Note This is about 47 KB when the self-programming function is used (For details, see CHAPTER 4).

48 KB

Note

R5F11FLL

R01UH0575EJ0120 Rev. 1.20 Page 3 of 920
Dec 22, 2016

RL78/G1H CHAPTER 1 OUTLINE

Fields of application:

A: Consumer applications, T

A = -40 to +85 °C

D: Industrial applications, T

A = -40 to +85 °C

Packaging specification

#20: Tray
#40: Embossed Tape

R 5 F 1 1 F L L A x x x N A # 2 0

Package type:

NA:HVQFN, 0.50 mm pitch

ROM number (Omitted with blank products)

ROM capacity:

J: 256 KB
K: 384 KB
L: 512 KB

Part No.

Pin count:

L: 64-pin

RL78/G1H

Memory type:

F : Flash memory

Renesas MCU

Renesas semiconductor product

1.2 Ordering Information

Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1H

R01UH0575EJ0120 Rev. 1.20 Page 4 of 920
Dec 22, 2016

RL78/G1H CHAPTER 1 OUTLINE

Table 1 - 1 Ordering Part Number List

Fields of

Pin count Package

64 pins 64-pin plastic HVQFN

× 9)

(9

Note For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1H.

Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part

numbers, refer to the target product page of the Renesas Electronics website.

Application

Note

A R5F11FLJANA#20,

D R5F11FLJDNA#20,

A R5F11FLKANA#20,

D R5F11FLKDNA#20,

A R5F11FLLANA#20,

D R5F11FLLDNA#20,

Ordering Part Number

R5F11FLJANA#40

R5F11FLJDNA#40

R5F11FLKANA#40

R5F11FLKDNA#40

R5F11FLLANA#40

R5F11FLLDNA#40

Code Flash

Memory

256 Kbytes 8 Kbytes

384 Kbytes

512 Kbytes

Data Flash

Memory

R01UH0575EJ0120 Rev. 1.20 Page 5 of 920
Dec 22, 2016

RL78/G1H CHAPTER 1 OUTLINE

REGIN

VSSDDC

VCCDDC

STANDBY

P156/ANI14

P155/ANI13

P22/ANI2

P21/ANI1/AV

REFM

P20/ANI0/AVREFP

P130

P04/SCK10

P03/SI10/RxD1

P02/SO10/TxD1

P144/SO30/TxD3

49
50
51
52
53
54
55
56
57
58

59
60
61
62
63
64

48 47 46 45 44 43

42 41 40 39 38 37 36 35 34 33

XOUT/REFCLKIN

XIN

AGNDRF1

RFIP

MODE2

VREGO3

VREGO2

GPIO4/ANTSW

GPIO3

GPIO2/ANTSELOUT1

GPIO1/ANTSELOUT0
GPIO0/CLKOUT
INTOUT
P82
P81
P80
P70/SCK21
P71/SI21

P75/INTP9
P76/INTP10
P77/INTP11
P31/TI03/TO03/INTP4
P63/SDAA1
P62/SCLA1
P61/SDAA0

P60/SCLA0

32
31
30
29
28
27
26
25
24
23

22
21
20
19
18
17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

P142/SCK30

P141/PCLBUZ1/INTP7

P140/PCLBUZ0/INTP6

P40/TOOL0

RESET

P124/XT2/EXCLKS

P123/XT1

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

V

SS

VDD

P143/SI30/RxD3

VCCRF

VREGO1

AGNDRF2

RFOUT

RFIN

MODE1

DDCOUT

P72/SO21

*Back: DIEGND

P120/ANI19

P100

<R>

1.3 Pin Configuration (Top View)

• 64-pin plastic HVQFN (9 × 9)

R01UH0575EJ0120 Rev. 1.20 Page 6 of 920
Dec 22, 2016

Caution Connect the metal pad (DIEGND) on the back of the package to GND of the board.

Remark

For pin identification, see 1.4 Pin Identification.

RL78/G1H CHAPTER 1 OUTLINE

1.4 Pin Identification

<MCU unit>

ANI0 to ANI2, ANI13: Analog Input P130, P137: Port 13

ANI14, ANI19: Analog Input P140 to P144: Port 14

REFM: Analog Reference P155, P156: Port 15

AV

Voltage Minus PCLBUZ0, PCLBUZ1: Programmable Clock Output/

REFP: Analog Reference Buzzer Output

AV

Voltage Plus REGC: Regulator Capacitance

EXCLK: External Clock Input RESET

(Main System Clock) RxD1, RxD3: Receive Data

EXCLKS: External Clock Input SCK10, SCK21,

(Subsystem Clock) SCK30: Serial Clock Input/Output

INTP0, INTP4: External Interrupt Input SCLA0, SCLA1: Serial Clock Output

INTP6, INTP7: SDAA0, SDAA1: Serial Data Input/Output

INTP9 to INTP11: SI10, SI21, SI30: Serial Data Input

P02 to P04: Port 0 SO10, SO21, SO30: Serial Clock Output

P20 to P22: Port 2 TI03: Timer Input

P31: Port 3 TO03: Timer Output

P40: Port 4 TOOL0: Data Input/Output for Tool

P60 to P63: Port 6 TxD1, TxD3: Transmit Data

P70 to P72,
P75 to P77:

P80 to P82: Port 8 V

P100: Port 10 X1, X2: Crystal Oscillator (Main System Clock)

P120 to P124: Port 12 XT1, XT2: Crystal Oscillator (Subsystem Clock)

Port 7 V

: Reset

DD: Power Supply

SS: Ground

<RF transceiver unit>

GPIO0-GPIO4 Transceiver I/O port VREGO1: Power supply stability

CLKOUT: Clock output capacity connection for RF

ANTSELOUT0, Antenna select XIN: Buffer input for the 48 MHz

ANTSELOUT1: X'tal oscillation

ANTSW: Antenna switch XOUT: 48 MHz crystal resonator output

VREGO2: Power supply stabilization REFCLKIN: External clock input

capacitor connection pin for VCO REGIN: Power supply input for the analog, and

VREGO3: Power supply stability capacity externally connect with DDCOUT

connection for PLL VSSDDC: DCDC converter GND

MODE1, MODE2: Mode switch DDCOUT: The DCDC converter output, to externally

RFIN: Transceiver GND connect with REGIN

RFIP: RF input VCCDDC: DCDC converter power supply

AGNDRF1: Transceiver GND STANDBY: Power down control input of the transceiver,

RFOUT: RF output and externally connect with P130

AGNDRF2: Transceiver GND INTOUT: Interrupt output

R01UH0575EJ0120 Rev. 1.20 Page 7 of 920
Dec 22, 2016

RL78/G1H CHAPTER 1 OUTLINE

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

INTERRUPUT

CONTROL

SERIAL ARRAY

UNIT1 (3ch)

RL78 CPU CORE

CSI20

A/D CONVERTER

CODE FLASH

MEMORY

DATA FLASH

MEMORY

RAM

DATA TRANSFER

CONTROL

EVENT LINK

CONTROLLER

BCD

ADJUSTMENT

PORT2

PORT3

PORT4

PORT6

PORT7

PORT8

PORT12

PORT13

PORT14

WINDOW

WATCHDOG

TIMER

12-BIT

INTERVAL

TIMER

REAL-TIME

CLOCK

RF TRANSCEIVER

PCLBUZ0
PCLBUZ1

INTP4

INTP6
INTP7

AV

REFP

AV

REFM

P16

SPI (SIN/SOUT/SCLK/SEN)

SCK20/P15

SI20/P14

SO20/P13

P130
P137

P121 to P12 4

4

P40

P31

3 P20 to P22

CONTROL

MCU part

RF part

PLL

ΔΣModulator

VCO

MAC

MODEM

LPFIFA

MIX

LPFIFA

MIX

LNA

～

HPA

ADC

ADC

RFIN

RFIP

RFOUT

DDC

OSC

XIN
XOUT/REFCLKIN

GPIO0/CLKOUT
GPIO1/ANTSELOUT0
GPIO2/ANTSELOUT1
GPIO3
GPIO4/ANTSW

VDD, VSS

VCCRF

DDCOUT
REGIN
VREGOUT1 to VREGOUT3

STANDBY

MODE1, MODE2

POR/LVD

CONTROL

POWER ON RESET/

VOLTAGE

DETECTOR

RESET

CONTROL

ON-CHIP DEBUG

SYSTEM

CONTROL

HIGH-SPEED

ON-CHIP

OSCILLATOR

VOLTAGE

REGULATOR

REGC

RESET

X1

X2/EXCLK

XT1

XT2/EXCLKS

TOOL0

PORT0 3 P02 to P0 4

P140 to P14 4

5

P80 to P82

3

P70 to P72
P75 to P77

6

P60 to P63

4

PORT1

TIMER ARRAY

UNIT0 (4ch)

ch0

TI03/TO03

2

2

ANI19/P120

3

INTP9
INTP10
INTP11

PORT10 P100

PORT15 2 P155, P156

SERIAL ARRAY

UNIT0 (1ch)

UART1

RxD1

TxD1

CSI10

SCK10

SI10

SO10

UART3

RxD3
TxD3

CSI30

SCK30

SI30

SO30

3

P10 to P12

Internal

Matching

BEF

ANI13, ANI14

VCCDDC, VSSDDC

VDC

AGNDRF1

AGNDRF2

ANI0 to ANI2

SERIAL

INTERFACE IICA 0

SDAA0
SCLA0

SERIAL

INTERFACE IICA 1

SDAA1
SCLA1

SCK21

SI21

SO21

CSI21

INTOUT

INTP0

LOW-SPEED

ON-CHIP

OSCILLATOR

TIMER RJ

ch1

ch2

ch3

TIMER ARRAY

UNIT1 (4ch)

ch0

ch1

ch2

ch3

3

2

MULTIPLIER&

DIVIDER

MULTIPLY-

ACCUMULATOR

P120

P30

INTP3

5

2

1.5 Block Diagram

R01UH0575EJ0120 Rev. 1.20 Page 8 of 920
Dec 22, 2016

RL78/G1H CHAPTER 1 OUTLINE

<R>

1.6 Outline of Functions

(1/2)

Item R5F11FLJ R5F11FLK R5F11FLL

Code flash memory (KB) 256 KB 384 KB 512 KB

Data flash memory (KB) 8 KB 8 KB 8 KB

RAM (KB)

24 KB 32 KB

Address space 1 MB

Main system clock High-speed system

clock

High-speed on-chip
oscillator clock (f

X1 (crystal/ceramic) oscillator, external main system clock input (EXCLK)
HS (high-speed main) mode: 1 to 20 MHz (V
HS (high-speed main) mode: 1 to 16 MHz (V
LS (low-speed main) mode: 1 to 8 MHz (V

HS (high-speed main) mode: 1 to 32 MHz (V

IH)

HS (high-speed main) mode: 1 to 16 MHz (V
LS (low-speed main) mode: 1 to 8 MHz (V

DD = 2.7 to 3.6 V)
DD = 2.4 to 3.6 V)

DD = 1.8 to 3.6 V)

DD = 2.7 to 3.6 V),
DD = 2.4 to 3.6 V),

DD = 1.8 to 3.6 V),

Subsystem clock XT1 (crystal) oscillator, external subsystem clock input (EXCLKS)

32.768 kHz (TYP.)

Low-speed on-chip oscillator clock 15 kHz (TYP.)

RF base clock 48 MHz (TYP.)

General-purpose register 8 bits

Minimum instruction execution time 0.03125

× 32 registers (8 bits × 8 registers × 4 banks)

μs (High-speed on-chip oscillator clock: fIH = 32 MHz operation)

μs (High-speed system clock: fMX = 20 MHz operation)

0.05

μs (Subsystem clock: fSUB = 32.768 kHz operation)

30.5

Instruction set • Data transfer (8/16 bits)

• Adder and subtractor/logical operation (8/16 bits)

• Multiplication (8 bits

× 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32

bits)

• Multiplication and Accumulation (16 bits

× 16 bits + 32 bits)

• Rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation),
etc.

I/O port Total

41

Note 2

CMOS I/O 26

CMOS input 5

CMOS output

N-ch open-drain I/O

1

Note 2

4

(6 V tolerance)

GPIO (RF unit) 5

SubGHz RF transceiver • IEEE802.15.4g standard specification SubGHz-band transceiver

• RF frequency range: 863 to 928 MHz

• Modulation method: 2FSK/GFSK, 4FSK/GFSK

Timer 16-bit timer 9 channels

Watchdog timer 1 channel

Real-time clock

1 channel

(RTC)

12-bit interval timer 1 channel

Timer output 1 channel

48 KB

Note 1

R01UH0575EJ0120 Rev. 1.20 Page 9 of 920
Dec 22, 2016

RL78/G1H CHAPTER 1 OUTLINE

(2/2)

Item R5F11FLJ R5F11FLK R5F11FLL

Clock output/buzzer output 2

• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: f

• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: f

10-bit resolution A/D converter 6 channels

Serial interface • CSI/UART: 2 channels

• CSI: 2 channels (1 channel of 2 channels is used for the internal communication between
MCU and RF transceiver.)

2

I

C bus

2 channels

Data transfer controller (DTC) 21 sources

Vectored interrupt
sources

Reset

Internal 26

External 7

• Reset by RESET

• Internal reset by watchdog timer

• Internal reset by power-on-reset

• Internal reset by voltage detector

• Internal reset by illegal instruction execution

• Internal reset by RAM parity error

• Internal reset by illegal-memory access

Power-on-reset circuit • Power-on-reset: 1.51 (TYP.)

• Power-down-reset: 1.50 (TYP.)

Voltage detector • Rising edge: 1.88 V to 3.13 V (10 stages)

• Falling edge: 1.84 V to 3.06 V (10 stages)

On-chip debug function Provided

Power supply voltage V

Operating ambient temperature T

DD = 1.8 to 3.6 V

A = -40 to +85 °C (A: Consumer applications, D: Industrial applications)

Package 64-pin HVQFN (9

MAIN = 20 MHz operation)

SUB = 32.768 kHz operation)

pin

Note 3

× 9), (0.5 mm pitch)

Note 1. This is about 47 KB when the self-programming function is used (For details, see CHAPTER 4).
Note 2. When using the RF transceiver, pins which a user uses for external connection between the MCU and RF transceiver on

the board are included.

Note 3. The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.

R01UH0575EJ0120 Rev. 1.20 Page 10 of 920
Dec 22, 2016

RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER

CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER

2.1 Connection Pins of MCU and RF Transceiver

Table 2 - 1 lists the pins connected inside the RL78/G1H. Table 2 - 2 lists the pins which need to be connected on the
board by the user.
These pins require initial settings for an appropriate mode/level before starting communication with the RF
transceiver.

Table 2 - 1 Internal Pin Connection

Pin Name

MCU RF

P10 OSCDRVSEL This is a switch signal that has the buffer drive capability for 48 MHz crystal

P11 DON This is an enable signal of DCDC converter of RF unit. It becomes active

P12 RFRESETB Hardware reset signal for the RF unit. RFRESETB=Low resets RF unit.

P13/SO20 SIN Serial interface used for internal communication between blocks. Since it is

P14/SI20

P15/SCK20 SCLK This is an operation clock of Serial interface for internal communication

P16 SEN This is a communication enable control signal of Serial interface (RF unit) for

P30/INTP3

SOUT

INTOUT

unit

Note

oscillator.
The buffer size (current) of the oscillator becomes smaller when
OSCDRVSEL is High.
The buffer size (current) of the oscillator becomes larger when OSCDRVSEL
is Low. P10, which is an internal I/O pin of MCU, controls OSCDRVSEL.

(DCDC converter is operable) when DON is set to High. P11, which is an
internal I/O pin of MCU, controls DON.

RFRESETB is controlled by P12 which is an internal I/O port of the MCU.

dedicated to internal communication (MCU: output data, RF unit: input data),
it cannot be used for communication with external modules.

Serial interface used for internal communication between blocks. Since it is
dedicated to internal communication (MCU: input data, RF unit: output data),
it cannot be used for communication with external modules.

between blocks. Since it is dedicated to internal communication, it cannot be
used for communication with external modules.

internal communication between blocks.
It becomes active (Serial communication enabled) when SEN is Low. P16,
which is an internal I/O of MCU, controls SEN.

Note

Interrupt request signal from RF transceiver. If an interrupt source is
generated in RF unit, the status is output from INTOUT. MCU receives this
status at INTP3, and can execute the interrupt processing.

Function Direction

MCU to RF unit

MCU to RF unit

MCU to RF unit

MCU to RF unit

RF unit to MCU

MCU to RF unit

MCU to RF unit

RF unit to MCU

Note These pin outputs might be high impedance causing state of RF transceiver. These pins are required to fix by MCU in

this case. For details, see CHAPTER 18 RF TRANSCEIVER.

Table 2 - 2 Pins Externally Connected on User Board

Pin Name

MCU RF unit

P130 STANDBY This is a power-down control signal of RF unit. RF unit becomes operable

when STANDBY is High. RF unit enters the SLEEP state when STANDBY
is Low. P130, which is an I/O pin of MCU, controls STANDBY. Connect
P130 and STANDBY externally (on the board).

Function Direction

MCU to RF unit

R01UH0575EJ0120 Rev. 1.20 Page 11 of 920
Dec 22, 2016

RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER

2.2 Communication Interface Between MCU and RF Transceiver

3-wire serial I/O (CSI) is used for the SPI interface for internal communication between the MCU and RF unit. For
data transfer between the MCU and RF unit, a transfer clock is output from the MCU to the RF unit and data is
transmitted and received. The operation of the 3-wire serial I/O (CSI) is shown in Table 2 - 3.

Table 2 - 3 3-Wire Serial IO Between MCU and RF Transceiver

Item CSI20 (dedicated for internal communication)

Target channel Channel 0 of serial array unit 1 (SAU1)

Pins used SCK20, SI20, SO20 (pins for communication/all on-chip dedicated internal pin), and P16 (pin for control

of the SEN pin/on-chip dedicated internal I/O pin)

Operation mode Only transmission mode or transmission/reception mode is supported.

Master/slave Only master is supported.

Interrupt Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)

can be selected.

Error detection flag Overrun error detection flag (OVF20)

Transfer data length Only 8-bit length is supported.

Transfer rate Within the range that satisfies the AC characteristics of the electrical specifications

Data phase Only Type 1 is supported.

Clock phase Only Type 1 is supported.

Data direction Only MSB first is supported.

Caution Use the RL78/G1D so that these conditions and the specifications of the AC characteristics (CHAPTER 31

ELECTRICAL SPECIFICATIONS) are satisfied.

R01UH0575EJ0120 Rev. 1.20 Page 12 of 920
Dec 22, 2016

RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER

2.3 Initial Settings of Unused Internal Pins of MCU

After reset release, the following internal pins of the MCU need to be set to output mode (set the port registers and
port mode registers to 0) by software.

P00, P01, P05, P06, P17, P23 to P27, P41 to P47, P50 to P57, P64 to P67, P73 to P74, P83 to P87
P101, P102, P110, P111, P145 to P147, P150 to P154

R01UH0575EJ0120 Rev. 1.20 Page 13 of 920
Dec 22, 2016

RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER

XIN

XOUT

2.4 Base Operation Clock of RF Unit

RF unit operation requires a 48 MHz clock. Table 2 - 4 shows clock resonator connection and Figure 2 - 1 shows the
clock configuration.

Table 2 - 4 Clock Resonator Connection (Using on-chip low-speed oscillator in the RF unit as a slow clock.)

Pin Name Funcion

XIN Base clock of the RF unit.

XOUT

Figure 2 - 1 Clock Configuration

Connect a 48 MHz crystal resonator.

Caution This figure only shows connection between the clock resonator pins and clock line.

R01UH0575EJ0120 Rev. 1.20 Page 14 of 920
Dec 22, 2016

RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER

47 μF

1 μF

* Place the entire capacitor and
inductor elements close to the pin.

1 μF

1 μF

1 μF

1 μF

1 μF

1 μF

0.47 μF

10 μH

1.8 to 3.6 V

RF

MCU

VDD VCCDDC VCCRF DDCOUT REGIN

VREGO1

VREGO2

VREGO3

VSSDDCVSS AGNDRF2AGNDRF1

REGC

2.5 Power Configuration

Power is supplied to both the MCU and RF unit. The RF unit includes a DC-DC converter. The power switched at
the DC-DC converter is output to the DDCOUT pin. The power is smoothed by an inductor and capacitor to step
down the voltage, and then supplied to the REGIN.
Figure 2 - 2 shows the power configuration of the RL78/G1H.

Figure 2 - 2 Power Configuration

R01UH0575EJ0120 Rev. 1.20 Page 15 of 920
Dec 22, 2016

RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER

2.6 Peripheral Circuits’Connection Diagram

Figure 2 - 3 RL78/G1H (64-pin) Peripheral Circuits’Connection Diagram (without ANTSW)

ANT

C8

VCC(3V)

C10

C11

XTAL(48MHz)

C12

C9

L3

C7

L2

L4

C6

C4C5

46.XIN

48.VCCRF

49.REGIN

C13

50.VSSDDC

C14

51.DDCOUT

L1

52.VCCDDC

C15

53.STANDBY

54.P100

55.P156

56.P155

57.P22

58.P21

59.P20

60.P130

61.P04

62.P03

63.P02

64.P144

1.P143

47.XOUT/REFCLKIN

2.P142

3.P141

45.VREGO1

4.P140

44.AGNDRF2

5.P120

41.RFIP

43.RFOUT

42.AGNDRF1

64HVQFN

8.P124

7.RESETB

6.P40

C1

R1

40.RFIN

9.P123

39.MODE1

10.P137

38.MODE2

11.P122

37.VREGO3

12.P121

36.VREGO2

13.REGC

C2

35GPIO4

14.VSS

34.GPIO3

15.VDD

33.GPIO2

32.GPIO1

31.GPIO0

30.INTOUT

29.P82

28.P81

27.P80

26.P70

25.P71

24.P72

23.P75

22.P76

21.P77

20.P31

19.P63

18.P62

17.P61

16.P60

C3

Part number Remarks

C6 Acceptable error: use ±0.25 pF accuracy part

C7 Acceptable error: use ±0.25 pF accuracy part

C8 Acceptable error: use ±0.25 pF accuracy part

L1(10 μH) MLZ1608M100WT(10.0 μH ±20 %) is comfortable. Required inductor with good DC superposition

characteristics.
Small loss (DC resistance and AC resistance at operational frequency) is comfortable.

L2, L3, L4 Use chip inductance for high frequency.

Required high Q at 1 GHz band, and self-resonance is higher than 1 GHz.

Caution The multiple power supply smoothing capacitors may be connected to a pin depending on the

routing of the board wiring, noise, and others

.

R01UH0575EJ0120 Rev. 1.20 Page 16 of 920
Dec 22, 2016

RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER

Figure 2 - 4 RL78/G1H (64-pin) Peripheral Circuits’Connection Diagram (with ANTSW)

ANT

VCC(3V)

C10

C11

X1

XTAL(48MHz)

C12

48.VCCRF

49.REGIN

C13

50.VSSDDC

C14

51.DDCOUT

L1

52.VCCDDC

C15

53.STANDBY

54.P100

55.P156

56.P155

57.P22

58.P21

59.P20

60.P130

61.P04

62.P03

63.P02

64.P144

1.P143

46.XIN

47.XOUT/REFCLKIN

2.P142

3.P141

C9

45.VREGO1

4.P140

RFSW

C17

C18

L5

43.RFOUT

42.AGNDRF1

44.AGNDRF2

64HVQFN

7.RESETB

6.P40

5.P120

41.RFIP

8.P124

C16

40.RFIN

39.MODE1

9.P123

10.P137

38.MODE2

11.P122

37.VREGO3

12.P121

C4C5

36.VREGO2

13.REGC

35GPIO4

14.VSS

34.GPIO3

15.VDD

33.GPIO2

30.INTOUT

16.P60

32.GPIO1

31.GPIO0

29.P82

28.P81

27.P80

26.P70

25.P71

24.P72

23.P75

22.P76

21.P77

20.P31

19.P63

18.P62

17.P61

C2

C1

R1

C3

Part number Remarks

C18 Acceptable error: use ±0.25 pF accuracy part

L1(10 μH) MLZ1608M100WT(10.0 μH ±20 %) is comfortable. Required inductor with good DC superposition

characteristics.
Small loss (DC resistance and AC resistance at operational frequency) is comfortable.

L5 Use chip inductance for high frequency.

Required high Q at 1 GHz band, and self-resonance is higher than 1 GHz.

Caution The multiple power supply smoothing capacitors may be connected to a pin depending on the

routing of the board wiring, noise, and others.

R01UH0575EJ0120 Rev. 1.20 Page 17 of 920
Dec 22, 2016

RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER

GND

GND

14.VSS

13.REGC

12.P121

9.P123

8.P124

7.RESETB

6.P40

5.P120

2.P142

1.P143

3.P141

4.P140

10.P137

11.P122

15.VDD

16.P60

30.INTOUT

31.GPIO0

32.GPIO1

29.P82

28.P81

27.P80

26.P70

25.P71

24.P72

23.P75

22.P76

21.P77

20.P31

19.P63

18.P62

17.P61

48.VCCRF

35GPIO4

36.VREGO2

37.VREGO3

40.RFIN

41.RFIP

42.AGNDRF1

43.RFOUT

44.AGNDRF2

47.XOUT/REFCLKIN

46.XIN

45.VREGO1

39.MODE1

38.MODE2

34.GPIO3

33.GPIO2

49.REGIN

51.DDCOUT

50.VSSDDC

52.VCCDDC

53.STANDBY

54.P100

55.P156

56.P155

57.P22

58.P21

59.P20

60.P130

61.P04

62.P03

63.P02

64.P144

C1

C2

C3

R1

VCC(3V)

L1

C15

C14

C13

ANT

VCC

OUT

1

2

4

3

TCXO

U1

C12

C11 C10

C9

L4

L2

L3

C6

C8

C7

C4C5

Figure 2 - 5 RL78/G1H (64-pin) Peripheral Circuit Connection Diagram (Using TCXO)

Part number Remarks

C10 100 pF

C11 100 pF

Caution The multiple power supply smoothing capacitors may be connected to a pin depending on the

routing of the board wiring, noise, and others.

R01UH0575EJ0120 Rev. 1.20 Page 18 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

CHAPTER 3 PIN FUNCTIONS

3.1 Port Functions

Pin I/O buffer power supplies depend on the pin. The relationship between these power supplies and the pins is
shown below.

Table 3 - 1 Pin I/O Buffer Power Supplies

Power Supply Corresponding Pins

DD • P02 to P04, P10 to P16, P20 to P22, P30, P31, P40, P60 to P63, P70 to P72, P75 to P77,

V

P80 to P82, P120 to P124, P130, P137, P140 to P144, P155, P156

, REGC

VCCDDC

• RESET

• GPIO0 to GPIO4, STANDBY, MODE1, MODE2, INTOUT

R01UH0575EJ0120 Rev. 1.20 Page 19 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions.

(1/2)

Function

Name

P02

P03

Pin Type I/O

Note 1

7-3-4

Note 1

8-3-4

I/O Prohibit

P04 8-1-4 Input port SCK10

Note 3

P10

P11

P12

P13

P14

P15

P16

— I/O Input port — Port 1.

Note 3

Note 3

Note 3

Note 3

Note 3

Note 3

P20 4-3-3 I/O Analog

P21 ANI1/AV

P22 ANI2

Note 3

P30

8-1-4 I/O Input port INTP3 Port 3.

P31 7-1-3 TI03/TO03/INTP4

P40 7-1-3 I/O Input port TOOL0 Port 4.

P60 12-1-2 I/O Input port SCLA0 Port 6.

P61 SDAA0

P62

P63 SDAA1

P70 7-1-3 I/O Input port SCK21 Port 7.

P71 7-1-4 SI21

P72 7-1-3 SO21

P75 NTP9

P76 INTP10

P77 INTP11

After Reset

Release

Note 2

I/O

function

Alternate Function Function

SO10/TxD1 Port 0.

SI10/RxD1

3-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
Input of P03 and P04 can be set to TTL input buffer.
Output of P02 to P04 can be set to N-ch open-drain
output (V
The digital I/O of P02 and P03 is prohibited at the
reset release

—

—

SO20

7-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.

SI20

SCK20

—

ANI0/AV

REFP Port 2.

REFM

3-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input

2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.

1-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.

4-bit I/O port.
Input/output can be specified in 1-bit units.

SCLA1

Output of P60 to P63 is N-ch open-drain output
(6 V tolerance).

6-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
Output of P71 can be set to N-ch open-drain output
(V

DD tolerance).

DD tolerance).

Note 2

.

Note 4

.

Note 1. Input of A/D converter is not supported.
Note 2. Each pin can be specified as digital I/O port by setting port mode control register x (PMCx) (Can be specified in 1-bit

units).

Note 3. This pin is used for connection between the MCU and RF transceiver. For details, refer to CHAPTER 2 CONNECTION

BETWEEN MCU AND RF TRANSCEIVER

.

Note 4. Each pin can be specified as either digital or analog by setting the A/D port configuration register (ADPC).

R01UH0575EJ0120 Rev. 1.20 Page 20 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

(2/2)

Function

Name

P80 8-1-4 I/O Input port — Port 8.

P81 —

P82 7-1-4 —

P100 7-3-3 I/O Prohibit I/O — Port 10.

P120 7-3-3 I/O Analog function ANI19 Port 12.

P121 2-2-1 Input Input port X1

P122 X2/EXCLK

P123 XT1

P124 XT2/EXCLKS

P130

P137 2-1-2 Input Input port INTP0

P140 7-1-3 I/O Input port PCLBUZ0/INTP6 Port 14.

P141 PCLBUZ1/INTP7

P142 8-1-4 SCK30

P143 SI30/RxD3

P144 7-1-4 SO30/TxD3

P155 4-3-3 I/O Analog function ANI13 Port 15.

P156 ANI14

RESET

Pin Type I/O

Note 2

1-1-1 Output Output port — Port 13.

2-1-1 Input — — Input-only pin for external reset.

After Reset

Release

Alternate Function Function

3-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting at input port.

1-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting at input port.
The digital I/O of P100 is prohibited at reset release

1-bit I/O port and 4-bit input-only port.
P120 can be set to analog I/O.
For only P120, input/output can be specified.
For only P120, use of an on-chip pull-up resistor can be specified
by a software setting at input port.

1-bit output-only port and 1-bit input-only port.

5-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting at input port.
Input of P142 and P143 can be set to TTL input buffer.
Output of P142 to P144 can be set to N-ch open-drain output

DD tolerance).

(V

2-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input

Connect to V
used.

DD directly or via a resistor when external reset is not

Note 3

.

Note 1

.

Note 1. Each pin can be specified as digital I/O port by setting port mode control register x (PMCx) (Can be specified in 1-bit

units).

Note 2. This pin is used for connection between the MCU and RF transceiver. For details, refer to CHAPTER 2 CONNECTION

BETWEEN MCU AND RF TRANSCEIVER

.

Note 3. Each pin can be specified as either digital or analog by setting the A/D port configuration register (ADPC).

R01UH0575EJ0120 Rev. 1.20 Page 21 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

3.2 Functions other than port pins

Function Name I/O Function

ANI0 to ANI2, ANI13, ANI14,
ANI19

INTP0, INTP3

Note

, INTP4, INTP6,

INTP7, INTP9 to INTP11

Input

Input

PCLBUZ0, PCLBUZ1 Output Clock output/buzzer output

REGC

RESET

Input

RxD1, RxD3 Input Serial data input pins of serial interface UART1 and UART3

TxD1, TxD3 Output Serial data output pins of serial interface UART1 and UART3

SCK10, SCK20

Note

, SCK21,

SCK30

SI10, SI20

SO10, SO20

Note

, SI21, SI30

Note

, SO21, SO30

Input

Output

SCLA0, SCLA1 I/O Serial clock I/O pins of serial interface IICA0 and IICA1

SDAA0, SDAA1 I/O Serial data I/O pins of serial interface IICA0 and IICA1

TI03 Input The pins for inputting an external count clock/capture trigger to 16-bit timer 03

TO03 Output Timer output pins of 16-bit timer 03

X1, X2 — Resonator connection for main system clock

EXCLK Input External clock input for main system clock

XT1, XT2 — Resonator connection for subsystem clock

EXCLKS Input External clock input for subsystem clock

V

DD — Positive power supply for all pins

REFP Input A/D converter reference potential (+ side) input

AV

REFM Input A/D converter reference potential (- side) input

AV

SS — Ground potential for all pins

V

TOOL0 I/O Data I/O for flash memory programmer/debugger

A/D converter analog input (see

Figure 13 - 30 Analog Input Pin Connection)

External interrupt request input
Valid edge specification: Rising edge, falling edge, or both rising and falling edges

Pin for connecting regulator output stabilization capacitance for internal operation.
Connect this pin to V

—

Also, use a capacitor with good characteristics, since it is used to stabilize internal

SS via a capacitor (0.47 to 1 μF).

voltage.

This is the active-low system reset input pin.
When the external reset pin is not used, connect this pin directly or via a resistor to

DD.

V

Serial clock I/O pins of serial interface CSI10, CSI20, CSI21, and CSI30

I/O

Serial data input pins of serial interface CSI10, CSI20, CSI21, and CSI30

Serial data output pins of serial interface CSI10, CSI20, CSI21, and CSI30

Note This pin is used for connection between the MCU and RF transceiver. For details, refer to CHAPTER 2 CONNECTION

BETWEEN MCU AND RF TRANSCEIVER

.

Caution After reset release, the relationships between P40/TOOL0 and the operating mode are as follows.

Table 3 - 2 Relationships Between P40/TOOL0 and Operation Mode After Reset Release

P40/TOOL0 Operating mode

DD Normal operation mode

V

0 V Flash memory programming mode

For details, see 27.3 Programming Method.

Remark

A bypass capacitor about 0.1 μF must be connected for measures of noises and latch-up between VDD and VSS lines on
the shortest distance and with comparative thick wire.

R01UH0575EJ0120 Rev. 1.20 Page 22 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

3.3 Connection of Unused Pins

Table 3 - 3 shows the Connection of Unused Pins.

<R>

Table 3 - 3 Connection of Unused Pins

Pin Name I/O Recommended Connection of Unused Pins

P02 to P04 I/O Input: Independently connect to V

P20 to P22

Output: Leave open.

P31

P40/TOOL0 Input: Independently connect to V

Output: Leave open.

P60 to P63 Input: Independently connect to V

Output: Set the port’s output latch to 0 and leave the pins open, or set the port’s output latch to

1 and independently connect the pins to V

P70 to P72, P75 to P77 Input: Independently connect to V

P80 to P82

Output: Leave open.

P100

P120

P121 to P124 Input Independently connect to V

P130 Output Leave open.

P137 Input Independently connect to V

P140 to P144 I/O Input: Independently connect to V

Output: Leave open.

P155, P156 Input: Independently connect to V

Output: Leave open.

RESET

REGC — Connect to V

Input Connect to VDD directly or via a resistor.

SS via a capacitor (0.47 to 1 μF).

GPIO0/CLKOUT I/O Input: Leave open or independently connect to VCCDDC or VSSDDC via a resistor.

GPIO1/ANTSELOUT0

Output: Leave open.

GPIO2/ANTSELOUT1

GPIO3

GPIO4/ANTSW

DD or VSS via a resistor.

DD via a resistor, or leave open.

DD or VSS via a resistor.

DD or VSS via a resistor.

DD or VSS via a resistor.

DD or VSS via a resistor.

DD or VSS via a resistor.

DD or VSS via a resistor.

DD or VSS via a resistor.

Remark For how to handle the ports other than the above, see CHAPTER 5 PORT FUNCTIONS.

R01UH0575EJ0120 Rev. 1.20 Page 23 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Output latch

(Pmn)

RD

WR

PORT

Internal bus

VDD

VSS

P-ch

N-ch

Pmn

RESET RESET

Alternate

function

Internal bus

RD

Pmn

3.4 Pin Block Diagrams

For the pin types listed in 3.1 Port Functions, pin block diagrams are shown in Figures 3 - 1 to 3 - 13.

Figure 3 - 1 Pin Block Diagram of Pin Type 1-1-1

Figure 3 - 2 Pin Block Diagram of Pin Type 2-1-1

Figure 3 - 3 Pin Block Diagram of Pin Type 2-1-2

Remark Refer to 3.1 Port Functions for alternate functions.

R01UH0575EJ0120 Rev. 1.20 Page 24 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Alternate function

Alternate function

RD

RD

Clock generator

OSCSEL/

OSCSELS

CMC

EXCLK, OSCSEL/

EXCLKS, OSCSELS

CMC

N-ch P-ch

P122/X2/EXCLK/Alternate function
P124/XT2/EXCLKS/Alternate function

P121/X1/Alternate function
P123/XT1/Alternate function

Internal bus

Figure 3 - 4 Pin Block Diagram of Pin Type 2-2-1

Remark Refer to 3.1 Port Functions for alternate functions.

R01UH0575EJ0120 Rev. 1.20 Page 25 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Internal bus

WRPORT

RDPORT

WRADPC

Output latch

(Pmn)

ADPC3 to ADPC0

N-ch

P-ch

A/D converter

PM register

(PMmn)

WRPM

PMS register

WRPMS

0: Analog input
1: Digital I/O

N-ch

P-ch

VDD

VSS

Pmn

1

0

1

0

ADPC

Figure 3 - 5 Pin Block Diagram of Pin Type 4-3-3

R01UH0575EJ0120 Rev. 1.20 Page 26 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Internal bus

Alternate function

(SAU)

PM register

(PMmn)

PMS register

Output latch

(Pmn)

Alternate function

PU register

(PUmn)

RDPORT

WRPORT

WRPMS

WRPU

Alternate function

(other than SAU)

WRPM

Pmn

P-ch

P-ch

N-ch

V

DD

VSS

VDD

Schmitt2

1

0

1

0

Figure 3 - 6 Pin Block Diagram of Pin Type 7-1-3

Remark 1. Refer to 3.1 Port Functions for alternate functions.
Remark 2. SAU: Serial array unit

R01UH0575EJ0120 Rev. 1.20 Page 27 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Internal bus

POM register

(POMmn)

PM register

(PMmn)

PMS register

Output latch

(Pmn)

Alternate function

PU register

(PUmn)

WRPORT

WRPMS

WRPU

Alternate function

(SAU)

WRPM

Pmn

P-ch

P-ch

N-ch

V

DD

VSS

VDD

Schmitt2

Alternate function

(other than SAU)

WRPOM

1

0

1

0

RDPORT

Figure 3 - 7 Pin Block Diagram of Pin Type 7-1-4

Remark 1. Refer to 3.1 Port Functions for alternate functions.
Remark 2. SAU: Serial array unit

R01UH0575EJ0120 Rev. 1.20 Page 28 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Internal bus

PM register

(PMmn)

PU register

(PUmn)

PMC register

(PMCmn)

Alternate function

Output latch

(Pmn)

PMS register

Alternate function

(SAU)

VDD

P-ch

N-ch

V

SS

Pmn

P-ch

VDD

WRPU

WRPMC

RDPORT

WRPORT

WRPMS

Schmitt2

P-ch

N-ch

A/D converter

Alternate function

(other than SAU)

WRPM

1

0

1

0

Figure 3 - 8 Pin Block Diagram of Pin Type 7-3-3

Remark 1. Refer to 3.1 Port Functions for alternate functions.
Remark 2. SAU: Serial array unit

R01UH0575EJ0120 Rev. 1.20 Page 29 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Internal bus

PM register

(PMmn)

PU register

(PUmn)

PMC register

(PMCmn)

Alternate function

Output latch

(Pmn)

PMS register

POM register

(POMmn)

VDD

P-ch

N-ch

V

SS

Pmn

P-ch

VDD

WRPU

WRPMC

RDPORT

WRPORT

WRPMS

Schmitt2

P-ch

N-ch

A/D converter

Alternate function

(SAU)

WRPM

Alternate function

(other than SAU)

WRPOM

1

0

1

0

Figure 3 - 9 Pin Block Diagram of Pin Type 7-3-4

Remark 1. Refer to 3.1 Port Functions for alternate functions.
Remark 2. SAU: Serial array unit

R01UH0575EJ0120 Rev. 1.20 Page 30 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Internal bus

PU register

(PUmn)

PIM register

(PIMmn)

Alternate function

Output latch

(Pmn)

PMS register

PM register

(PMmn)

Alternate function

(SAU)

WRPMS

WRPORT

RDPORT

WRPIM

WRPU

VDD

P-ch

N-ch

V

SS

Pmn

P-ch

VDD

CMOS

TTL

Alternate function

(other than SAU)

WRPM

Schmitt2

1

0

1

0

Figure 3 - 10 Pin Block Diagram of Pin Type 8-1-3

Remark 1. Refer to 3.1 Port Functions for alternate functions.
Remark 2. SAU: Serial array unit

R01UH0575EJ0120 Rev. 1.20 Page 31 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Internal bus

PU register

(PUmn)

PIM register

(PIMmn)

Alternate function

Output latch

(Pmn)

PMS register

PM register

(PMmn)

POM register

(POMmn)

WRPMS

WRPORT

RDPORT

WRPIM

WRPU

VDD

P-ch

N-ch

V

SS

Pmn

P-ch

VDD

CMOS

TTL

Alternate function

(SAU)

WRPM

Alternate function

(other than SAU)

WRPOM

Schmitt2

1

0

1

0

Figure 3 - 11 Pin Block Diagram of Pin Type 8-1-4

Remark 1. Refer to 3.1 Port Functions for alternate functions.
Remark 2. SAU: Serial array unit

R01UH0575EJ0120 Rev. 1.20 Page 32 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

CMOS

TTL

Pmn

Internal bus

PU register

(PUmn)

PIM register

(PIMmn)

PMC register

(PMCmn)

Alternate function

Output latch

(Pmn)

PMS register

PM register

(PMmn)

POM register

(POMmn)

P-ch

N-ch

A/D converter

P-ch

N-ch

VDD

VSS

P-ch

VDD

WRPU

WRPIM

WRPMC

RDPORT

WRPORT

WRPMS

Alternate function

(SAU)

WRPM

Schmitt2

Alternate function

(other than SAU)

WRPOM

1

0

1

0

Figure 3 - 12 Pin Block Diagram of Pin Type 8-3-4

Remark 1. Refer to 3.1 Port Functions for alternate functions.
Remark 2. SAU: Serial array unit

R01UH0575EJ0120 Rev. 1.20 Page 33 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

Internal bus

Output latch

(Pmn)

Alternate function

PMS register

Alternate function

(SAU)

PM register

(PMmn)

WRPORT

WRPMS

RDPORT

N-ch

VSS

Pmn

Schmitt1

Alternate function

(other than SAU)

WRPM

1

0

1

0

Figure 3 - 13 Pin Block Diagram of Pin Type 12-1-2

Remark 1. Refer to 3.1 Port Functions for alternate functions.
Remark 2. SAU: Serial array unit

R01UH0575EJ0120 Rev. 1.20 Page 34 of 920
Dec 22, 2016

RL78/G1H CHAPTER 3 PIN FUNCTIONS

STANDBY, MODE1, MODE2 Input

Input enable

GPIO0 to GPIO4

Output enable
Data

Input

Figure 3 - 14 Pin Block Diagram of STANDBY, MODE1, MODE2

Figure 3 - 15 Pin Block Diagram of Pin GPIO0 to GPIO4

Figure 3 - 16 Pin Block Diagram of Pin INTOUT

INTOUT

Output enable
Data

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Dec 22, 2016

RL78/G1H CHAPTER 4 CPU ARCHITECTURE

CHAPTER 4 CPU ARCHITECTURE

4.1 Memory Space

Products in the RL78/G1H can access a 1 MB address space. Figures 4 - 1 to 4 - 3 show the memory maps.

R01UH0575EJ0120 Rev. 1.20 Page 36 of 920
Dec 22, 2016

RL78/G1H CHAPTER 4 CPU ARCHITECTURE

FFFFFH

FFEE0H
FFEDFH
F9F00H
F9EFFH

F3000H
F2FFFH

F1000H
F0FFFH

F0800H
F07FFH

F0000H
EFFFFH

40000H
3FFFFH

00000H

Data memory

space

Program

memory

space

FFF00H
FFEFFH

Special function register (SFR)

256 bytes

General-purpose register

32 bytes

RAM

Notes 1, 2

24 Kbytes

Mirror

27.75 Kbytes

Data flash memory

8 Kbytes

Reserved

Extended special function register

(2nd SFR)

2 Kbytes

Reserved

Code flash memory

256 Kbytes

00000H

01FFFH

010CEH
010CDH

010C4H
010C3H

010C0H
010BFH

01080H
0107FH

000CEH
000CDH

01000H
00FFFH

3FFFFH

000C4H
000C3H

000C0H
000BFH

00080H
0007FH

Boot cluster 0

Note 4

Boot cluster 1

Program area

Program area

CALLT table area

64 bytes

Vector table area

128 bytes

Option byte area

Note 3

4 bytes

CALLT table area

64 bytes

Vector table area

128 bytes

On-chip debug security

ID setting area

Note 3

10 bytes

Option byte area

Note 3

4 bytes

On-chip debug security

ID setting area

Note 3

10 bytes

Figure 4 - 1 Memory Map (R5F11FLJ)

Note 1. Do not allocate RAM addresses which are used as a stack area, a data buffer, a branch destination of vector interrupt

processing, and a DTC transfer destination/transfer source to the area FFE20H to FFEDFH when performing self­programming and rewriting the data flash memory.

Note 2. Instructions can be executed from the RAM area excluding the general-purpose register area.
Note 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H

When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug

Note 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.6 Security Settings).
Note 5. Use of the area FA300H to FA6FFH is prohibited when using the on-chip debugging trace function.

Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to

proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively.

Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 24.3.3 RAM parity

error detection function.

R01UH0575EJ0120 Rev. 1.20 Page 37 of 920
Dec 22, 2016

to 000CDH.

security IDs to 000C4H to 000CDH and 010C4H to 010CDH.

RL78/G1H CHAPTER 4 CPU ARCHITECTURE

FFFFFH

FFEE0H
FFEDFH
F7F00H
F7EFFH

F3000H
F2FFFH

F1000H
F0FFFH

F0800H
F07FFH

F0000H
EFFFFH

60000H
5FFFFH

00000H

Data memory

space

Program

memory

space

FFF00H
FFEFFH

Special function register (SFR)

256 bytes

General-purpose register

32 bytes

RAM

Notes 1, 2

32 Kbytes

Mirror

19.75 Kbytes

Data flash memory

8 Kbytes

Reserved

Extended special function register

(2nd SFR)

2 Kbytes

Reserved

Code flash memory

384 Kbytes

00000H

01FFFH

010CEH
010CDH

010C4H
010C3H

010C0H
010BFH

01080H
0107FH

000CEH
000CDH

01000H
00FFFH

5FFFFH

000C4H
000C3H

000C0H
000BFH

00080H
0007FH

Boot cluster 0

Note 4

Boot cluster 1

Program area

Program area

CALLT table area

64 bytes

Vector table area

128 bytes

Option byte area

Note 3

4 bytes

CALLT table area

64 bytes

Vector table area

128 bytes

On-chip debug security

ID setting area

Note 3

10 bytes

Option byte area

Note 3

4 bytes

On-chip debug security

ID setting area

Note 3

10 bytes

Figure 4 - 2 Memory Map (R5F11FLK)

Note 1. Do not allocate RAM addresses which are used as a stack area, a data buffer, a branch destination of vector interrupt

processing, and a DTC transfer destination/transfer source to the area FFE20H to FFEDFH when performing self­programming and rewriting the data flash memory.

Note 2. Instructions can be executed from the RAM area excluding the general-purpose register area.
Note 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H

to 000CDH.

When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug

security IDs to 000C4H to 000CDH and 010C4H to 010CDH.

Note 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.6 Security Settings).

Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to

proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively.

Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 24.3.3 RAM parity

error detection function.

R01UH0575EJ0120 Rev. 1.20 Page 38 of 920
Dec 22, 2016

RL78/G1H CHAPTER 4 CPU ARCHITECTURE

FFFFFH

FFEE0H
FFEDFH
F3F00H
F3EFFH

F3000H
F2FFFH

F1000H
F0FFFH

F0800H
F07FFH

F0000H
EFFFFH

80000H
7FFFFH

00000H

Data memory

space

Program

memory

space

FFF00H
FFEFFH

Special function register (SFR)

256 bytes

General-purpose register

32 bytes

RAM

Notes 1, 2

48 Kbytes

Mirror

3.75 Kbytes

Data flash memory

8 Kbytes

Reserved

Extended special function register

(2nd SFR)

2 Kbytes

Reserved

Code flash memory

512 Kbytes

00000H

01FFFH

010CEH
010CDH

010C4H
010C3H

010C0H
010BFH

01080H
0107FH

000CEH
000CDH

01000H
00FFFH

7FFFFH

000C4H
000C3H

000C0H
000BFH

00080H
0007FH

Boot cluster 0

Note 4

Boot cluster 1

Program area

Program area

CALLT table area

64 bytes

Vector table area

128 bytes

Option byte area

Note 3

4 bytes

CALLT table area

64 bytes

Vector table area

128 bytes

On-chip debug security

ID setting area

Note 3

10 bytes

Option byte area

Note 3

4 bytes

On-chip debug security

ID setting area

Note 3

10 bytes

Figure 4 - 3 Memory Map (R5F11FLL)

Note 1. Do not allocate RAM addresses which are used as a stack area, a data buffer, a branch destination of vector interrupt

processing, and a DTC transfer destination/transfer source to the area FFE20H to FFEDFH when performing self­programming and rewriting the data flash memory. Also, use of the area F3F00H to F4309H is prohibited, because this
area is used for each library.

Note 2. Instructions can be executed from the RAM area excluding the general-purpose register area.
Note 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H

to 000CDH.

When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug

security IDs to 000C4H to 000CDH and 010C4H to 010CDH.

Note 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.6 Security Settings).
Note 5. Use of the area F4300H to F46FFH is prohibited when using the on-chip debugging trace function.

Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to

proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively.

Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 24.3.3 RAM parity

error detection function.

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Tables 4 - 1

to 4 - 4 Correspondence Between Address Values and Block Numbers in Flash Memory.

Correspondence between the address values and block numbers in the flash memory are shown below.

Table 4 - 1 Correspondence Between Address Values and Block Numbers in Flash Memory (1/4)

Address Value

00000H to 003FFH 00H 08000H to 083FFH 20H 10000H to 103FFH 40H 18000H to 183FFH 60H

00400H to 007FFH 01H 08400H to 087FFH 21H 10400H to 107FFH 41H 18400H to 187FFH 61H

00800H to 00BFFH 02H 08800H to 08BFFH 22H 10800H to 10BFFH 42H 18800H to 18BFFH 62H

00C00H to 00FFFH 03H 08C00H to 08FFFH 23H 10C00H to 10FFFH 43H 18C00H to 18FFFH 63H

01000H to 013FFH 04H 09000H to 093FFH 24H 11000H to 113FFH 44H 19000H to 193FFH 64H

01400H to 017FFH 05H 09400H to 097FFH 25H 11400H to 117FFH 45H 19400H to 197FFH 65H

01800H to 01BFFH 06H 09800H to 09BFFH 26H 11800H to 11BFFH 46H 19800H to 19BFFH 66H

01C00H to 01FFFH 07H 09C00H to 09FFFH 27H 11C00H to 11FFFH 47H 19C00H to 19FFFH 67H

02000H to 023FFH 08H 0A000H to 0A3FFH 28H 12000H to 123FFH 48H 1A000H to 1A3FFH 68H

02400H to 027FFH 09H 0A400H to 0A7FFH 29H 12400H to 127FFH 49H 1A400H to 1A7FFH 69H

02800H to 02BFFH 0AH 0A800H to 0ABFFH 2AH 12800H to 12BFFH 4AH 1A800H to 1ABFFH 6AH

02C00H to 02FFFH 0BH 0AC00H to 0AFFFH 2BH 12C00H to 12FFFH 4BH 1AC00H to 1AFFFH 6BH

03000H to 033FFH 0CH 0B000H to 0B3FFH 2CH 13000H to 133FFH 4CH 1B000H to 1B3FFH 6CH

03400H to 037FFH 0DH 0B400H to 0B7FFH 2DH 13400H to 137FFH 4DH 1B400H to 1B7FFH 6DH

03800H to 03BFFH 0EH 0B800H to 0BBFFH 2EH 13800H to 13BFFH 4EH 1B800H to 1BBFFH 6EH

03C00H to 03FFFH 0FH 0BC00H to 0BFFFH 2FH 13C00H to 13FFFH 4FH 1BC00H to 1BFFFH 6FH

04000H to 043FFH 10H 0C000H to 0C3FFH 30H 14000H to 143FFH 50H 1C000H to 1C3FFH 70H

04400H to 047FFH 11H 0C400H to 0C7FFH 31H 14400H to 147FFH 51H 1C400H to 1C7FFH 71H

04800H to 04BFFH 12H 0C800H to 0CBFFH 32H 14800H to 14BFFH 52H 1C800H to 1CBFFH 72H

04C00H to 04FFFH 13H 0CC00H to 0CFFFH 33H 14C00H to 14FFFH 53H 1CC00H to 1CFFFH 73H

05000H to 053FFH 14H 0D000H to 0D3FFH 34H 15000H to 153FFH 54H 1D000H to 1D3FFH 74H

05400H to 057FFH 15H 0D400H to 0D7FFH 35H 15400H to 157FFH 55H 1D400H to 1D7FFH 75H

05800H to 05BFFH 16H 0D800H to 0DBFFH 36H 15800H to 15BFFH 56H 1D800H to 1DBFFH 76H

05C00H to 05FFFH 17H 0DC00H to 0DFFFH 37H 15C00H to 15FFFH 57H 1DC00H to 1DFFFH 77H

06000H to 063FFH 18H 0E000H to 0E3FFH 38H 16000H to 163FFH 58H 1E000H to 1E3FFH 78H

06400H to 067FFH 19H 0E400H to 0E7FFH 39H 16400H to 167FFH 59H 1E400H to 1E7FFH 79H

06800H to 06BFFH 1AH 0E800H to 0EBFFH 3AH 16800H to 16BFFH 5AH 1E800H to 1EBFFH 7AH

06C00H to 06FFFH 1BH 0EC00H to 0EFFFH 3BH 16C00H to 16FFFH 5BH 1EC00H to 1EFFFH 7BH

07000H to 073FFH 1CH 0F000H to 0F3FFH 3CH 17000H to 173FFH 5CH 1F000H to 1F3FFH 7CH

07400H to 077FFH 1DH 0F400H to 0F7FFH 3DH 17400H to 177FFH 5DH 1F400H to 1F7FFH 7DH

07800H to 07BFFH 1EH 0F800H to 0FBFFH 3EH 17800H to 17BFFH 5EH 1F800H to 1FBFFH 7EH

07C00H to 07FFFH 1FH 0FC00H to 0FFFFH 3FH 17C00H to 17FFFH 5FH 1FC00H to 1FFFFH 7FH

Block

Number

Address Value

Block

Number

Address Value

Block

Number

Address Value

Block

Number

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 2 Correspondence Between Address Values and Block Numbers in Flash Memory (2/4)

Address Value

20000H to 203FFH 80H 28000H to 283FFH A0H 30000H to 303FFH C0H 38000H to 383FFH E0H

20400H to 207FFH 81H 28400H to 287FFH A1H 30400H to 307FFH C1H 38400H to 387FFH E1H

20800H to 20BFFH 82H 28800H to 28BFFH A2H 30800H to 30BFFH C2H 38800H to 38BFFH E2H

20C00H to 20FFFH 83H 28C00H to 28FFFH A3H 30C00H to 30FFFH C3H 38C00H to 38FFFH E3H

21000H to 213FFH 84H 29000H to 293FFH A4H 31000H to 313FFH C4H 39000H to 393FFH E4H

21400H to 217FFH 85H 29400H to 297FFH A5H 31400H to 317FFH C5H 39400H to 397FFH E5H

21800H to 21BFFH 86H 29800H to 29BFFH A6H 31800H to 31BFFH C6H 39800H to 39BFFH E6H

21C00H to 21FFFH 87H 29C00H to 29FFFH A7H 31C00H to 31FFFH C7H 39C00H to 39FFFH E7H

22000H to 223FFH 88H 2A000H to 2A3FFH A8H 32000H to 323FFH C8H 3A000H to 3A3FFH E8H

22400H to 227FFH 89H 2A400H to 2A7FFH A9H 32400H to 327FFH C9H 3A400H to 3A7FFH E9H

22800H to 22BFFH 8AH 2A800H to 2ABFFH AAH 32800H to 32BFFH CAH 3A800H to 3ABFFH EAH

22C00H to 22FFFH 8BH 2AC00H to 2AFFFH ABH 32C00H to 32FFFH CBH 3AC00H to 3AFFFH EBH

23000H to 233FFH 8CH 2B000H to 2B3FFH ACH 33000H to 333FFH CCH 3B000H to 3B3FFH ECH

23400H to 237FFH 8DH 2B400H to 2B7FFH ADH 33400H to 337FFH CDH 3B400H to 3B7FFH EDH

23800H to 23BFFH 8EH 2B800H to 2BBFFH AEH 33800H to 33BFFH CEH 3B800H to 3BBFFH EEH

23C00H to 23FFFH 8FH 2BC00H to 2BFFFH AFH 33C00H to 33FFFH CFH 3BC00H to 3BFFFH EFH

24000H to 243FFH 90H 2C000H to 2C3FFH B0H 34000H to 343FFH D0H 3C000H to 3C3FFH F0H

24400H to 247FFH 91H 2C400H to 2C7FFH B1H 34400H to 347FFH D1H 3C400H to 3C7FFH F1H

24800H to 24BFFH 92H 2C800H to 2CBFFH B2H 34800H to 34BFFH D2H 3C800H to 3CBFFH F2H

24C00H to 24FFFH 93H 2CC00H to 2CFFFH B3H 34C00H to 34FFFH D3H 3CC00H to 3CFFFH F3H

25000H to 253FFH 94H 2D000H to 2D3FFH B4H 35000H to 353FFH D4H 3D000H to 3D3FFH F4H

25400H to 257FFH 95H 2D400H to 2D7FFH B5H 35400H to 357FFH D5H 3D400H to 3D7FFH F5H

25800H to 25BFFH 96H 2D800H to 2DBFFH B6H 35800H to 35BFFH D6H 3D800H to 3DBFFH F6H

25C00H to 25FFFH 97H 2DC00H to 2DFFFH B7H 35C00H to 35FFFH D7H 3DC00H to 3DFFFH F7H

26000H to 263FFH 98H 2E000H to 2E3FFH B8H 36000H to 363FFH D8H 3E000H to 3E3FFH F8H

26400H to 267FFH 99H 2E400H to 2E7FFH B9H 36400H to 367FFH D9H 3E400H to 3E7FFH F9H

26800H to 26BFFH 9AH 2E800H to 2EBFFH BAH 36800H to 36BFFH DAH 3E800H to 3EBFFH FAH

26C00H to 26FFFH 9BH 2EC00H to 2EFFFH BBH 36C00H to 36FFFH DBH 3EC00H to 3EFFFH FBH

27000H to 273FFH 9CH 2F000H to 2F3FFH BCH 37000H to 373FFH DCH 3F000H to 3F3FFH FCH

27400H to 277FFH 9DH 2F400H to 2F7FFH BDH 37400H to 377FFH DDH 3F400H to 3F7FFH FDH

27800H to 27BFFH 9EH 2F800H to 2FBFFH BEH 37800H to 37BFFH DEH 3F800H to 3FBFFH FEH

27C00H to 27FFFH 9FH 2FC00H to 2FFFFH BFH 37C00H to 37FFFH DFH 3FC00H to 3FFFFH FFH

Block

Number

Address Value

Block

Number

Address Value

Block

Number

Address Value

Block

Number

Remark R5F11FLJ: Block numbers 00H to FFH

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 3 Correspondence Between Address Values and Block Numbers in Flash Memory (3/4)

Address Value

40000H to 403FFH 100H 48000H to 483FFH 120H 5

40400H to 407FFH 101H 48400H to 487FFH 121H 50400H to 507FFH 141H 58400H to 587FFH 161H

40800H to 40BFFH 102H 48800H to 48BFFH 122H 50800H to 50BFFH 142H 58800H to 58BFFH 162H

40C00H to 40FFFH 103H 48C00H to 48FFFH 123H 50C00H to 50FFFH 143H 58C00H to 58FFFH 163H

41000H to 413FFH 104H 49000H to 493FFH 124H 51000H to 513FFH 144H 59000H to 593FFH 164H

41400H to 417FFH 105H 49400H to 497FFH 125H 51400H to 517FFH 145H 59400H to 597FFH 165H

41800H to 41BFFH 106H 49800H to 49BFFH 126H 51800H to 51BFFH 146H 59800H to 59BFFH 166H

41C00H to 41FFFH 107H 49C00H to 49FFFH 127H 51C00H to 51FFFH 147H 59C00H to 59FFFH 167H

42000H to 423FFH 108H 4A000H to 4A3FFH 128H 52000H to 523FFH 148H 5A000H to 5A3FFH 168H

42400H to 427FFH 109H 4A400H to 4A7FFH 129H 52400H to 527FFH 149H 5A400H to 5A7FFH 169H

42800H to 42BFFH 10AH 4A800H to 4ABFFH 12AH 52800H to 52BFFH 14AH 5A800H to 5ABFFH 16AH

42C00H to 42FFFH 10BH 4AC00H to 4AFFFH 12BH 52C00H to 52FFFH 14BH 5AC00H to 5AFFFH 16BH

43000H to 433FFH 10CH 4B000H to 4B3FFH 12CH 53000H to 533FFH 14CH 5B000H to 5B3FFH 16CH

43400H to 437FFH 10DH 4B400H to 4B7FFH 12DH 53400H to 537FFH 14DH 5B400H to 5B7FFH 16DH

43800H to 43BFFH 10EH 4B800H to 4BBFFH 12EH 53800H to 53BFFH 14EH 5B800H to 5BBFFH 16EH

43C00H to 43FFFH 10FH 4BC00H to 4BFFFH 12FH 53C00H to 53FFFH 14FH 5BC00H to 5BFFFH 16FH

44000H to 443FFH 110H 4C000H to 4C3FFH 130H 54000H to 543FFH 150H 5C000H to 5C3FFH 170H

44400H to 447FFH 111H 4C400H to 4C7FFH 131H 54400H to 547FFH 151H 5C400H to 5C7FFH 171H

44800H to 44BFFH 112H 4C800H to 4CBFFH 132H 54800H to 54BFFH 152H 5C800H to 5CBFFH 172H

44C00H to 44FFFH 113H

45000H to 453FFH 114H 4D000H to 4D3FFH 134H 55000H to 553FFH 154H 5D000H to 5D3FFH 174H

45400H to 457FFH 115H 4D400H to 4D7FFH 135H 55400H to 557FFH 155H 5D400H to 5D7FFH 175H

45800H to 45BFFH 116H 4D800H to 4DBFFH 136H 55800H to 55BFFH 156H 5D800H to 5DBFFH 176H

45C00H to 45FFFH 117H

46000H to 463FFH 118H 4E000H to 4E3FFH 138H 56000H to 563FFH 158H 5E000H to 5E3FFH 178H

46400H to 467FFH 119H 4E400H to 4E7FFH 139H 56400H to 567FFH 159H 5E400H to 5E7FFH 179H

46800H to 46BFFH 11AH 4E800H to 4EBFFH 13AH 56800H to 56BFFH 15AH 5E800H to 5EBFFH 17AH

46C00H to 46FFFH 11BH 4EC00H to 4EFFFH 13BH 56C00H to 56FFFH 15BH 5EC00H to 5EFFFH 17BH

47000H to 473FFH 11CH 4F000H to 4F3FFH 13CH 57000H to 573FFH 15CH 5F000H to 5F3FFH 17CH

47400H to 477FFH 11DH 4F400H to 4F7FFH 13DH 57400H to 577FFH 15DH 5F400H to 5F7FFH 17DH

47800H to 47BFFH 11EH 4F800H to 4FBFFH 13EH 57800H to 57BFFH 15EH 5F800H to 5FBFFH 17EH

47C00H to 47FFFH 11FH 4FC00H to 4FFFFH 13FH 57C00H to 57FFFH 15FH 5FC00H to 5FFFFH 17FH

Block

Number

Address Value

4CC00H to 4CFFFH

4DC00H to 4DFFFH

Block

Number

133H 54C00H to 54FFFH 153H

137H 55C00H to 55FFFH 157H

Address Value

0000H to 503FFH 140H 58000H to 583FFH 160H

Block

Number

Address Value

5CC00H to 5CFFFH

5DC00H to 5DFFFH

Block

Number

173H

177H

Remark R5F11FLK: Block numbers 00H to 17FH

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 4 Correspondence Between Address Values and Block Numbers in Flash Memory (4/4)

Address Value

60000H to 603FFH 180H 68000H to 683FFH 1A0H 70000H to 703FFH 1C0H 78000H to 783FFH 1E0H

60400H to 607FFH 181H 68400H to 687FFH 1A1H 70400H to 707FFH 1C1H 78400H to 787FFH 1E1H

60800H to 60BFFH 182H 68800H to 68BFFH 1A2H 70800H to 70BFFH 1C2H 78800H to 78BFFH 1E2H

60C00H to 60FFFH 183H 68C00H to 68FFFH 1A3H 70C00H to 70FFFH 1C3H 78C00H to 78FFFH 1E3H

61000H to 613FFH 184H 69000H to 693FFH 1A4H 71000H to 713FFH 1C4H 79000H to 793FFH 1E4H

61400H to 617FFH 185H 69400H to 697FFH 1A5H 71400H to 717FFH 1C5H 79400H to 797FFH 1E5H

61800H to 61BFFH 186H 69800H to 69BFFH 1A6H 71800H to 71BFFH 1C6H 79800H to 79BFFH 1E6H

61C00H to 61FFFH 187H 69C00H to 69FFFH 1A7H 71C00H to 71FFFH 1C7H 79C00H to 79FFFH 1E7H

62000H to 623FFH 188H 6A000H to 6A3FFH 1A8H 72000H to 723FFH 1C8H 7A000H to 7A3FFH 1E8H

62400H to 627FFH 189H 6A400H to 6A7FFH 1A9H 72400H to 727FFH 1C9H 7A400H to 7A7FFH 1E9H

62800H to 62BFFH 18AH 6A800H to 6ABFFH 1AAH 72800H to 72BFFH 1CAH 7A800H to 7ABFFH 1EAH

62C00H to 62FFFH 18BH 6AC00H to 6AFFFH 1ABH 72C00H to 72FFFH 1CBH 7AC00H to 7AFFFH 1EBH

63000H to 633FFH 18CH 6B000H to 6B3FFH 1ACH 73000H to 733FFH 1CCH 7B000H to 7B3FFH 1ECH

63400H to 637FFH 18DH 6B400H to 6B7FFH 1ADH 73400H to 737FFH 1CDH 7B400H to 7B7FFH 1EDH

63800H to 63BFFH 18EH 6B800H to 6BBFFH 1AEH 73800H to 73BFFH 1CEH 7B800H to 7BBFFH 1EEH

63C00H to 63FFFH 18FH 6BC00H to 6BFFFH 1AFH 73C00H to 73FFFH 1CFH 7BC00H to 7BFFFH 1EFH

64000H to 643FFH 190H 6C000H to 6C3FFH 1B0H 74000H to 743FFH 1D0H 7C000H to 7C3FFH 1F0H

64400H to 647FFH 191H 6C400H to 6C7FFH 1B1H 74400H to 747FFH 1D1H 7C400H to 7C7FFH 1F1H

64800H to 64BFFH 192H 6C800H to 6CBFFH 1B2H 74800H to 74BFFH 1D2H 7C800H to 7CBFFH 1F2H

64C00H to 64FFFH 193H

65000H to 653FFH 194H 6D000H to 6D3FFH 1B4H 75000H to 753FFH 1D4H 7D000H to 7D3FFH 1F4H

65400H to 657FFH 195H 6D400H to 6D7FFH 1B5H 75400H to 757FFH 1D5H 7D400H to 7D7FFH 1F5H

65800H to 65BFFH 196H 6D800H to 6DBFFH 1B6H 75800H to 75BFFH 1D6H 7D800H to 7DBFFH 1F6H

65C00H to 65FFFH 197H

66000H to 663FFH 198H 6E000H to 6E3FFH 1B8H 76000H to 763FFH 1D8H 7E000H to 7E3FFH 1F8H

66400H to 667FFH 199H 6E400H to 6E7FFH 1B9H 76400H to 767FFH 1D9H 7E400H to 7E7FFH 1F9H

66800H to 66BFFH 19AH 6E800H to 6EBFFH 1BAH 76800H to 76BFFH 1DAH 7E800H to 7EBFFH 1FAH

66C00H to 66FFFH 19BH 6EC00H to 6EFFFH 1BBH 76C00H to 76FFFH 1DBH 7EC00H to 7EFFFH 1FBH

67000H to 673FFH 19CH 6F000H to 6F3FFH 1BCH 77000H to 773FFH 1DCH 7F000H to 7F3FFH 1FCH

67400H to 677FFH 19DH 6F400H to 6F7FFH 1BDH 77400H to 777FFH 1DDH 7F400H to 7F7FFH 1FDH

67800H to 67BFFH 19EH 6F800H to 6FBFFH 1BEH 77800H to 77BFFH 1DEH 7F800H to 7FBFFH 1FEH

67C00H to 67FFFH 19FH 6FC00H to 6FFFFH 1BFH 77C00H to 77FFFH 1DFH 7FC00H to 7FFFFH 1FFH

Block

Number

Address Value

6CC00H to 6CFFFH

6DC00H to 6DFFFH

Block

Number

1B3H 74C00H to 74FFFH 1D3H

1B7H 75C00H to 75FFFH 1D7H

Address Value

Block

Number

Address Value

7CC00H to 7CFFFH

7DC00H to 7DFFFH

Block

Number

1F3H

1F7H

Remark R5F11FLL: Block numbers 00H to 1FFH

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

4.1.1 Internal program memory space

The internal program memory space stores the program and table data.
The internal program memory space is divided into the following areas.

(1) Vector table area

The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for
branch upon reset or generation of each interrupt request are stored in the vector table area. Furthermore,
the interrupt jump address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to
be 2 bytes.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
To use the boot swap function, set a vector table also at 01000H to 0107FH.
For details, see CHAPTER 19 INTERRUPT FUNCTIONS.

(2) CALLT instruction table area

The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction
(CALLT). Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address
code is 2 bytes).
To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH.

(3) Option byte area

A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to
010C3H when the boot swap is used. For details, see CHAPTER 26 OPTION BYTE.

(4) On-chip debug security ID setting area

A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security
ID setting area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is
not used and at 000C4H to 000CDH and at 010C4H to 010CDH when the boot swap is used. For details,
see CHAPTER 28 ON-CHIP DEBUG FUNCTION.

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

4.1.2 Mirror area

The code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the code flash area to
be mirrored is set by the processor mode control register (PMC)).
By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can
be used, and thus the contents of the code flash can be read with the shorter code. However, the code flash area
is not mirrored to the special function register (SFR), extended special function register (2nd SFR), RAM, data
flash memory, and use prohibited areas.
The mirror area can only be read and no instruction can be fetched from this area.
The following show examples.

The PMC register is described below.

• Processor mode control register (PMC)
This register sets the flash memory space for mirroring to area from F0000H to FFFFFH.
The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.

Figure 4 - 4 Format of Configuration of Processor mode control register (PMC)

Address: FFFFEH After reset: 00H R/W

Symbol7654321<0>

PMC0000000MAA

MAA Selection of flash memory space for mirroring to area from F0000H to FFFFFH

0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH

1 10000H to 1FFFFH is mirrored to F0000H to FFFFFH

Caution After setting the PMC register, wait for at least one instruction and access the mirror area.

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

4.1.3 Internal data memory space

The internal RAM can be used as a data area and a program area where instructions are fetched (it is prohibited
to use the general-purpose register area for fetching instructions). Four general-purpose register banks
consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to FFEFFH of the internal
RAM area.
The internal RAM is used as stack memory.

Caution 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching

instructions or as a stack area.

Caution 2. Do not allocate RAM addresses which are used as a stack area, a data buffer, a branch

destination of vector interrupt processing, and a DTC transfer destination/transfer source to

the area FFE20H to FFEDFH when performing self-programming and rewriting the data flash

memory.

Caution 3. Use of the RAM areas of the following products is prohibited when performing self-

programming and rewriting the data flash memory, because these areas are used for each

library.

R5F11FLL: F3F00H to F4309H

Caution 4. The internal RAM area in the following products cannot be used as stack memory when using

the on-chip debugging trace function.

R5F11FLL: F4300H to F46FFH

4.1.4 Special function register (SFR) area

On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see

Tables 4 - 5 to 4 - 9 in 4.2.4 Special function registers (SFRs)).

Caution Do not access addresses to which SFRs are not assigned.

4.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area

On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH
(see Tables 4 - 10 to 4 - 16 in 4.2.5 Extended special function registers (2nd SFRs: 2nd Special Function

Registers)).

Caution 1. Do not access addresses to which extended SFRs are not assigned.

Caution 2. When accessing timer RJ counter register 0 (TRJ0) allocated in F0500H of the extended SFR

(2nd SFR), the CPU does not proceed to the next instruction processing but enters the wait

state for CPU processing. For this reason, if this wait state occurs, the number of instruction

execution clocks is increased by the number of wait clocks. The number of wait clocks for

access to timer RJ counter register 0 (TRJ0) is one clock for both writing and reading.

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

FFFFFH

FFEE0H
FFEDFH
FFE20H

FFF00H
FFEFFH

Special function register (SFR)

256 bytes

General-purpose register

32 bytes

RAM

24K to 48 Kbytes

Register addressing

Short direct
addressing

Direct addressing

Register indirect addressing

Based addressing

Based indexed addressing

SFR addressing

F1000H
F0FFFH

F0800H
F07FFH

F0000H
EFFFFH

Mirror area

Data flash memory

8 Kbytes

Reserved

Extended special function register

(2nd SFR)

2 Kbytes

Reserved

FFF20H
FFF1FH

FFE1FH

00000H

Code flash memory
256K to 512 Kbytes

4.1.6 Data memory addressing

Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for
the RL78/G1H, based on operability and other considerations. For areas containing data memory in particular,
special addressing methods designed for the functions of the special function registers (SFR) and general­purpose registers are available for use. Figure 4 - 5 shows correspondence between data memory and
addressing.

Figure 4 - 5 Correspondence Between Data Memory and Addressing

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

4.2 Processor Registers

The RL78/G1H products incorporate the following processor registers.

4.2.1 Control registers

The control registers control the program sequence, statuses and stack memory. The control registers consist of
a program counter (PC), a program status word (PSW) and a stack pointer (SP).

(1) Program counter (PC)

The program counter is a 20-bit register that holds the address information of the next program to be
executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to
be fetched. When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program
counter.

Figure 4 - 6 Format of Program Counter

19 0

PC

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged
or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW
instructions.
Reset signal generation sets the PSW register to 06H.

Figure 4 - 7 Format of Program Status Word

7 0

PSW IE Z RBS1 AC RBS0 ISP1 ISP0 CY

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are
disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and maskable interrupt requests
acknowledgment is controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for
various interrupt sources, and a priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

(b) Zero flag (Z)

When the operation result is zero or equal, this flag is set (1). It is reset (0) in all other cases.

(c) Register bank select flags (RBS0, RBS1)

These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.

(e) In-service priority flags (ISP1, ISP0)

This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt
requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers
(PRn0L, PRn0H, PRn1L, PRn1H, PRn2L, PRn2H) (see 19.3.3) can not be acknowledged. Actual
vectored interrupt requests acknowledgment is controlled by the interrupt enable flag (IE).

Remark n = 0, 1

(f) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction
execution.

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can
be set as the stack area.

Figure 4 - 8 Format of Stack Pointer

15 0

SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

In stack addressing through a stack pointer, the SP is decremented ahead of write (save) to the stack
memory and is incremented after read (restore) from the stack memory.

Caution 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the

SP before using the stack.

Caution 2.It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for

fetching instructions or as a stack area.

Caution 3. Do not allocate RAM addresses which are used as a stack area, a data buffer, a branch

destination of vector interrupt processing, and a DTC transfer destination/transfer source

to the area FFE20H to FFEDFH when performing self-programming and rewriting the data

flash memory.

Caution 4. Use of the RAM areas of the following products is prohibited when performing self-

programming and rewriting the data flash memory, because these areas are used for

each library.

R5F11FLL: F3F00H to F4309H

Caution 5. The internal RAM area in the following products cannot be used as stack memory when

using the on-chip debugging trace function.

R5F11FLL: F4300H to F46FFH

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Register bank 0 HL

DE

BC

AX

H

L

D

E

B

C

A

X

8-bit processing

15 0 7

16-bit processing

0

Register bank 1

Register bank 2

Register bank 3

FFEE0H

FFEE8H

FFEF0H

FFEF8H

FFEFFH

4.2.2 General-purpose registers

General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L,
and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit
register (AX, BC, DE, and HL).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupt processing for each bank.

Caution It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching

instructions or as a stack area.

Figure 4 - 9 Configuration of General-Purpose Registers

(a) Function name

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Special function register

(SFR) 256 bytes

Extended special function register

(2nd SFR) 2 Kbytes

FFFFFH

00000H

Code flash memory

F0000H

EFFFFH

Data memory space

!addr16

!addr16

→ F 0000H - FFFFH

→

0H - FH 0000H - FFFFH

ES:!addr16

ES:!addr16

4.2.3 ES and CS registers

The ES register and CS register are used to specify the higher address for data access and when a branch
instruction is executed (register direct addressing), respectively.
The default value of the ES register after reset is 0FH, and that of the CS register is 00H.

Figure 4 - 10 Configuration of ES and CS Registers

76543210

ES 0 0 0 0 ES3 ES2 ES1 ES0

76543210

CS 0 0 0 0 CS3 CS2 CS1 CS0

Though the data area which can be accessed with 16-bit addresses is the 64 Kbytes from F0000H to FFFFFH,
using the ES register as well extends this to the 1 Mbyte from 00000H to FFFFFH.

Figure 4 - 11 Extension of Data Area Which Can Be Accessed

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

4.2.4 Special function registers (SFRs)

Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.

• 1-bit manipulation
Describe as follows for the 1-bit manipulation instruction operand (sfr.bit).
When the bit name is defined: <Bit name>
When the bit name is not defined: <Register name>.<Bit number> or <Address>.<Bit number>

• 8-bit manipulation
Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.

• 16-bit manipulation
Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (sfrp). When
specifying an address, describe an even address.

Tables 4 - 5 to 4 - 9 give lists of the SFRs. The meanings of items in the table are as follows.

• Symbol
This item indicates the address of a special function register. It is a reserved word in the assembler, and is
defined as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger,
and simulator, symbols can be written as an instruction operand.

•R/W
This item indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only

• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “—” indicates a bit unit for which manipulation is not possible.

• After reset
This item indicates each register status upon reset signal generation.

Caution Do not access addresses to which SFRs are not assigned.

Remark For extended SFRs (2nd SFRs), see 4.2.5 Extended special function registers (2nd SFRs: 2nd

Special Function Registers).

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 5 Special Function Register (SFR) List (1/5)

Address

FFF00H Port register 0 P0 R/W

FFF01H Port register 1 P1 R/W

FFF02H Port register 2 P2 R/W

FFF03H Port register 3 P3 R/W

FFF04H Port register 4 P4 R/W

FFF05H Port register 5 P5 R/W

FFF06H Port register 6 P6 R/W

FFF07H Port register 7 P7 R/W

FFF08H Port register 8 P8 R/W

FFF0AH Port register 10 P10 R/W

FFF0BH Port register 11 P11 R/W

FFF0CH Port register 12 P12 R/W

FFF0DH Port register 13 P13 R/W

FFF0EH Port register 14 P14 R/W

FFF0FH Port register 15 P15 R/W

FFF14H Serial data register 12 RXD3/

FFF15H — — —

FFF16H Serial data register 13 RXD3 SDR13 R/W —

FFF17H — — —

FFF18H Timer data register 00 TDR00 R/W — —

FFF19H

FFF1AH Timer data register 01 TDR01L TDR01 R/W —

FFF1BH TDR01H —

FFF1EH 10-bit A/D conversion result register ADCR R — —

FFF1FH 8-bit A/D conversion result

FFF20H Port mode register 0 PM0 R/W

FFF21H Port mode register 1 PM1 R/W

FFF22H Port mode register 2 PM2 R/W

FFF23H Port mode register 3 PM3 R/W

FFF24H

FFF25H

FFF26H Port mode register 6 PM6 R/W

FFF27H Port mode register 7 PM7 R/W

Special Function Register (SFR)

Name

register

Port mode register 4 PM4 R/W

Port mode register 5 PM5 R/W

Symbol R/W

SDR12 R/W —

SIO30

ADCRH R —

Manipulable Bit Range

1-bit 8-bit 16-bit

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√— Undefined

√√— Undefined

√√—00H

√√—00H

√√0000H

√√0000H

√ 0000H

√√00H

√ 00H

√ 0000H

√ —00H

√√—FFH

√√—FFH

√√—FFH

√√—FFH

√√—FFH

√√—FFH

√√—FFH

√√—FFH

After Reset

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 6 Special Function Register (SFR) List (2/5)

Address

FFF28H Port mode register 8 PM8 R/W

FFF2AH Port mode register 10 PM10 R/W

FFF2BH Port mode register 11 PM11 R/W

FFF2CH Port mode register 12 PM12 R/W

FFF2EH Port mode register 14 PM14 R/W

FFF2FH Port mode register 15 PM15 R/W

FFF30H A/D converter mode register 0 ADM0 R/W

FFF31H Analog input channel specification

FFF32H A/D converter mode register 1 ADM1 R/W

FFF38H External interrupt rising edge enable

FFF39H External interrupt falling edge enable

FFF3AH External interrupt rising edge enable

FFF3BH External interrupt falling edge enable

FFF44H Serial data register 02 TXD1/

FFF45H — — —

FFF46H Serial data register 03 RXD1 SDR03 R/W —

FFF47H — — —

FFF48H Serial data register 10 SIO20 SDR10 R/W —

FFF49H — — —

FFF4AH Serial data register 11 SIO21 SDR11 R/W —

FFF4BH — — —

FFF50H IICA shift register 0 IICA0 R/W —

FFF51H IICA status register 0 IICS0 R

FFF52H IICA flag register 0 IICF0 R/W

FFF54H IICA shift register 1 IICA1 R/W —

FFF55H IICA status register 1 IICS1 R

FFF56H IICA flag register 1 IICF1 R/W

FFF64H Timer data register 02 TDR02 R/W — —

FFF65H

FFF66H Timer data register 03 TDR03L TDR03 R/W —

FFF67H TDR03H —

FFF70H Timer data register 10 TDR10 R/W — —

FFF71H

Special Function Register (SFR)

Name

register

register 0

register 0

register 1

register 1

Symbol R/W

ADS R/W

EGP0 R/W

EGN0 R/W

EGP1 R/W

EGN1 R/W

SDR02 R/W —

SIO10

Manipulable Bit Range

1-bit 8-bit 16-bit

√√—FFH

√√—FFH

√√—FFH

√√—FFH

√√—FFH

√√—FFH

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√0000H

√√0000H

√√0000H

√√0000H

√ —00H

√√—00H

√√—00H

√ —00H

√√—00H

√√—00H

√ 0000H

√√00H

√ 00H

√ 0000H

After Reset

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 7 Special Function Register (SFR) List (3/5)

Manipulable Bit Range

1-bit 8-bit 16-bit

After Reset

Address

Special Function Register (SFR)

Name

Symbol R/W

FFF72H Timer data register 11 TDR11L TDR11 R/W —

FFF73H TDR11H —

FFF74H Timer data register 12 TDR12 R/W — —

FFF75H

FFF76H Timer data register 13 TDR13L TDR13 R/W —

FFF77H TDR13H —

FFF90H 12-bit interval timer control register ITMC R/W — —

FFF91H

FFF92H Second count register SEC R/W —

FFF93H Minute count register MIN R/W —

FFF94H

FFF95H Week count register WEEK R/W — √ —00H

FFF96H Day count register DAY R/W —

FFF97H Month count register MONTH R/W —

FFF98H Year count register YEAR R/W —

FFF99H Watch error correction register SUBCUD R/W —

FFF9AH Alarm minute register ALARMWM R/W —

FFF9BH Alarm hour register ALARMWH R/W —

FFF9CH Alarm week register ALARMWW R/W —

FFF9DH Real-time clock control register 0 RTCC0 R/W

FFF9EH Real-time clock control register 1 RTCC1 R/W

FFFA0H Clock operation mode control register CMC R/W —

FFFA1H Clock operation status control

FFFA2H Oscillation stabilization time counter

FFFA3H Oscillation stabilization time select

FFFA4H System clock control register CKC R/W

FFFA5H Clock output select register 0 CKS0 R/W

FFFA6H Clock output select register 1 CKS1 R/W

Hour count register HOUR

CSC

register

OSTC

status register

OSTS

register

R/W —

R/W

R

R/W

√√—00H

√√—00H

√√—C0H

√√—00H

—

√√—00H

√√—00H

√√—00H

√√00H

√ 00H

√ 0000H

√√00H

√ 00H

√ 0FFFH

√ —00H

√ —00H

√ —

√ —01H

√ —01H

√ —00H

√ —00H

√ —00H

√ —12H

√ —00H

√ —00H

√ —07H

12H

Note

Note The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1 after reset.

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 8 Special Function Register (SFR) List (4/5)

Manipulable Bit Range

1-bit 8-bit 16-bit

After Reset

Address

Special Function Register (SFR)

Name

Symbol R/W

00H

Note 1

Note 1

Note 1

Note 2

Reset by

LVD

FFFA8H Reset control flag register RESF

FFFA9H Voltage detection register LVIM

FFFAAH Voltage detection level register LVIS

FFFABH Watchdog timer enable register WDTE

FFFACH CRC input register CRCIN R/W — √ —00H

FFFD0H Interrupt request flag register 2L IF2L IF2 R/W

FFFD1H Interrupt request flag register 2H IF2H R/W

FFFD4H Interrupt mask flag register 2L MK2L MK2 R/W

FFFD5H Interrupt mask flag register 2H MK2H R/W

FFFD8H Priority specification flag register 02L PR02L PR02 R/W

FFFD9H Priority specification flag register 02H PR02H R/W

FFFDCH Priority specification flag register 12L PR12L PR12 R/W

FFFDDH Priority specification flag register 12H PR12H R/W

Note 1. These values vary depending on the reset source.

Reset Source

Register

RESF TRAP Cleared (0) Set (1) Held Held

WDTRF Held Set (1) Held

RPERF Held Set (1) Held

IAWRF Held Set (1)

LVIRF Held Set (1)

LVI M LVIS EN Cl ear ed (0) Held

LVI OMSK He ld

LVI F

LVIS Cleared (00H/01H/81H)

RESET

Input

Reset by

POR

Reset by

Execution of

Illegal Instruction

R

R/W

R/W

R/W

Reset by

WDT

—

√√—

√√—

— √ —

√√√ 00H

√√ 00H

√√√ FFH

√√ FFH

√√√ FFH

√√ FFH

√√√ FFH

√√ FFH

Reset by RAM

√ —

parity error

Undefined

00H/01H/81H

9AH/1AH

Reset by illegal­memory access

Note 2. The reset value of the WDTE register is determined by the setting of the option byte.

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 9 Special Function Register (SFR) List (5/5)

Manipulable Bit Range

Address Special Function Register (SFR) Name Symbol R/W

1-bit 8-bit 16-bit

After Reset

FFFE0H Interrupt request flag register 0L IF0L IF0 R/W

FFFE1H Interrupt request flag register 0H IF0H R/W

FFFE2H Interrupt request flag register 1L IF1L IF1 R/W

FFFE3H Interrupt request flag register 1H IF1H R/W

FFFE4H Interrupt mask flag register 0 MK0L MK0 R/W

FFFE5H MK0H R/W

FFFE6H Interrupt mask flag register 1 MK1L MK1 R/W

FFFE7H MK1H R/W

FFFE8H Priority specification flag register 00 PR00L PR00 R/W

FFFE9H PR00H R/W

FFFEAH Priority specification flag register 01 PR01L PR01 R/W

FFFEBH PR01H R/W

FFFECH Priority specification flag register 10 PR10L PR10 R/W

FFFEDH PR10H R/W

FFFEEH Priority specification flag register 11 PR11L PR11 R/W

FFFEFH PR11H R/W

FFFF0H Multiply and accumulation register (L) MACRL R/W — —

FFFF1H

FFFF2H Multiply and accumulation register (H) MACRH R/W — —

FFFF3H

FFFFEH Processor mode control register PMC R/W

√√√00H

√√ 00H

√√√00H

√√ 00H

√√√FFH

√√ FFH

√√√FFH

√√ FFH

√√√FFH

√√ FFH

√√√FFH

√√ FFH

√√√FFH

√√ FFH

√√√FFH

√√ FFH

√√—00H

√ 0000H

√ 0000H

Remark For extended SFRs (2

nd

SFRs), see Tables 4 - 10 to 4 - 16 Extended SFR (2

nd

SFR) List.

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

4.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)

Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H
to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte
longer than an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit
manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.

• 1-bit manipulation
Describe as follows for the 1-bit manipulation instruction operand (!addr16.bit)
When the bit name is defined: <Bit name>
When the bit name is not defined: <Register name>.<Bit number> or <Address>.<Bit number>

• 8-bit manipulation
Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (!addr16). This
manipulation can also be specified with an address.

• 16-bit manipulation
Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (!addr16). When
specifying an address, describe an even address.

Tables 4 - 10 to 4 - 16 give lists of the extended SFRs. The meanings of items in the table are as follows.

• Symbol
This item indicates the address of an extended SFR. It is a reserved word in the assembler, and is defined as
an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and
simulator, symbols can be written as an instruction operand.

•R/W
This item indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only

• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “—” indicates a bit unit for which manipulation is not possible.

• After reset
This item indicates each register status upon reset signal generation.

Caution Do not access addresses to which extended SFRs are not assigned.

Remark For SFRs in the SFR area, see 4.2.4 Special function registers (SFRs).

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 10 Extended Special Function Register (2nd SFR) List (1/7)

Manipulable Bit Range

1-bit 8-bit 16-bit

After Reset

Address

Extended Special Function Register

(2nd SFR) Name

Symbol R/W

F0010H A/D converter mode register 2 ADM2 R/W

F0011H Conversion result comparison upper limit

setting register

F0012H Conversion result comparison lower limit

F0013H A/D test register ADTES R/W —

F0030H Pull-up resistor option register 0 PU0 R/W

F0031H Pull-up resistor option register 1 PU1 R/W

F0033H Pull-up resistor option register 3 PU3 R/W

F0034H Pull-up resistor option register 4 PU4 R/W

F0037H Pull-up resistor option register 7 PU7 R/W

F0038H Pull-up resistor option register 8 PU8 R/W

F003AH Pull-up resistor option register 10 PU10 R/W

F003CH Pull-up resistor option register 12 PU12 R/W

F003EH Pull-up resistor option register 14 PU14 R/W

F0040H Port input mode register 0 PIM0 R/W

F0048H Port input mode register 8 PIM8 R/W

F004EH Port input mode register 14 PIM14 R/W

F0050H Port output mode register 0 POM0 R/W

F0057H Port output mode register 7 POM7 R/W

F0058H Port output mode register 8 POM8 R/W

F005EH Port output mode register 14 POM14 R/W

F0060H

F006AH

F006CH

F006EH

F0070H

F0071H

F0074H

F0076H

F0078H Invalid memory access detection control

F007AH

F007BH

F0090H

F00A0H High-speed on-chip oscillator trimming register HIOTRM R/W —

setting register

Port mode control register 0 PMC0

Port mode control register 10 PMC10

Port mode control register 12 PMC12

Port mode control register 14 PMC14

Noise filter enable register 0 NFEN0

Noise filter enable register 1 NFEN1

Timer input select register 0 TIS0

A/D port configuration register ADPC

register

Peripheral enable register 1 PER1

Port mode select register PMS

Data flash control register DFLCTL

ADUL R/W —

ADLL R/W —

R/W

R/W

R/W

R/W

R/W

R/W

R/W —

R/W —

IAWCTL R/W —

R/W

R/W

R/W

√√— 00H

√ —FFH

√ — 00H

√ — 00H

√√— 00H

√√— 00H

√√— 00H

√√— 01H

√√— 00H

√√— 00H

√√— 00H

√√— 00H

√√— 00H

√√— 00H

√√— 00H

√√— 00H

√√— 00H

√√— 00H

√√— 00H

√√— 00H

√√—FFH

√√—FFH

√√—FFH

√√—FFH

√√— 00H

√√— 00H

√ — 00H

√ — 00H

√ — 00H

√√— 00H

√√— 00H

√√— 00H

√ — Undefined

Note 1

F00A8H High-speed on-chip oscillator frequency select

register

Note 1. The value after a reset is adjusted at the time of shipment.
Note 2. The value after a reset is a value set in FRQSEL2 to FRQSEL0 of the option byte (000C2H).

HOCODIV R/W — √ — Undefined

Note 2

R01UH0575EJ0120 Rev. 1.20 Page 60 of 920
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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 11 Extended Special Function Register (2nd SFR) List (2/7)

Manipulable Bit Range

1-bit 8-bit 16-bit

After Reset

Address

Extended Special Function Register

(2nd SFR) Name

Symbol R/W

F00F0H Peripheral enable register 0 PER0 R/W

F00F3H

F00F5H RAM parity error control register RPECTL R/W

F00FEH BCD correction result register BCDADJ R —

F0104H Serial status register 02 SSR02L SSR02 R —

F0105H — — —

F0106H Serial status register 03 SSR03L SSR03 R —

F0107H — — —

F0108H Serial flag clear trigger register 00 SIR00L SIR00 R/W —

F0109H — — —

F010AH Serial flag clear trigger register 01 SIR01L SIR01 R/W —

F010BH — — —

F010CH Serial flag clear trigger register 02 SIR02L SIR02 R/W —

F010DH — — —

F010EH Serial flag clear trigger register 03 SIR03L SIR03 R/W —

F010FH — — —

F0114H Serial mode register 02 SMR02 R/W — —

F0115H

F0116H Serial mode register 03 SMR03 R/W — —

F0117H

F011CH Serial communication operation setting

F011DH

F011EH Serial communication operation setting

F011FH

F0120H Serial channel enable status register 0 SE0L SE0 R

F0121H — — —

Subsystem clock supply mode control
register

register 02

register 03

OSMC

SCR02 R/W — —

SCR03 R/W — —

R/W —

√√— 00H

√√— 00H

√√√0000H

√ — 00H

√ — Undefined

√√0000H

√√0000H

√√0000H

√√0000H

√√0000H

√√0000H

√ 0020H

√ 0020H

√ 0087H

√ 0087H

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 12 Extended Special Function Register (2nd SFR) List (3/7)

Manipulable Bit Range

1-bit 8-bit 16-bit

After Reset

Address

Extended Special Function Register

(2nd SFR) Name

Symbol R/W

F0122H Serial channel start register 0 SS0L SS0 R/W

F0123H — — —

F0124H Serial channel stop register 0 ST0L ST0 R/W

F0125H — — —

F0126H Serial clock select register 0 SPS0L SPS0 R/W —

F0127H — — —

F0128H Serial output register 0 SO0 R/W — —

F0129H

F012AH Serial output enable register 0 SOE0L SOE0 R/W

F012BH — — —

F0134H Serial output level register 0 SOL0L SOL0 R/W —

F0135H — — —

F0140H Serial status register 10 SSR10L SSR10 R —

F0141H — — —

F0142H Serial status register 11 SSR11L SSR11 R —

F0143H — — —

F0144H Serial status register 12 SSR12L SSR12 R —

F0145H — — —

F0146H Serial status register 13 SSR13L SSR13 R —

F0147H — — —

F0148H Serial flag clear trigger register 10 SIR10L SIR10 R/W —

F0149H — — —

F014AH Serial flag clear trigger register 11 SIR11L SIR11 R/W —

F014BH — — —

F014CH Serial flag clear trigger register 12 SIR12L SIR12 R/W —

F014DH — — —

F014EH Serial flag clear trigger register 13 SIR13L SIR13 R/W —

F014FH — — —

F0150H Serial mode register 10 SMR10 R/W — —

F0151H

F0152H Serial mode register 11 SMR11 R/W — —

F0153H

F0154H Serial mode register 12 SMR12 R/W — —

F0155H

F0156H Serial mode register 13 SMR13 R/W — —

F0157H

F0158H Serial communication operation

F0159H

F015AH Serial communication operation

F015BH

setting register 10

setting register 11

SCR10 R/W — —

SCR11 R/W — —

√√√0000H

√√√0000H

√√√0000H

√√0000H

√ 0F0FH

√√0000H

√√0000H

√√0000H

√√0000H

√√0000H

√√0000H

√√0000H

√√0000H

√√0000H

√ 0020H

√ 0020H

√ 0020H

√ 0020H

√ 0087H

√ 0087H

R01UH0575EJ0120 Rev. 1.20 Page 62 of 920
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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 13 Extended Special Function Register (2nd SFR) List (4/7)

Manipulable Bit Range

1-bit 8-bit 16-bit

After Reset

Address

Extended Special Function Register

(2nd SFR) Name

Symbol R/W

F015CH Serial communication operation

F015DH

F015EH Serial communication operation

F015FH

F0160H Serial channel enable status register 1SE1L SE1 R

F0161H — — —

F0162H Serial channel start register 1 SS1L SS1 R/W

F0163H — — —

F0164H Serial channel stop register 1 ST1L ST1 R/W

F0165H — — —

F0166H Serial clock select register 1 SPS1L SPS1 R/W —

F0167H — — —

F0168H Serial output register 1 SO1 R/W — —

F0169H

F016AH Serial output enable register 1 SOE1L SOE1 R/W

F016BH — — —

F0174H Serial output level register 1 SOL1L SOL1 R/W —

F0175H — — —

F0180H Timer counter register 00 TCR00 R — —

F0181H

F0182H Timer counter register 01 TCR01 R — —

F0183H

F0184H Timer counter register 02 TCR02 R — —

F0185H

F0186H Timer counter register 03 TCR03 R — —

F0187H

F0190H Timer mode register 00 TMR00 R/W — —

F0191H

F0192H Timer mode register 01 TMR01 R/W — —

F0193H

F0194H Timer mode register 02 TMR02 R/W — —

F0195H

F0196H Timer mode register 03 TMR03 R/W — —

F0197H

F01A0H Timer status register 00 TSR00L TSR00 R —

F01A1H — — —

F01A2H Timer status register 01 TSR01L TSR01 R —

F01A3H — — —

F01A4H Timer status register 02 TSR02L TSR02 R —

F01A5H — — —

setting register 12

setting register 13

SCR12 R/W — —

SCR13 R/W — —

√√√0000H

√√√0000H

√√√0000H

√√√0000H

√ 0087H

√ 0087H

√√0000H

√ 0F0FH

√√0000H

√ FFFFH

√ FFFFH

√ FFFFH

√ FFFFH

√ 0000H

√ 0000H

√ 0000H

√ 0000H

√√0000H

√√0000H

√√0000H

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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 14 Extended Special Function Register (2nd SFR) List (5/7)

Manipulable Bit Range

1-bit 8-bit 16-bit

After Reset

Address

Extended Special Function Register

(2nd SFR) Name

Symbol R/W

F01A6H Timer status register 03 TSR03L TSR03 R —

F01A7H — — —

F01B0H Timer channel enable status register 0TE0L TE0 R

F01B1H — — —

F01B2H Timer channel start register 0 TS0L TS0 R/W

F01B3H — — —

F01B4H Timer channel stop register 0 TT0L TT0 R/W

F01B5H — — —

F01B6H Timer clock select register 0 TPS0 R/W — —

F01B7H

F01B8H Timer output register 0 TO0L TO0 R/W —

F01B9H — — —

F01BAH Timer output enable register 0 TOE0L TOE0 R/W

F01BBH — — —

F01BCH Timer output level register 0 TOL0L TOL0 R/W —

F01BDH — — —

F01BEH Timer output mode register 0 TOM0L TOM0 R/W —

F01BFH — — —

F01C0H Timer counter register 10 TCR10 R — —

F01C1H

F01C2H Timer counter register 11 TCR11 R — —

F01C3H

F01C4H Timer counter register 12 TCR12 R — —

F01C5H

F01C6H Timer counter register 13 TCR13 R — —

F01C7H

F01D0H Timer mode register 10 TMR10 R/W — —

F01D1H

F01D2H Timer mode register 11 TMR11 R/W — —

F01D3H

F01D4H Timer mode register 12 TMR12 R/W — —

F01D5H

F01D6H Timer mode register 13 TMR13 R/W — —

F01D7H

F01E0H Timer status register 10 TSR10L TSR10 R/W —

F01E1H — — —

F01E2H Timer status register 11 TSR11L TSR11 R/W —

F01E3H — — —

F01E4H Timer status register 12 TSR12L TSR12 R/W —

F01E5H — — —

√√√0000H

√√√0000H

√√√0000H

√√√0000H

√√0000H

√ 0000H

√√0000H

√√0000H

√√0000H

√ FFFFH

√ FFFFH

√ FFFFH

√ FFFFH

√ 0000H

√ 0000H

√ 0000H

√ 0000H

√√0000H

√√0000H

√√0000H

R01UH0575EJ0120 Rev. 1.20 Page 64 of 920
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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 15 Extended Special Function Register (2nd SFR) List (6/7)

Manipulable Bit Range

1-bit 8-bit 16-bit

After Reset

Address

Extended Special Function Register

(2nd SFR) Name

Symbol R/W

F01E6H Timer status register 13 TSR13L TSR13 R/W —

F01E7H — — —

F01F0H Timer channel enable status register 1TE1L TE1 R/W —

F01F1H — — —

F01F2H Timer channel start register 1 TS1L TS1 R/W —

F01F3H — — —

F01F4H Timer channel stop register 1 TT1L TT1 R/W —

F01F5H — — —

F01F6H Timer clock select register 1 TPS1 R/W

F01F7H

F01F8H Timer output register 1 TO1L TO1 R/W —

F01F9H — — —

F01FAH Timer output enable register 1 TOE1L TOE1 R/W —

F01FBH — — —

F01FCH Timer output level register 1 TOL1L TOL1 R/W —

F01FDH — — —

F01FEH Timer output mode register 1 TOM1L TOM1 R/W —

F01FFH — — —

F0230H IICA control register 00 IICCTL00 R/W

F0231H IICA control register 01 IICCTL01 R/W

F0232H IICA low-level width setting register 0 IICWL0 R/W —

F0233H IICA high-level width setting register 0 IICWH0 R/W —

F0234H Slave address register 0 SVA0 R/W —

F0238H IICA control register 10 IICCTL10 R/W

F0239H IICA control register 11 IICCTL11 R/W

F023AH IICA low-level width setting register 1 IICWL1 R/W —

F023BH IICA high-level width setting register 1 IICWH1 R/W —

F023CH Slave address register 1 SVA1 R/W —

F0240H Timer RJ control register 0 TRJCR0 R/W —

F0242H Timer RJ mode register 0 TRJMR0 R/W

F02E0H DTC base address register DTCBAR R/W

F02E8H DTC activation enable register 0 DTCEN0 R/W

F02E9H DTC activation enable register 1 DTCEN1 R/W

F02EAH DTC activation enable register 2 DTCEN2 R/W

F02EBH DTC activation enable register 3 DTCEN3 R/W

F02ECH DTC activation enable register 4 DTCEN4 R/W

F02F0H Flash memory CRC control register CRC0CTL R/W

F02F2H Flash memory CRC operation result

register

PGCRCL R/W — —

——

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—FDH

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√—00H

√√0000H

√√0000H

√√0000H

√√0000H

√ 0000H

√√0000H

√√0000H

√√0000H

√√0000H

√ —FFH

√ —FFH

√ —00H

√ —FFH

√ —FFH

√ —00H

√ —00H

√ 0000H

R01UH0575EJ0120 Rev. 1.20 Page 65 of 920
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RL78/G1H CHAPTER 4 CPU ARCHITECTURE

Table 4 - 16 Extended Special Function Register (2nd SFR) List (7/7)

Manipulable Bit Range

1-bit 8-bit 16-bit

After Reset

Address

Extended Special Function Register

(2nd SFR) Name

Symbol R/W

F02FAH CRC data register CRCD R/W — —

F0300H Event output destination select register 00 ELSELR00 R/W —

F0303H Event output destination select register 03 ELSELR03 R/W —

F0304H Event output destination select register 04 ELSELR04 R/W —

F0307H Event output destination select register 07 ELSELR07 R/W —

F030DH Event output destination select register 13 ELSELR13 R/W —

F0310H Event output destination select register 16 ELSELR16 R/W —

F0311H Event output destination select register 17 ELSELR17 R/W —

F0312H Event output destination select register 18 ELSELR18 R/W —

F0313H Event output destination select register 19 ELSELR19 R/W —

F0314H Event output destination select register 20 ELSELR20 R/W —

F0315H Event output destination select register 21 ELSELR21 R/W —

F0316H Event output destination select register 22 ELSELR22 R/W —

F0317H Event output destination select register 23 ELSELR23 R/W —

F0500H

F0501H

Remark For SFRs in the SFR area, see Tables 4 - 5 to 4 - 9 SFR List.

Timer RJ counter register 0 TRJ0

R/W — —

√ 0000H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ — 00H

√ FFFFH

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

CHAPTER 5 PORT FUNCTIONS

5.1 Port Functions

The RL78/G1H microcontrollers are provided with digital I/O ports, which enable variety of control operations.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate
functions, see CHAPTER 3 PIN FUNCTIONS.

The MCU internal pins described below must be set to output mode after reset release by using the software (set the
port register and port mode register to 0).

• P00, P01, P05, P06, P17, P23 to P27, P41 to P47, P50 to P57, P64 to P67, P73 to P74, P83 to P87, P101, P102,
P110, P111, P145 to P147, P150 to P154

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.2 Port Configuration

Ports include the following hardware.

Table 5 - 1 Port Configuration

Item Configuration

Control registers Port mode registers (PM0 to PM8, PM10 to PM12, PM14, PM15)

Port registers (P0 to P8, P10 to P15)
Pull-up resistor option registers (PU0, PU1, PU3, PU4, PU7, PU8, PU10, PU12, PU14)
Port input mode registers (PIM0, PIM8, PIM14)
Port output mode registers (POM0, POM7, POM8, POM14)
Port mode control registers (PMC0, PMC10, PMC12, PMC14)
A/D port configuration register (ADPC)

Port Total: 41 (CMOS I/O: 31 (N-ch open-drain I/O [V

CMOS input: 5, CMOS output: 1, N-ch open-drain I/O [6 V tolerance]: 4)

Pull-up resistor Total: 28

DD tolerance]: 15),

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.2.1 Port 0

Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using
port mode register 0 (PM0). When the P02 to P04 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Input to the P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 0 (PIM0).
Output from the P02 to P04 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using
port output mode register 0 (POM0).
To use P02 and P03 as digital input/output pins, set them in the digital I/O mode by using port mode control
register 0 (PMC0) (can be specified in 1-bit units).
This port can also be used for A/D converter analog input, serial interface data I/O, and clock I/O.
When reset signal is generated, the following configuration will be set.

• P04 pin.........................................................................................Input port

• P02 and P03 pins......................................................................... Digital I/O is prohibited.

5.2.2 Port 1

Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using
port mode register 1 (PM1). When the P10 to P16 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
This port can also be used for serial interface data I/O, and clock output.
Reset signal generation sets port 1 to input mode.
P10 to P16 pins are used for internal connection between the MCU and RF transceiver. For details, see

CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER.

5.2.3 Port 2

Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using
port mode register 2 (PM2).
This port can also be used for A/D converter analog input and reference voltage (+ side and - side) input.
To use P20/ANI0, P21/ANI1, and P22/ANI2 as digital I/O pins, set them to digital I/O using the A/D port
configuration register (ADPC). Use these pins starting from the upper bit.
To use P20/ANI0, P21/ANI1, and P22/ANI2 as analog input pins, set them to analog function using the A/D port
configuration register (ADPC) and input mode using the PM2 register. Use these pins starting from the lower bit.

All pins are set in the analog function mode when the reset signal is generated.

Table 5 - 2 Setting Functions of P20/ANI0, P21/ANI1, P22/ANI2 Pins

ADPC Register PM2 Register ADS Register

Digital I/O selection Input mode — Digital input

Output mode — Digital output

Analog function selection Input mode Selects ANI. Analog input (to be converted)

Does not select ANI. Analog input

Output mode Selects ANI. Setting prohibited

Does not select ANI.

P20/ANI0, P21/ANI1,

P22/ANI2 Pins

(not to be converted)

All P2 are set in the analog function mode when the reset signal is generated.

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.2.4 Port 3

Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using
port mode register 3 (PM3). When the P30, P31 pins are used as input ports, use of on-chip pull-up resistors can
be specified by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input.
Reset signal generation sets port 3 to input port.
P30 pin is used for internal connection between the MCU and RF transceiver. For details, see CHAPTER 2

CONNECTION BETWEEN MCU AND RF TRANSCEIVER. .

5.2.5 Port 4

Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using
port mode register 4 (PM4). When the P40 pin is used as an input port, use of an on-chip pull-up resistor can be
specified by pull-up resistor option register 4 (PU4).
This port can also be used for data I/O for a flash memory programmer/debugger.
Reset signal generation sets port 4 to input port.

5.2.6 Port 6

Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using
port mode register 6 (PM6).
The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface data I/O and clock I/O.
Reset signal generation sets port 6 to input port.

5.2.7 Port 7

Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using
port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in 1­bit units by pull-up resistor option register 7 (PU7).
Output from the P71 pin can be specified as N-ch open-drain output (V
register 7 (POM7).
This port can also be used for serial interface data I/O, clock I/O, and external interrupt request input.
Reset signal generation sets port 7 to input port.

DD tolerance) using port output mode

5.2.8 Port 8

Port 8 is an I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using
port mode register 8 (PM8). When used as an input port, use of an on-chip pull-up resistor can be specified in 1­bit units by pull-up resistor option register 8 (PU8).
Input to the P80 and P81 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 8 (PIM8).
Output from the P80 to P82 pin can be specified as N-ch open-drain output (V
port output mode register 8 (POM8).
Reset signal generation sets port 8 to input port.

DD tolerance) in 1-bit units using

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

P130

Set by software

Reset signal

5.2.9 Port 10

Port 10 is an I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using
port mode register 10 (PM10). When the P100 to P102 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 10 (PU10).
Set the P100 pin to digital I/O using port mode control register 10 (PMC10).
Reset signal generation sets P100 to prohibit digital I/O.

5.2.10 Port 12

P120 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using
port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 12 (PU12).
P121 to P124 are 4-bit input ports.
To use the P120 pin as a digital I/O port, set it to digital I/O using port mode control register 12 (PMC12).
This port can also be used for A/D converter analog input, resonator connection for the subsystem clock,
external clock input for the main system clock, and external clock input for the subsystem clock.
Reset signal generation sets P120 to analog function, and sets P121 to P124 to input port.

5.2.11 Port 13

P130 is a 1-bit output-only port with an output latch. P137 is a 1-bit input-only port.
P130 is fixed an output port, and P137 is fixed an input ports.
This port can also be used for external interrupt request input.
Connect the P130 pin to STANDBY pin.

Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the CPU reset signal.

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.2.12 Port 14

Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using
port mode register 14 (PM14). When the P140 to P144 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 14 (PIM14).
Output from the P142 to P144 pin can be specified as N-ch open-drain output (V

DD tolerance) in 1-bit units using

port output mode register 14 (POM14).
To use the P147 set it to digital I/O using port mode control register 14 (PMC14).
This port can also be used for clock/buzzer output, external interrupt request input, serial interface data I/O, and
clock I/O.
Reset signal generation sets port 14 to input port.

5.2.13 Port 15

Port 15 is an I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using
port mode register 15 (PM15).
This port can also be used for A/D converter analog input.
To use P155/ANI13 and P156/ANI14 as digital I/O pins, set them to digital I/O using the A/D port configuration
register (ADPC). Use these pins starting from the upper bit.
To use P155/ANI13 and P156/ANI14 as analog input pins, set them to analog function using the A/D port
configuration register (ADPC) and input mode using the PM15 register. Use these pins starting from the lower bit.

Table 5 - 3 Setting Functions of P155/ANI13 and P156/ANI14 Pins

ADPC Register PM15 Register ADS Register

Digital I/O selection Input mode — Digital input

Output mode — Digital output

Analog function selection Input mode Selects ANI. Analog input (to be converted)

Does not select ANI. Analog input

Output mode Selects ANI. Setting prohibited

Does not select ANI.

P155/ANI13 and P156/ANI14

Pins

(not to be converted)

All P15 are set in the analog function mode when the reset signal is generated.

5.2.14 GPIO port

GPIO port is an I/O port with an output latch. For GPIO port, SCI20 enables the mode setting and I/O.
For details, see CHAPTER 18 RF TRANSCEIVER.

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.3 Registers Controlling Port Function

Port functions are controlled by the following registers.

• Port mode registers (PMxx)

• Port registers (Pxx)

• Pull-up resistor option registers (PUxx)

• Port input mode registers (PIMxx)

• Port output mode registers (POMxx)

• Port mode control registers (PMCxx)

• A/D port configuration register (ADPC)

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

Table 5 - 4 PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits (1/2)

Bit name

Port

Port 0 2 PM02 P02 PU02 — POM02 PMC02

3 PM03 P03 PU03 PIM03 POM03 PMC03

4 PM04 P04 PU04 PIM04 POM04 —

Port 1 0 PM10 P10 PU10 — — —

1 P M11 P 11 PU 11 — — —

2PM12 P12 PU12 — — —

3PM13 P13 PU13 — — —

4PM14 P14 PU14 — — —

5PM15 P15 PU15 — — —

6PM16 P16 PU16 — — —

Port 2 0 PM20 P20 — — — —

1PM21 P21 — — — —

2PM22 P22 — — — —

Port 3 0 PM30 P30 PU30 — — —

1PM31 P31 PU31 — — —

Port 4 0 PM40 P40 PU40 — — —

Port 6 0 PM60 P60 — — — —

1PM61 P61 — — — —

2PM62 P62 — — — —

3PM63 P63 — — — —

Port 7 0 PM70 P70 PU70 — — —

1 PM71 P71 PU71 — POM71 —

2PM72 P72 PU72 — — —

5PM75 P75 PU75 — — —

6PM76 P76 PU76 — — —

7PM77 P77 PU77 — — —

Port 8 0 PM80 P80 PU80 PIM80 POM80 —

1 PM81 P81 PU81 PIM81 POM81 —

2 PM82 P82 PU82 — POM82 —

Port 10 0 PM100 P100 PU100 — — PMC100

Port 12 0 PM120 P120 PU120 — — PMC120

1— P121 — — — —

2— P122 — — — —

3— P123 — — — —

4— P124 — — — —

Port 13 0 — P130 — — — —

7— P137 — — — —

PMxx

register

Pxx

register

PUxx

register

PIMxx

register

POMxx
register

PMCxx
register

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

Table 5 - 5 PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits (2/2)

Bit name

Port

Port 14 0 PM140 P140 PU140 — — —

1 PM141 P141 PU141 — — —

2 PM142 P142 PU142 PIM142 POM142 —

3 PM143 P143 PU143 PIM143 POM143 —

4 PM144 P144 PU144 — POM144 —

Port 15 5 PM155 P155 — — — —

6 PM156 P156 — — — —

PMxx

register

Pxx

register

PUxx

register

PIMxx

register

POMxx
register

PMCxx
register

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.3.1 Port mode registers (PMxx)

These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register by referencing 5.5 Register

Settings When Using Alternate Function.

Figure 5 - 1 Format of Port mode register

Symbol76543210 Address After reset R/W

PM0

1

PM1 PM17

Note 1

PM2 PM27

Note 1

PM3

111111PM31

PM4 PM47

Note 1

PM5 PM57

Note 1

PM6 PM67

Note 1

PM7

PM77 PM76 PM75

PM8 PM87

Note 1

PM06

Note 1

PM16

Note 2

PM26

Note 1

PM46

Note 1

PM56

Note 1

PM66

Note 1

PM86

Note 1

PM05

Note 1

PM15

Note 2

PM25

Note 1

PM45

Note 1

PM55

Note 1

PM65

Note 1

PM85

Note 1

PM00

PM12

Note 2

PM01

Note 1

PM11

Note 2

Note 1

PM10

Note 2

FFF20H FFH R/W

FFF21H FFH R/W

PM22 PM21 PM20 FFF22H FFH R/W

PM42

Note 1

PM52

Note 1

PM30

Note 3

PM41

PM40 FFF24H FFH R/W

Note 1

PM51

PM50

Note 1

Note 1

FFF23H FFH R/W

FFF25H FFH R/W

PM72 PM71 PM70 FFF27H FFH R/W

PM82 PM81 PM80 FFF28H FFH R/W

PM04 PM03 PM02

PM14

PM13

Note 3

Note 2

PM24

PM23

Note 1

Note 1

PM44

PM43

Note 1

Note 1

PM54

PM53

Note 1

Note 1

PM64

PM63 PM62 PM61 PM60 FFF26H FFH R/W

Note 1

PM73

PM74

Note 1

Note 1

PM84

PM83

Note 1

Note 1

PM10

PM11

11111

111111

PM102

Note 1

PM101

Note 1

PM 111

Note 1

PM100 FFF2AH FFH R/W

PM110

Note 1

FFF2BH FFH R/W

PM121111111PM120FFF2CH FFH R/W

PM146

Note 1

PM145

PM144 PM143 PM142 PM141 PM140 FFF2EH FFH R/W

Note 1

PM153

PM152

PM154

Note 1

Note 1

PM151

Note 1

Note 1

PM150

Note 1

FFF2FH FFH R/W

PM14 PM147

Note 1

PM15

1 PM156 PM155

PMmn Pmn pin I/O mode selection (m = 0 to 8, 10 to 12, 14, 15; n = 0 to 7)

0 Output mode (the pin functions as an output port (output buffer on))

1 Input mode (the pin functions as an input port (output buffer off))

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

Note 1. Control bits for internal pins. After reset release, be sure to set to output mode by software (set 0 to port

mode register).

Note 2. Control bits for internal connecting pins. After reset release, be sure to set to output mode by software (set 0

to port mode register).

Note 3. Control bits for internal connecting pins. After reset release, be sure to set to input mode by software (set 1 to

port mode register).

Caution Be sure to set bits that are not mounted to their initial values. For the register that has an instruction

to clear the bit to 0, clear it to 0.

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.3.2 Port registers (Pxx)

These registers set the output latch value of a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is

Note

read
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.

Note When P20 to P22, P120 are set to the analog function, if a port is read in input mode, the read value

.

is always 0, not the pin level.

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

Figure 5 - 2 Format of Port register

Symbol76543210 Address After reset R/W

P0

0

P1 P17

Note 3

P2 P27

Note 3

P06

Note 3

P05

Note 3

P04 P03 P02

Note 3

P16 P15 P14 P13 P12 P11 P10 FFF01H 00H (output latch) R/W

P26

Note 3

P25

Note 3

P24

Note 3

P23

Note 3

P22 P21 P20 FFF02H 00H (output latch) R/W

P01

P00

Note 3

FFF00H 00H (output latch) R/W

P3000000P31P30FFF03H00H (output latch)R/W

P4 P47

Note 3

P5 P57

Note 3

P6 P67

Note 3

P7

P77 P76 P75

P8 P87

Note 3

P46

Note 3

P56

Note 3

P66

Note 3

P86

Note 3

P45

Note 3

P55

Note 3

P65

Note 3

P85

Note 3

P44

Note 3

P54

Note 3

P64

Note 3

P74

Note 3

P84

Note 3

P43

Note 3

P53

Note 3

P42

Note 3

P52

Note 3

P41

Note 3

P51

Note 3

P40 FFF04H 00H (output latch) R/W

P50

Note 3

FFF05H 00H (output latch) R/W

P63 P62 P61 P60 FFF06H 00H (output latch) R/W

P73

Note 3

Note 3

P72 P71 P70 FFF07H 00H (output latch) R/W

P83

P82 P81 P80 FFF08H 00H (output latch) R/W

P10

00000

P11

000000

P12

0 0 0 P124 P123 P122 P121 P120 FFF0CH Undefined

P13

P137000000P130FFF0DH

P14 P147

Note 3

P15

P146

Note 3

P145

Note 3

0P156P155

Pmn

Output data control (in output mode) Input data read (in input mode)

P144 P143 P142 P141 P140 FFF0EH 00H (output latch) R/W

P154

Note 3

P513

Note 3

Note 3

Note 3

P101

P102

Note 3

Note 3

P152

Note 3

P100 FFF0AH 00H (output latch) R/W

P110

P111

Note 3

P151

P150

Note 3

m = 0 to 8, 10 to 15; n = 0 to 7

FFF0BH 00H (output latch) R/W

FFF0FH 00H (output latch) R/W

0 Output 0 Input low level

1 Output 1 Input high level

Note 1. P121 to P124, and P137 are read-only.
Note 2. P137: Undefined

P130: 0 (output latch)

Note 3. Control bits for internal pins. After reset release, be sure to set 0 to port mode register.

Note 2

R/W

R/W

Note 1

Note 1

Caution Be sure to set bits that are not mounted to their initial values.

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.3.3 Pull-up resistor option registers (PUxx)

These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can
be used in 1-bit units only for the bits set to input mode (PMmn = 1 and POMmn = 0) for the pins to which the use
of an on-chip pull-up resistor has been specified in these registers. On-chip pull-up resistors cannot be
connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of
these registers. Similarly, on-chip pull-up resistors cannot be connected to the pins used as alternate-function
output pins and the pins set to the analog function.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H (Only PU4 is set to 01H).

Figure 5 - 3 Format of Pull-up resistor option register

Symbol76543210 Address After reset R/W

PU0 0 0 0 PU04 PU03 PU02 0 0 F0030H 00H R/W

PU1 0 PU16 PU15 PU14 PU13 PU12 PU11 PU10 F0031H 00H R/W

PU3000000PU31PU30F0033H 00H R/W

PU40000000PU40F0034H 01H R/W

PU7 PU77 PU76 PU75 0 0 PU72 PU71 PU70 F0037H 00H R/W

PU800000PU82PU81PU80F0038H 00H R/W

PU100000000PU100F003AH 00H R/W

PU120000000PU120F003CH 00H R/W

PU14 0 0 0 PU144 PU143 PU142 PU141 PU140 F003EH 00H R/W

PUmn Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 8, 10 to 12, 14; n = 0 to 7)

0 On-chip pull-up resistor not connected

1 On-chip pull-up resistor connected

Caution Be sure to set bits that are not mounted to their initial values.

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.3.4 Port input mode registers (PIMxx)

These registers set the input buffer in 1-bit units.
TTL input buffer can be selected during serial communication with an external device of the different potential.
Port input mode registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.

Figure 5 - 4 Format of Port input mode register

Symbol76543210 Address After reset R/W

PIM0000PIM04PIM03000 F0040H 00H R/W

PIM8000000PIM81PIM80F0048H 00H R/W

PIM140000PIM143PIM14200 F004EH 00H R/W

PIMmn Pmn pin input buffer selection (m = 0, 1, 3 to 5, 8, 14; n = 0 to 7)

0 Normal input buffer

1 TTL input buffer

Caution Be sure to set bits that are not mounted to their initial values.

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RL78/G1H CHAPTER 5 PORT FUNCTIONS

5.3.5 Port output mode registers (POMxx)

These registers set the output mode in 1-bit units.
N-ch open-drain output (VDD tolerance) mode can be selected during serial communication with an external
device of the different potential.
In addition, POMxx register is set with PUxx register, whether or not to use the on-chip pull-up resistor.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.

Caution An on-chip pull-up resistor is not connected to a bit for which N-ch open-drain output (V

DD

tolerance) mode (POMmn = 1) is set.

Figure 5 - 5 Format of Port output mode register

Symbol76543210 Address After reset R/W

POM0 0 0 0 POM04 POM03 POM02 0 0 F0050H 00H R/W

POM7000000POM710 F0057H 00H R/W

POM8

POM14000

00000POM82POM81POM80

POM144 POM143 POM142

POMmn Pmn pin output mode selection (m = 0, 1, 3 to 5, 7, 8, 14; n = 0 to 5, 7)

0 Normal output mode

1 N-ch open-drain output (V

Caution Be sure to set bits that are not mounted to their initial values.

DD tolerance) mode

0 0 F005EH 00H R/W

F0058H 00H R/W

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