Datasheet
RJK6013DPP-A0
600V - 11A - MOS FET
High Speed Power Switching
Features
Low on-resistance
R
= 0.58 typ. (at ID = 5.5 A, VGS = 10 V, Ta = 25 C)
DS(on)
Low leakage current
High speed switching
Quality grade: Standard
Outline
RENESAS Package code:
(Package name:
TO-220FPA)
1
2
3
PRSS0003AP-A
R07DS1433EJ0100
Rev.1.00
Mar.10.2021
D
1. Gate
G
S
2. Drain
3. Source
Absolute Maximum Ratings
(Ta = 25 C)
Item Symbol Ratings Unit
Drain to source voltage V
Gate to source voltage V
Drain current I
Drain peak current I
Body-drain diode reverse drain current IDR 11 A
Body-drain diode reverse drain peak current I
Avalanche current I
Avalanche energy E
Channel dissipation Pch
Channel temperature Tch 150 C
Storage temperature Tstg –55 to +150 C
Note: Continuous heavy condition (e.g. high temperature/voltage/current or high variation of temperature) may affect a
reliability even if it is within the absolute maximum ratings. Please consider derating condition for appropriate
reliability in reference Renesas Semiconductor Reliability Handbook (Recommendation for Handling and Usage
of
Semiconductor Devices) and individual reliability data
Notes: 1. PW 10 s, duty cycle 1 %
2. Value at Tc = 25 C
3. STch = 25 C, Tch 150 C
4. Limited by maximum safe operation area
DR (pulse)
600 V
DSS
30 V
GSS
Notes4
11 A
D
Notes1
D (pulse)
AP
AR
33 A
Notes1
33 A
Notes3
4 A
Notes3
0.87 mJ
Notes2
30 W
.
R07DS1433EJ0100 Rev.1.00 Page 1 of 6
Mar.10.2021
RJK6013DPP-A0
Thermal Resistance Characteristics
(Ta = 25 C)
Item Symbol Max. Value
Notes5
Unit
Channel to case thermal impedance ch-c 4.17 CW
Notes: 5. Designed target value on Renesas measurement condition. (Not tested)
Electrical Characteristics
(Ta = 25 C)
Item Symbol Min Typ Max Unit Test conditions
Drain to source breakdown voltage V
Zero gate voltage drain current I
Gate to source leak current I
Gate to source cutoff voltage V
Static drain to source on state
resistance
Input capacitance Ciss — 1450 — pF VDS = 25 V
Output capacitance Coss — 140 — pF
Reverse transfer capacitance Crss — 17 — pF
Turn-on delay time t
Rise time tr — 20 — ns
Turn-off delay time t
Fall time tf — 15 — ns
Total gate charge Qg — 37.5 — nC VDD = 480 V
Gate to source charge Qgs — 7.3 — nC
Gate to drain charge Qgd — 16.4 — nC
Body-drain diode forward voltage VDF — 0.87 1.45 V IF = 11 A, VGS = 0
Body-drain diode reverse recovery time trr — 350 — ns IF = 11 A, VGS = 0
Notes: 6. Pulse test
600 — — V ID = 10 mA, VGS = 0
(BR)DSS
— — 1 A VDS = 600 V, VGS = 0
DSS
— — 0.1 A VGS = 30 V, VDS = 0
GSS
3.0 — 4.5 V VDS = 10 V, ID = 1 mA
GS(off)
R
— 0.58 0.70 ID = 5.5 A, VGS = 10 V
DS(on)
V
= 0
GS
f = 1 MHz
— 33 — ns ID = 5.5 A
d(on)
V
= 10 V
GS
R
= 54.5
— 87 — ns
d(off)
L
Rg = 10
V
= 10 V
GS
I
= 11 A
D
di
dt = 100 As
F
Notes6
Notes6
R07DS1433EJ0100 Rev.1.00 Page 2 of 6
Mar.10.2021
RJK6013DPP-A0
Main Characteristics
Maximum Safe Operation Area
100
P
10
(A)
D
1
Operation in this
area is limited by
R
DS(on)
Tc = 25C
1 shot
Notes7
0.1 1 10 100 1000
Drain Current I
0.001
0.1
0.01
W
1
0
s
=
1
0
0
s
(A)
D
Drain Current I
Typical Output Characteristics
20
Ta = 25C
Pulse Test
16
12
8
4
0
048121620
10 V
7 V
6 V
5.8 V
5.6 V
V
.
4
5
V
.
5
2
V
=
V
5
G
S
Drain to Source Voltage V
DS
Typical Transfer Characteristics
20
VDS = 10 V
Pulse Test
16
(A)
D
12
8
Drain Current I
4
0
Tc = 75C
02 46810
Gate to Source Voltage V
25C
25C
GS
Static Drain to Source on State Resistance
vs. Temperature (Typical)
2.0
()
VGS= 10 V
Pulse Test
DS(on)
1.6
(V)
(V)
Drain to Source Voltage VDS (V)
Static Drain to Source on State Resistance
vs. Drain Current (Typical)
10
()
R
Drain to Source on State Resistance
VGS = 10 V
Ta = 25C
Pulse Test
DS(on)
1
0.1
1 10010
Drain Current ID (A)
Body-Drain Diode Reverse
Recovery Time (Typical)
1000
(ns)
rr
1.2
0.8
0.4
0
R
Static Drain to Source on State Resistance
-25 0 5025 75 100 125 150
ID = 11 A
3 A
5.5 A
Case Temperature Tc (C)
100
di / dt = 100 A / s
V
= 0, Ta = 25C
Reverse Recovery Time t
10
0.1
Reverse Drain Current IDR (A)
GS
1 10 100
Notes: 7. Designed target value on Renesas measurement condition. (Not tested)
Renesas recommends that operating conditions are designed according to a document “Power MOS FET・
IGBT Attention of Handling Semiconductor Devices”.
R07DS1433EJ0100 Rev.1.00 Page 3 of 6
Mar.10.2021