Renesas RJK6006DPP-A0 Datasheet

Datasheet
RJK6006DPP-A0
600V - 5A - MOS FET High Speed Power Switching
Features
Low on-resistance
= 1.4 typ. (at ID = 2.5 A, VGS = 10 V, Ta = 25 C)
DS(on)
Low leakage current High speed switching Quality grade: Standard
Outline
RENESAS Package code: (Package name:
TO-220FPA)
1
2
3
PRSS0003AP-A
R07DS1432EJ0100
Rev.1.00
Mar.10.2021
D
1. Gate
G
S
2. Drain
3. Source
Absolute Maximum Ratings
(Ta = 25 C)
Item Symbol Ratings Unit
Drain to source voltage V
Gate to source voltage V
Drain current I
Drain peak current I
Body-drain diode reverse drain current IDR 5 A
Body-drain diode reverse drain peak current I
Avalanche current I
Avalanche energy E
Channel dissipation Pch
Channel temperature Tch 150 C
Storage temperature Tstg –55 to +150 C
Note: Continuous heavy condition (e.g. high temperature/voltage/current or high variation of temperature) may affect a
reliability even if it is within the absolute maximum ratings. Please consider derating condition for appropriate reliability in reference Renesas Semiconductor Reliability Handbook (Recommendation for Handling and Usage of
Semiconductor Devices) and individual reliability data
Notes: 1. PW  10 s, duty cycle  1 %
2. Value at Tc = 25 C
3. STch = 25 C, Tch 150 C
4. Limited by maximum safe operation area
DR (pulse)
600 V
DSS
30 V
GSS
Notes4
5 A
D
Notes1
D (pulse)
AP
AR
15 A
Notes1
15 A
Notes3
5 A
Notes3
1.36 mJ
Notes2
29 W
.
R07DS1432EJ0100 Rev.1.00 Page 1 of 6 Mar.10.2021
RJK6006DPP-A0
Thermal Resistance Characteristics
(Ta = 25 C)
Item Symbol Max. Value
Channel to case thermal impedance ch-c 4.31 CW
Notes: 5. Designed target value on Renesas measurement condition. (Not tested)
Notes5
Unit
Electrical Characteristics
(Ta = 25 C)
Item Symbol Min Typ Max Unit Test conditions
Drain to source breakdown voltage V
Zero gate voltage drain current I
Gate to source leak current I
Gate to source cutoff voltage V
Static drain to source on state resistance
Input capacitance Ciss 600 pF VDS = 25 V
Output capacitance Coss 70 pF
Reverse transfer capacitance Crss 10 pF
Turn-on delay time t
Rise time tr — 17 — ns
Turn-off delay time t
Fall time tf — 10 — ns
Total gate charge Qg 19 nC VDD = 480 V
Gate to source charge Qgs 3.4 nC
Gate to drain charge Qgd 9.2 nC
Body-drain diode forward voltage VDF — 0.9 1.5 V IF = 5 A, VGS = 0
Body-drain diode reverse recovery time trr — 250 — ns IF = 5 A, VGS = 0
Notes: 6. Pulse test
600 — — V ID = 10 mA, VGS = 0
(BR)DSS
— — 1 A VDS = 600 V, VGS = 0
DSS
— — 0.1 A VGS = 30 V, VDS = 0
GSS
3.0 — 4.5 V VDS = 10 V, ID = 1 mA
GS(off)
R
— 1.4 1.6  ID = 2.5 A, VGS = 10 V
DS(on)
V
= 0
GS
f = 1 MHz
— 25 — ns ID = 2.5 A
d(on)
V
= 10 V
GS
R
= 80
— 60 — ns
d(off)
L
Rg = 10
V
= 10 V
GS
I
= 5 A
D
di
dt = 100 As
F
Notes6
Notes6
R07DS1432EJ0100 Rev.1.00 Page 2 of 6 Mar.10.2021
RJK6006DPP-A0
Main Characteristics
Maximum Safe Operation Area
100
10
(A)
D
1
Tc = 25C 1 shot Notes7
Operation in this area is limited by R
DS(on)
0.1
Drain Current I
0.01
0.001
0.1 1 10 100 1000
P
W
1
0
s
=
1
00
s
(A)
D
Drain Current I
Typical Output Characteristics
10
Ta = 25C Pulse Test
8
0
1
6
4
2
0
048121620
V
6
V
7
V
6
V
.
5
V
8
.
5
4
V
.
5
.
5
2
V
V
5
V
=
8
.
4
V
G
S
Drain to Source Voltage V
DS
Typical Transfer Characteristics
10
VDS = 10 V
Pulse Test
8
(A)
D
6
4
Drain Current I
2
0
02 46810
Gate to Source Voltage V
Tc = 25C
25C
75C
GS
Static Drain to Source on State Resistance
vs. Temperature (Typical)
5
()
VGS= 10 V Pulse Test
DS(on)
4
ID = 5 A
3
2
1 A
2.5 A
(V)
(V)
Drain to Source Voltage VDS (V)
Static Drain to Source on State Resistance
vs. Drain Current (Typical)
10
()
DS(on)
R
Drain to Source on State Resistance
VGS = 10 V Ta = 25C Pulse Test
1
0.1 110010
Drain Current ID (A)
Body-Drain Diode Reverse
Recovery Time (Typical)
1000
(ns)
rr
100
1
0
R
Static Drain to Source on State Resistance
-25 0 5025 75 100 125 150
Case Temperature Tc (C)
Reverse Recovery Time t
10
110100
Reverse Drain Current IDR (A)
di / dt = 100 A / s V
= 0, Ta = 25C
GS
Notes: 7. Designed target value on Renesas measurement condition. (Not tested)
Renesas recommends that operating conditions are designed according to a document “Power MOS FET IGBT Attention of Handling Semiconductor Devices”.
R07DS1432EJ0100 Rev.1.00 Page 3 of 6 Mar.10.2021
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