Renesas REJ06B0732-0100 User Manual

APPLICATION NOTE

SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

Introduction

This application note describes the operation of the DMAC, and is intended for reference to help in the design of user
software.

Target Device

SH7211

Contents

1. Introduction ....................................................................................................................................... 2

2. Description of Sample Application.................................................................................................... 3

3. Documents of Reference................................................................................................................11

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Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

1. Introduction

1.1 Specification

• DMAC channel 0 is used.

• Auto-request mode is used as the interrupt source for activating DMA transfer.

• Cycle-stealing mode is used as the bus mode.

1.2 Used Module

• Direct memory access controller (DMAC channel 0)

1.3 Applicable Conditions

• Microcontroller: SH7211

• Operating Frequency: Internal clock 160 MHz

Bus clock 40 MHz
Peripheral clock 40 MHz

• C Compiler: SuperH RISC engine family C/C++ compiler package Ver.9.01,

from Renesas Technology

SH7211 Group

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SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

2. Description of Sample Application

In this sample application, the direct memory access controller (DMAC) is set to auto request mode to transfer 512­Kbtyte data stored in the on-chip RAM to another address.

2.1 Operation of Modules Used

When a DMA transfer request is made, the DMAC starts to transfer data in accordance with the priority order of
channels and continues the transfer operation until the transfer end condition is met. Transfer requests for the DMAC
are of three kinds: auto requests, external requests, and on-chip peripheral module requests. The bus mode is selectable
as burst mode or cycle-stealing mode.

For details on the DMAC, refer to the section on the direct memory access controller in the SH7211 Group Hardware
Manual.

An overview of the DMAC is given in table 1. Examples of DMA transfer in cycle-stealing mode and burst mode are
shown in figures 1 and 2, respectively. In addition, a block diagram of the DMAC is shown in figure 3.

Table 1 Overview of DMAC

Item Description

Number of channels 8 (CH0 to CH7)

Only 4 (CH0 to CH3) can receive external requests.
Address space 4 Gbytes
Length of transfer data Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword × 4)
Maximum transfer count 16,777,216 (24 bits) transfers
Address mode Single address mode and dual address mode
Transfer request External request, on-chip peripheral module request, and auto request

(SCIF: 8 sources, IIC3: two sources, A/D converter: one source, MTU2:

five sources, CMT: two sources)
Bus mode

Priority level Channel priority fixed mode and round-robin mode
Interrupt request

External request detection DREQ input low/high level detection, rising/falling edge detection
Transfer request acknowledge

signal/transfer end signal

Cycle-stealing mode (normal mode and intermittent mode) and burst

mode

An interrupt request to the CPU is made when half or all of a transfer

process is completed.

Active levels for DACK and TEND can be set independently

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SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

In the normal mode of cycle stealing, bus mastership is given to another bus master after each DMA
transfer of one transfer unit (byte, word, longword, or 16-byte unit). When a subsequent transfer
request occurs, bus mastership is obtained from the other bus master and transfer proceeds for one
transfer unit. When that transfer ends, the bus mastership is passed to another bus master. This is
repeated until the transfer end condition is satisfied.
The cycle-stealing normal mode can be used in transfer across any interval, regardless of the
requesting source, source, and destination of the transfer.

DREQ

Bus mastership returned to CPU once

Bus cycle

CPU CPU CPU DMAC DMAC DMAC DMAC CPUCPU

WriteRead WriteRead

Figure 1 DMA Transfer Example in Cycle-Stealing Normal Mode

(Dual Address, DREQ Low Level Detection)

In burst mode, once the DMAC has obtained bus mastership, it continues to perform transfer without
releasing the bus until the transfer end condition is satisfied. In external mode, however, when the DREQ
signal is being level-detected and changes to the non-active level, even if the tranfer end condition has not
been satisfied, bus mastership is passed to another bus master on completion of the DMA transfer request
for which the request has already been accepted.

DREQ

Bus cycle

CPU CPU CPU

DMAC DMAC DMAC DMAC CPUCPU

Read Write Read Write

Figure 2 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection)

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