Renesas R8C/Tiny Series Software Manual

REJ09B0001-0200Z

R8C/Tiny Series

16

Software Manual

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Rev. 2.00 Revision date: Oct 17, 2005

www.renesas.com

Keep safety first in your circuit designs!

1.

Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1.

These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2.

Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3.

All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com).

4.

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8.

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Using This Manual

This software manual is written for the R8C/Tiny Series. It applies to all microcomputers integrating the R8C/Tiny Series CPU core. The reader of this manual is assumed to have a basic knowledge of electrical circuits, logic circuits, and microcomputers. This manual consists of six chapters. The chapters and the subjects they cover are listed below.

• Outline of the R8C/Tiny Series and its features ...............................Chapter 1, “Overview”

•

Operation of addressing modes.......................................................

• Instruction functions (syntax, operation, function, selectable src/dest (labels), flag changes,

description example, related instructions).......................................... Chapter

Instruction codes and cycles ...............................

•

• Instruction interrupts...........................................................................Chapter 5, “Interrupts”

How to calculate the number of cycles ................

•

This manual also contains quick reference sections immediately following the table of contents. These quick reference sections can be used to rapidly find the pages referring to specific functions, instruction codes, and cycle counts.

Chapter

4, “Instruction Codes/Number of Cycles”

6, “Calculating the Number of Cycles”

Chapter

2, “Addressing Modes”

3, “Functions”

• Alphabetic listing by mnemonic................................Quick Reference in Alphabetic Order

• Listing of mnemonics by function.......................................... Quick Reference by Function

• Listing of addressing modes by mnemonic ...........Quick Reference by Addressing Mode

A Q&A table, symbols, a glossary, and an index are appended at the end of this manual.

M16C Family Documents

The following documents were prepared for the M16C family.

(1)

Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, periph-

eral specifications, electrical characteristics, timing charts). *Refer to the application note for how to use peripheral functions.

Software Manual Detailed description of assembly instructions and microcomputer

performance of each instruction

Application Note • Usage and application examples of peripheral functions

• Sample programs

• Introduction to the basic functions in the M16C family

• Programming method with Assembly and C languages RENESAS TECHNICAL Preliminary report about the specification of a product, a document, etc. UPDATE

NOTES:

1. Before using this material, please visit the our website to verify that this is the most updated document available.

Quick Reference in Alphabetic Order

Mnemonic

ABS 39 ADC 40 ADCF 41 ADD 42 ADJNZ 44 AND 45 BAND 47 BCLR 48 BMCnd 49 BMEQ/Z 49 BMGE 49 BMGEU/C 49 BMGT 49 BMGTU 49 BMLE 49 BMLEU 49 BMLT 49 BMLTU/NC 49 BMN 49 BMNE/NZ 49 BMNO 49 BMO 49 BMPZ 49 BNAND 50 BNOR 51 BNOT 52 BNTST 53 BNXOR 54 BOR 55 BRK 56 BSET 57 BTST 58 BTSTC 59 BTSTS 60 BXOR 61 CMP 62 DADC 64 DADD 65 DEC 66 DIV 67

Page No. for

Function

Page No. for

Instruction Code

/No. of Cycles

138 138 140 140 146 147 150 150 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 153 154 154 155 156 156 157 157 158 159 160 160 161 165 167 169 170

Mnemonic

DIVU 68 DIVX 69 DSBB 70 DSUB 71 ENTER 72 EXITD 73 EXTS 74 FCLR 75 FSET 76 INC 77 INT 78 INTO 79 J

Cnd

JEQ/Z 80 JGE 80 JGEU/C 80 JGT 80 JGTU 80 JLE 80 JLEU 80 JLT 80 JLTU/NC 80 JN 80 JNE/NZ 80 JNO 80 JO 80 JPZ 80 JMP 81 JMPI 82 JSR 83 JSRI 84 LDC 85 LDCTX 86 LDE 87 LDINTB 88 LDIPL 89 MOV 90 MOVA 92

Page No. for

Function

Instruction Code

/No. of Cycles

80

Page No. for

171 172 173 175 177 178 178 179 180 180 181 182 182 182 182 182 182 182 182 182 182 182 182 182 182 182 182 183 185 187 188 189 191 191 192 193 193 200

Quick Reference-1

Quick Reference in Alphabetic Order

Mnemonic

MOV

Dir

MOVHH 93 MOVHL 93 MOVLH 93 MOVLL 93 MUL 94 MULU 95 NEG 96 NOP 97 NOT 98 OR 99 POP 101 POPC 102 POPM 103 PUSH 104 PUSHA 105 PUSHC 106 PUSHM 107 REIT 108 RMPA 109 ROLC 110 RORC 111

Page No. for

Function

93

Page No. for

Instruction Code

/No. of Cycles

201 201 201 201 201 203 205 207 207 208 209 211 213 213 214 216 216 217 217 218 218 219

Mnemonic

ROT 112 RTS 113 SBB 114 SBJNZ 115 SHA 116 SHL 117 SMOVB 118 SMOVF 119 SSTR 120 STC 121 STCTX 122 STE 123 STNZ 124 STZ 125 STZX 126 SUB 127 TST 129 UND 130 WAIT 131 XCHG 132 XOR 133

Page No. for

Function

Page No. for

Instruction Code

/No. of Cycles

220 221 222 224 225 228 230 231 231 232 233 233 235 235 236 236 239 241 241 242 243

Quick Reference-2

Quick Reference by Function

Function

Transfer

Bit manipulation

Shift

Arithmetic

Mnemonic

MOV Transfer 90 193 MOVA Transfer effective address 92 200 MOVDir Transfer 4-bit data 93 201 POP Restore register/memory 101 211 POPM Restore multiple registers 103 213 PUSH Save register/memory/immediate data 104 214 PUSHA Save effective address 105 216 PUSHM Save multiple registers 107 217 LDE Transfer from extended data area 87 191 STE Transfer to extended data area 123 233 STNZ Conditional transfer 124 235 STZ Conditional transfer 125 235 STZX Conditional transfer 126 236 XCHG Exchange 132 242 BAND Logically AND bits 47 150 BCLR Clear bit 48 150 BM

Cnd

BNAND Logically AND inverted bits 50 153 BNOR Logically OR inverted bits 51 154 BNOT Invert bit 52 154 BNTST Test inverted bit 53 155 BNXOR Exclusive OR inverted bits 54 156 BOR Logically OR bits 55 156 BSET Set bit 57 157 BTST Test bit 58 158 BTSTC Test bit and clear 59 159 BTSTS Test bit and set 60 160 BXOR Exclusive OR bits 61 160 ROLC Rotate left with carry 110 218 RORC Rotate right with carry 111 219 ROT Rotate 112 220 SHA Shift arithmetic 116 215 SHL Shift logical 117 228 ABS Absolute value 39 138 ADC Add with carry 40 138 ADCF Add carry flag 41 140 ADD Add without carry 42 140 CMP Compare 62 161 DADC Decimal add with carry 64 165

Conditional bit transfer 49 152

Description

Page No. for

Function

Page No. for

Instruction Code

/No. of Cycles

Quick Reference-3

Quick Reference by Function

Function

Arithmetic

Logical

Jump

String

Other

Mnemonic

DADD Decimal add without carry 65 167 DEC Decrement 66 169 DIV Signed divide 67 170 DIVU Unsigned divide 68 171 DIVX Signed divide 69 172 DSBB Decimal subtract with borrow 70 173 DSUB Decimal subtract without borrow 71 175 EXTS Extend sign 74 178 INC Increment 77 180 MUL Signed multiply 94 203 MULU Unsigned multiply 95 205 NEG Complement of two 96 207 RMPA Calculate sum-of-products 109 218 SBB Subtract with borrow 114 222 SUB Subtract without borrow 127 236 AND Logical AND 45 147 NOT Invert all bits 98 208 OR Logical OR 99 209 TST Test 129 239 XOR Exclusive OR 133 243 ADJNZ Add and conditional jump 44 146 SBJNZ Subtract and conditional jump 115 224 JCnd Jump on condition 80 182 JMP Unconditional jump 81 184 JMPI Jump indirect 82 185 JSR Subroutine call 83 187 JSRI Indirect subroutine call 84 188 RTS Return from subroutine 113 221 SMOVB Transfer string backward 118 230 SMOVF Transfer string forward 119 231 SSTR Store string 120 231 BRK Debug interrupt 56 157 ENTER Build stack frame 72 177 EXITD Deallocate stack frame 73 178 FCLR Clear flag register bit 75 179 FSET Set flag register bit 76 180 INT Interrupt by INT instruction 78 181 INTO Interrupt on overflow 79 182 LDC Transfer to control register 85 189 LDCTX Restore context 86 189 LDINTB Transfer to INTB register 88 192

Description

Page No. for

Function

Page No. for

Instruction Code

/No. of Cycles

Quick Reference-4

Quick Reference by Function

Function

Other LDIPL Set interrupt enable level 89 193

Mnemonic

NOP No operation 97 207 POPC Restore control register 102 213 PUSHC Save control register 106 216 REIT Return from interrupt 108 216 STC Transfer from control register 121 232 STCTX Save context 122 233 UND Interrupt for undefined instruction 130 241 WAIT Wait 131 241

Description

Page No. for

Function

Page No. for

Instruction Code

/No. of Cycles

Quick Reference-5

Quick Reference by Addressing Mode (General Instruction Addressing)

Mnemonic

ABS ADC ADCF

*1

ADD ADJNZ

*1

AND CMP DADC DADD DEC

R0L/R0

R0H/R1

R1L/R2

R1H/R3

Addressing Mode

An

[An]

dsp:8[An]

dsp:8[SB/FB]

dsp:16[An]

dsp:16[SB]

abs16

#IMM8

#IMM16

#IMM20

Page No. for

Function

#IMM

39 40 41 42 44 45 62 64 65 66

Page No. for

Instruction

Code

/No. of Cycles

138 138 140 140 146 147 161 165 167 169

DIV DIVU DIVX DSBB DSUB ENTER EXTS INC *3

*2

*4

INT

*1

JMPI

*1

JSRI

*1

LDC

*1

LDE LDINTB LDIPL

*1 Has special instruction addressing.

*2 Only R1L can be selected. *3 Only R0L can be selected. *4 Only R0H can be selected.

67 68 69 70 71 72 74 77 78 82 83 85 87 88 89

170 171 172 173 175 177 178 180 181 185 187 189 191 192 193

Quick Reference-6

Quick Reference by Addressing Mode (General Instruction Addressing)

Mnemonic

*1

MOV MOVA MOV

Dir

MUL MULU NEG NOT OR POP

*1

POPM

R0L/R0

R0H/R1

R1L/R2

R1H/R3

Addressing Mode

An

[An]

dsp:8[An]

dsp:8[SB/FB]

dsp:16[An]

dsp:16[SB]

abs16

#IMM8

#IMM16

#IMM20

Page No. for

Function

#IMM

90 92 93 94 95 96 98

99 101 103

Page No. for

Instruction

Code

/No. of Cycles

193 200 201 203 205 207 208 209 211

213 PUSH PUSHA PUSHM

*1

ROLC RORC ROT SBB SBJNZ SHA SHL STC STCTX STE

*1

STNZ STZ

*1 Has special instruction addressing.

104 105 107 110 111 112 114 115 116 117 121 122 123 124 125

214

216

217

218

219

220

222

224

225

228

232

233

235

Quick Reference-7

Quick Reference by Addressing Mode (General Instruction Addressing)

Mnemonic

STZX SUB TST XCHG XOR

R0L/R0

R0H/R1

R1L/R2

R1H/R3

Addressing Mode

An

[An]

dsp:8[An]

dsp:8[SB/FB]

dsp:16[An]

dsp:16[SB]

abs16

#IMM8

#IMM16

#IMM20

Page No. for

Function

#IMM

126 127 129 132 133

Page No. for

Instruction

Code

/No. of Cycles

236 236 239 242 243

Quick Reference-8

Quick Reference by Addressing Mode (Special Instruction Addressing)

Mnemonic

*1

ADD ADJNZ

*1

JCnd JMP

*1

JMPI JSR

*1

JSRI

*1

LDC LDCTX

*1

LDE LDINTB

*1

MOV

dsp:20[A0]

dsp:20[A1]

abs20

Addressing Mode

R2R0/R3R1

A1A0

[A1A0]

dsp:8[SP]

label

SB/FB

ISP/USP

FLG

INTBL/INTBH

*2

Page No. for

Function

PC

42 44 80 81 82 83 84 85 86 87 88 90

Page No. for

Instruction

Code

/No. of Cycles

140 146 182 184 185 187 188 189 189 191 192

193 POPC POPM PUSHC PUSHM SBJNZ

*1

SHA

*1

SHL

*1

STC STCTX

*1

STE

*1

102 103 106 107 115 116 117 121 122 123

*1 Has general instruction addressing. *2 INTBL and INTBH can be set simultaneously when using the LDINTB instruction.

213

216

217

224

225

228

232

233

Quick Reference-9

Quick Reference by Addressing Mode (Bit Instruction Addressing)

Mnemonic

BAND BCLR BM

Cnd

BNAND BNOR BNOT BNTST BNXOR BOR

bit,Rn

Addressing Mode

bit,An

[An]

base:8[An]

bit,base:8[SB/FB]

base:16[An]

bit,base:16[SB]

bit,base:16

Page No. for

Function

bit,base:11

U/I/O/B/S/Z/D/C

47 48 49 50 21 52 53 54 55

Page No. for

Instruction

Code

/No. of Cycles

150 150 152 153 154 154 155 156

156 BSET BTST BTSTC BTSTS BXOR FCLR FSET

57 58 59 60 61 75 76

157

158

159

160

179

180

Quick Reference-10

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Quick Reference-11

Chapter 1

Overview

1.1 Features of R8C/Tiny Series

1.2 Address Space

1.3 Register Configuration

1.4 Flag Register (FLG)

1.5 Register Banks

1.6 Internal State after Reset is Cleared

1.7 Data Types

1.8 Data Arrangement

1.9 Instruction Formats

1.10 Vector Tables

Chapter 1 Overview

1.1 Features of R8C/Tiny Series

The R8C/Tiny Series of single-chip microcomputers was developed for embedded applications. The R8C/Tiny Series supports instructions tailored for the C language, with frequently used instructions implemented in one-byte op-code. It thus allows development of efficient programs with reduced memory requirements when using either assembly language or C. Furthermore, some instructions can be executed in a single clock cycle, enabling fast arithmetic processing.

The instruction set comprises 89 discrete instructions matched to the R8C’s many addressing modes. This powerful instruction set provides support for register-register, register-memory, and memory-memory operations, as well as arithmetic/logic operations using single-bit and 4-bit data. Some R8C/Tiny Series models incorporate an on-chip multiplier, allowing for high-speed computation.

1.1.1 Features of R8C/Tiny Series

●Register configuration

Data registers: Four 16-bit registers (of which two can be used as 8-bit registers) Address registers: Two 16-bit registers Base registers: Two 16-bit registers

●Versatile instruction set

Instructions suited to C language (stack frame manipulation): ENTER, EXITD, etc. Instructions that do not discriminate by register or memory area MOV, ADD, SUB, etc. Powerful bit manipulation instructions: BNOT, BTST, BSET, etc. 4-bit transfer instructions: MOVLL, MOVHL, etc. Frequently used 1-byte instructions: MOV, ADD, SUB, JMP, etc. High-speed 1-cycle instructions: MOV, ADD, SUB, etc.

●Fast instruction execution time

Minimum 1-cycle instructions: Of 89 instructions, 20 are 1-cycle instructions. (Approximately 75% of instructions execute in five cycles or fewer.)

1.1.2 Speed Performance

Register-register transfer 2 cycles Register-memory transfer 2 cycles Register-register addition/subtraction 2 cycles 8 bits x 8 bits register-register operation 4 cycles 16 bits x 16 bits register-register operation 5 cycles 16 bits / 8 bits register-register operation 18 cycles 32 bits / 16 bits register-register operation 25 cycles

Rev.2.00 Oct 17, 2005 page 2 of 263 REJ09B0001-0200

Chapter 1 Overview

1.2 Address Space

Figure 1.2.1 shows the address space. Addresses 0000016 through 002FF16 make up an SFR (special function register) area. In some models in the R8C/Tiny Series, the SFR area extends from 002FF16 to lower addresses. Addresses from 0040016 and below make up the memory area. In some models in the R8C/Tiny Series, the RAM area extends from address 0040016 to higher addresses, and the ROM area extends from 0FFFF16 to lower addresses. Addresses 0FFDC16 through 0FFFF16 make up a fixed vector area.

0000016

002FF16

0040016

0FFDC16 0FFFF16

SFR area

Internal RAM area

Internal ROM area

Fixed vector area

The SFR area of some models extends to lower-address locations.

The RAM area of some models extends to higher-address locations.

The ROM area of some models extends to lower-address locations.

FFFFF16

Figure 1.2.1 Address Space

Rev.2.00 Oct 17, 2005 page 3 of 263 REJ09B0001-0200

Extention area

Chapter 1 Overview

A

1.3 Register Configuration

The central processing unit (CPU) contains the 13 registers shown in figure 1.3.1. Of these registers, R0, R1, R2, R3, A0, A1, and FB each consist of two sets of registers configured as two register banks.

b31

R2 R3

b15

R0H (High-order of R0) R1H (High-order of R1)

b19

b15

INTBH INTBH is the upper 4 bits of INTB.

INTBL is the lower 16 bits of INTB.

b19

b15

IPL

b8 b7 b0

R0L (Low-order of R0) R1L (Low-order of R1)

R2 R3

A0 A1

FB

INTBL

PC

USP ISP SB

FLG

b7 b8

Data register*

Address register*

Frame base register*

b0

Interrupt table register

b0

Program counter

b0

User stack pointer Interrupt stack pointer

Static base register

b0

Flag register

b0

CDZSBOIU

Carry flag Debug flag

Zero flag Sign flag

Register bank select flag Overflow flag Interrupt enable flag

Stack pointer select flag Reserved area

Processor interrupt priority level Reserved area

Note: * These registers configure register banks.This register

bank consists of two sets.

Figure 1.3.1 CPU Register Configuration

1.3.1 Data Registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)

The data registers (R0, R1, R2, and R3) each consist of 16 bits and are used primarily for transfers and arithmetic/logic operations. Registers R0 and R1 can be divided into separate high-order (R0H, R1H) and low-order (R0L, R1L) parts for use as 8-bit data registers. For some instructions, moreover, R2 and R0 or R3 and R1 can be combined to configure a 32-bit data register (R2R0 or R3R1).

Rev.2.00 Oct 17, 2005 page 4 of 263 REJ09B0001-0200

Chapter 1 Overview

1.3 Register Configuration

1.3.2 Address Registers (A0 and A1)

The address registers (A0 and A1) are 16-bit registers with functions similar to those of the data registers. These registers are used for address register-based indirect addressing and address registerbased relative addressing. For some instructions, registers A1 and A0 can be combined to configure a 32-bit address register (A1A0).

1.3.3 Frame Base Register (FB)

The frame base register (FB) is a 16-bit register used for FB-based relative addressing.

1.3.4 Program Counter (PC)

The program counter (PC) is a 20-bit register that indicates the address of the instruction to be executed next.

1.3.5 Interrupt Table Register (INTB)

The interrupt table register (INTB) is a 20-bit register that indicates the initial address of the interrupt vector table.

1.3.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

There are two types of stack pointers: a user stack pointer (USP) and an interrupt stack pointer (ISP). Each consists of 16 bits. The stack pointer (USP/ISP) to be used can be switched with the stack pointer select flag (U flag). The stack pointer select flag (U flag) is bit 7 of the flag register (FLG).

1.3.7 Static Base Register (SB)

The static base register (SB) is a 16-bit register used for SB-based relative addressing.

1.3.8 Flag Register (FLG)

The flag register (FLG) is an 11-bit register used as flags in one-bit units. For details on the functions of the flags, see Section 1.4, “Flag Register (FLG).”

Rev.2.00 Oct 17, 2005 page 5 of 263 REJ09B0001-0200

Chapter 1 Overview

1.4 Flag Register (FLG)

Figure 1.4.1 shows the configuration of the flag register (FLG). The function of each flag is described below.

1.4.1 Bit 0: Carry Flag (C Flag)

This flag holds bits carried, borrowed, or shifted-out by the arithmetic/logic unit.

1.4.2 Bit 1: Debug Flag (D Flag)

This flag enables a single-step interrupt. When this flag is set to 1, a single-step interrupt is generated after an instruction is executed. When the interrupt is acknowledged, the flag is cleared to 0.

1.4.3 Bit 2: Zero Flag (Z Flag)

This flag is set to 1 when an arithmetic operation results in 0; otherwise, its value is 0.

1.4.4 Bit 3: Sign Flag (S Flag)

This flag is set to 1 when an arithmetic operation results in a negative value; otherwise, its value is 0.

1.4.5 Bit 4: Register Bank Select Flag (B Flag)

This flag selects a register bank. If it is set to 0, register bank 0 is selected; if it is set to 1, register bank 1 is selected.

1.4.6 Bit 5: Overflow Flag (O Flag)

This flag is set to 1 when an arithmetic operation results in an overflow.

1.4.7 Bit 6: Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt. When this flag is set to 0, the interrupt is disabled; when it is set to 1, the interrupt is enabled. When the interrupt is acknowledged, the flag is cleared to 0.

1.4.8 Bit 7: Stack Pointer Select Flag (U Flag)

When this flag is set to 0, the interrupt stack pointer (ISP) is selected; when it is set to 1, the user stack pointer (USP) is selected. This flag is cleared to 0 when a hardware interrupt is acknowledged or an INT instruction is executed for software interrupt numbers 0 to 31.

1.4.9 Bits 8 to 11: Reserved

Rev.2.00 Oct 17, 2005 page 6 of 263 REJ09B0001-0200

Chapter 1 Overview

1.4 Flag Register (FLG)

1.4.10 Bits 12 to 14: Processor Interrupt Priority Level (IPL)

The processor interrupt priority level (IPL) consists of three bits, enabling specification of eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt’s priority level is higher than the processor interrupt priority level (IPL), the interrupt is enabled.

1.4.11 Bit 15: Reserved

b15 b0

IPL U I O B S Z D C

Flag register (FLG)

Carry flag Debug flag Zero flag Sign flag

Figure 1.4.1 Configuration of Flag Register (FLG)

Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area

Rev.2.00 Oct 17, 2005 page 7 of 263 REJ09B0001-0200

Chapter 1 Overview

1.5 Register Banks

The R8C/Tiny has two register banks, each comprising data registers (R0, R1, R2, and R3), address registers (A0 and A1), and a frame base register (FB). These two register banks are switched by the register bank select flag (B flag) in the flag register (FLG). Figure 1.5.1 shows the configuration of the register banks.

Register bank 0 (B flag = 0) Register bank 1 (B flag = 1)

b15 b8b7 b0

R0 H L R1 H L R2 R3 A0 A1 FB

Figure 1.5.1 Configuration of Register Banks

b15 b8b7 b0

R0 H L R1 H L R2 R3 A0 A1 FB

Rev.2.00 Oct 17, 2005 page 8 of 263 REJ09B0001-0200

Chapter 1 Overview

1.6 Internal State after Reset is Cleared

The contents of each register after a reset is cleared are as follows.

• Data registers (R0, R1, R2, and R3): 000016

• Address registers (A0 and A1): 000016

• Frame base register (FB): 000016

• Interrupt table register (INTB): 0000016

• User stack pointer (USP): 000016

• Interrupt stack pointer (ISP): 000016

• Static base register (SB): 000016

• Flag register (FLG): 000016

1.6 Internal State after Reset is Cleared

Rev.2.00 Oct 17, 2005 page 9 of 263 REJ09B0001-0200

Chapter 1 Overview

1.7 Data Types

There are four data types: integer, decimal, bit, and string.

1.7.1 Integer

An integer can be signed or unsigned. A negative value of a signed integer is represented by two’s complement.

b7 b0

Signed byte (8 bit) integer

Unsigned byte (8 bit) integer

Signed word (16 bit) integer

Unsigned word (16 bit) integer

Signed long word (32 bit) integer

Unsigned long word (32 bit) integer

b15 b0

S

b15 b0

b31 b0

S

b31 b0

S

b7 b0

S: Sign bit

Figure 1.7.1 Integer Data

Rev.2.00 Oct 17, 2005 page 10 of 263 REJ09B0001-0200

Chapter 1 Overview

1.7.2 Decimal

The decimal data type is used by the DADC, DADD, DSBB, and DSUB instructions.

1.7 Data Types

Pack format (2 digits) Pack format (4 digits)

Figure 1.7.2 Decimal Data

b7 b0

b15 b0

Rev.2.00 Oct 17, 2005 page 11 of 263 REJ09B0001-0200

Chapter 1 Overview

1.7 Data Types

1.7.3 Bits

●Register bits

Figure 1.7.3 shows register bit specification. Register bits can be specified by register directly (bit, Rn or bit, An). Use bit, Rn to specify a bit in a data register (Rn); use bit, An to specify a bit in an address register (An). The bits in each register are assigned bit numbers from 0 to 15, from LSB to MSB. Therefore, bit, Rn and bit, An can be used to specify a bit number from 0 to 15.

b15 b0

bit,Rn (bit: 0 to 15, n: 0 to 3)

Rn

b15 b0

bit,An (bit: 0 to 15, n: 0 to 1)

An

Figure 1.7.3 Register Bit Specification

●Memory bits

Figure 1.7.4 shows the addressing modes used for memory bit specification. Table 1.7.1 lists the address range in which bits can be specified in each addressing mode. Be sure to observe the address range in Table 1.7.1 when specifying memory bits.

Addressing modes

Absolute addressing

SB-based relative addressing

FB-based relative addressing

Address register-based indirect addressing

Address register-based relative addressing

bit,base:8

bit,base:16

bit,base:8[SB] bit,base:11[SB] bit,base:16[SB]

bit,base:8[FB]

[An]

base:8[An] base:16[An]

Figure 1.7.4 Addressing Modes Used for Memory Bit Specification

Table 1.7.1 Bit Specification Address Range

Addressing Specification range

Lower Limit (Address) Upper Limit (Address)

Remarks

bit,base:16 0000016 01FFF16 bit,base:8[SB] [SB] [SB]+0001F16 The access range is 0000016 to 0FFFF16. bit,base:11[SB] [SB] [SB]+000FF16 The access range is 0000016 to 0FFFF16. bit,base:16[SB] [SB] [SB]+01FFF16 The access range is 0000016 to 0FFFF16. bit,base:8[FB] [FB]–0001016 [FB]+0000F16 The access range is 0000016 to 0FFFF16. [An] 0000016 01FFF16 base:8[An] base:8 base:8+01FFF16 The access range is 0000016 to 020FE16. base:16[An] base:16 base:16+01FFF16 The access range is 0000016 to 0FFFF16.

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Chapter 1 Overview

1.7 Data Types

(1) Bit Specification by Bit, Base

Figure 1.7.5 shows the relationship between the memory map and the bit map. Memory bits can be handled as an array of consecutive bits. Bits can be specified by a combination of bit and base. Using bit 0 of the address that is set in base as the reference (= 0), set the desired bit position in bit. Figure 1.7.6 shows examples of how to specify bit 2 of address 0000A16.

Address

b7 b0

0

n-1

n

n+1

nÅ{1 n nÅ|1 0

n+1 n n–1

b7 b0b7 b0b7 b0 b7 b0

Memory map

Bit map

Figure 1.7.5 Relationship between Memory Map and Bit Map

Address 0000A16

b7 b2 b0

BSET 2,AH ;

Address 0000916

b15 b10 b8b7 b0

BSET 10,9H ;

Address 0000816

b23 b18 b16b15 b8b7 b0

BSET 18,8H ;

b87 b82 b80b79 b72 b7 b0

BSET 82,0H ;

Address 00000

16

These specification examples all specify bit 2 of address 0000A

16.

Figure 1.7.6 Examples of How to Specify Bit 2 of Address 0000A16

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Chapter 1 Overview

1.7 Data Types

(2) SB/FB Relative Bit Specification

For SB/FB-based relative addressing, use bit 0 of the address that is the sum of the address set in static base register (SB) or frame base register (FB) plus the address set in base as the reference (= 0), and set the desired bit position in bit.

(3) Address Register Indirect/Relative Bit Specification

For address register-based indirect addressing, use bit 0 of address 0000016 as the reference (= 0) and set the desired bit position in the address register (An). For address register-based relative addressing, use bit 0 of the address set in base as the reference (= 0) and set the desired bit position in the address register (An).

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Chapter 1 Overview

1.7 Data Types

1.7.4 String

String data consists of a given length of consecutive byte (8-bit) or word (16-bit) data. This data type can be used in three string instructions: character string backward transfer (SMOVB instruction), character string forward transfer (SMOVF instruction), and specified area initialize (SSTR instruction).

Byte (8-bit) data Word (16-bit) data

b7 b0

Figure 1.7.7 String Data

b15 b0

•

b15 b0

•

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Chapter 1 Overview

1.8 Data Arrangement

1.8.1 Data Arrangement in Register

Figure 1.8.1 shows the relationship between a register’s data size and bit numbers.

Nibble (4-bit) data

Byte (8-bit) data

b15 b0

Word (16-bit) data

b31 b0

Long word (32-bit) data

MSB LSB

1.8 Data Arrangement

b3 b0

b7 b0

Figure 1.8.1 Data Arrangement in Register

Rev.2.00 Oct 17, 2005 page 16 of 263 REJ09B0001-0200

Chapter 1 Overview

1.8 Data Arrangement

1.8.2 Data Arrangement in Memory

Figure 1.8.2 shows the data arrangement in memory. Figure 1.8.3 shows some operation examples.

b7 b0

N DATA N+1 N+2 N+3

Byte (8-bit) data

b7 b0

N DATA(L) N+1 DATA(M) N+2 DATA(H) N+3

20-bit (Address) data

Figure 1.8.2 Data Arrangement in Memory

b7 b0

N DATA(L) N+1 DATA(H) N+2 N+3

Word (16-bit) data

b7 b0

N DATA(LL) N+1 DATA(LH) N+2 DATA(HL) N+3 DATA(HH)

Long Word (32-bit) data

MOV.B N,R0H

b7 b0

N DATA N+1 N+2 N+3

Byte (8-bit) data

MOV.W N,R0

b7 b0

N DATA(L) N+1 DATA(H) N+2 N+3

Word (16-bit) data

Figure 1.8.3 Operation Examples

R0

Does not change.

b15 b0

DATA

HL

b15 b0

DATA(H) DATA(L)

HL

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Chapter 1 Overview

1.9 Instruction Formats

The instruction formats can be classified into four types: generic, quick, short, and zero. The number of instruction bytes that can be chosen by a given format is least for the zero format, and increases successively for the short, quick, and generic formats, in that order. The features of each format are described below.

1.9.1 Generic Format (:G)

The op-code in this format comprises two bytes. This op-code contains information on the operation and the src*1 and dest*2 addressing modes. The instruction code is composed of op-code (2 bytes), src code (0 to 3 bytes), and dest code (0 to 3 bytes).

1.9.2 Quick Format (:Q)

The op-code in this format comprises two bytes. This op-code contains information on the operation and the immediate data and dest addressing modes. Note, however, that the immediate data in the opcode is a numeric value that can be expressed as -7 to +8 or -8 to +7 (depending on the instruction). The instruction code is composed of op-code (2 bytes) containing immediate data and dest code (0 to 2 bytes).

1.9.3 Short Format (:S)

The op-code in this format comprises one byte. This op-code contains information on the operation and the src and dest addressing modes. Note, however, that the usable addressing modes are limited. The instruction code is composed of op-code (1 byte), src code (0 to 2 bytes), and dest code (0 to 2 bytes).

1.9.4 Zero Format (:Z)

The op-code in this format comprises one byte. This op-code contains information on the operation (plus immediate data) and dest addressing modes. Note, however, that the immediate data is fixed at 0, and that the usable addressing modes are limited. The instruction code is composed of op-code (1 byte) and dest code (0 to 2 bytes).

*1 src is an abbreviation of “source.” *2 dest is an abbreviation of “destination.”

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Chapter 1 Overview

1.10 Vector Tables

Interrupt vector tables are the only vector tables. There are two types of interrupt vector tables: fixed and variable.

1.10.1 Fixed Vector Tables

A fixed vector table is an address-fixed vector table. Part of the interrupt vector table is allocated to addresses 0FFDC16 through 0FFFF16. Figure 1.10.1 shows a fixed vector table. Interrupt vector tables are composed of four bytes per table. Each vector table must contain the interrupt handler routine’s entry address.

0FFDC16

Interrupt vector table

0FFFF16

Figure 1.10.1 Fixed Vector Table

FFFDC16 FFFE016 FFFE416 FFFE816 FFFEC16 FFFF016 FFFF416

FFFF816 FFFFC16

Undefined instruction Overflow

BRK instruction Address match

Single step

Oscillation stop detection/

watchdog timer

(Reserved) (Reserved)

Reset

Rev.2.00 Oct 17, 2005 page 19 of 263 REJ09B0001-0200

Chapter 1 Overview

1.10 Vector Tables

1.10.2 Variable Vector Tables

A variable vector table is an address-variable vector table. Specifically, this type of vector table is a 256byte interrupt vector table that uses the value indicated by the interrupt table register (INTB) as the entry address (IntBase). Figure 1.10.2 shows a variable vector table. Variable vector tables are composed of four bytes per table. Each vector table must contain the interrupt handler routine’s entry address. Each vector table has software interrupt numbers (0 to 63), which are used by the INT instruction. Interrupts for the on-chip peripheral functions of each M16C model are allocated to software interrupt numbers 0 through 31.

b19 b0

INTB IntBase

IntBase+4 IntBase+8

IntBase+252

Figure 1.10.2 Variable Vector Table

0 1

31 32 33

63





         

Vectors accommodat-





ing peripheral I/O



interrupts





Software interrupt numbers

      

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Addressing Modes

2.1 Addressing Modes

2.2 Guide to This Chapter

2.3 General Instruction Addressing

2.4 Special Instruction Addressing

2.5 Bit Instruction Addressing

Chapter 2

Chapter 2 Addressing Modes

2.1 Addressing Modes

This section describes the symbols used to represent addressing modes and operations of each addressing mode. The R8C/Tiny Series has three types of addressing modes as outlined below.

2.1.1 General Instruction Addressing

This addressing mode type accesses the area from address 0000016 through address 0FFFF16. The names of the general instruction addressing modes are as follows:

• Immediate

• Register direct

• Absolute

• Address register indirect

• Address register relative

• SB relative

• FB relative

• Stack pointer relative

2.1.2 Special Instruction Addressing

This addressing mode type accesses the area from address 0000016 through address FFFFF16 and the control registers. The names of the specific instruction addressing modes are as follows:

• 20-bit absolute

• Address register relative with 20-bit displacement

• 32-bit address register indirect

• 32-bit register direct

• Control register direct

• Program counter relative

2.1.3 Bit Instruction Addressing

This addressing mode type accesses the area from address 0000016 through address 0FFFF16. The names of the bit instruction addressing modes are as follows:

• Register direct

• Absolute

• Address register indirect

• Address register relative

• SB relative

• FB relative

• FLG direct

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Chapter 2 Addressing Modes

2.2 Guide to This Chapter

An example illustrating how to read this chapter is shown below.

(1)

Address register relative

2.2 Guide to This Chapter

The value indicated by the displacement (dsp) plus the content of the address register (A0/A1)—added without the sign bits—is the effective address for the operation.

However, if the addition results in a value exceeding 0FFFF16, bits 17 and above are ignored, and the address returns to 0000016.

(2)

(3)

(4)

dsp:8[A0] dsp:8[A1] dsp:16[A0] dsp:16[A1]

(1) Name

The name of the addressing mode.

(2) Symbol

The symbol representing the addressing mode.

A0 / A1

Register

address

Memory

dsp

(3) Description

A description of the addressing operation and the effective address range.

(4) Operation diagram

A diagram illustrating the addressing operation.

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Chapter 2 Addressing Modes

2.3 General Instruction Addressing

Immediate

#IMM #IMM8 #IMM16 #IMM20

Register direct

R0L R0H R1L R1H R0 R1 R2 R3 A0 A1

The immediate data indicated by #IMM is the object of the operation.

The specified register is the object of the operation.

2.3 General Instruction Addressing

#IMM8

#IMM16

b19

#IMM20

R0L / R1L

R0H / R1H

R0 / R1 / R2 / R3 / A0 / A1

b15

Register

b15 b8

b15

b8

b7

b0

Absolute

abs16

The value indicated by abs16 is the effective address for the operation.

The effective address range is 0000016 to 0FFFF16.

Address register indirect

[A0] [A1]

The value indicated by the content of the address register (A0/A1) is the effective address for the operation.

The effective address range is 0000016 to 0FFFF16.

A0 / A1

abs16

Register

Memory

address

Rev.2.00 Oct 17, 2005 page 24 of 263 REJ09B0001-0200

Chapter 2 Addressing Modes

Address register relative

2.3 General Instruction Addressing

dsp:8[A0] dsp:8[A1] dsp:16[A0] dsp:16[A1]

SB relative

dsp:8[SB] dsp:16[SB]

The value indicated by the displacement (dsp) plus the content of the address register (A0/A1)—added without the sign bits—is the effective address for the operation.

However, if the addition results in a value exceeding 0FFFF16, bits 17 and above are ignored, and the address returns to 0000016.

The address indicated by the content of the static base register (SB) plus the value indicated by the displacement (dsp)—added without the sign bits—is the effective address for the operation.

However, if the addition results in a value exceeding 0FFFF16, bits 17 and above are ignored, and the address returns to 0000016.

A0 / A1

SB

Register

address

Register

address

Memory

dsp

Memory

address

dsp

FB relative

dsp:8[FB]

Rev.2.00 Oct 17, 2005 page 25 of 263 REJ09B0001-0200

The address indicated by the content of the frame base register (FB) plus the value indicated by the displacement (dsp)—added including the sign bits—is the effective address for the operation.

However, if the addition results in a value outside the range 0000016 to 0FFFF16, bits 17 and above are ignored, and the address returns to 0000016 or 0FFFF16.

If the dsp value is negative

dsp

Register

FB

address

If the dsp value is positive

address

dsp

Memory

Chapter 2 Addressing Modes

Stack pointer relative

2.3 General Instruction Addressing

dsp:8[SP]

The address indicated by the content of the stack pointer (SP) plus the value indicated by

If the dsp value is negative the displacement (dsp)—added including the sign bits—is the effective address for the operation. The stack pointer (SP) here is the one indicated by the U flag.

However, if the addition results in a value outside the range 00000

16 to 0FFFF16, bits

SP

17 and above are ignored, and the address returns to 0000016 or 0FFFF16.

This addressing mode can be used with the MOV instruction.

If the dsp value is positive

Memory

dsp

Register

address

dsp

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Chapter 2 Addressing Modes

2.4 Special Instruction Addressing

20-bit absolute

2.4 Special Instruction Addressing

abs20

The value indicated by abs20 is the effective address for the operation.

The effective address range is 0000016 to FFFFF16.

This addressing mode can be used with the LDE, STE, JSR, and JMP instructions.

Address register relative with 20-bit displacement

dsp:20[A0] dsp:20[A1]

The address indicated by the displacement (dsp) plus the content of the address register (A0/A1)—added without the sign bits—is the effective address for the operation.

However, if the addition results in a value exceeding FFFFF

16, bits 21 and above are

ignored, and the address returns to

0000016. This addressing mode can be used with

the LDE, STE, JMPI, and JSRI instructions.

abs20

LDE, STE instructions

Register

A0

address

JMPI, JSRI instructions

Register

A0 / A1

address

Memory

dsp

Memory

dsp

Valid addressing mode and instruction combinations are as follows.

dsp: 20[A0]

LDE, STE, JMPI, and JSRI instructions

dsp: 20[A1]

JMPI and JSRI instructions

32-bit address register indirect

[A1A0]

The address indicated by the 32 concatenated bits of the address registers (A0 and A1) is the effective address for the operation.

However, if the concatenated register value exceeds FFFFF16, bits 21 and above are ignored.

This addressing mode can be used with the LDE and STE instructions.

A1

b31

address-H

PC

Register

b16 b15 b0

address-L

A0

Memory

address

Rev.2.00 Oct 17, 2005 page 27 of 263 REJ09B0001-0200

Chapter 2 Addressing Modes

32-bit register direct

R2R0 R3R1 A1A0

The 32-bit concatenated register content of two specified registers is the object of the operation.

This addressing mode can be used with the SHL, SHA, JMPI, and JSRI instructions.

Valid register and instruction combinations are as follows.

2.4 Special Instruction Addressing

SHL, SHA instructions

R2R0

b31

R3R1

JMPI, JSRI instructions

b15b16

b0

R2R0, R3R1

A1A0

JMPI and JSRI instructions

Control register direct

INTBL

The specified control register is the object of the operation.

INTBH ISP SP

This addressing mode can be used with the LDC, STC, PUSHC, and POPC instructions.

SB FB FLG

If SP is specified, the stack pointer indicated by the U flag is the object of the operation.

SHL, SHA, JMPI, and JSRI instructions

R2R0 R3R1 A1A0

INTBL

INTBH

ISP

USP

b31

PC

b15

b16

Register

b15

b4

b3

b0

Rev.2.00 Oct 17, 2005 page 28 of 263 REJ09B0001-0200

SB

FB

FLG

b15

b0

Chapter 2 Addressing Modes

Program counter relative

2.4 Special Instruction Addressing

label

• If the jump length specifier (.length) is (.S), the base address plus the value indicated by the displacement (dsp)—added without the sign bits—is the effective address.

This addressing mode can be used with the JMP instruction.

• If the jump length specifier (.length) is (.B) or (.W), the base address plus the value indicated by the displacement (dsp)—added including the sign bits—is the effective address.

However, if the addition results in a value outside the range 0000016 to FFFFF16, bits 21 and above are ignored, and the address returns to 0000016 or FFFFF16.

Memory

Base address

dsp

label

+0 dsp +7

*1 The base address is (start address of instruction + 2).

Memory

If the dsp value is negative

dsp

Base address

dsp

label

This addressing mode can be used with the JMP and JSR instructions.

If the dsp value is positive

label

If the specifier is (.B), -128 dsp +127 If the specifier is (.W), -32768 dsp +32767

*2 The base address varies depending on the instruction.

Rev.2.00 Oct 17, 2005 page 29 of 263 REJ09B0001-0200

Chapter 2 Addressing Modes

2.5 Bit Instruction Addressing

2.5. Bit Instruction Addressing

This addressing mode type can be used with the following instructions: BCLR, BSET, BNOT, BTST, BNTST, BAND, BNAND, BOR, BNOR, BXOR, BNXOR, BM

Register direct

Cnd

, BTSTS, BTSTC

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1

Absolute

bit,base:16

The specified register bit is the object of the operation.

A value of 0 to 15 may be specified as the bit position (bit).

The bit that is the number of bits indicated by bit away from bit 0 at the address indicated by base is the object of the operation.

Bits at addresses 0000016 through 01FFF16 can be the object of the operation.

bit,R0

b15

base

R0

Bit position

b7

b0

Address register indirect

[A0] [A1]

Rev.2.00 Oct 17, 2005 page 30 of 263 REJ09B0001-0200

The bit that is the number of bits indicated by the address register (A0/ A1) away from bit 0 at address 0000016 is the object of the operation.

Bits at addresses 0000016 through 01FFF16 can be the object of the operation.

0000016

Bit position

b7

Bit position

b0

Chapter 2 Addressing Modes

Address register relative

2.5 Bit Instruction Addressing

base:8[A0] base:8[A1] base:16[A0] base:16[A1]

The bit that is the number of bits indicated by the address register (A0/A1) away from bit 0 at the address indicated by base is the object of the operation.

However, if the address of the bit that is the object of the operation exceeds 0FFFF16, bits 17 and above are ignored and the address returns to 0000016.

The address range that can be specified by the address register (A0/A1) extends 8,192 bytes from base.

base

b7

Bit position

b0

SB relative

bit,base:8[SB] bit,base:11[SB] bit,base:16[SB]

The bit that is the number of bits indicated by bit away from bit 0 at the address indicated by the static base register (SB) plus the value indicated by base (added without the sign bits) is the object of the operation.

However, if the address of the bit that is the object of the operation exceeds 0FFFF16, bits 17 and above are ignored and the address returns to 0000016.

The address ranges that can be specified by bit,base:8, bit,base:11, and bit,base:16, respectively, extend 32 bytes, 256 bytes, and 8,192 bytes from the static base register (SB) value.

SB

Register

address

base

address

Memory

b7

Bit position

b0

Rev.2.00 Oct 17, 2005 page 31 of 263 REJ09B0001-0200

Chapter 2 Addressing Modes

FB relative

2.5 Bit Instruction Addressing

bit,base:8[FB]

The bit that is the number of bits indicated by bit away from bit 0 at the address indicated by the frame base register (FB) plus the value indicated by base (added including the sign bit) is the object of the operation.

However, if the address of the bit that is the object of the operation is outside the range 0000016 to 0FFFF16, bits 17 and above are ignored and the address returns to 0000016 or 0FFFF16.

The address range that can be specified by bit, base:8 extends 16 bytes toward lower addresses or 15 bytes toward higher addresses from the frame base register (FB) value.

If the base value is negative

FB

If the base value is positive

Register

address

Memory

(Bit position)

base

address

base

Bit position

FLG direct

U I O B S Z D C

The specified flag is the object of the operation.

This addressing mode can be used with the FCLR and FSET instructions.

Register

FLG

UI OBS ZDC

b0b7

Rev.2.00 Oct 17, 2005 page 32 of 263 REJ09B0001-0200

3.1 Guide to This Chapter

3.2 Functions

Chapter 3

Functions

Chapter 3 Functions

3.1 Guide to This Chapter

In this chapter each instruction’s syntax, operation, function, selectable src/dest, and flag changes are listed, and description examples and related instructions are shown. An example illustrating how to read this chapter is shown below.

(1) (2)

(3)

(4)

(5)

(6)

Chapter 3 Functions

3.2 Functions

MOV

[ Syntax ]

MOV.size (:format) src,dest

[ Operation ]

Transfer

MOVe

G , Q , Z , S (Can be specified) B , W

[ Instruction Code/Number of Cycles ]

dest src

[ Function ]

• This instruction transfers

• If

dest

is A0 or A1 and the selected size specifier (.size) is (.B),

transfer data in 16 bits. If

[ Selectable

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 dsp:8[SP] R2R0 R3R1 A1A0 dsp:8[SP]

src/dest

]

src dest

src

to

dest

.

src

is zero-expanded to

src

is A0 or A1, the 8 low-order bits of A0 or A1 are transferred.

(See next page for src/dest classified by format.)

MOV

Page: 193

(7)

(8)

(9)

Rev.2.00 Oct 17, 2005 page 34 of 263 REJ09B0001-0200

[ Flag Change ]

Flag Change

Conditions

[ Related Instruction]

UI OBSZDC

S : The flag is set when the transfer results in MSB of dest = 1; otherwise cleared. Z : The flag is set when the transfer results in 0; otherwise cleared.

[ Description Example ]

MOV.B:S #0ABH,R0L MOV.W #-1,R2

LDE, STE, XCHG

90

Chapter 3 Functions

3.1 Guide to This Chapter

(1) Mnemonic

The mnemonic explained in the page.

(2) Instruction Code/Number of Cycles

The page on which the instruction code and number of cycles is listed. Refer to this page for information on the instruction code and number of cycles.

(3) Syntax

The syntax of the instruction using symbols. If (:format) is omitted, the assembler chooses the optimum specifier.

MOV.size (: format) src , dest

G , Q , S , Z (f) B , W (e)

(a) (b) (c) (d)

(a) Mnemonic MOV

Shows the mnemonic.

(b) Size specifier .size

Shows the data sizes in which data is handled. The following data sizes may be specified:

.B Byte (8 bits) .W Word (16 bits) .L Long word (32 bits) Some instructions do not have a size specifier.

(c) Instruction format specifier (: format)

Shows the instruction format. If (: format) is omitted, the assembler chooses the optimum specifier. If (: format) is entered, its content is given priority. The following instruction formats may be specified:

:G Generic format :Q Quick format :S Short format :Z Zero format Some instructions do not have an instruction format specifier.

(d) Operands src, dest

Shows the operands.

(e) Shows the data sizes that can be specified in (b).

(f) Shows the instruction formats that can be specified in (c).

Rev.2.00 Oct 17, 2005 page 35 of 263 REJ09B0001-0200

Chapter 3 Functions

3.1 Guide to This Chapter

(1) (2)

(3)

(4)

(5)

(6)

Chapter 3 Functions

3.2 Functions

MOV

[ Syntax ]

MOV.size (:format) src,dest

[ Operation ]

Transfer

MOVe

G , Q , Z , S (Can be specified) B , W

[ Instruction Code/Number of Cycles ]

dest src

[ Function ]

src

to

dest

• This instruction transfers

• If

dest

is A0 or A1 and the selected size specifier (.size) is (.B),

data in 16 bits. If

[ Selectable

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 dsp:8[SP] R2R0 R3R1 A1A0 dsp:8[SP]

src/dest

src

is A0 or A1, the 8 low-order bits of A0 or A1 are transferred.

]

src dest

.

src

is zero-expanded to transfer

(See next page for src/dest classified by format.)

MOV

Page: 193

(7)

(8)

(9)

Rev.2.00 Oct 17, 2005 page 36 of 263 REJ09B0001-0200

[ Flag Change ]

Flag

Change

Conditions

UI OBSZDC

S : The flag is set when the transfer results in MSB of dest = 1; otherwise cleared. Z : The flag is set when the transfer results in 0; otherwise cleared.

[ Description Example ]

MOV.B:S #0ABH,R0L MOV.W #-1,R2

[ Related Instruction] LDE, STE, XCHG

90

Chapter 3 Functions

3.1 Guide to This Chapter

(4) Operation

Explains the operation of the instruction using symbols.

(5) Function

Explains the function of the instruction and precautions to be taken when using the instruction.

(6) Selectable

If the instruction has operands, the valid formats are listed here.

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 dsp:8[SP] R2R0 R3R1 A1A0 dsp:8[SP]

(a) Items that can be selected as

(b) Items that can be selected as

(c) Addressing modes that can be selected

(d) Addressing modes that cannot be selected

src

/

dest

(label)

src dest

src

(source)

dest

(destination)

(a)

(b)

(c)

(d)

(e)

Shown on the left side of the slash (R0H) is the addressing mode when data is handled in bytes (8 bits). Shown on the right side of the slash (R1) is the addressing mode when data is handled in words (16 bits).

(7) Flag change

Shows a flag change that occurs after the instruction is executed. The symbols in the table mean the following.

“—” The flag does not change. “O” The flag changes depending on a condition.

(8) Description example

Description examples for the instruction.

(9) Related instructions

Related instructions that cause an operation similar or opposite to that of the instruction.

Rev.2.00 Oct 17, 2005 page 37 of 263 REJ09B0001-0200

Chapter 3 Functions

The syntax of the jump instructions JMP, JPMI, JSR, and JSRI are illustrated below by example .

3.1 Guide to This Chapter

Chapter 3 Functions

(1) (2)

(3)

JMP

[ Syntax ] JMP (.length) label

(3) Syntax

Indicates the instruction syntax using symbols.

JMP (.length) label

(a) (b) (c)

(a) Mnemonic JMP

Shows the mnemonic.

Unconditional jump

JuMP

S, B, W, A (Can be specified)

S, B, W, A

(d)

3.2 Functions

JMP

[ Instruction Code/Number of Cycles ]

Page: 183

(b) Jump distance specifier .length

Shows the distance of the jump. If (.length) is omitted from the JMP or JSR instruction, the assembler chooses the optimum specifier. If (.length) is entered, its content is given priority. The following jump distances may be specified:

.S 3-bit PC forward relative (+2 to +9) .B 8-bit PC relative .W 16-bit PC relative .A 20-bit absolute

(c) Operand label

Shows the operand.

(d) Shows the jump distances that can be specified in (b).

Rev.2.00 Oct 17, 2005 page 38 of 263 REJ09B0001-0200

Chapter 3 Functions

ABS

Absolute value

ABSolute

3.2 Functions

ABS

[ Syntax ]

ABS.size dest

[ Operation ]

dest dest

[ Function ]

• This instruction takes the absolute value of

[ Selectable dest

]

B , W

[ Instruction Code/Number of Cycles ]

dest

and stores it in

R0L/R0 R0H/R1 R1L/R2 R1H/R3

A0/A0 A1/A1 [A0] [A1]

dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0

dest

.

dest

Page: 138

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

Rev.2.00 Oct 17, 2005 page 39 of 263 REJ09B0001-0200

UIOBSZDC

O:

The flag is set (= 1) when dest before the operation is –128 (.B) or –32768 (.W); otherwise cleared (= 0). S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared. C : The flag value is undefined.

ABS.B R0L ABS.W A0

Chapter 3 Functions

Add with carry

ADdition with Carry

3.2 Functions

ADCADC

[ Syntax ]

ADC.size src,dest

B , W

[ Operation ]

dest src + dest + C

[ Function ]

• This instruction adds

• If

dest

is A0 or A1 and the selected size specifier (.size) is (.B), calculation in 16 bits. If A1.

[ Selectable src/dest ]

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3

*1

A0/A0 dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

A1/A1

*1

dest, src

src dest

[A0] [A1] A0/A0

, and the C flag and stores the result in

src

is A0 or A1, the operation is performed on the eight low-order bits of A0 or

*1

[ Instruction Code/Number of Cycles ]

dest

.

src

is zero-expanded to perform

*1

A1/A1

[A0] [A1]

Page: 138

*1 If (.B) is selected as the size specifier (.size), A0 or A1 cannot be chosen for

neously.

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

UIOBSZDC

O : The flag is set when a signed operation results in a value exceeding +32767 (.W) or –32768 (.W)

or +127 (.B) or –128 (.B); otherwise cleared. S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared. C : The flag is set when an unsigned operation results in a value exceeding +65535 (.W) or +255 (.B);

otherwise cleared.

ADC.B #2,R0L ADC.W A0,R0 ADC.B A0,R0L ADC.B R0L,A0

; 8 low-order bits of A0 and R0L are added. ; R0L is zero-expanded and added to A0.

src

and

dest

simulta-

[ Related Instructions ] ADCF, ADD, SBB, SUB

Rev.2.00 Oct 17, 2005 page 40 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Add carry flag

ADCF ADCF

ADdition Carry Flag

[ Syntax ]

ADCF.size dest

[ Operation ]

dest dest + C

[ Function ]

This instruction adds

[ Selectable dest ]

B , W

dest

and the C flag and stores the result in

R0L/R0 R0H/R1 R1L/R2 R1H/R3

A0/A0 A1/A1 [A0] [A1]

dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0

[ Instruction Code/Number of Cycles ]

Page: 140

dest

.

dest

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] ADC, ADD, SBB, SUB

Rev.2.00 Oct 17, 2005 page 41 of 263 REJ09B0001-0200

UIOBSZDC

O : The flag is set when a signed operation results in a value exceeding +32767 (.W) or –32768 (.W)

or +127 (.B) or –128 (.B); otherwise cleared. S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared. C : The flag is set when an unsigned operation results in a value exceeding +65535 (.W) or +255 (.B);

otherwise cleared.

ADCF.B R0L ADCF.W Ram:16[A0]

Chapter 3 Functions

3.2 Functions

Add without carry

ADD ADD

ADDition

[ Syntax ]

ADD.size (:format) src,dest

G , Q , S (Can be specified) B , W

[ Operation ]

dest dest + src

[ Function ]

• This instruction adds

•

If

dest

is A0 or A1 and the selected size specifier (.size) is (.B),

in 16 bits. If

• If

dest

calculation in 16 bits.

[ Selectable src/dest ]

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3

*1

A0/A0 dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

*1 If (.B) is selected as the size specifier (.size), A0 or A1 cannot be chosen for

src

is a stack pointer and the selected size specifier (.size) is (.B),

*1

A1/A1

dest

and

src

and stores the result in

is A0 or A1, the operation is performed on the eight low-order bits of A0 or A1.

(See next page for

src dest

[A0] [A1] A0/A0

*1

[ Instruction Code/Number of Cycles ]

dest

.

src

is zero-expanded to perform calculation

src

is sign extended to perform

src /dest

A1/A1

classified by format.)

*1

[A0] [A1]

src

and

dest

simultaneously.

Page: 140

*2

The operation is performed on the stack pointer indicated by the U flag. Only #IMM can be selected for

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

UIOBSZDC

O : The flag is set when a signed operation results in a value exceeding +32767 (.W) or –32768 (.W)

or +127 (.B) or –128 (.B); otherwise cleared. S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared. C : The flag is set when an unsigned operation results in a value exceeding +65535 (.W) or +255 (.B);

otherwise cleared.

ADD.B A0,R0L ADD.B R0L,A0 ADD.B Ram:8[SB],R0L ADD.W #2,[A0]

; 8 low-order bits of A0 and R0L are added. ; R0L is zero-expanded and added to A0.

src

.

[ Related Instructions ] ADC, ADCF, SBB, SUB

Rev.2.00 Oct 17, 2005 page 42 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

[src/dest Classified by Format]

G format

src dest

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0

*1

A1/A1

*1

[A0] [A1] A0/A0

*1

A1/A1

*1

[A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

*1 If (.B) is selected as the size specifier (.size), A0 or A1 cannot be chosen for *2

The operation is performed on the stack pointer indicated by the U flag. Only #IMM can be selected for

src

and

dest

simultaneously.

*2

src

.

Q format

src dest

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM

*3

dsp:20[A0] dsp:20[A1] abs20 SP/SP

*2

R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

*2

The operation is performed on the stack pointer indicated by the U flag. Only #IMM can be selected for

*3 The acceptable range of values is –8 < #IMM < +7.

S format

*4

src dest

R0L R0H dsp:8[SB] dsp:8[FB] R0L R0H dsp:8[SB] dsp:8[FB] abs16 #IMM abs16 A0 A1

R0L

*5

R0H

*5

dsp:8[SB] dsp:8[FB] R0L

*5

R0H

*5

dsp:8[SB] dsp:8[FB]

abs16 #IMM abs16 A0 A1

*4 Only (.B) can be selected as the size specifier (.size). *5 The same register cannot be used for

src

and

dest

simultaneously.

src

.

Rev.2.00 Oct 17, 2005 page 43 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Add and conditional jump

ADJNZ ADJNZ

ADdition then Jump on Not Zero

[ Syntax ]

ADJNZ.size src,dest,label

B , W

[ Operation ]

dest dest + src

if dest 0 then jump label

[ Function ]

• This instruction adds

• If the addition results in any value other than 0, control jumps to label. If the addition results in 0, the

next instruction is executed.

• The op-code of this instruction is the same as that of SBJNZ.

[ Selectable src/dest/label ]

src dest label

*1

#IMM

dest

and

src

and stores the result in

R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[A0] PC*2–126 label PC*2+129 dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

[ Instruction Code/Number of Cycles ]

Page: 146

dest

.

*1 The acceptable range of values is –8 < #IMM < +7. *2 PC indicates the start address of the instruction.

[ Flag Change ]

Flag

Change

[ Description Example ]

UIOBSZDC

ADJNZ.W #–1,R0,label

[ Related Instructions ] SBJNZ

Rev.2.00 Oct 17, 2005 page 44 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Logically AND

AND AND

AND

[ Syntax ]

AND.size (:format) src,dest

G , S (Can be specified) B , W

[ Operation ]

dest src dest

[ Function ]

• This instruction logically ANDs

• If

dest

is A0 or A1 and the selected size specifier (.size) is (.B),

calculation in 16 bits. If

[ Selectable src/dest ]

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3

*1

A0/A0 dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

*1 If (.B) is selected as the size specifier (.size), A0 or A1 cannot be chosen for

neously.

A1/A1

*1

src

src dest

[A0] [A1] A0/A0

dest

and

src

and stores the result in

is A0 or A1, operation is performed on the eight low-order bits of A0 or A1.

(See next page for

*1

[ Instruction Code/Number of Cycles ]

dest

.

src

is zero-expanded to perform

A1/A1

src/dest

*1

classified by format.)

[A0] [A1]

src

and

dest

Page: 147

simulta-

[ Flag Change ]

Flag

UIOBSZDC

Change

Conditions

S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared.

[ Description Example ]

AND.B Ram:8[SB],R0L AND.B:G A0,R0L AND.B:G R0L,A0 AND.B:S #3,R0L

[ Related Instructions ] OR, XOR, TST

Rev.2.00 Oct 17, 2005 page 45 of 263 REJ09B0001-0200

; 8 low-order bits of A0 and R0L are ANDed. ; R0L is zero-expanded and ANDed with A0.

Chapter 3 Functions

3.2 Functions

[src/dest Classified by Format]

G format

src dest

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0

*1

A1/A1

*1

[A0] [A1] A0/A0

*1

A1/A1

*1

[A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

*1 If (.B) is selected as the size specifier (.size), A0 or A1 cannot be chosen for

src

and

dest

neously.

simulta-

S format

*2

src dest

R0L R0H dsp:8[SB] dsp:8[FB] R0L R0H dsp:8[SB] dsp:8[FB] abs16 #IMM abs16 A0 A1

R0L

*3

R0H

*3

dsp:8[SB] dsp:8[FB] R0L

*3

R0H

*3

dsp:8[SB] dsp:8[FB]

abs16 #IMM abs16 A0 A1

*2 Only (.B) can be selected as the size specifier (.size). *3 The same register cannot be used for

src

and

dest

.

Rev.2.00 Oct 17, 2005 page 46 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Logically AND bits

BAND BAND

Bit AND carry flag

[ Syntax ]

BAND src

[ Operation ]

C src C

[ Function ]

• This instruction logically ANDs the C flag and

[ Selectable src ]

src

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

bit,base:11[SB]

bit,base:16

[ Instruction Code/Number of Cycles ]

src

and stores the result in the C flag.

Page: 150

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] BOR, BXOR, BNAND, BNOR, BNXOR

Rev.2.00 Oct 17, 2005 page 47 of 263 REJ09B0001-0200

UIOBSZDC

C : The flag is set when the operation results in 1; otherwise cleared.

BAND flag BAND 4,Ram BAND 16,Ram:16[SB] BAND [A0]

Chapter 3 Functions

BCLR

Clear bit

Bit CLeaR

3.2 Functions

BCLR

[ Syntax ]

BCLR (:format) dest

[ Operation ]

dest 0

[ Function ]

• This instruction stores 0 in

[ Selectable dest ]

dest

[ Instruction Code/Number of Cycles ]

Page: 150

G , S (Can be specified)

.

dest

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

*1 This

bit,base:11[SB]

dest

can only be selected when in S format.

*1

bit,base:16

[ Flag Change ]

Flag

Change

[ Description Example ]

[ Related Instructions ] BSET, BNOT, BNTST, BTST, BTSTC, BTSTS

Rev.2.00 Oct 17, 2005 page 48 of 263 REJ09B0001-0200

UIOBSZDC

BCLR flag BCLR 4,Ram:8[SB] BCLR 16,Ram:16[SB] BCLR [A0]

Chapter 3 Functions

BM

Cnd

Conditional bit transfer

Bit Move Condition

3.2 Functions

BM

Cnd

[ Syntax ]

BM

Cnd

[ Operation ]

if true then dest 1 else dest 0

[ Function ]

• This instruction transfers the true or false value of the condition indicated by condition is true, 1 is transferred; if false, 0 is transferred.

• The supported types of

Cnd

GEU/C C=1 Equal to or greater than LTU/NC C=0 Less than

EQ/Z Z=1 Equal to = NE/NZ Z=0 Not equal

GTU

C Z=1 Greater than LEU PZ S=0 Positive or zero 0 N S=1 Negative 0 GE S O=0 Equal to or greater than LE (S O) Z=1 Equal to or less than

GT (S O) Z=0 O O=1 O flag is 1. NO O=0 O flag is 0.

A

dest

Cnd

are as follows.

Condition

C flag is 1. C flag is 0.

____

A

Z flag is 1. Z flag is 0.

(signed value) (signed value) Greater than (signed value)

Expression

Cnd

LT S O=1

[ Instruction Code/Number of Cycles ]

Cnd

to

Condition

____

C Z=0 Equal to or less than

A

Less than (signed value)

Expression

Page: 152

dest

. If the

[ Selectable dest ]

[ Flag Change ]

Flag

Change

[ Description Example ]

[ Related Instructions ] J

Rev.2.00 Oct 17, 2005 page 49 of 263 REJ09B0001-0200

UIOBSZDC

BMN 3,Ram:8[SB] BMZ C

Cnd

*1

dest

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB] C

*1 The flag changes if the C flag was specified for

bit,base:11[SB]

bit,base:16

dest

.

Chapter 3 Functions

BNAND

Logically AND inverted bits

Bit Not AND carry flag

3.2 Functions

BNAND

[ Syntax ]

BNAND src

[ Operation ]

C src C

[ Function ]

• This instruction logically ANDs the C flag and the inverted value of

[ Selectable src ]

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

______

flag.

src

bit,base:16

bit,base:11[SB]

[ Instruction Code/Number of Cycles ]

Page: 153

src

and stores the result in the C

[ Flag Change ]

Flag

Change

Condition

[ Description Example ]

[ Related Instructions ] BAND, BOR, BXOR, BNOR, BNXOR

Rev.2.00 Oct 17, 2005 page 50 of 263 REJ09B0001-0200

UIOBSZDC

C : The flag is set when the operation results in 1; otherwise cleared.

BNAND flag BNAND 4,Ram BNAND 16,Ram:16[SB] BNAND [A0]

Chapter 3 Functions

3.2 Functions

Logically OR inverted bits

BNOR BNOR

Bit Not OR carry flag

[ Syntax ]

BNOR src

[ Operation ]

C src C

[ Function ]

[ Selectable src ]

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

______

• This instruction logically ORs the C flag and the inverted value of flag.

src

bit,base:16

bit,base:11[SB]

[ Instruction Code/Number of Cycles ]

Page: 154

src

and stores the result in the C

[ Flag Change ]

Flag

Change

Condition

[ Description Example ]

[ Related Instructions ] BAND, BOR, BXOR, BNAND, BNXOR

Rev.2.00 Oct 17, 2005 page 51 of 263 REJ09B0001-0200

UIOBSZDC

C : The flag is set when the operation results in 1; otherwise cleared.

BNOR flag BNOR 4,Ram BNOR 16,Ram:16[SB] BNOR [A0]

Chapter 3 Functions

Invert bit

Bit NOT

3.2 Functions

BNOTBNOT

[ Syntax ]

BNOT(:format) dest

[ Operation ]

dest dest

[ Function ]

• This instruction inverts

[ Selectable dest ]

________

G , S (Can be specified)

dest

and stores the result in

[ Instruction Code/Number of Cycles ]

Page: 154

dest

.

dest

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

*1 This

bit,base:11[SB]

dest

can only be selected when in S format.

*1

bit,base:16

[ Flag Change ]

Flag

Change

[ Description Example ]

[ Related Instructions ] BCLR, BSET, BNTST, BTST, BTSTC, BTSTS

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UIOBSZDC

BNOT flag BNOT 4,Ram:8[SB] BNOT 16,Ram:16[SB] BNOT [A0]

Chapter 3 Functions

3.2 Functions

Test inverted bit

BNTST BNTST

Bit Not TeST

[ Syntax ]

BNTST src

[ Operation ]

Z src C src

[ Function ]

[ Selectable src ]

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

______

• This instruction transfers the inverted value of flag.

src

bit,base:16

bit,base:11[SB]

[ Instruction Code/Number of Cycles ]

src

to the Z flag and the inverted value of

Page: 155

src

to the C

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] BCLR, BSET, BNOT, BTST, BTSTC, BTSTS

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UIOBSZDC

Z : The flag is set when C : The flag is set when

BNTST flag BNTST 4,Ram:8[SB] BNTST 16,Ram:16[SB] BNTST [A0]

src src

is 0; otherwise cleared.

Chapter 3 Functions

BNXOR

Exclusive OR inverted bits

Bit Not eXclusive OR carry flag

3.2 Functions

BNXOR

[ Syntax ]

BNXOR src

[ Operation ]

C src C

[ Function ]

• This instruction exclusive ORs the C flag and the inverted value of

[ Selectable src ]

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

flag.

______

A

bit,base:11[SB]

src

bit,base:16

[ Instruction Code/Number of Cycles ]

Page: 156

src

and stores the result in the C

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] BAND, BOR, BXOR, BNAND, BNOR

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UIOBSZDC

C : The flag is set when the operation results in 1; otherwise cleared.

BNXOR flag BNXOR 4,Ram BNXOR 16,Ram:16[SB] BNXOR [A0]

Chapter 3 Functions

3.2 Functions

Logically OR bits

BOR BOR

Bit OR carry flag

[ Syntax ]

BOR src

[ Operation ]

C src C

[ Function ]

• This instruction logically ORs the C flag and

[ Selectable src ]

src

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

bit,base:11[SB]

bit,base:16

[ Instruction Code/Number of Cycles ]

src

and stores the result in the C flag.

Page: 156

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] BAND, BXOR, BNAND, BNOR, BNXOR

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UIOBSZDC

C : The flag is set when the operation results in 1; otherwise cleared.

BOR flag BOR 4,Ram BOR 16,Ram:16[SB] BOR [A0]

Chapter 3 Functions

3.2 Functions

Debug interrupt

BRK BRK

BReaK

[ Syntax ]

BRK

[ Operation ]

SP SP – 2 M(SP) (PC + 1)H, FLG SP SP – 2 M(SP) (PC + 1)ML PC M(FFFE416)

[ Function ]

• This instruction generates a BRK interrupt.

• The BRK interrupt is a nonmaskable interrupt.

[ Instruction Code/Number of Cycles ]

Page: 157

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] INT, INTO

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UIOBSZDC

U : The flag is cleared. I : The flag is cleared. D : The flag is cleared.

BRK

*1

*1 The flags are saved to the stack area before the BRK in-

struction is executed. After the interrupt, the flags change state as shown at left.

Chapter 3 Functions

3.2 Functions

Set bit

BSET BSET

Bit SET

[ Syntax ]

BSET (:format) dest

[ Operation ]

dest 1

[ Function ]

• This instruction stores 1 in

[ Selectable dest ]

dest

[ Instruction Code/Number of Cycles ]

Page: 157

G , S (Can be specified)

.

dest

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

*1 This

bit,base:11[SB]

dest

can only be selected when in S format.

*1

bit,base:16

[ Flag Change ]

Flag

Change

[ Description Example ]

[ Related Instructions ] BCLR, BNOT, BNTST, BTST, BTSTC, BTSTS

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UIOBSZDC

BSET flag BSET 4,Ram:8[SB] BSET 16,Ram:16[SB] BSET [A0]

Chapter 3 Functions

3.2 Functions

Test bit

BTST BTST

Bit TeST

[ Syntax ]

BTST (:format) src

[ Operation ]

Z src C src

[ Function ]

[ Selectable src ]

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

*1 This

______

• This instruction transfers the inverted value of the C flag.

src

bit,base:16

bit,base:11[SB]

src

can only be selected when in S format.

*1

[ Instruction Code/Number of Cycles ]

G , S (Can be specified)

src

to the Z flag and the non-inverted value of

Page: 158

src

to

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] BCLR, BSET, BNOT, BNTST, BTSTC, BTSTS

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UIOBSZDC

Z : The flag is set when C : The flag is set when

BTST flag BTST 4,Ram:8[SB] BTST 16,Ram:16[SB] BTST [A0]

src src

is 0; otherwise cleared.

is 1; otherwise cleared.

Chapter 3 Functions

3.2 Functions

Test bit and clear

BTSTC BTSTC

Bit TeST and Clear

[ Syntax ]

BTSTC dest

[ Operation ]

Z C dest dest 0

[ Function ]

• This instruction transfers the inverted value of

dest

[ Selectable dest ]

________

dest

to the C flag. Then it stores 0 in

dest

[ Instruction Code/Number of Cycles ]

dest

to the Z flag and the non-inverted value of

.

dest

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

bit,base:11[SB]

bit,base:16

Page: 159

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] BCLR, BSET, BNOT, BNTST, BTST, BTSTS

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UIOBSZDC

Z : The flag is set when C : The flag is set when

BTSTC flag BTSTC 4,Ram BTSTC 16,Ram:16[SB] BTSTC [A0]

dest dest

is 0; otherwise cleared. is 1; otherwise cleared.

Chapter 3 Functions

3.2 Functions

Test bit and set

BTSTS BTSTS

Bit TeST and Set

[ Syntax ]

BTSTS dest

[ Operation ]

Z C dest dest 1

[ Function ]

• This instruction transfers the inverted value of the C flag. Then it stores 1 in

[ Selectable dest ]

________

dest

.

[ Instruction Code/Number of Cycles ]

Page: 160

dest

to the Z flag and the non-inverted value of

dest

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

bit,base:11[SB]

bit,base:16

dest

to

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] BCLR, BSET, BNOT, BNTST, BTST, BTSTC

Rev.2.00 Oct 17, 2005 page 60 of 263 REJ09B0001-0200

UIOBSZDC

Z : The flag is set when C : The flag is set when

BTSTS flag BTSTS 4,Ram BTSTS 16,Ram:16[SB] BTSTS [A0]

dest dest

is 0; otherwise cleared. is 1; otherwise cleared.

Chapter 3 Functions

BXOR

Exclusive OR bits

Bit eXclusive OR carry flag

3.2 Functions

BXOR

[ Syntax ]

BXOR src

[ Operation ]

C src C

[ Function ]

• This instruction exclusive ORs the C flag and

[ Selectable src ]

bit,R0 bit,R1 bit,R2 bit,R3 bit,A0 bit,A1 [A0] [A1] base:8[A0] base:8[A1] bit,base:8[SB] bit,base:8[FB] base:16[A0] base:16[A1] bit,base:16[SB]

C

A

src

bit,base:16

bit,base:11[SB]

[ Instruction Code/Number of Cycles ]

src

and stores the result in the C flag.

Page: 160

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] BAND, BOR, BNAND, BNOR, BNXOR

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UIOBSZDC

C : The flag is set when the operation results in 1; otherwise cleared.

BXOR flag BXOR 4,Ram BXOR 16,Ram:16[SB] BXOR [A0]

Chapter 3 Functions

3.2 Functions

Compare

CMP CMP

CoMPare

[ Syntax ]

CMP.size (:format) src,dest

G , Q , S (Can be specified) B , W

[ Operation ]

dest – src

[ Function ]

• Flag bits in the flag register change depending on the result of subtraction of

• If

dest

is A0 or A1 and the selected size specifier (.size) is (.B),

operation in 16 bits. If

[ Selectable src/dest ]

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3

*1

A0/A0 dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

*1 If (.B) is selected as the size specifier (.size), A0 or A1 cannot be chosen for

neously.

A1/A1

*1

src

is A0 or A1, operation is performed on the 8 low-order bits of A0 or A1.

(See next page for

src dest

[A0] [A1] A0/A0

*1

[ Instruction Code/Number of Cycles ]

src

from

dest

src

is zero-expanded to perform

A1/A1

src/dest

*1

classified by format.)

[A0] [A1]

src

and

dest

Page: 161

.

simulta-

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

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UIOBSZDC

O : The flag is set when a signed operation results in a value exceeding +32767 (.W) or –32768 (.W),

or +127 (.B) or –128 (.B); otherwise cleared. S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared. C : The flag is set when an unsigned operation results in any value equal to or greater than 0;

otherwise cleared.

CMP.B:S #10,R0L CMP.W:G R0,A0 CMP.W #–3,R0 CMP.B #5,Ram:8[FB] CMP.B A0,R0L

; 8 low-order bits of A0 and R0L are compared.

Chapter 3 Functions

3.2 Functions

[src/dest Classified by Format]

G format

src dest

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0

*1

A1/A1

*1

[A0] [A1] A0/A0

*1

A1/A1

*1

[A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

*1 If (.B) is selected as the size specifier (.size), A0 or A1 cannot be chosen for

src

and

dest

neously.

Q format

simulta-

src dest

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM

*2

dsp:20[A0] dsp:20[A1] abs20 SP/SP

R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

*2 The acceptable range of values is –8 < #IMM < +7.

S format

*3

src dest

R0L R0H dsp:8[SB] dsp:8[FB] R0L R0H dsp:8[SB] dsp:8[FB] abs16 #IMM abs16 A0 A1

R0L

*4

R0H

*4

dsp:8[SB] dsp:8[FB] R0L

*4

R0H

*4

dsp:8[SB] dsp:8[FB]

abs16 #IMM abs16 A0 A1

*3 Only (.B) can be selected as the size specifier (.size). *4 The same register cannot be used for

src

and

dest

.

Rev.2.00 Oct 17, 2005 page 63 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Decimal add with carry

DADC DADC

Decimal ADdition with Carry

[ Syntax ]

DADC.size src,dest

B , W

[ Operation ]

dest src + dest + C

[ Function ]

• This instruction adds

[ Selectable src/dest ]

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

dest, src

src dest

, and the C flag as decimal data and stores the result in

[ Instruction Code/Number of Cycles ]

dest

Page: 165

.

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] DADD, DSUB, DSBB

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UIOBSZDC

S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared. C : The flag is set when the operation results in a value exceeding +9999 (.W) or +99 (.B); otherwise

cleared.

DADC.B #3,R0L DADC.W R1,R0

Chapter 3 Functions

3.2 Functions

Decimal add without carry

DADD DADD

Decimal ADDition

[ Syntax ]

DADD.size src,dest

B , W

[ Operation ]

dest src + dest

[ Function ]

• This instruction adds

[ Selectable src/dest ]

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

dest

and

src

as decimal data and stores the result in

src dest

[ Instruction Code/Number of Cycles ]

dest

.

Page: 167

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] DADC, DSUB, DSBB

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UIOBSZDC

S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared. C : The flag is set when the operation results in a value exceeding +9999 (.W) or +99 (.B); otherwise

cleared.

DADD.B #3,R0L DADD.W R1,R0

Chapter 3 Functions

3.2 Functions

Decrement

DEC DEC

DECrement

[ Syntax ]

DEC.size dest

[ Operation ]

dest dest – 1

[ Function ]

• This instruction decrements

[ Selectable dest ]

B , W

dest

by 1 and stores the result in

R0L abs16

*1 Only (.B) can be specified as the size specifier (.size).

[ Instruction Code/Number of Cycles ]

Page: 169

dest

.

dest

*1

R0H

*2

A0

*1

dsp:8[SB]*1dsp:8[FB]

*2

A1

*1

*2 Only (.W) can be specified as the size specifier (.size).

[ Flag Change ]

Flag

Change

UIOBSZDC

Conditions

S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared.

[ Description Example ]

DEC.W A0 DEC.B R0L

[ Related Instructions ] INC

Rev.2.00 Oct 17, 2005 page 66 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Signed divide

DIV DIV

DIVide

[ Syntax ]

DIV.size src

B , W

[ Operation ]

If the size specifier (.size) is (.B)

R0L (quotient), R0H (remainder) R0 src

If the size specifier (.size) is (.W)

R0 (quotient), R2 (remainder) R2R0 src

[ Function ]

• This instruction divides R2R0 (R0) and the remainder in R2 (R0H)*1. The remainder has the same sign as the dividend. Items in parentheses and followed by selected as the size specifier (.size).

• If

src

is A0 or A1 and the selected size specifier (.size) is (.B), the operation is performed on the 8 low-

order bits of A0 or A1.

• If (.B) is selected as the size specifier (.size), the O flag is set when the operation results in a quotient exceeding 8 bits or the divisor is 0. In this case, R0L and R0H are undefined.

• If (.W) is selected as the size specifier (.size), the O flag is set when the operation results in a quotient exceeding 16 bits or the divisor is 0. In this case, R0 and R2 are undefined.

“*1”

( )*1 indicate registers that are the object of the operation when (.B) is

*1

by the signed value of

[ Instruction Code/Number of Cycles ]

Page: 170

src

and stores the quotient in R0 (R0L)

*1

[ Selectable src ]

src

R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM R2R0 R3R1 A1A0

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

UIOBSZDC

O : The flag is set when the operation results in a quotient exceeding 16 bits (.W) or 8 bits (.B) or the

divisor is 0; otherwise cleared.

DIV.B A0 ;Value of 8 low-order bits of A0 is the divisor. DIV.B #4 DIV.W R0

[ Related Instructions ] DIVU, DIVX, MUL, MULU

Rev.2.00 Oct 17, 2005 page 67 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Unsigned divide

DIVU DIVU

DIVide Unsigned

[ Syntax ]

DIVU.size src

B , W

[ Operation ]

If the size specifier (.size) is (.B)

R0L (quotient), R0H (remainder) R0 src

If the size specifier (.size) is (.W)

R0 (quotient), R2 (remainder) R2R0 src

[ Function ]

• This instruction divides R2R0 (R0) (R0L)*1 and the remainder in R2 (R0H)*1. Items in parentheses and followed by registers that are the object of the operation when (.B) is selected as the size specifier (.size).

• If

src

is A0 or A1 and the selected size specifier (.size) is (.B), the operation is performed on the 8 low-

order bits of A0 or A1.

• If (.B) is selected as the size specifier (.size), the O flag is set when the operation results in a quotient exceeding 8 bits or the divisor is 0. In this case, R0L and R0H are undefined.

• If (.W) is selected as the size specifier (.size), the O flag is set when the operation results in a quotient exceeding 16 bits or the divisor is 0. In this case, R0 and R2 are undefined.

*1

by the unsigned value of

[ Instruction Code/Number of Cycles ]

src

and stores the quotient in R0

“*1”

( )*1 indicate

Page: 171

[ Selectable src ]

src

R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM R2R0 R3R1 A1A0

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

UIOBSZDC

O : The flag is set when the operation results in a quotient exceeding 16 bits (.W) or 8 bits (.B) or the

divisor is 0; otherwise cleared.

DIVU.B A0 ;Value of 8 low-order bits of A0 is the divisor. DIVU.B #4 DIVU.W R0

[ Related Instructions ] DIV, DIVX, MUL, MULU

Rev.2.00 Oct 17, 2005 page 68 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Signed divide

DIVX DIVX

DIVide eXtension

[ Syntax ]

DIVX.size src

B , W

[ Operation ]

If the size specifier (.size) is (.B)

R0L (quotient), R0H (remainder) R0 src

If the size specifier (.size) is (.W)

R0 (quotient), R2 (remainder) R2R0 src

[ Function ]

• This instruction divides R2R0 (R0)*1 by the signed value of remainder in R2 (R0H)*1. The remainder has the same sign as the divisor. Items in parentheses and followed

“*1”

by

( )*1 indicate registers that are the object of the operation when (.B) is selected as the size specifier (.size).

• If

src

is A0 or A1 and the selected size specifier (.size) is (.B), the operation is performed on the 8 low-

order bits of A0 or A1.

• If (.B) is selected as the size specifier (.size), the O flag is set when the operation results in a quotient exceeding 8 bits or the divisor is 0. At this time, R0L and R0H are undefined.

• If (.W) is selected as the size specifier (.size), the O flag is set when the operation results in a quotient exceeding 16 bits or the divisor is 0. At this time, R0 and R2 are undefined.

[ Instruction Code/Number of Cycles ]

Page: 172

src

and stores the quotient in R0 (R0L)*1 and the

[ Selectable src ]

src

R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM R2R0 R3R1 A1A0

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

UIOBSZDC

O : The flag is set when the operation results in a quotient exceeding 16 bits (.W) or 8 bits (.B) or the

divisor is 0; otherwise cleared.

DIVX.B A0 ;Value of 8 low-order bits of A0 is the divisor. DIVX.B #4 DIVX.W R0

[ Related Instructions ] DIV, DIVU, MUL, MULU

Rev.2.00 Oct 17, 2005 page 69 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Decimal subtract with borrow

DSBB DSBB

Decimal SuBtract with Borrow

[ Syntax ]

DSBB.size src,dest

B , W

[ Operation ]

dest dest – src – C

[ Function ]

• This instruction subtracts stores the result in

[ Selectable src/dest ]

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

dest

src dest

____

src

and the inverted value of the C flag from

.

[ Instruction Code/Number of Cycles ]

dest

as decimal data and

Page: 173

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] DADC, DADD, DSUB

Rev.2.00 Oct 17, 2005 page 70 of 263 REJ09B0001-0200

UIOBSZDC

S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared. C : The flag is set when the operation results in any value equal to or greater than 0; otherwise

cleared.

DSBB.B #3,R0L DSBB.W R1,R0

Chapter 3 Functions

3.2 Functions

Decimal subtract without borrow

DSUB DSUB

[ Syntax ]

DSUB.size src,dest

[ Operation ]

dest dest – src

[ Function ]

Decimal SUBtract

[ Instruction Code/Number of Cycles ]

Page: 175

B , W

• This instruction subtracts

[ Selectable src/dest ]

src dest

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

[ Flag Change ]

Flag Change

UIOBSZDC

src

from

dest

as decimal data and stores the result in

dest

.

Conditions

S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared. C : The flag is set when the operation results in any value equal to or greater than 0; otherwise

cleared.

[ Description Example ]

DSUB.B #3,R0L DSUB.W R1,R0

[ Related Instructions ] DADC, DADD, DSBB

Rev.2.00 Oct 17, 2005 page 71 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Build stack frame

ENTER ENTER

[ Syntax ]

ENTER src

[ Operation ]

SP SP – 2 M(SP) FB FB SP SP SP – src

[ Function ]

• This instruction generates a stack frame.

• The diagrams below show the stack area status before and after the ENTER instruction is executed at

the beginning of a called subroutine.

ENTER function

src

represents the size of the stack frame.

[ Instruction Code/Number of Cycles ]

Page: 177

Before instruction execution

SP

[ Selectable src ]

#IMM8

[ Flag Change ]

Flag

Change

Return address (L) Return address (M) Return address (H)

Argument of function

UIOBSZDC

src

Direction in which address increases

SP

FB

After instruction execution

Auto variable area

FB (L)

FB (H)

Return address (L)

Return address (M)

Return address (H)

Argument of fun

ction

Number of bytes indicated by

src

[ Description Example ]

ENTER #3

[ Related Instructions ] EXITD

Rev.2.00 Oct 17, 2005 page 72 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Deallocate stack frame

EXITD EXITD

[ Syntax ]

EXITD

[ Operation ]

SP FB FB M(SP) SP SP + 2 PCML M(SP) SP SP + 2 PCH M(SP) SP SP + 1

[ Function ]

• This instruction deallocates a stack frame and exits from the subroutine.

EXIT and Deallocate stack frame

[ Instruction Code/Number of Cycles ]

Page: 178

• Use this instruction in combination with the ENTER instruction.

• The diagrams below show the stack area status before and after the EXITD instruction is executed

at the end of a subroutine in which an ENTER instruction was executed.

Before instruction execution After instruction execution

SP

Auto variable area

FB

FB (L)

Direction in which address increases

FB (H)

Return address (L)

Return address (M) Return address (H)

Argument of function

[ Flag Change ]

Flag

Change

UIOBSZDC

Argument of function

SP

[ Description Example ]

EXITD

[ Related Instructions ] ENTER

Rev.2.00 Oct 17, 2005 page 73 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Extend sign

EXTS EXTS

EXTend Sign

[ Syntax ]

EXTS.size dest

B , W

[ Operation ]

dest EXT(dest)

[ Function ]

• This instruction sign extends

• If (.B) is selected as the size specifier (.size),

• If (.W) is selected as the size specifier (.size), R0 is sign extended to 32 bits. In this case, R2 is used

for the upper bytes.

[ Selectable dest ]

dest

and stores the result in

dest

is sign extended to 16 bits.

R0L/R0 R0H/R1 R1L/R2 R1H/R3

A0/A0 A1/A1 [A0] [A1]

dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0

[ Instruction Code/Number of Cycles ]

Page: 178

dest

.

dest

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

Rev.2.00 Oct 17, 2005 page 74 of 263 REJ09B0001-0200

UIOBSZDC

S : If (.B) is selected as the size specifier (.size), the flag is set when the operation results in MSB =

1; otherwise cleared. The flag does not change if (.W) is selected as the size specifier (.size).

Z : If (.B) is selected as the size specifier (.size), the flag is set when the operation results in 0;

otherwise cleared. The flag does not change if (.W) is selected as the size specifier (.size).

EXTS.B R0L EXTS.W R0

Chapter 3 Functions

FCLR

Clear flag register bit

Flag register CLeaR

3.2 Functions

FCLR

[ Syntax ]

FCLR dest

[ Operation ]

dest 0

[ Function ]

• This instruction stores 0 in

[ Selectable dest ]

dest

[ Instruction Code/Number of Cycles ]

Page: 179

.

dest

CDZSBOI U

[ Flag Change ]

Flag

Change

[ Description Example ]

[ Related Instructions ] FSET

Rev.2.00 Oct 17, 2005 page 75 of 263 REJ09B0001-0200

UIOBSZDC

*1 *1 *1 *1 *1 *1 *1 *1

FCLR I FCLR S

*1 The selected flag is cleared to 0.

Chapter 3 Functions

3.2 Functions

Set flag register bit

FSET FSET

Flag register SET

[ Syntax ]

FSET dest

[ Operation ]

dest 1

[ Function ]

• This instruction stores 1 in

[ Selectable dest ]

dest

[ Instruction Code/Number of Cycles ]

Page: 180

.

dest

CDZSBOI U

[ Flag Change ]

Flag

Change

[ Description Example ]

[ Related Instructions ] FCLR

Rev.2.00 Oct 17, 2005 page 76 of 263 REJ09B0001-0200

UIOBSZDC

*1 *1 *1 *1 *1 *1 *1 *1

FSET I FSET S

*1 The selected flag is set (= 1).

Chapter 3 Functions

3.2 Functions

Increment

INC INC

INCrement

[ Syntax ]

INC.size dest

[ Operation ]

dest dest + 1

[ Function ]

• This instruction adds 1 to

[ Selectable dest ]

B , W

dest

and stores the result in

[ Instruction Code/Number of Cycles ]

Page: 180

dest

.

dest

*1

R0L abs16

*1

R0H

*2

A0

*1

dsp:8[SB]*1dsp:8[FB]

*2

A1

*1

*1 Only (.B) can be selected as the size specifier (.size). *2 Only (.W) can be selected as the size specifier (.size).

[ Flag Change ]

Flag

Change

UIOBSZDC

Conditions

S : The flag is set when the operation results in MSB = 1; otherwise cleared. Z : The flag is set when the operation results in 0; otherwise cleared.

[ Description Example ]

INC.W A0 INC.B R0L

[ Related Instructions ] DEC

Rev.2.00 Oct 17, 2005 page 77 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Interrupt by INT instruction

INT INT

INTerrupt

[ Syntax ]

INT src

[ Operation ]

SP SP – 2 M(SP) (PC + 2) SP SP – 2 M(SP) (PC + 2)ML PC M(IntBase + src 4)

[ Function ]

• This instruction generates a software interrupt specified by number.

• If

src

is 31 or smaller, the U flag is cleared to 0 and the interrupt stack pointer (ISP) is used.

• If

src

is 32 or larger, the stack pointer indicated by the U flag is used.

• The interrupts generated by the INT instruction are nonmaskable.

[ Selectable src ]

*1*2

#IMM

*1 #IMM denotes a software interrupt number.

H, FLG

src

[ Instruction Code/Number of Cycles ]

Page: 181

src

.

src

represents a software interrupt

*2 The acceptable range of values is 0 < #IMM < 63.

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

UIOBSZDC

U : The flag is cleared if the software interrupt number is 31 or smaller. The flag does not change if

the software interrupt number is 32 or larger. I : The flag is cleared. D : The flag is cleared.

INT #0

*3 The flags are saved to the stack area before the INT in-

struction is executed. After the interrupt, the flags change state as shown at left.

[ Related Instructions ] BRK, INTO

Rev.2.00 Oct 17, 2005 page 78 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Interrupt on overflow

INTO INTO

INTerrupt on Overflow

[ Syntax ]

INTO

[ Operation ]

SP SP – 2 M(SP) (PC + 1)H, FLG SP SP – 2 M(SP) (PC + 1)ML PC M(FFFE016)

[ Function ]

• If the O flag is set to 1, this instruction generates an overflow interrupt. If the flag is cleared to 0, the

next instruction is executed.

• The overflow interrupt is nonmaskable.

[ Instruction Code/Number of Cycles ]

Page: 182

[ Flag Change ]

Flag

Change

Conditions

[ Description Example ]

[ Related Instructions ] BRK, INT

Rev.2.00 Oct 17, 2005 page 79 of 263 REJ09B0001-0200

UIOBSZDC

U : The flag is cleared. I : The flag is cleared. D : The flag is cleared.

INTO

*1 The flags are saved to the stack area before the INTO

instruction is executed. After the interrupt, the flags change state as shown at left.

Chapter 3 Functions

J

Cnd

Jump on condition

Jump on Condition

3.2 Functions

J

Cnd

[ Syntax ]

J

Cnd

label

[ Operation ]

if true then jump label

[ Function ]

• This instruction causes program flow to branch after checking the execution result of the preceding

instruction against the following condition. If the condition indicated by label. If false, the next instruction is executed.

• The following conditions can be used for

Cnd

GEU/C C=1 Equal to or greater than LTU/NC C=0 Smaller than

EQ/Z Z=1 Equal to = NE/NZ Z=0 Not equal

GTU PZ S=0 Positive or zero 0 N S=1 Negative 0 GE S O=0 Equal to or greater than LE (S O) Z=1 Equal to or smaller than

GT (S O) Z=0 O O=1 O flag is 1. NO O=0 O flag is 0.

____

C Z=1 Greater than LEU

A

Condition

C flag is 1. C flag is 0.

Z flag is 1. Z flag is 0.

(signed value) (signed value) Greater than (signed value)

Cnd

Expression

:

Cnd

LT S O=1

[ Instruction Code/Number of Cycles ]

Cnd

is true, control jumps to

Condition

____

C Z=0 Equal to or smaller than

A

Smaller than (signed value)

Expression

Page: 182

[ Selectable label ]

label

PC*1–127 label PC*1+128 GEU/C, GTU, EQ/Z, N, LTU/NC, LEU, NE/NZ, PZ PC*1–126 label PC*1+129 LE, O, GE, GT, NO, LT

*1 PC indicates the start address of the instruction.

[ Flag Change ]

Flag

Change

[ Description Example ]

[ Related Instructions ] BM

Rev.2.00 Oct 17, 2005 page 80 of 263 REJ09B0001-0200

UIOBSZDC

JEQ label JNE label

Cnd

Chapter 3 Functions

3.2 Functions

Unconditional jump

JMP JMP

JuMP

[ Syntax ]

JMP(.length) label

[ Operation ]

PC label

[ Function ]

• This instruction causes control to jump to label.

[ Selectable label ]

.length label

.S PC*1+2 label PC*1+9 .B PC*1–127 label PC*1+128 .W .A abs20

PC*1–32767 label PC*1+32768

[ Instruction Code/Number of Cycles ]

Page: 184

S , B , W , A (Can be specified)

*1 PC indicates the start address of the instruction.

[ Flag Change ]

Flag

Change

[ Description Example ]

UIOBSZDC

JMP label

[ Related Instructions ] JMPI

Rev.2.00 Oct 17, 2005 page 81 of 263 REJ09B0001-0200

Chapter 3 Functions

3.2 Functions

Jump indirect

JMPI JMPI

JuMP Indirect

[ Syntax ]

JMPI.length src

W , A

[ Operation ]

When jump distance specifier (.length) is (.W) When jump distance specifier (.length) is (.A)

PC PC src PC src

[ Function ]

• This instruction causes control to jump to the address indicated by

memory, specify the address at which the low-order address is stored.

•

If (.W) is selected as the jump distance specifier (.length), control jumps to the start address of the instruction plus the address indicated by required memory capacity is 2 bytes.

• If

src

is a location in the memory and (.A) is selected as the jump distance specifier (.length), the

required memory capacity is 3 bytes.

[ Selectable src ]

If (.W) is selected as the jump distance specifier (.length)

src

R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1]

dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB]

dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20

R2R0 R3R1 A1A0

src

(added including the sign bits).

[ Instruction Code/Number of Cycles ]

Page: 185

src

. If

src

is a location in the

If

src

is a location in the memory, the

If (.A) is selected as the jump distance specifier (.length)

src

R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1]

dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB]

dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0

[ Flag Change ]

Flag

Change

[ Description Example ]

[ Related Instructions ] JMP

UIOBSZDC

JMPI.A A1A0 JMPI.W R0

Rev.2.00 Oct 17, 2005 page 82 of 263 REJ09B0001-0200

Renesas R8C/Tiny Series Software Manual

Using This Manual

Table of Contents

Quick Reference in Alphabetic Order

Quick Reference by Function

Quick Reference by Addressing Mode (General Instruction Addressing)

Quick Reference by Addressing Mode (Special Instruction Addressing)

Quick Reference by Addressing Mode (Bit Instruction Addressing)

1.1 Features of R8C/Tiny Series

1.2 Address Space

1.3 Register Configuration

1.4 Flag Register (FLG)

1.5 Register Banks

1.6 Internal State after Reset is Cleared

1.7 Data Types

1.8 Data Arrangement

1.9 Instruction Formats

1.10 Vector Tables

2.1 Addressing Modes

2.3 General Instruction Addressing

2.4 Special Instruction Addressing

2.5 Bit Instruction Addressing