Renesas M16C FAMILY, Tiny SERIES, R8C series Hardware Manual
REJ09B0222-0130
R8C/18 Group, R8C/19 Group
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MCU
M16C FAMILY / R8C/Tiny SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev.1.30
Revision Date: Apr 14, 2006
www.renesas.com
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Renesas Technology Corp. or a third party.
2.
Renesas Technology Corp. assumes no responsibility for any damage, or infringement of
any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corp. without notice due to
product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://
www.renesas.com).
4.
When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information
and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
5.
Renesas Technology Corp. semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at
stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology
Corp. product distributor when considering the use of a product contained herein for any
specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
6.
The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7.
If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
8.
Please contact Renesas Technology Corp. for further details on these materials or the
products contained therein.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MC U pr o duct s fr om R e nesas. For d et a il ed usa ge not es on the
products covered by this manual, refer to the relevant sections of the manu a l . If the descri pt ion s un der General
Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description
in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register settings and pins
are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are
not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
When the clock signal is generated with an external resonator (or from an external oscillator) during
a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,
when switching to a clock signal produced with an external resonator (or by an external oscillator)
while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm that the
change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different type numbers, implement a system-evaluation test for each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/18 Group, R8C/19 Group. Make sure to refer to the latest versions of these
documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site.
Document Type Description Document Title Document No.
Datasheet Hardware overview and electrical characte ristics R8C/18 Group,
R8C/19 Group
Datasheet
Hardware manual Hardware specifications (pin assignments,
memory maps, peripheral function
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
Software manual Description of CPU instruction set R8C/Tiny Series
Application note Information on using peripheral functions and
application examples
Sample programs
Information on writing programs in assembly
language and C
Renesas
technical update
Product specifications, updates on documents,
etc.
R8C/18 Group,
R8C/19 Group
Hardware Manual
Software Manual
Available from Renesas
Technology Web site.
REJ03B0124
This hardware
manual
REJ09B0001
2. Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “b” is appended to numeric valu es given i n binary format. However, nothing is appended t o the
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
3. Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
0
XXX0
XXX1
(b2)
(b3)
XXX4
XXX5
XXX6
XXX7
*1
Symbol Address After Reset
XXX XXX 00h
Bit NameBit Symbol
XXX bits
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Reserved bits
XXX bits
XXX bit
b1 b0
1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
Set to 0.
Function varies according to the operating
mode.
0: XXX
1: XXX
Function
RW
RW
RW
RW
RW
WO
RW
RO
*2
*3
*4
*1
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2
RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
4. List of Abbreviations and Acronyms
Abbreviation Full Form
ACIA Asynchronous Communication Interface Adapter
bps bits per second
CRC Cyclic Redundancy Check
DMA Direct Memory Access
DMAC Direct Memory Access Controller
GSM Global System for Mobile Communications
Hi-Z High Impedance
IEBus Inter Equipment bus
I/O Input/Output
IrDA Infrared Data Association
LSB Least Significant Bit
MSB Most Significant Bit
NC Non-Connection
PLL Phase Locked Loop
PWM Pulse Width Modulation
SFR Special Function Registers
SIM Subscriber Identity Module
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
Table of Contents
SFR Page Reference B - 1
1. Overview 1
1.1 Applications.................................................................................................1
1.2 Performance Overview................................................................................2
1.3 Block Diagram.............................................................................................4
1.4 Product Information.....................................................................................5
1.5 Pin Assignments..........................................................................................7
1.6 Pin Functions.............................................................................................10
2. Central Processing Unit (CPU) 13
2.1 Data Registers (R0, R1, R2, and R3)........................................................14
2.2 Address Registers (A0 and A1).................................................................14
2.3 Frame Base Register (FB) ........................................................................14
2.4 Interrupt Table Register (INTB).................................................................14
2.5 Program Counter (PC) ..............................................................................14
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP).....................14
2.7 Static Base Register (SB)..........................................................................14
2.8 Flag Register (FLG)...................................................................................14
2.8.1 Carry Flag (C).....................................................................................14
2.8.2 Debug Flag (D)...................................................................................14
2.8.3 Zero Flag (Z).......................................................................................14
2.8.4 Sign Flag (S).......................................................................................14
2.8.5 Register Bank Select Flag (B)............................................................14
2.8.6 Overflow Flag (O)...............................................................................14
2.8.7 Interrupt Enable Flag (I)......................................................................15
2.8.8 Stack Pointer Select Flag (U).............................................................15
2.8.9 Processor Interrupt Priority Level (IPL) ..............................................15
2.8.10 Reserved Bit.......................................................................................15
3. Memory 16
3.1 R8C/18 Group...........................................................................................16
3.2 R8C/19 Group...........................................................................................17
A - 1
4. Special Function Registers (SFRs) 18
5. Resets 22
5.1 Hardware Reset ........................................................................................24
5.1.1 When Power Supply is Stable............................................................24
5.1.2 Power On............................................................................................24
5.2 Power-On Reset Function.........................................................................26
5.3 Voltage Monitor 1 Reset ...........................................................................27
5.4 Voltage Monitor 2 Reset............................................................................27
5.5 Watchdog Timer Reset..............................................................................27
5.6 Software Reset..........................................................................................27
6. Programmable I/O Ports 28
6.1 Functions of Programmable I/O Ports.......................................................28
6.2 Effect on Peripheral Functions..................................................................28
6.3 Pins Other than Programmable I/O Ports..................................................28
6.4 Port settings ..............................................................................................35
6.5 Unassigned Pin Handling..........................................................................39
7. Voltage Detection Circuit 40
7.1 VCC Input Voltage.....................................................................................46
7.1.1 Monitoring Vdet1 ................................................................................46
7.1.2 Monitoring Vdet2 ................................................................................46
7.1.3 Digital Filter.........................................................................................46
7.2 Voltage Monitor 1 Reset............................................................................48
7.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset......................... 49
8. Processor Mode 51
8.1 Processor Modes ...................................................................................... 51
9. Bus 52
10. Clock Generation Circuit 53
10.1 Main Clock.................................................................................................60
10.2 On-Chip Oscillator Clocks.........................................................................61
10.2.1 Low-Speed On-Chip Oscillator Clock.................................................61
10.2.2 High-Speed On-Chip Oscillator Clock................................................61
A - 2
10.3 CPU Clock and Peripheral Function Clock................................................62
10.3.1 System Clock......................................................................................62
10.3.2 CPU Clock..........................................................................................62
10.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32)...............................62
10.3.4 fRING and fRING128..........................................................................62
10.3.5 fRING-fast...........................................................................................62
10.3.6 fRING-S..............................................................................................62
10.4 Power Control............................................................................................63
10.4.1 Standard Operating Mode..................................................................63
10.4.2 Wait Mode ..........................................................................................64
10.4.3 Stop Mode..........................................................................................66
10.5 Oscillation Stop Detection Function..........................................................68
10.5.1 How to Use Oscillation Stop Detection Function................................68
10.6 Notes on Clock Generation Circuit............................................................70
10.6.1 Stop Mode and Wait Mode.................................................................70
10.6.2 Oscillation Stop Detection Function....................................................70
10.6.3 Oscillation Circuit Constants...............................................................70
10.6.4 High-Speed On-Chip Oscillator Clock................................................70
11. Protection 71
12. Interrupts 72
12.1 Interrupt Overview.....................................................................................72
12.1.1 Types of Interrupts..............................................................................72
12.1.2 Software Interrupts.............................................................................73
12.1.3 Special Interrupts................................................................................74
12.1.4 Peripheral Function Interrupt..............................................................74
12.1.5 Interrupts and Interrupt Vectors..........................................................75
12.1.6 Interrupt Control..................................................................................77
12.2 INT Interrupt..............................................................................................85
12.2.1 INT0 Interrupt .....................................................................................85
12.2.2 INT0 Input Filter..................................................................................86
12.2.3 INT1 Interrupt .....................................................................................87
12.2.4 INT3 Interrupt .....................................................................................88
12.3 Key Input Interrupt.....................................................................................90
12.4 Address Match Interrupt............................................................................92
A - 3
12.5 Notes on Interrupts....................................................................................94
12.5.1 Reading Address 00000h...................................................................94
12.5.2 SP Setting...........................................................................................94
12.5.3 External Interrupt and Key Input Interrupt ..........................................94
12.5.4 Watchdog Timer Interrupt...................................................................94
12.5.5 Changing Interrupt Sources................................................................95
12.5.6 Changing Interrupt Control Register Contents ...................................96
13. Watchdog Timer 97
13.1 Count Source Protection Mode Disabled................................................100
13.2 Count Source Protection Mode Enabled.................................................101
14. Timers 102
14.1 Timer X....................................................................................................103
14.1.1 Timer Mode ......................................................................................106
14.1.2 Pulse Output Mode...........................................................................107
14.1.3 Event Counter Mode.........................................................................109
14.1.4 Pulse Width Measurement Mode .....................................................110
14.1.5 Pulse Period Measurement Mode....................................................113
14.1.6 Notes on Timer X..............................................................................116
14.2 Timer Z....................................................................................................117
14.2.1 Timer Mode ......................................................................................122
14.2.2 Programmable Waveform Generation Mode....................................124
14.2.3 Programmable One-shot Generation Mode .....................................127
14.2.4 Programmable Wait One-Shot Generation Mode.............................130
14.2.5 Notes on Timer Z..............................................................................134
14.3 Timer C....................................................................................................135
14.3.1 Input Capture Mode..........................................................................141
14.3.2 Output Compare Mode.....................................................................143
14.3.3 Notes on Timer C .............................................................................145
15. Serial Interface 146
15.1 Clock Synchronous Serial I/O Mode .......................................................152
15.1.1 Polarity Select Function....................................................................155
15.1.2 LSB First/MSB First Select Function................................................155
15.1.3 Continuous Receive Mode ...............................................................156
A - 4
15.2 Clock Asynchronous Serial I/O (UART) Mode ........................................157
15.2.1 CNTR0 Pin Select Function..............................................................160
15.2.2 Bit Rate.............................................................................................161
15.3 Notes on Serial Interface......................................................................... 162
16. Comparator 163
16.1 One-Shot Mode.......................................................................................167
16.2 Repeat Mode........................................................................................... 169
16.3 Notes on Comparator..............................................................................171
17. Flash Memory Version 172
17.1 Overview.................................................................................................172
17.2 Memory Map...........................................................................................174
17.3 Functions to Prevent Rewriting of Flash Memory....................................176
17.3.1 ID Code Check Function ..................................................................176
17.3.2 ROM Code Protect Function ............................................................177
17.4 CPU Rewrite Mode..................................................................................178
17.4.1 EW0 Mode........................................................................................179
17.4.2 EW1 Mode........................................................................................179
17.4.3 Software Commands........................................................................188
17.4.4 Status Register.................................................................................192
17.4.5 Full Status Check .............................................................................193
17.5 Standard Serial I/O Mode........................................................................195
17.5.1 ID Code Check Function ..................................................................195
17.6 Parallel I/O Mode.....................................................................................199
17.6.1 ROM Code Protect Function ............................................................199
17.7 Notes on Flash Memory Version............................................................. 200
17.7.1 CPU Rewrite Mode...........................................................................200
18. Electrical Characteristics 202
19. Usage Notes 217
19.1 Notes on Clock Generation Circuit..........................................................217
19.1.1 Stop Mode and Wait Mode...............................................................217
19.1.2 Oscillation Stop Detection Function..................................................217
19.1.3 Oscillation Circuit Constants.............................................................217
19.1.4 High-Speed On-Chip Oscillator Clock..............................................217
A - 5
19.2 Notes on Interrupts..................................................................................218
19.2.1 Reading Address 00000h.................................................................218
19.2.2 SP Setting.........................................................................................218
19.2.3 External Interrupt and Key Input Interrupt ........................................218
19.2.4 Watchdog Timer Interrupt.................................................................218
19.2.5 Changing Interrupt Sources..............................................................219
19.2.6 Changing Interrupt Control Register Contents .................................220
19.3 Notes on Timers......................................................................................221
19.3.1 Notes on Timer X..............................................................................221
19.3.2 Notes on Timer Z..............................................................................222
19.3.3 Notes on Timer C .............................................................................222
19.4 Notes on Serial Interface......................................................................... 223
19.5 Notes on Comparator..............................................................................224
19.6 Notes on Flash Memory Version............................................................. 225
19.6.1 CPU Rewrite Mode...........................................................................225
19.7 Notes on Noise........................................................................................227
19.7.1 Inserting a Bypass Capacitor between VCC and VSS Pins as
a Countermeasure against Noise and Latch-Up ..............................227
19.7.2 Countermeasures against Noise Error of Port Control Registers.....227
20. Notes on On-chip Debugger 228
Appendix 1. Package Dimensions 229
Appendix 2. Connection Examples between Serial Writer and
On-Chip Debugging Emulator 231
Appendix 3. Example of Oscillation Evaluation Circuit 232
Register Index 233
A - 6
SFR Page Reference
Address Register Symbol Page
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 51
0005h Processor Mode Register 1 PM1 51
0006h System Clock Control Register 0 CM0 55
0007h System Clock Control Register 1 CM1 56
0008h
0009h Address Match Interrupt Enable Register AIER 93
000Ah Protect Register PRCR 71
000Bh
000Ch Oscillation Stop Detection Register OCD 57
000Dh Watchdog Timer Reset Register WDTR 99
000Eh Watchdog Timer Start Register WDTS 99
000Fh Watchdog Timer Control Register WDC 98
0010h Address Match Interrupt Register 0 RMAD0 93
0011h
0012h
0013h
0014h Address Match Interrupt Register 1 RMAD1 93
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 99
001Dh
001Eh
INT0 Input Filter Select Register
001Fh
0020h High-Speed On-Chip Oscillator Control
Register 0
0021h High-Speed On-Chip Oscillator Control
Register 1
0022h High-Speed On-Chip Oscillator Control
Register 2
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h Voltage Detection Register 1 VCA1 43
0032h Voltage Detection Register 2 VCA2
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register VW1C
0037h Voltage Monitor 2 Circuit Control Register VW2C 45
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
INT0F 85
HRA0 58
HRA1 59
HRA2 59
NOTE:
1. The blank regions are reserved. Do not access locations
in these regions.
Address Register Symbol Page
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC 77
004Eh Comparator Conversion Interrupt Control Registe r ADIC 77
004Fh
0050h Compare 1 Interrupt Control Register CMP1IC 77
0051h UART0 Transmit Interrupt Control Register S0TIC 77
0052h UART0 Receive Interrupt Control Register S0RIC 77
0053h UART1 Transmit Interrupt Control Register S1TIC 77
0054h UART1 Receive Interrupt Control Register S1RIC 77
0055h
0056h Timer X Interrupt Control Register TXIC 77
0057h
0058h Timer Z Interrupt Control Registe r TZIC 77
0059h
INT1 Interrupt Control Register
005Ah
INT3 Interrupt Control Register
005Bh Timer C Interrupt Control Register TCIC 77
005Ch Compare 0 Interrupt Control Register CMP0IC 77
005Dh
INT0 Interrupt Control Register
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
43
44
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
INT1IC 77
INT3IC 77
INT0IC 78
B - 1
Address Register Symbol Page
0080h Timer Z Mode Register TZMR 118
0081h
0082h
0083h
0084h Timer Z Waveform Output Control Register PUM 120
0085h Prescaler Z Register PREZ 119
0086h Timer Z Secondary Register TZSC 119
0087h Timer Z Primary Register TZPR 119
0088h
0089h
008Ah Timer Z Output Control Register TZOC 120
008Bh Timer X Mode Register TXMR 104
008Ch Prescaler X Register PREX 105
008Dh Timer X Register TX 105
008Eh Timer Count Source Set Register TCSS 105,121
008Fh
0090h Timer C Register TC 137
0091h
0092h
0093h
0094h
0095h
0096h External Input Enable Register INTEN 85
0097h
0098h Key Input Enable Register KIEN 91
0099h
009Ah Timer C Control Register 0 TCC0 138
009Bh Timer C Control Register 1 TCC1 139
009Ch Capture, Compare 0 Register TM0 137
009Dh
009Eh Compare 1 Register TM1 137
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 149
00A1h UART0 Bit Rate Register U0BRG 148
00A2h UART0 Transmit Buffer Register U0TB 148
00A3h
00A4h UART0 Transmit/Receive Control Register 0 U0C0 150
00A5h UART0 Transmit/Receive Control Register 1 U0C1 151
00A6h UART0 Receive Buffer Register U0RB 148
00A7h
00A8h UART1 Transmit/Receive Mode Register U1MR 149
00A9h UART1 Bit Rate Register U1BRG 148
00AAh UART1 Transmit Buffer Register U1TB 148
00ABh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 150
00ADh UART1 Transmit/Receive Control Register 1 U1C1 151
00AEh UART1 Receive Buffer Register U1RB 148
00AFh
00B0h UART Transmit/Receive Control Register 2 UCON 151
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
NOTE:
1. The blank regions, 0100h to 01AFh, and 01C0h to 02FFh
are reserved. Do not access locations in these regions.
Address Register Symbol Page
00C0h A/D Register AD 166
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h A/D Control Register 2 ADCON2 166
00D5h
00D6h A/D Control Register 0 ADCON0 165
00D7h A/D Control Register 1 ADCON1 165
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h Port P1 Register P1 33
00E2h
00E3h Port P1 Direction Register PD1 33
00E4h
00E5h Port P3 Register P3 33
00E6h
00E7h Port P3 Direction Register PD3 33
00E8h Port P4 Register P4 33
00E9h
00EAh Port P4 Direction Register PD4 33
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh Pull-Up Control Register 0 PUR0 34
00FDh Pull-Up Control Register 1 PUR1 34
00FEh Port P1 Drive Capacity Control Register DRR 34
00FFh Timer C Output Control Register TCOUT 140
01B3h Flash Memory Control Register 4 FMR4 184
01B4h
01B5h Flash Memory Control Register 1 FMR1 183
01B6h
01B7h Flash Memory Control Register 0 FMR0 182
0FFFFh Optional Function Select Register OFS 98,177
B - 2
R8C/18 Group, R8C/19 Group
REJ09B0222-0130
SINGLE-CHIP 16-BIT CMOS MCU
Apr 14, 2006
1. Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the
R8C/Tiny Series CPU core, and is packaged in a 20-pin molded-plastic LSSOP, SDIP or a 28-pin plastic
molded-HWQFN. It implements sophisticated instructions for a high level of instruction efficiency. With 1
Mbyte of address space, they are capable of executing instructions at high speed.
Furthermore, the R8C/19 Group has on-chip data flash ROM (1 KB × 2 blocks).
The difference between the R8C/18 Group and R8C/19 Group is only the presence or absence of data
flash ROM. Their peripheral functions are the same.
1.1 Applications
Electric household appliances, office equipment, housing equipment (sensors, security systems), general
industrial equipment, audio equipment, etc.
Rev.1.30
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R8C/18 Group, R8C/19 Group 1. Overview
1.2 Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/18 Group and Table 1.2 outlines the
Functions and Specifications for R8C/19 Group.
Table 1.1 Functions and Specifications for R8C/18 Group
Item Specification
CPU Number of fundamental
instructions
Minimum instruction execution
time
Operation mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.3 Product Information for R8C/18
Peripheral
Functions
Electric
Characteristics
Flash Memory
Operating Ambient Temperature -20 to 85°C
Package 20-pin molded-plastic LSSOP
Ports I/O ports: 13 pins (including LED drive port)
LED drive ports I/O ports: 4 pins
Timers Timer X: 8 bits × 1 channel, timer Z: 8 bits × 1 channel
Serial interfaces 1 channel
Comparator 1-bit comparator: 1 circuit, 4 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
Interrupts Internal: 10 sources, External: 4 sources, Software: 4
Clock generation circuits 2 circuits
Oscillation stop detection
function
Voltage detection circuit On-chip
Power-on reset circuit On-chip
Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
Current consumption
Programming and erasure voltage
Programming and erasure
endurance
89 instructions
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Group
Input port: 3 pins
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits × 1 channel
(Input capture and output compare circuits)
Clock synchronous serial I/O, UART
1 channel
UART
Reset start selectable, count source protection mode
sources,
Priority levels: 7 levels
• Main clock oscillation circuit (with on-chip feedback
resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency
adjustment function
Main clock oscillation stop detection function
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Typ. 9 mA
Typ. 5 mA
Typ. 35 µA (VCC = 3.0 V, wait mode, peripheral clock off)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
VCC = 2.7 to 5.5 V
100 times
-40 to 85°C (D version)
20-pin molded-plastic SDIP
28-pin molded-plastic HWQFN
(VCC = 5.0 V, f(XIN) = 20 MHz, comparator stopped)
(VCC = 3.0V, f(XIN) = 10 MHz, comparator stopped)
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Table 1.2 Functions and Specifications for R8C/19 Group
Item Specification
CPU Number of fundamental
instructions
Minimum instruction
execution time
Operation mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.4 Product Information for R8C/19
Peripheral
Functions
Electric
Characteristics
Flash Memory
Operating Ambient Temperature -20 to 85°C
Package 20-pin molded-plastic LSSOP
Ports I/O ports: 13 pins (including LED drive port)
LED drive ports I/O ports: 4 pins
Timers Timer X: 8 bits × 1 channel, timer Z: 8 bits × 1 channel
Serial interfaces 1 channel
Comparator 1-bit comparator: 1 circuit, 4 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
Interrupts Internal: 10 sources, External: 4 sources , Software: 4
Clock generation circuits 2 circuits
Oscillation stop detection
function
Voltage detection circuit On-chip
Power-on reset circuit On-chip
Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
Current consumption
Programming and erasure voltage
Programming and erasure
endurance
89 instructions
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Group
Input port: 3 pins
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits × 1 channel
(Input capture and output compare circuits)
Clock synchronous serial I/O, UART
1 channel
UART
Reset start selectable, count source protection mode
sources,
Priority levels: 7 levels
• Main clock generation circuit (with on-chip feedback
resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency
adjustment function
Main clock oscillation stop detection function
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Typ. 9 mA
Typ. 5 mA
Typ. 35 µA
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
VCC = 2.7 to 5.5 V
10,000 times (data flash)
1,000 times (program ROM)
-40 to 85°C (D version)
20-pin molded-plastic SDIP
28-pin molded-plastic HWQFN
(VCC = 5.0 V, f(XIN) = 20 MHz, comparator stopped)
(VCC = 3.0 V, f(XIN) = 10MHz, comparator stopped)
(VCC = 3.0 V, wait mode, peripheral clock off)
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R8C/18 Group, R8C/19 Group 1. Overview
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
I/O ports Port P1
Peripheral Functions
Timers
Timer X (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
Watchdog timer
(15 bits)
Comparator
(1 bit
× 4 channels)
UART or
clock synchronous serial I/O
(8 bits
(8 bits
R8C/Tiny Series CPU core
R0H R0L
R1H
R2
R3
A0
A1
FB
8
× 1 channel)
UART
× 1 channel)
R1L
4
Port P3 Port P4
System clock generator
XIN-XOUT
High-speed on-chip
oscillator
Low-speed on-chip
oscillator
Memory
SB
USP
ISP
INTB
PC
FLG
ROM
RAM
Multiplier
1 3
(1)
(2)
Figure 1.1 Block Diagram
NOTES:
1. ROM size varies with MCU t y pe .
2. RAM size varies with MCU type.
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R8C/18 Group, R8C/19 Group 1. Overview
1.4 Product Information
Table 1.3 lists Product Information for R8C/18 Group and Table 1.4 lists Product Information for R8C/19
Group.
Table 1.3 Product Information for R8C/18 Group Current of Apr. 2006
Type No. ROM Capacity RAM Capacity Package Type Remarks
R5F21181SP 4 Kbytes 384 bytes PLSP0020JB-A Flash memory version
R5F21182SP 8 Kbytes 512 bytes PLSP0020JB-A
R5F21183SP 12 Kbytes 768 bytes PLSP0020JB-A
R5F21184SP 16 Kbytes 1 Kbyte PLSP0020JB-A
R5F21181DSP (D) 4 Kbytes 384 bytes PLSP0020JB-A D version
R5F21182DSP (D) 8 Kbytes 512 bytes PLSP0020JB-A
R5F21183DSP (D) 12 Kbytes 768 bytes PLSP0020JB-A
R5F21184DSP (D) 16 Kbytes 1 Kbyte PLSP0020JB-A
R5F21181DD 4 Kbytes 384 bytes PRDP0020BA-A Flash memory version
R5F21182DD 8 Kbytes 512 bytes PRDP0020BA-A
R5F21183DD 12 Kbytes 768 bytes PRDP0020BA-A
R5F21184DD 16 Kbytes 1 Kbyte PRDP0020BA-A
R5F21182NP 8 Kbytes 512 bytes PWQN0028KA-B Flash memory version
R5F21183NP 12 Kbytes 768 bytes PWQN0028KA-B
R5F21184NP 16 Kbytes 1 Kbyte PWQN0028KA-B
(D): Under Development
Type No. R 5 F 21 18 4 D SP
Package type:
SP: PLSP0020JB-A
DD: PRDP0020BA-A
NP: PWQN0028KA-B
Classification
D: Operating ambient temperature -40°C to 85°C
No Symbol: Operating ambient temperature -20°C to 85°C
ROM capa city
2: 8 KB
3: 12 KB
4: 16 KB
R8C/18 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductors
Figure 1.2 Type Number, Memory Size, and Package of R8C/18 Group
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Table 1.4 Product Information for R8C/19 Group Current of Apr. 2006
Type No.
ROM Capacity
Program ROM
Data flash
RAM
Capacity
Package Type Remark s
R5F21191SP 4 Kbytes 1 Kbyte × 2 384 bytes PLSP0020JB-A Flash memory version
R5F21192SP 8 Kbytes 1 Kbyte × 2 512 bytes PLSP0020JB-A
R5F21193SP 12 Kbytes 1 Kbyte × 2 768 bytes PLSP0020JB-A
R5F21194SP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLSP0020JB-A
R5F21191DSP (D) 4 Kbytes 1 Kbyte × 2 384 bytes PLSP0020JB-A D version
R5F21192DSP (D) 8 Kbytes 1 Kbyte × 2 512 bytes PLSP0020JB-A
R5F21193DSP (D) 12 Kbytes 1 Kbyte × 2 768 bytes PLSP0020JB-A
R5F21194DSP (D) 16 Kbytes 1 Kbyte × 2 1 Kbyte PLSP0020JB-A
R5F21191DD 4 Kbytes 1 Kbyte × 2 384 bytes PRDP0020BA-A Flash memory version
R5F21192DD 8 Kbytes 1 Kbyte × 2 512 bytes PRDP0020BA-A
R5F21193DD 12 Kbytes 1 Kbyte × 2 768 bytes PRDP0020BA-A
R5F21194DD 16 Kbytes 1 Kbyte × 2 1 Kbyte PRDP0020BA-A
R5F21192NP 8 Kbytes 1 Kbyte × 2 512 bytes PWQN0028KA-B Flash memory version
R5F21193NP 12 Kbytes 1 Kbyte × 2 768 bytes PWQN0028KA-B
R5F21194NP 16 Kbytes 1 Kbyte × 2 1 Kbyte PWQN002 8KA-B
(D): Under Development
Type No. R 5 F 21 19 4 D SP
Package type:
SP: PLSP0020JB-A
DD: PRDP0020BA-A
NP: PWQN0028KA-B
Classification
D: Operating ambient temperature -40°C to 85°C
No Symbol: Operating ambient temperature -20
ROM capacity
2: 8 KB
3: 12 KB
4: 16 KB
R8C/19 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MC U
Renesas sem icon ductors
Figure 1.3 Type Number, Memory Size, and Package of R8C/19 Group
°C to 8 5 ° C
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R8C/18 Group, R8C/19 Group 1. Overview
1.5 Pin Assignments
Figure 1.4 shows Pin Assignments for PLSP0020JB-A Package (Top View), Figure 1.5 shows Pin
Assignments for PRDP0020BA-A Package (Top View) and Figure 1.6 shows Pin Assignments for
PWQN0028KA-B Package (Top View).
PIN assignments (top view)
P3_5/CMP1_2
P3_7/CNTR0/TXD1
RESET
XOUT/P4_7
VSS/AVSS
XIN/P4_6
VCC/AVCC
MODE
P4_5/INT0/RXD1
P1_7/CNTR00/INT10
1
2
3
(1)
4
5
6
7
8
9
10
R8C/18 Group
R8C/19 Group
20 P3_4/CMP1_1
19 P3_3/TCIN/INT3/CMP1_0
18 P1_0/KI0/AN8/CMP0_0
17
16 P4_2/VREF
15 P1_2/KI2/AN10/CMP0_2
14 P1_3/KI3/AN11/TZOUT
13 P1_4/TXD0
12 P1_5/RXD0/CNTR01/INT11
11 P1_6/CLK0
NOTE:
1. P4_7 is an input-only port.
Package: PLSP0020JB-A(20P2F-A)
Figure 1.4 Pin Assignments for PLSP0020JB-A Package (Top View)
P1_1/KI1/AN9/CMP0_1
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PIN assignments (top view)
P3_5/CMP1_2
P3_7/CNTR0/TXD1
RESET
XOUT/P4_7
VSS/AVSS
XIN/P4_6
VCC/AVCC
MODE
P4_5/INT0/RXD1
P1_7/CNTR00/INT10
1
2
3
R8C/18 Group
(1)
4
5
6
7
8
9
10
R8C/19 Group
20 P3_4/CMP1_1
19 P3_3/TCIN/INT3/CMP1_0
18 P1_0/KI0/AN8/CMP0_0
17 P1_1/KI1/AN9/CMP0_1
16 P4_2/VREF
15 P1_2/KI2/AN10/CMP0_2
14 P1_3/KI3/AN11/TZOUT
13 P1_4/TXD0
12 P1_5/RXD0/CNTR01/INT11
11 P1_6/CLK0
NOTE:
1. P4_7 is an input-only port.
Package: PRDP0020BA-A(20P4B)
Figure 1.5 Pin Assignments for PRDP0020BA-A Package (Top View)
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R8C/18 Group, R8C/19 Group 1. Overview
PIN Assignment (top view)
P1_3/AN11/KI3/TZOUT
P1_2/AN10/KI2/CMP0_2
NC
NC
P4_2/VREF
NC
21 20 19 18 17 16 15
NC
P1_1/AN9/KI1/CMP0_1
P1_0/AN8/KI0/CMP0_0
P3_3/TCIN/INT3/CMP1_0
P3_4/CMP1_1
P3_5/CMP1_2
P3_7/CNTR0/TXD1
RESET
22
23
24
25
26
27
28
R8C/18 Group
R8C/19 Group
1 2 3 4 5 6 7
(1)
NC
XOUT/P4_7
NC
VSS/AVSS
NOTES:
1. P4_7 is a port for the input.
NC
XIN/P4_6
14
13
12
11
10
9
8
NC
P1_4/TXD0
P1_5/RXD0/CNTR01/INT11
P1_6/CLK0
P1_7/CNTR00/INT10
P4_5/INT0/RXD1
MODE
VCC/AVCC
Package: PWQN0028KA-B(28PJW-B)
Figure 1.6 Pin Assignments for PWQN0028KA-B Package (Top View)
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R8C/18 Group, R8C/19 Group 1. Overview
1.6 Pin Functions
Table 1.5 lists Pin Functions, Table 1.6 lists Pin Name Information by Pin Number of PLSP0020JB-A,
PRDP0020BA-A packages, and Table 1.7 lists Pin Name Information by Pin Number of PWQN0028KAB package.
Table 1.5 Pin Functions
Type Symbol I/O Type Description
Power supply input VCC
VSS
Analog power
supply input
Reset input RESET
MODE MODE I Connect this pin to VCC via a resistor.
Main clock input XIN I These pins are provided for main clock generation
Main clock output XOUT O
INT
interrupt INT0, INT1, INT3 IINT interrupt input pins
Key input interrupt KI0
Timer X CNTR0 I/O Timer X I/O pin
Timer Z TZOUT O Timer Z output pin
Timer C TCIN I Timer C input pin
Serial interface CLK0 I/O Transfer clock I/O pin
Reference voltage
input
Comparator AN8 to AN11 I Analog input pins to comparator
I/O port P1_0 to P1_7, P3_3
Input port P4_2, P4_6, P4_7 I Input-only ports
I: Input O: Output I/O: Input and outpu t
AVCC, A VSS I Power supply for the comparator
to KI3 I Key input interrupt input pins
CNTR0
CMP0_0 to CMP0_2,
CMP1_0 to CMP1_2
RXD0, RXD1 I Serial data input pins
TXD0, TXD1 O Serial data output pins
VREF I Reference voltage input pin to comparator
to P3_5, P3_7, P4_5
I Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to
the VSS pin.
Connect a capacitor between AVCC and AVSS.
I Input “L” on this pin resets the MCU.
circuit I/O. Connect a ceramic resonator or a
crystal oscillator between the XIN and XOUT pins.
To use an external clock, input it to the XIN pin
and leave the XOUT pin open.
O Timer X output pin
O Timer C output pins
I/O CMOS I/O ports. Each port has an I/O select
direction register, allowing each pin in the port to
be directed for input or output individually.
Any port set to input can be set to use a pull-up
resistor or not by a program.
P1_0 to P1_3 also function as LED drive ports.
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R8C/18 Group, R8C/19 Group 1. Overview
Table 1.6 Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A packages
Pin
Number
1 P3_5 CMP1_2
2P3_7
3
4XOUTP4_7
5 VSS/AVSS
6XINP4_6
7 VCC/AVCC
8MODE
9P4_5
10 P1_7
11 P1_6 CLK0
12 P1_5
13 P1_4 TXD0
14 P1_3
15 P1_2
16 VREF P4_2
17 P1_1
18 P1_0
19 P3_3
20 P3_4 CMP1_1
Control
Pin
RESET
Port
Interrupt Timer Serial Interface Comparator
INT0
INT10
INT11
KI3
KI2
KI1
KI0
INT3
I/O Pin Functions for Peripheral Modules
CNTR0
CNTR00
CNTR01 RXD0
TZOUT AN11
CMP0_2 AN10
CMP0_1 AN9
CMP0_0 AN8
TCIN/CMP1_0
TXD1
RXD1
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Table 1.7 Pin Name Information by Pin Number of PWQN0028KA-B package
Pin
Number
1NC
2XOUTP4_7
3
4NC
5NC
6XINP4_6
7NC
8 VCC/AVCC
9MODE
10 P4_5
11 P1_7
12 P1_6 CLK0
13 P1_5
14 P1_4 TXD0
15 NC
16 P1_3
17 P1_2
18 NC
19 NC
20 VREF P4_2
21 NC
22 P1_1
23 P1_0
24 P3_3
25 P3_4 CMP1_1
26 P3_5 CMP1_2
27 P3_7
28
Control
Pin
VSS/AVSS
RESET
Port
Interrupt Timer Serial Interface Comparator
INT0
INT10
INT11
KI3
KI2
KI1
KI0
INT3
I/O Pin of Peripheral Function
RXD1
CNTR00
CNTR01 RXD0
TZOUT AN11
CMP0_2 AN10
CMP0_1 AN9
CMP0_0 AN8
TCIN/CMP1_0
CNTR0
TXD1
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R8C/18 Group, R8C/19 Group 2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB
configure a register bank. There are two sets of register bank.
b31
R2
R3
b15 b8b7
R0H (high-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R0L (low-order of R0)
R2
R3
A0
A1
FB
b15b19
INTBH
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
b19
INTBL
PC
b15
USP
ISP
SB
b0
Data registers
Address registers
Frame base register
b0
Interrupt table register
b0
Program counter
b0
User stack pointer
Interrupt stack pointer
Static base register
(1)
(1)
(1)
b15
IPL
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
b15
b0
FLG
b8
b7
b0
C
DZSBOIU
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
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R8C/18 Group, R8C/19 Group 2. Central Processing Unit (CPU)
2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. T he same applies to R1 to R3. R0
can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data
registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a
32-bit data register (R2R0). R3R1 is analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
It is also used for transfer, arithmetic and logic operations. A1 is analogous to A0. A1 can be combined
with A0 and used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide, indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch
between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bits that have been generated by the arithmetic and logic
unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when the operation results in an overflow; otherwise to 0.
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R8C/18 Group, R8C/19 Group 2. Central Processing Unit (CPU)
2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is
set to 0 when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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