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REJ09B0250-0200
R8C/20 Group, R8C/21 Group
16
Hardware Manual
RENESAS MCU
R8C FAMILY / R8C/2x SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev.2.00
Revision Date: Aug 27, 2008
www.renesas.com
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Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Page 3
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
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How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/20 Group and R8C/21 Group. Make sure to refer to the latest versions of
these documents. The newest versions of the documents li sted may be obtained fro m the Renesas Technology Web
site.
Document Type Description Document Title Document No.
Datasheet Hardware overview and electrical characteristics R8C/20 Group,
R8C/21 Group
Datasheet
Hardware manual Hardware specifications (pin assignments,
memory maps, peripheral function
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
Software manual Description of CPU instruction set R8C/Tiny Series
Application note Information on using peripheral functions and
application examples
Sample programs
Information on writing programs in assembly
language and C
Renesas
technical update
Product specifications, updates on documents,
etc.
R8C/20 Group,
R8C/21 Group
Hardware Manual
Software Manual
Available from Renesas
Technology Web site.
REJ03B0120
This hardware
manual
REJ09B0001
Page 5
2. Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “b” is appended to numeric valu es given i n binary format. However, nothing is appended to the
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
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3. Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
0
XXX0
XXX1
(b2)
(b3)
XXX4
XXX5
XXX6
XXX7
*1
Symbol Address After Reset
XXX XXX 00h
Bit NameBit Symbol
XXX bits
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Reserved bits
XXX bits
XXX bit
b1 b0
1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
Set to 0.
Function varies according to the operating
mode.
0: XXX
1: XXX
Function
RW
RW
RW
RW
RW
WO
RW
RO
*2
*3
*4
*1
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2
RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
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4. List of Abbreviations and Acronyms
Abbreviation Full Form
ACIA Asynchronous Communication Interface Adapter
bps bits per second
CRC Cyclic Redundancy Check
DMA Direct Memory Access
DMAC Direct Memory Access Controller
GSM Global System for Mobile Communications
Hi-Z High Impedance
IEBus Inter Equipment Bus
I/O Input / Output
IrDA Infrared Data Association
LSB Least Significant Bit
MSB Most Significant Bit
NC Non-Connect
PLL Phase Locked Loop
PWM Pulse Width Modulation
SIM Subscriber Identity Module
UART Universal Asynchronous Receiver / Transmitter
VCO Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.All trademarks and registered trademarks are the property of their respective owners.
Page 8
Table of Contents
SFR Page Reference ........................................................................................................................... B - 1
1. Overview ......................... ............................................. .............................................................. ... .. 1
1.1 Applications ............................................................................................................................................... 1
1.2 Performance Overview .............................................................................................................................. 2
1.3 Block Diagram ......................................... .................................. ............................................................... 4
1.4 Product Information .................................................................................................................................. 5
1.5 Pin Assignments ........................................................................................................................................ 7
1.6 Pin Functions ............................................................................................................................................. 8
2. Central Processing Unit (CPU) ........................................ ... ... ... .......................................... ... ....... 10
2.1 Data Registers (R0, R1, R2 and R3) ....................................................................................................... 11
2.2 Address Registers (A0 and A1) ............................................................................................................... 11
2.3 Frame Base Register (FB) ....................................................................................................................... 11
2.4 Interrupt Table Register (INTB) .............................................................................................................. 11
2.5 Program Counter (PC) ................................................................... .......................................................... 11
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................. 11
2.7 Static Base Register (SB) ....................................................................................... ................................. 11
2.8 Flag Register (FLG) ................................................................................................................................ 11
2.8.1 Carry Flag (C) ..................................................................................................................................... 11
2.8.2 Debug Flag (D) ................................................................................................................................... 11
2.8.3 Zero Flag (Z) ....................................................................................................................................... 11
2.8.4 Sign Flag (S) ....................................................................................................................................... 11
2.8.5 Register Bank Select Flag (B) ............................................................................................................ 11
2.8.6 Overflow Flag (O) .............................................................................................................................. 11
2.8.7 Interrupt Enable Flag (I) ................................................................... .................................................. 12
2.8.8 Stack Pointer Select Flag (U) .............................................................................................................. 12
2.8.9 Processor Interrupt Priority Level (IPL) ........................................... .................................. ................ 12
2.8.10 Reserved Bit ................................................................ ........................................................................ 12
3. Memory ..................................... ............................................. ....................................................... 13
3.1 R8C/20 Group ......................................................................................................................................... 13
3.2 R8C/21 Group ......................................................................................................................................... 14
4. Special Function Registers (SFRs) ............................................................................................... 15
5. Resets ....................................... .......................... .......................... ......................... ....................... 21
5.1 Hardware Reset ....................................................................................................................................... 24
5.1.1 When Power Supply is Stable .................................................................... ......................................... 24
5.1.2 Power On ............................................................................................................................................ 24
5.2 Power-On Reset Function ....................................................................................................................... 26
5.3 Voltage Monitor 1 Reset ......................................................................................................................... 27
5.4 Voltage Monitor 2 Reset ......................................................................................................................... 27
5.5 Watchdog Timer Reset ............................................................................................................................ 27
5.6 Software Reset ......................................................................................................................................... 27
6. Voltage Detection Circuit .............................................................................................................. 28
6.1 VCC Input Voltage .................................................................................................................................. 34
6.1.1 Monitoring Vdet1 ............................................................ .................................. ................................. 34
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6.1.2 Monitoring Vdet2 ............................................................ .................................. ................................. 34
6.2 Voltage Monitor 1 Reset ......................................................................................................................... 35
6.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..................................................................... 36
7. Programmable I/O Ports ............................................................................................................... 38
7.1 Functions of Programmable I/O Ports ..................................................................................................... 38
7.2 Effect on Peripheral Functions ................................................................................................................ 39
7.3 Pins Other than Programmable I/O Ports ................................................................................................ 39
7.4 Port Settings ..................................... ................................. .................................. .................................... 50
7.5 Unassigned Pin Handling ........................................................................................................................ 61
8. Processor Mode ............................................................................................................................ 62
8.1 Processor Modes .................................... .................................. .................................. .............................. 62
9. Bus ..................................... ................. ................ ................ ................ ................ .......................... 63
10. Clock Generation Circuit ............................................................................................................... 64
10.1 XIN Clock ..................................... .................................. ................................. ....................................... 71
10.2 On-Chip Oscillator Clocks ...................................................................................................................... 72
10.2.1 Low-Speed On-Chip Oscillator Clock ................................................................................................ 72
10.2.2 High-Speed On-Chip Oscillator Clock ............................................................................................... 72
10.3 CPU Clock and Peripheral Function Clock ............................................................................................. 73
10.3.1 System Clock ...................................................................................................................................... 73
10.3.2 CPU Clock ........................................................................................ .................................................. 73
10.3.3 Peripheral Function Clock (f1, f2, f4, f8 and f32) .............................................................................. 73
10.3.4 fOCO ................................................................................................................................................... 73
10.3.5 fOCO40M ........................................................................................................................................... 73
10.3.6 fOCO-F ............................................................................................................................................... 73
10.3.7 fOCO-S ............................................................................................................................................... 73
10.3.8 fOCO128 ............................................................................................................................................. 73
10.4 Power Control .......................................................................................................................................... 74
10.4.1 Standard Operating Mode ................................................................................................................... 74
10.4.2 Wait Mode ................................................................................ .......................................................... 75
10.4.3 Stop Mode ........................................................................................................................................... 79
10.5 Oscillation Stop Detection Function ....................................................................................................... 82
10.5.1 How to Use Oscillation Stop Detection Function ............................................................................... 82
10.6 Notes on Clock Generation Circuit ......................................................................................................... 85
10.6.1 Stop Mode ........................................................................................................................................... 85
10.6.2 Wait Mode ................................................................................ .......................................................... 85
10.6.3 Oscillation Stop Detection Function ................................................................................................... 85
10.6.4 Oscillation Circuit Constants .............................................................................................................. 85
11. Protection ........................ ................ ................ ................. ................ ................ ............................. 86
12. I nterrupts ...................... ....................... ...................... .......................... .......................................... 87
12.1 Interrupt Overview .................................................................................................................................. 87
12.1.1 Types of Interrupts .............................................................................................................................. 87
12.1.2 Software Interrupts ............................................................................................................................. 88
12.1.3 Special Interrupts ................................................................................................................................ 89
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12.1.4 Peripheral Function Interrupt .............................................................................................................. 89
12.1.5 Interrupts and Interrupt Vector ........................................................................................................... 90
12.1.6 Interrupt Control ........................................ .. .................................. ..................................................... 92
12.2 INT
12.2.1 INTi
12.2.2 INTi
Interrupt ......................................................................................................................................... 101
Interrupt (i = 0 to 3) .................................................................................................................. 101
Input Filter (i = 0 to 3) ................................................... .................................. ... ...................... 103
12.3 Key Input Interrupt ............................................................................................................ .................... 104
12.4 Address Match Interrupt ........................... ............................................................................................. 106
12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts and I
2
C bus Interface
Interrupts (Interrupts with Multiple Interrupt Request Sources) ........................................................... 108
12.6 Notes on Interrupts ................................................................................................................................ 110
12.6.1 Reading Address 00000h .................................................................................................................. 110
12.6.2 SP Setting .......................................................................................................................................... 110
12.6.3 External Interrupt and Key Input Interrupt ....................................................................................... 110
12.6.4 Changing Interrupt Sources .............................................................................................................. 111
12.6.5 Changing Interrupt Control Register Contents ................................................................................. 112
13. Watchdog Timer ........................................................................................................................... 113
13.1 Count Source Protection Mode Disabled .............................................................................................. 116
13.2 Count Source Protection Mode Enabled ............................................................................................... 117
14. Timers ....................... .................................................................... ............................................... 118
14.1 Timer RA ............................................................................................................................................... 120
14.1.1 Timer Mode ...................................................................................................................................... 124
14.1.2 Pulse Output Mode ..................................................... ................................. ..................................... 126
14.1.3 Event Counter Mode ......................................................................................................................... 128
14.1.4 Pulse Width Measurement Mode .............................................................................................. ........ 130
14.1.5 Pulse Period Measurement Mode ..................................................................................................... 133
14.1.6 Notes on Timer RA ........................................................................................................................... 136
14.2 Timer RB ......................................................................................................................................... ...... 137
14.2.1 Timer Mode ...................................................................................................................................... 141
14.2.2 Programmable Waveform Generation Mode ....................................... .................................. ........... 144
14.2.3 Programmable One-shot Generation Mode ...................................................................................... 147
14.2.4 Programmable Wait One-shot Generation Mode ............................................................................. 151
14.2.5 Notes on Timer RB ........................................................................................................................... 155
14.3 Timer RD ............................................................................................................................................... 159
14.3.1 Count Source .................................................................................................................... ................. 164
14.3.2 Buffer Operation .............................................................................................................. ................. 165
14.3.3 Synchronous Operation ........................ .................................. ........................................................... 167
14.3.4 Pulse Output Forced Cutoff .............................................................................................................. 168
14.3.5 Input Capture Function ............................................................................................................... ...... 170
14.3.6 Output Compare Function ......................... ................................................................... .................... 184
14.3.7 PWM Mode ........................................................... .................................. .................................. ........ 200
14.3.8 Reset Synchronous PWM Mode ....................................................................................................... 213
14.3.9 Complementary PWM Mode ............................................................................................................ 223
14.3.10 PWM3 Mode ....................................................................................................................... .............. 237
14.3.11 Timer RD Interrupt ........................................................................................................................... 249
14.3.12 Notes on Timer RD ................................................................................................................... ........ 251
14.4 Timer RE .................................................................................................................................... ........... 257
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14.4.1 Output Compare Mode ...................................................................................... ... ............................ 258
14.4.2 Notes on Timer RE ........................................................................................................................... 264
15. Serial Interface ............................................................................................................................ 265
15.1 Clock Synchronous Serial I/O Mode .............. ....................................................................................... 271
15.1.1 Polarity Select Function .................................................................................................................... 274
15.1.2 LSB First/MSB First Select Function ............................................................................................... 274
15.1.3 Continuous Receive Mode ................................................................................................................ 275
15.2 Clock Asynchronous Serial I/O (UART) Mode .......................................... .......................................... 276
15.2.1 Bit Rate .................................................................... .................................. ....................................... 280
15.3 Notes on Serial Interface ....................................................................................................................... 281
16. Cloc k Synchronous Serial Interface ............................................................................................ 282
16.1 Mode Selection ...................................................................................................................................... 282
16.2 Clock Synchronous Serial I/O with Chip Select (SSU) ........................................................................ 283
16.2.1 Transfer Clock .................................................................................................................................. 292
16.2.2 SS Shift Register (SSTRSR) ............................................................................................................. 294
16.2.3 Interrupt Requests ............................................................................. ............................... ................. 295
16.2.4 Communicatio n Modes and Pin Functions ....................................................................................... 296
16.2.5 Clock Synchronous Communication Mode ...................................................................................... 297
16.2.6 Operation in 4-Wire Bus Communication Mode .............................................................................. 304
16.2.7 SCS
Pin Control and Arbitration ...................................................................................................... 310
16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 311
16.3 I
2
C Bus Interface ................................................................................................................................... 312
16.3.1 Transfer Clock .................................................................................................................................. 322
16.3.2 Interrupt Requests ............................................................................. ............................... ................. 323
16.3.3 I
2
C Bus Interface Mode .................................................................................................................... 324
16.3.4 Clock Synchronous Serial Mode ...................................................................................................... 335
16.3.5 Noise Canceller ................................................................................................................................. 338
16.3.6 Bit Synchronization Circuit .............................................................................................................. 339
16.3.7 Examples of Register Setting ............................................................................................................ 340
16.3.8 Notes on I
2
C Bus Interface ............................................................................................................... 344
17. H ardw are LI N ......................... ... ... ... .... ... ... ... ... ....................................... ... .... ... ... ... .... ................. 345
17.1 Features ............................................................................................................................. .................... 345
17.2 I nput/Output Pins .................................................................................. ................................................ 346
17.3 Register Configuration .................................................................................................................. ........ 347
17.4 Functional Description .......................................................................................................................... 349
17.4.1 Master Mode ..................................................................................................................................... 349
17.4.2 Slave Mode ....................................................................................................................................... 352
17.4.3 Bus Collision Detection Function ..................................................................................................... 356
17.4.4 Hardware LIN End Processing ...................................................................................................... ... 357
17.5 I nterrupt Requests ......... .................................. .................................. ..................................................... 358
17.6 Notes on Hardware LIN ................................................................................................................ ........ 359
18. A/D Converter ............................................................................................................................. 360
18.1 One-Shot Mode ..................................................................................................................................... 364
18.2 Repeat Mode .................................................................................................................................. ........ 367
18.3 S ample and Hold .................................................... .................................. ............................................. 370
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18.4 A/D Conversion Cycles .................................... ..................................................................................... 371
18.5 Internal Equivalent Circuit of Analog Input .......................................................................................... 372
18.6 Output Impedance of Sensor Under A/D Conversion ........................................................................... 373
18.7 Notes on A/D Converter ........................................................................................................................ 374
19. Flash Memory ............................................................................................................................. 375
19.1 Overview ................................................................................................................................. .............. 375
19.2 Memory Map ............................................... .......................................................................................... 377
19.3 Functions to Prevent Rewriting of Flash Memory ................................................................................ 380
19.3.1 ID Code Check Function .................................................................................................................. 380
19.3.2 ROM Code Protect Function ............................................................................................................ 381
19.4 CPU Rewrite Mode ........................................................... .................................. .................................. 382
19.4.1 EW0 Mode .......................................................................................................................... .............. 383
19.4.2 EW1 Mode .......................................................................................................................... .............. 383
19.4.3 Software Commands ......................................................................................................................... 392
19.4.4 Status Registers ................................................................................................................................. 397
19.4.5 Full Status Check .............................................................................................................................. 398
19.5 Standard Serial I/O Mode ...................................................................................................................... 400
19.5.1 ID Code Check Function .................................................................................................................. 400
19.6 P arallel I/O Mode .................................................................................................................................. 404
19.6.1 ROM Code Protect Function ............................................................................................................ 404
19.7 Notes on Flash Memory ........................................................................................................................ 405
19.7.1 CPU Rewrite Mode ......................................... .................................................................................. 405
20. Electrical Characteristics ............................................................................................................ 408
21. Usage Notes ............................................................................................................................... 428
21.1 Notes on Clock Generation Circuit ....................................................................................................... 428
21.1.1 Stop Mode ......................................................................................................................................... 428
21.1.2 Wait Mode ................................................................................ ........................................................ 428
21.1.3 Oscillation Stop Detection Function ...................................................................................... ........... 428
21.1.4 Oscillation Circuit Constants ............................................................................................................ 428
21.2 Notes on Interrupts ................................................................................................................................ 429
21.2.1 Reading Address 00000h .................................................................................................................. 429
21.2.2 SP Setting .......................................................................................................................................... 429
21.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 429
21.2.4 Changing Interrupt Sources .............................................................................................................. 430
21.2.5 Changing Interrupt Control Register Contents ................................................................................. 431
21.3 Notes on Timers ......................................................................................................................... ........... 432
21.3.1 Notes on Timer RA ........................................................................................................................... 432
21.3.2 Notes on Timer RB ........................................................................................................................... 433
21.3.3 Notes on Timer RD ........................................................................................................................... 437
21.3.4 Notes on Timer RE ........................................................................................................................... 443
21.4 Notes on Serial Interface ....................................................................................................................... 444
21.5 Clock Synchronous Serial Interface ...................................................................................................... 445
21.5.1 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 445
21.5.2 Notes on I
2
C Bus Interface ............................................................................................................... 445
21.6 Notes on Hardware LIN ................................................................................................................ ........ 446
21.7 Notes on A/D Converter ........................................................................................................................ 447
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21.8 Notes on Flash Memory ........................................................................................................................ 448
21.8.1 CPU Rewrite Mode ......................................... .................................................................................. 448
21.9 Notes on Noise ...................................................................................................................................... 451
21.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ............................................................................................................................................ 451
21.9.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 451
22. Notes on On-Chip Debugger ...................................................................................................... 452
23. Notes on Emulator Debugger ..................................................................................................... 453
Appendix 1. Package Dimensions ........................................................................................................ 454
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 455
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 456
Index ..................................................................................................................................................... 457
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SFR Page Reference
Address
0000h
0001h
0002h
0003h
0004h
Processor Mode Register 0 PM0 62
0005h
Processor Mode Register 1 PM1 62
0006h
System Clock Control Register 0 CM0 66
0007h
System Clock Control Register 1 CM1 67
0008h
0009h
000Ah
Protect Register PRCR 86
000Bh
000Ch
Oscillation Stop Detection Register OCD 68
000Dh
Watchdog Timer Reset Register WDTR 115
000Eh
Watchdog Timer Start Register WDTS 115
000Fh
Watchdog Timer Control Register WDC 114
0010h
Address Match Interrupt Register 0 RMAD0 107
0011h
0012h
0013h
Address Match Interrupt Enable Register AIER 107
0014h
Address Match Interrupt Register 1 RMAD1 107
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Count Source Protect Mode Regist er CSPR 115
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
High-Speed On-Chip O s cillator Co ntro l Reg ister 0
0024h
High-Speed On-Chip O s cillator Co ntro l Reg ister 1
0025h
High-Speed On-Chip O s cillator Co ntro l Reg ister 2
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
Voltage Detection Register 1 VCA1 31
0032h
Voltage Detection Register 2 VCA2 31, 70
0033h
0034h
0035h
0036h
Voltage Monitor 1 Circuit Control Register VW1C 32
0037h
Voltage Monitor 2 Circuit Control Register VW2C 33
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Register Symbol Page
FRA0 69
FRA1 69
FRA2 70
NOTE:
1. Blank columns are all reserved space. No access is allowed.
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h Timer RD0 Interrupt Control Register TRD0IC
0049h Timer RD1 Interrupt Control Register TRD1IC
004Ah Timer RE Interrupt Control Register TREIC
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC
004Eh A/D Conversion Interrupt Control Register ADIC
004Fh SSU Interrupt Control Register/IIC Bus
Interrupt Control Register
0050h
0051h UART0 Transmit Interrupt Control Register S0TIC
0052h UART0 Receive Interrupt Control Regist er S0RIC
0053h UART1 Transmit Interrupt Control Register S1TIC
0054h UART1 Receive Interrupt Control Regist er S1RIC
0055h INT2 Interrupt Control Register INT2IC
0056h Timer RA Interrupt Control Register TRAIC
0057h
0058h Timer RB Interrupt Control Register TRBIC
0059h INT1 Interrupt Control Register INT1IC
005Ah INT3 Interrupt Control Register INT3IC
005Bh
005Ch
005Dh INT0 Interrupt Control Register INT0IC
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Register Symbol Page
SSUIC/IICIC
93
93
92
92
92
93
92
92
92
92
94
92
92
94
94
94
B - 1
Page 15
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
UART0 Transmit/Receive Mode Register U0MR 268
00A1h
UART0 Bit Rate Register U0BRG 267
00A2h
UART0 Transmit Buffer Register U0TB 267
00A3h
00A4h
UART0 Transmit/Receive Control Register 0 U0C0 269
00A5h
UART0 Transmit/Receive Control Register 1 U0C1 269
00A6h
UART0 Receive Buffer Register U0RB 267
00A7h
00A8h
UART1 Transmit/Receive Mode Register U1MR 268
00A9h
UART1 Bit Rate Register U1BRG 267
00AAh
UART1 Transmit Buffer Register U1TB 267
00ABh
00ACh
UART1 Transmit/Receive Control Register 0 U1C0 269
00ADh
UART1 Transmit/Receive Control Register 1 U1C1 269
00AEh
UART1 Receive Buffer Register U1RB 267
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
SS Control Register H/IIC Bus Contr ol Regis ter 1
00B9h
SS Control Register L/IIC Bus Control Register 2
00BAh SS Mode Register/IIC Bus Mode Register 1 SSMR/ICMR
00BBh SS Enable Register/IIC Bus Interrupt Enable
Register
00BCh SS Status Register/IIC Bus Status Register SSSR/ICSR
00BDh SS Mode Register 2/Slave Address Register SSMR2/SAR
00BEh SS Transmit Data Register/IIC Bus Transmit
Data Register
00BFh SS Receive Data Register/IIC Bus Receive
Data Register
Register Symbol Page
SSCRH/ICCR1
SSCRL/ICCR2
SSER/ICIER
SSTDR/ICDRT
SSRDR/
ICDRR
NOTE:
1. Blank columns are all reserved space. No access is allowed.
285, 315
286, 316
287, 317
288, 318
289, 319
290, 320
291, 320
291, 321
Address
00C0h
A/D Register AD 363
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
A/D Control Register 2 ADCON2 363
00D5h
00D6h
A/D Control Register 0 ADCON0 362, 365, 368
00D7h
A/D Control Register 1 ADCON1 363, 366, 369
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
Port P0 Register P0 48
00E1h
Port P1 Register P1 48
00E2h
Port P0 Direction Register PD0 48
00E3h
Port P1 Direction Register PD1 48
00E4h
Port P2 Register P2 48
00E5h
Port P3 Register P3 48
00E6h
Port P2 Direction Register PD2 48
00E7h
Port P3 Direction Register PD3 48
00E8h
Port P4 Register P4 48
00E9h
00EAh
Port P4 Direction Register PD4 48
00EBh
00ECh
Port P6 Register P6 48
00EDh
00EEh
Port P6 Direction Register PD6 48
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
UART1 Function Select Register U1SR 270
00F6h
00F7h
00F8h Port Mode Register PMR
00F9h External Input Enable Register INTEN
00FAh INT Input Filter Select Register INTF
00FBh Key Input Enable Register KIEN
00FCh Pull-Up Control Register 0 PUR0
00FDh Pull-Up Control Register 1 PUR1
00FEh
00FFh
Register Symbol Page
49, 270, 291,
321
101
102
105
49
49
B - 2
Page 16
Address
0100h Timer RA Control Register TRACR
0101h Timer RA I/O Control Register TRAIOC
0102h Timer RA Mode Register TRAMR
0103h Timer RA Prescaler Register TRAPRE
0104h Timer RA Register TRA
0105h
0106h LIN Control Register LINCR
0107h LIN Status Register LINST
0108h Timer RB Control Register TRBCR
0109h Timer RB One-Shot Control Register TRBOCR
010Ah Timer RB I/O Control Register TRBIOC
010Bh Timer RB Mode Register TRBMR
010Ch Timer RB Prescaler Register TRBPRE
010Dh Timer RB Secondary Register TRBSC
010Eh Timer RB Primary TRBPR
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Counter Data Register TRESEC
0119h Timer RE Compare Data Register TREMIN
011Ah
011Bh
011Ch Timer RE Control Register 1 TRECR1
011Dh Timer RE Control Register 2 TRECR2
011Eh Timer RE Count Source Select Register TRECSR
011Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h Timer RD Start Register TRDSTR
0138h Timer RD Mode Register TRDMR
0139h Timer RD PWM Mode Register TRDPMR
013Ah Timer RD Function Control Register TRDFCR
013Bh Timer RD Output Master Enable Register 1 TRDOER1
013Ch Timer RD Output Master Enable Register 2 TRDOER2
013Dh Timer RD Output Control Register TRDOCR
013Eh Timer RD Digital Filter Function Select
Register 0
013Fh Timer RD Digital Filter Function Select
Register 1
Register Symbol Page
TRDDF0
TRDDF1
NOTE:
1. Blank columns are all reserved space. No access is allowed.
121
121, 124, 127,
129, 131, 134
122
122
123
347
348
138
138
139, 141, 145,
148, 153
139
140
140
140
260
260
261
261
262
172, 186, 202,
215, 225, 239
172, 186, 203,
216, 226, 240
173, 187, 203
174, 188, 204,
216, 227, 240
189, 205, 217,
228, 241
189, 205, 217,
228, 241
190, 206, 242
175
175
Address
0140h Timer RD Control Register 0 TRDCR0
0141h Timer RD I/O Control Register A0 TRDIORA0
0142h Timer RD I/O Control Register C0 TRDIORC0
0143h Timer RD Status Register 0 TRDSR0
0144h Timer RD Interrupt Enable Register 0 TRDIER0
0145h Timer RD PWM Mode Output Level Control
Register 0
0146h Timer RD Counter 0 TRD0
0148h Timer RD General Register A0 TRDGRA0
014Ah Timer RD General Register B0 TRDGRB0
014Ch Timer RD General Register C0 TRDGRC0
014Eh Timer RD General Register D0 TRDGRD0
0150h Timer RD Control Register 1 TRDCR1
0151h Timer RD I/O Control Register A1 TRDIORA1
0152h Timer RD I/O Control Register C1 TRDIORC1
0153h Timer RD Status Register 1 TRDSR1
0154h Timer RD Interrupt Enable Register 1 TRDIER1
0155h Timer RD PWM Mode Output Level Control
Register 1
0156h Timer RD Counter 1 TRD1
0158h Timer RD General Register A1 TRDGRA1
015Ah Timer RD General Register B1 TRDGRB1
015Ch Timer RD General Register C1 TRDGRC1
015Eh Timer RD General Register D1 TRDGRD1
01B0h
01B1h
01B2h
01B3h Flash Memory Co ntrol Register 4 FMR4
01B4h
01B5h Flash Memory Co ntrol Register 1 FMR1
01B6h
01B7h Flash Memory Co ntrol Register 0 FMR0
01B8h
01B9h
01BAh
01BBh
FFFFh Option Function Select Register OFS
Register Symbol Page
TRDPOCR0
TRDPOCR1
176, 191, 206,
218, 229, 243
177, 192
178, 193
179, 194, 207,
219, 230, 244
180, 195, 208,
220, 231, 245
209
180, 195, 209,
220, 232, 2450147h
181, 196, 210,
221, 232, 2460149h
181, 196, 210,
221, 232, 246014Bh
181, 196, 210,
221, 246014Dh
181, 196, 210,
221, 232, 246014Fh
176, 191, 206,
229
177, 192
178, 193
179, 194, 207,
219, 230, 244
180, 195, 208,
220, 231, 245
209
180, 195, 209,
2320157h
181, 196, 210,
221, 232, 2460159h
181, 196, 210,
221, 232, 246015Bh
181, 196, 210,
221, 232, 246015Dh ,
181, 196, 210,
221, 232, 246015Fh
388
387
386
23, 114, 381
B - 3
Page 17
R8C/20 Group, R8C/21 Group
REJ09B0250-0200
RENESAS MCU
Aug 27, 2008
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using the R8C CPU core and is packaged
in a 48-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of
instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed. This
Furthermore, the data flash (1 KB x 2 blocks) is embedded in the R8C/21 Group.
The difference between R8C/20 and R8C/21 Groups is only the existence of the data flash. Their peripheral functi ons
are the same.
1.1 Applications
Automotive, etc.
Rev.2.00
Rev.2.00 Aug 27, 2008 Page 1 of 458
REJ09B0250-0200
Page 18
R8C/20 Group, R8C/21 Group 1. Overview
1.2 Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/20 Group and Table 1.2 outlines the Functions and
Specifications for R8C/21 Group.
Table 1.1 Functions and Specifications for R8C/20 Group
Item Specification
CPU Number of fundamental instructions 89 instructions
Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.3 Product Information for R8C/20 Group
Peripheral
Function
Electric
Characteristics
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Operating Ambient Temperature -40 to 85°C
Package 48-pin mold-plastic LQFP
NOTES:
1. When using options, be sure to inquire about the specification .
2
2. I
C bus is a registered trademark of Koninklijke Philips Electronics N.V.
Ports I/O ports: 41 pins, Input port: 3 pins
Timers Timer RA: 8 bits x 1 channel,
Timer RB: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits x 2 channel
(Circuits of input capture and output compare)
Timer RE: With compare match function
Serial interface 1 channel (UART0)
Clock synchronous I/O, UART
1 channel (UART1)
UART
Clock synchronous serial interface
LIN module
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 1 1 sources, Extern al: 5 sources, Software: 4 sources,
Clock generation circuits 2 circuits
Oscillation stop detection
function
Voltage detection circuit On-chip
Power-on reset circuit include On-chip
Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version)
Current consumption Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on-
Programming and erasure
endurance
1 channel
I2C bus interface
select
Hardware LIN: 1 channel
(timer RA, UART0)
Reset start selectable
Priority level: 7 levels
XIN clock generation circuit (with on-chip feedback resistor)
On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency adjustment
function.
Stop detection of XIN clock oscillation
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
chip oscillator stopping)
Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip
oscillator stopping)
100 times
-40 to 125°C (option
(2)
, Clock synchronous serial I/O with chip
(1)
)
Rev.2.00 Aug 27, 2008 Page 2 of 458
REJ09B0250-0200
Page 19
R8C/20 Group, R8C/21 Group 1. Overview
Table 1.2 Functions and Specifications for R8C/21 Group
Item Specification
CPU Number of fundamental instructions 89 instructions
Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.4 Product Information for R8C/21 Group
Peripheral
Function
Electric
Characteristics
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Operating Ambient Temperature -40 to 85°C
Package 48-pin mold-plastic LQFP
Ports I/O ports: 41 pins, Input port: 3 pins
Timers Timer RA: 8 bits x 1 channel,
Timer RB: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits x 2 channel
(Circuits of input capture and output compare)
Timer RE: With compare match function
Serial interface 1 channel (UART0)
Clock synchronous I/O, UART
1 channel (UART1)
UART
Clock synchronous serial interface
LIN module
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits x 1 channel (with prescaler)
Interrupts Internal: 11 sources, External: 5 sources, Software: 4 sources,
Clock generation circuits 2 circuits
Oscillation stop detection
function
Voltage detection circuit On-chip
Power-on reset circuit include On-chip
Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version)
Current consumption Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on-
Programming and erasure
endurance
1 channel
I2C bus interface
select
Hardware LIN: 1 channel
(Timer RA, UART0)
Reset start selectable
Priority level: 7 levels
XIN clock generation circuit (with on-chip feedback resistor)
On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency adjustment
function.
Stop detection of XIN clock oscillation
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
chip oscillator stopping)
Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip
oscillator stopping)
10,000 times (data flash)
1,000 times (program ROM)
-40 to 125°C (option
(2)
, Clock synchronous serial I/O with chip
(1)
)
NOTES:
1. When using options, be sure to inquire about the specification .
2
2. I
C bus is a registered trademark of Koninklijke Philips Electronics N.V.
Rev.2.00 Aug 27, 2008 Page 3 of 458
REJ09B0250-0200
Page 20
R8C/20 Group, R8C/21 Group 1. Overview
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
I/O port
Timer
Timer RA (8 bits)
Timer RB (8 bits)
Timer RD (16 bits
Timer RE (8 bits)
Watchdog timer
(15 bits)
Port P0
× 2 channels)
8
8
Port P1
A/D converter
(10 bits
× 12 channels)
UART or
clock synchronous serial I/O
(8 bits × 1 channel)
(8 bits
I2C bus interface or
clock synchronous serial I/O
with chip select
(8 bits × 1 channel)
LIN module
(1 channel)
R8C CPU core
R0H R0L
R1H
R2
R3
A0
A1
FB
Port P2
UART
× 1 channel)
R1L
8
6
Port P3
3 3
Port P4
8
Port P6
System clock
generation circuit
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
Memory
SB
USP
ISP
INTB
PC
FLG
(1)
ROM
(2)
RAM
Multiplier
Figure 1.1 Block Diagram
Rev.2.00 Aug 27, 2008 Page 4 of 458
REJ09B0250-0200
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Page 21
R8C/20 Group, R8C/21 Group 1. Overview
1.4 Product Information
Table 1.3 lists Product Information for R8C/20 Group and Table 1.4 lists Product Information for R8C/21 Group.
Table 1.3 Product Information for R8C/20 Group Current of Aug. 2008
Type No. ROM Capacity RAM Capacity Package Type Remarks
R5F21206JFP 32 Kbytes 2 Kbytes PLQP0048KB-A J version Flash memory
R5F21207JFP 48 Kbytes 2.5 Kbytes PLQP0048KB-A
R5F21208JFP 64 Kbytes 3 Kbytes PLQP0048KB-A
R5F2120AJFP 96 Kbytes 5 Kbytes PLQP0048KB-A
R5F2120CJFP
128 Kbytes
(1)
6 Kbytes PLQP0048KB-A
R5F21206KFP 32 Kbytes 2 Kbytes PLQP0048KB-A K version
R5F21207KFP 48 Kbytes 2.5 Kbytes PLQP0048KB-A
R5F21208KFP 64 Kbytes 3 Kbytes PLQP0048KB-A
R5F2120AKFP 96 Kbytes 5 Kbytes PLQP0048KB-A
R5F2120CKFP
128 Kbytes
(1)
6 Kbytes PLQP0048KB-A
NOTE:
1. Do not use addresses 20000h to 23FFFh because these area s are used for the emulator debu gger .
Refer to 23. Notes on Emulator Debugger.
version
Part number R 5 F 21 20 6 J XXX FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin-pitch, 7 mm square body)
ROM number
Classification
J: Operating ambient temperature -40°C to 85°C (J version)
K: Operating ambient temperature -40°C to 125°C (K version)
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/20 Group
R8C/2x Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group
Rev.2.00 Aug 27, 2008 Page 5 of 458
REJ09B0250-0200
Page 22
R8C/20 Group, R8C/21 Group 1. Overview
Table 1.4 Product Information for R8C/21 Group Current of Aug. 2008
Type No.
ROM Capacity
Program ROM
Data Flash
RAM Capacity Package T ype Remarks
R5F21216JFP 32 Kbytes 1 Kbyte X 2 2 Kbytes PLQP0048KB-A J version Flash
R5F21217JFP 48 Kbytes 1 Kbyte X 2 2.5 Kbytes PLQP0048KB-A
R5F21218JFP 64 Kbytes 1 Kbyte X 2 3 Kbytes PLQP0048KB-A
memory
version
R5F2121AJFP 96 Kbytes 1 Kbyte X 2 5 Kbytes PLQP0048KB-A
R5F2121CJFP
128 Kbytes
(1)
1 Kbyte X 2 6 Kbytes PLQP0048KB-A
R5F21216KFP 32 Kbytes 1 Kbyte X 2 2 Kbytes PLQP0048KB-A K version
R5F21217KFP 48 Kbytes 1 Kbyte X 2 2.5 Kbytes PLQP0048KB-A
R5F21218KFP 64 Kbytes 1 Kbyte X 2 3 Kbytes PLQP0048KB-A
R5F2121AKFP 96 Kbytes 1 Kbyte X 2 5 Kbytes PLQP0048KB-A
R5F2121CKFP
128 Kbytes
(1)
1 Kbyte X 2 6 Kbytes PLQP0048KB-A
NOTE:
1. Do not use addresses 20000h to 23FFFh because these area s are used for the emulator debu gger .
Refer to 23. Notes on Emulator Debugger.
Part number R 5 F 21 21 6 J XXX FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin-pitch, 7 mm square body)
ROM number
Classification
J: Operating ambient temperature -40°C to 85°C (J version)
K: Operating ambient temperature -40°C to 125°C (K version)
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/21 Group
R8C/2x Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.3 Type Number, Memory Size, and Package of R8C/21 Group
Rev.2.00 Aug 27, 2008 Page 6 of 458
REJ09B0250-0200
Page 23
R8C/20 Group, R8C/21 Group 1. Overview
1.5 Pin Assignments
Figure 1.4 shows Pin Assignments (Top View).
Pin assignments (top view)
P4_5/INT0
P6_6/INT2/TXD1
P6_7/INT3/RXD1
P1_2/KI2 /AN10
P1_1/KI1 /AN9
P1_0/KI0 /AN8
P3_1/TRBO
P3_0/TRAO
P6_5
P6_4
P6_3
P0_7/AN0
25
26
27
28
29
30
31
32
33
34
35
36
P3_7/SSO
37P0_6/AN1
38P0_5/AN2
39P0_4/AN3
40P4_2/VREF
41P6_0/TREO
42P6_2
43P6_1
44P0_3/AN4
45P0_2/AN5
46P0_1/AN6
47P0_0/AN7
48
R8C/20 Group,
R8C/21 Group
9VSS/AVSS
8
7RESET
6P4_4
5P4_3
4MODE
3P3_4/SDA/SCS
2P3_3/SSI
1P3_5/SCL/SSCK
10P4_6/XIN
24
23
22
21
20
19
18
17
16
15
14
13
12
11VCC/AVCC
P1_3/KI3/AN11
P1_4/TXD0
P1_5/RXD0/(TRAIO)/(INT1)
P1_6/CLK0
P1_7/TRAIO/INT1
P2_0/TRDIOA0/TRDCLK
P2_1/TRDIOB0
P2_2/TRDIOC0
P2_3/TRDIOD0
P2_4/TRDIOA1
P2_5/TRDIOB1
P2_6/TRDIOC1
(2)
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a program.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.4 Pin Assignments (Top View)
P4_7/XOUT
(1)
P2_7/TRDIOD1
Package: PLQP0048KB-A
0.5 mm pin pitch, 7 mm square body
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R8C/20 Group, R8C/21 Group 1. Overview
1.6 Pin Functions
Table 1.5 lists the Pin Functions and Table 1.6 lists the Pin Name Information by Pin Number.
Table 1.5 Pin Functions
Type Symbol I/O Type Description
Power Supply Input VCC
VSS
Analog Power Supply
Input
Reset Input RESET
MODE MODE I Connect this pin to VCC via a resistor.
XIN Clock Input XIN I These pins are provided for the XIN clock generation
XIN Clock Output XOUT O
Interrupt Input INT0 to INT3 IINT interrupt input pins.
INT
Key Input Interrupt KI0
Timer RA TRAIO I/O Timer RA I/O pin.
Timer RB TRBO O Timer RB output pin.
Timer RD TRDIOA0, TRDIOA1,
Timer RE TREO O Divided clock output pin.
Serial Interface CLK0 I/O Transfer clock I/O pin.
2
C Bus Interface
I
Clock Synchronous
Serial I/O with Chip
Select
Reference Voltage Input VREF I Reference voltage input pin to A/D converter.
A/D Converter AN0 to AN11 I Analog input pins to A/D converter.
I/O Port P0_0 to P0_7,
Input Port P4_2, P4_6, P4_7 I Input only ports.
A VCC, AVSS I Applies the power supply for the A/D converter. Connect
to KI3 I Key input interrupt input pins.
TRAO O Timer RA output pin.
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
TRDCLK I External clock input pin.
RXD0, RXD1 I Serial data input pins.
TXD0, TXD1 O Serial data output pins.
SCL I/O Clock I/O pin.
SDA I/O Data I/O pin.
SSI I/O Data I/O pin.
SCS
SSCK I/O Clock I/O pin.
SSO I/O Data I/O pin.
P1_0 to P1_7,
P2_0 to P2_7,
P3_0, P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_5,
P6_0 to P6_7
I: Input O: Output I/O: Input and output
I Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the
VSS pin.
a capacitor between A VCC and AVSS.
I Input “L” on this pin resets the MCU.
circuit I/O. Connect a ceramic resonator or a crystal
oscillator between the XIN and XOUT pins. To use an
externally derived clock, input it to the XIN pin and leave
the XOUT pin open.
Timer RD input pins.
INT0
Timer RA input pins.
INT1
I/O Timer RD I/O ports.
I/O Chip-select signal I/O pin.
I/O CMOS I/O ports. Each port contains an input/output
select direction register, allowing each pin in that port to
be directed for input or output individually.
Any port set to input can select whether to use a pull-up
resistor or not by a program.
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R8C/20 Group, R8C/21 Group 1. Overview
Table 1.6 Pin Name Information by Pin Number
I/O Pin Functions for of Peripheral Modules
Pin
Number
Control Pin Port
Interrupt Timer
Serial
Interface
1 P3_5 SSCK SCL
2 P3_3 SSI
3P3_4
4MODE
5P4_3
6P4_4
7
RESET
8XOUTP4_7
9 VSS/AVSS
10 XIN P4_6
11 VCC/AVCC
12 P2_7 TRDIOD1
13 P2_6 TRDIOC1
14 P2_5 TRDIOB1
15 P2_4 TRDIOA1
16 P2_3 TRDIOD0
17 P2_2 TRDIOC0
18 P2_1 TRDIOB0
19 P2_0 TRDIOA0/TRDCLK
20 P1_7
INT1
TRAIO
21 P1_6 CLK0
22 P1_5
(INT1
(1)
)
(TRAIO)
(1)
RXD0
23 P1_4 TXD0
24 P1_3
25 P4_5
26 P6_6
27 P6_7
28 P1_2
29 P1_1
30 P1_0
KI3
INT0
INT2
INT3
KI2
KI1
KI0
INT0
TXD1
RXD1
31 P3_1 TRBO
32 P3_0 TRAO
33 P6_5
34 P6_4
35 P6_3
36 P0_7 AN0
37 P0_6 AN1
38 P0_5 AN2
39 P0_4 AN3
40 VREF P4_2
41 P6_0 TREO
42 P6_2
43 P6_1
44 P0_3 AN4
45 P0_2 AN5
46 P0_1 AN6
47 P0_0 AN7
48 P3_7 SSO
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Clock Synchronous
Serial I/O
with Chip Select
SCS
2
I
C Bus
Interface
SDA
A/D
Converter
AN1 1
AN10
AN9
AN8
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R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB
comprise a register bank. Two sets of register banks are provided.
b31
R2
R3
b15 b8b7
R0H (high-order of R0)
R0 L (low -ord er o f R0 )
R1H (high-order of R1) R1L (low-order of R1)
R2
R3
A0
A1
FB
b15b19
INTBH
The 4-high order bits of INTB are INTBH and
the 16-low order bits of INTB are INTBL.
b19
INTBL
PC
b15
USP
ISP
SB
b0
Data registers
Address registers
Frame base registers
b0
Interrupt table register
b0
Program counter
b0
User stack pointer
Interrupt stack pointer
Static base register
(1)
(1)
(1)
b15
IPL
NOTE:
1. A register bank comprises these registers. Two sets of register banks are provided.
Figure 2.1 C PU Registers
b15
b0
FLG
b8
b7
b0
C
DZSBOIU
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
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R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU)
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3.
R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The
same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register
(R2R0). The same applies R3R1 as R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also
are used for transfer, arithmetic and logic operations. The same applies to A1 as A0.
A1 can be combined with A0 to be used a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB, a 20-bit register, indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU status.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is 0. The register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when the operation resulted in an overflow; otherwise, 0.
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R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU)
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to
0 when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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R8C/20 Group, R8C/21 Group 3. Memory
3. Memory
3.1 R8C/20 Group
Figure 3.1 shows a Memory Map of R8C/20 Group. The R8C/20 Group has 1 Mbyte of address space from
address 00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal
ROM is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future
user and cannot be accessed by users.
00000h
002FFh
00400h
0XXXXh
01300h
02000h
03000h
0SSSSh
0YYYYh
0FFFFh
ZZZZZh
FFFFFh
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Do not use addresses 20000h to 23FFFh because these areas are used for the emul ator debugger. Refer to 23. Notes on
Emulator Debugger.
Part Number
R5F21206JFP, R5F21206KFP
R5F21207JFP, R5F21207KFP
R5F21208JFP, R5F21208KFP
R5F2120AJFP, R5F2120AKFP
R5F2120CJFP, R5F2120CKFP
SFR
(Refer to 4. Special
Function Registers
(SFRs))
Internal RAM
Reserved area
Internal RAM
Internal ROM
(program ROM)
Internal ROM
(program ROM)
(2)
Size Address 0YYYYh Address ZZZZZh
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Internal ROM
08000h
04000h
04000h
04000h
04000h
0FFDCh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Watchdog timer•oscillation stop detection•voltage detection
-
13FFFh
1BFFFh
23FFFh
Address break
Size
2 Kbytes
2.5 Kbytes
3 Kbytes
5 Kbytes
6 Kbytes
Single step
(Reserved)
Reset
Internal RAM
Address 0XXXXh
00BFFh
00DFFh
00FFFh
00FFFh
00FFFh
Address 0SSSSh
037FFh
03BFFh
-
-
-
Figure 3.1 Memory Map of R8C/20 Group
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R8C/20 Group, R8C/21 Group 3. Memory
3.2 R8C/21 Group
Figure 3.2 shows a Memory Map of R8C/21 Group. The R8C/21 Group has 1 Mbyte of address space from
address 00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated them. All addresses within the SFR, which have nothing allocated are reserved for future
use and cannot be accessed by users.
00000h
002FFh
00400h
0XXXXh
01300h
02000h
02400h
02BFFh
03000h
0SSSSh
0YYYYh
0FFFFh
ZZZZZh
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locati ons in these regions.
3. Do not use addresses 20000h to 23FFFh because these areas are used for t he emulator debugger. Refer to 23. Notes on
Emulator Debugger.
Part Number
R5F21216JFP, R5F21216KFP
R5F21217JFP, R5F21217KFP
R5F21218JFP, R5F21218KFP
R5F2121AJFP, R5F2121AKFP
R5F2121CJFP, R5F2121CKFP
SFR
(Refer to 4. Special
Function Registers
(SFRs))
Internal RAM
Reserved area
Internal ROM
(data flash)
Internal RAM
Internal ROM
(program ROM)
Internal ROM
(program ROM)
(1)
(3)
Size Address 0YYYYh Address ZZZZZh
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Internal ROM
08000h
04000h
04000h
04000h
04000h
0FFDCh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Watchdog timer•oscillation stop detection•voltage detection
-
-
13FFFh
1BFFFh
23FFFh
Address break
Size
2 Kbytes
2.5 Kbytes
3 Kbytes
5 Kbytes
6 Kbytes
Single step
(Reserved)
Reset
Internal RAM
Address 0XXXXh
00BFFh
00DFFh
00FFFh
00FFFh
00FFFh
Address 0SSSSh
037FFh
03BFFh
-
-
-
Figure 3.2 Memory Map of R8C/21 Group
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R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function.
Table 4.1 to Table 4.6 list the SFR Information.
Table 4.1 SFR Information (1)
Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 0110 1000b
0007h System Clock Control Register 1 CM1 00100000b
0008h
0009h
000Ah Protect Register PRCR 00h
000Bh
000Ch Oscillation Stop Detection Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 00X11111b
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h 00h
0013h Address Match Interrupt Enable Register AIER 00h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h 00h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protect Mode Register CSPR 00h
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h
0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping
0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h
0026h
(1)
10000000b
(8)
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Fh
Voltage Detection Register 1
Voltage Detection Register 2
Voltage Monitor 1 Circuit Control Regist er
Voltage Monitor 2 Circuit Control Regist er
(2)
(6)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1.
4. Power-on reset, voltage monitor 1 reset or the LVD0ON bit in the OFS register is set to 0.
5. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3.
6. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b7.
7. Software reset, the watchdog timer rest, and the voltage monitor 2 reset do not affect other than the b0 and b6.
8. The CSPROINI bit in the OFS register is 0.
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REJ09B0250-0200
VCA1 00001000b
VCA2
(7)
(5)
VW1C
VW2C 00h
(3)
00h
01000000b
0000X000b
0100X001b
(4)
(3)
(4)
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R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs)
Table 4.2 SFR Information (2)
Address Register Symbol After reset
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b
0049h Timer RD1 Interrupt Control Register TRD1IC XXXXX000b
004Ah Timer RE Interrupt Control Register TREIC XXXXX000b
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b
004Fh
0050h
0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b
0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b
0055h INT2 Interrupt Control Register INT2IC XX00X000b
0056h Timer RA Interrupt Control Register TRAIC XXXXX000b
0057h
0058h Timer RB Interrupt Control Register TRBIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XX00X000b
005Ah INT3 Interrupt Control Register INT3IC XX00X000b
005Bh
005Ch
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
SSU Interrupt Control Register/IIC Bus Interrupt Control Register
(1)
(2)
SSUIC/IICIC XXXXX000b
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
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R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs)
Table 4.3 SFR Information (3)
Address Register Symbol After reset
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Rate Register U0BRG XXh
00A2h UART0 Transmit Buffer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b
00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h UART1 Transmit/Receive Mode Register U1MR 00h
00A9h UART1 Bit Rate Register U1BRG XXh
00AAh UART1 Transmit Buffer Register U1TB XXh
00ABh XXh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b
00ADh UART1 Transmit/Receive Control Register 1 U1C1 00000010b
00AEh UART1 Receive Buffer Register U1RB XXh
00AFh XXh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
SS Control Register H/IIC Bus Control Register 1
SS Control Register L/IIC Bus Control Register 2
SS Mode Register/IIC Bus Mode Reg i ster 1
SS Enable Register/IIC Bus Interrupt Enable Register
SS Status Register/IIC Bus Status Register
SS Mode Register 2/Slave Address Register
SS Transmit Data Register/IIC Bus Transmit Data Register
SS Receive Data Register/IIC Bus Receive Data Register
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
SSCRH/ICCR1 00h
SSCRL/ICCR2 01111101b
SSMR/ICMR 00011000b
SSER/ICIER 00h
SSSR/ICSR 00h/0000X000b
SSMR2/SAR 00h
SSTDR/ICDRT FFh
SSRDR/ICDRR FFh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
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R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs)
Table 4.4 SFR Information (4)
Address Register Symbol After reset
00C0h A/D Register AD XXh
00C1h XXh
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h A/D Control Register 2 ADCON2 00h
00D5h
00D6h A/D Control Register 0 ADCON0 00h
00D7h A/D Control Register 1 ADCON1 00h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 XXh
00E1h Port P1 Register P1 XXh
00E2h Port P0 Dir ection Register PD0 00h
00E3h Port P1 Dir ection Register PD1 00h
00E4h Port P2 Register P2 XXh
00E5h Port P3 Register P3 XXh
00E6h Port P2 Dir ection Register PD2 00h
00E7h Port P3 Dir ection Register PD3 00h
00E8h Port P4 Register P4 XXh
00E9h
00EAh Port P4 Direction Register PD4 00h
00EBh
00ECh Port P6 Register P6 XXh
00EDh
00EEh Port P6 Direction Register PD6 00h
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h UART1 Function Select Register U1SR XXh
00F6h
00F7h
00F8h Port Mode Register PMR 00h
00F9h External Input Enable Register INTEN 00h
00FAh INT Input Filter Select Register INTF 00h
00FBh Key Input Enable Register KIEN 00h
00FCh Pull-Up Control Register 0 PUR0 00h
00FDh Pull-Up Control Register 1 PUR1 XX00XX00b
00FEh
00FFh
(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
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R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs)
Table 4.5 SFR Information (5)
Address Register Symbol After reset
0100h Timer RA Control Register TRACR 00h
0101h Timer RA I/O Control Register TRAIOC 00h
0102h Timer RA Mode Register TRAMR 00h
0103h Timer RA Prescaler Register TRAPRE FFh
0104h Timer RA Register TRA FFh
0105h
0106h LIN Control Register LINCR 00h
0107h LIN Status Register LINST 00h
0108h Timer RB Control Register TRBCR 00h
0109h Timer RB One-Shot Control Register TRBOCR 00h
010Ah Timer RB I/O Control Register TRBIOC 00h
010Bh Timer RB Mode Register TRBMR 00h
010Ch Timer RB Prescaler Register TRBPRE FFh
010Dh Timer RB Secondary Register TRBSC FFh
010Eh Timer RB Primary TRBPR FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Counter Data Register TRESEC 00h
0119h Timer RE Compare Data Register TREMIN 00h
011Ah
011Bh
011Ch Timer RE Control Register 1 TRECR1 00h
011Dh Timer RE Control Register 2 TRECR2 00h
011Eh Timer RE Count Source Select Register TRECSR 00001000b
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h Timer RD Start Register TRDSTR 11111100b
0138h Timer RD Mode Register TRDMR 00001110b
0139h Timer RD PWM Mode Register TRDPMR 10001000b
013Ah Timer RD Function Control Register TRDFCR 10000000b
013Bh Timer RD Output Master Enable Register 1 TRDOER1 FFh
013Ch Timer RD Output Master Enable Register 2 TRDOER2 01111111b
013Dh Timer RD Output Control Register TRDOCR 00h
013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 00h
013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 00h
(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
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R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs)
Table 4.6 SFR Information (6)
Address Register Symbol After reset
0140h Timer RD Control Register 0 TRDCR0 00h
0141h Timer RD I/O Control Register A0 TRDIORA0 10001000b
0142h Timer RD I/O Control Register C0 TRDIORC0 10001000b
0143h Timer RD Status Register 0 TRDSR0 11100000b
0144h Timer RD Interrupt Enable Register 0 TRDIER0 11100000b
0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 11111000b
0146h Timer RD Counter 0 TRD0 00h
0147h 00h
0148h Timer RD General Register A0 TRDGRA0 FFh
0149h FFh
014Ah Timer RD General Register B0 TRDGRB0 FFh
014Bh FFh
014Ch Timer RD General Register C0 TRDGRC0 FFh
014Dh FFh
014Eh Timer RD General Register D0 TRDGRD0 FFh
014Fh FFh
0150h Timer RD Control Register 1 TRDCR1 00h
0151h Timer RD I/O Control Register A1 TRDIORA1 10001000b
0152h Timer RD I/O Control Register C1 TRDIORC1 10001000b
0153h Timer RD Status Register 1 TRDSR1 11000000b
0154h Timer RD Interrupt Enable Register 1 TRDIER1 11100000b
0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 11111000b
0156h Timer RD Counter 1 TRD1 00h
0157h 00h
0158h Timer RD General Register A1 TRDGRA1 FFh
0159h FFh
015Ah Timer RD General Register B1 TRDGRB1 FFh
015Bh FFh
015Ch Timer RD General Register C1 TRDGRC1 FFh
015Dh FFh
015Eh Timer RD General Register D1 TRDGRD1 FFh
015Fh FFh
(1)
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register 1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
FFFFh Option Function Select Register OFS (Note 2)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
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R8C/20 Group, R8C/21 Group 5. Resets
5. Resets
There are resets: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer
reset, and software reset.
Table 5.1 lists the Reset Names and Sources.
Table 5.1 Reset Names and Sour ce s
Reset Name Source
Hardware reset Input voltage of RESET
Power-on reset
(1)
Voltage monitor 1 reset
Voltage monitor 2 reset
(1)
(1)
VCC rises
VCC falls (monitor voltage: Vdet1)
VCC falls (monitor voltage: Vdet2)
Watchdog timer reset Underflow of watchdog timer
Software reset Write 1 to PM03 bit in PM0 register
NOTE:
1. Because this product is under development, specifications may be changed.
pin is held “L”
RESET
VCC
Power-on reset
circuit
Voltage
detection
circuit
Watchdog
timer
CPU
Hardware reset
Power-on reset
Voltage monitor
1 reset
Voltage monitor
2 reset
Watchdog timer
reset
Software reset
SFR
VCA26,
VW1C0 and
VW1C6 bits
SFR
VCA13, VCA27,
VW1C1,
VW1F0, VW1F1, VW1C7,
VW2C2 and VW2C3 bits
Pin, CPU and
SFR bits other than
those listed above
VCA13: Bit in VCA1 regis ter
VCA26, VCA27: Bits in VCA2 register
VW1C0, VW1C1, VW1F0, VW1F 1, VW1C6, VW1C7: Bits in VW 1C register
VW2C2, VW2C3 bits: Bits in VW2C register
Figure 5.1 Block Diagram of Reset Circuit
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R8C/20 Group, R8C/21 Group 5. Resets
Table 5.2 lists the Pin Functions after Reset, Figure 5.2 shows CPU Register Status after Reset, Figure 5.3 shows
Reset Sequence, and Figure 5.4 shows the OFS Register.
Table 5.2 Pin Functions after Reset
Pin Name Pin Functions
P0, P1, P2 Input port
P3_0, P3_1, P3_3
to P3_5, P3_7 Input port
P4_2 to P4_7 Input port
P6 Input port
b15
b15
0000h
0000h
0000h
0000h
0000h
0000h
0000h
b19
00000h
Content of addresses 0FFFEh to 0FFFCh
b15
0000h
0000h
0000h
b15
0000h
b8
b7
IPL
DZSBOIU
b0
Data register (R0)
Data register (R1)
Data register (R2)
Data register (R3)
Address register (A0)
Address register (A1)
Frame base register (FB)
b0
Interrupt table register (INTB)
Program counter (PC)
b0
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
b0
Flag register (FLG)
b0
C
Figure 5.2 CPU Register Status after Reset
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R8C/20 Group, R8C/21 Group 5. Resets
fOCO-S
RESET pin
10 cycles or more are needed
fOCO-S clock × 32 cycles
Internal reset
signal
CPU clock
Address
(internal address
signal)
NOTES:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same.
Start time of flash memory
(CPU clock × 14 cycles)
Figure 5.3 R eset Sequence
Option Function Selec t Register
b7 b6 b5 b4 b3 b2 b1 b0
11 1
NOTES:
1.
The OFS register is on the flash m emory. Write to the OFS register w ith a program. After writing is completed, do not
write additions to the OFS register.
2.
To use the power-on reset, set the LVD1ON bit to 0 (voltage monitor 1 reset enabled after reset).
3.
I f the block including the OFS register is erased, FFh is set to the OFS register.
Symbol Address Before Shipment
OFS
Bit Symbol Bit Name Function RW
WDTO N
—
(b1)
ROMCR
ROMCP1
—
(b5-b4)
LVD1ON
CSPROINI
(1)
(2)
CPU clock × 28 cycles
0FFFCh 0FFFEh
0FFFDh
(1)
0FFFFh FFh
Watchdog tim er start
select bit
Reserved bit
ROM code protect
disabled bit
0 : Starts watchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Set to 1
0 : ROM code protect disabled
1 : ROMCP1 enabled
ROM code protect bit 0 : ROM code protect enabled
1 : ROM code protect disabled
R e served bits Set to 1
Voltage detection circuit
(2)
start bit
Count source protect
mode after reset select
0 : Voltage monitor 1 reset enabled after reset
1 : Voltage monitor 1 reset disabled after reset
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
bit
Content of reset vector
(3)
RW
RW
RW
RW
RW
RW
RW
Figure 5.4 O FS Register
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R8C/20 Group, R8C/21 Group 5. Resets
5.1 Hardware Reset
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply
voltage meets the recommended performance condition, the pins, CPU, and SFR are reset (refer to Table 5.2 Pin
Functions after Reset). When the input level applied to the RESET
executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator
clock divided-by-8 is automatically selected for the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after reset.
The internal RAM is not reset. If the RESET
RAM will be in indeterminate state.
Figure 5.5 shows the Example of Hardware Reset Circuit and Operation and Figure 5.6 shows the Example of
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
pin is pulled “L” during writing to the internal RAM, the internal
pin changes “L” to “H”, the program is
5.1.1 When Power Supply is Stable
(1) Apply “L” to the RESET pin.
(2) Wait for 10µs or more.
(3) Apply “H” to the RESET
pin.
5.1.2 Power On
(1) Apply “L” to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended performance condition.
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 20. Electrical
Characteristics).
(4) Wait for 10µs or more.
(5) Apply “H” to the RESET
pin.
Rev.2.00 Aug 27, 2008 Page 24 of 458
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R8C/20 Group, R8C/21 Group 5. Resets
VCC
VCC
0 V
RESET
RESET
0 V
NOTE:
1. Refer to 20. Electrical Characteristics.
2.7 V
td(P-R) + 10 µs or more
Figure 5.5 Example of Hardware Reset Circuit and Operation
5 V
VCC
0 V
5 V
RESET
RESET VCC
Power supply
voltage detection
circuit
0.2 VCC or below
2.7 V
0 V
td(P-R) + 10 µs or more
Example when
VCC = 5 V
NOTE:
1. Refer to 20. Electrical Characteristics.
Figure 5.6 Example of Hardware Rese t Circuit (Usage Example of External Supply Voltage
Detection Circuit) and Operation
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R8C/20 Group, R8C/21 Group 5. Resets
5.2 Power-On Reset Function
(1)
When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises, the
power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is connected to
the RESET
pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches to the Vdet0 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divide-by-8 is
automatically selected for the CPU after reset.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after power-on reset.
The voltage monitor 0 reset is enabled after power-on reset.
Figure 5.7 shows the Example of Power-On Reset Circuit and Operation.
NOTE:
1. When using power-on reset function, set the LVD1ON bit to 0 (voltage monitor 1 reset enabled after reset).
VCC
4.7 kΩ
(reference)
RESET
(3)
Vdet1
External power Vcc
Vpor1
tw(por1)
Internal reset signal
NOTES:
(“L” valid)
1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit for details.
4. Refer to 20. Electrical Characteristics.
5. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0
(voltage monitor 1 reset enabled after reset), bits VW1C0 and VW1C6 in the VW1C register to 1 (enable) and the VCA26 bit
in the VCA2 register to 1 (voltage detection 1 circuit enabled).
trth
1
fOCO-S
td(Vdet1-A)
Sampling time
× 32
2.0 V
(1, 2)
trth
Vpor2
1
fOCO-S
Figure 5.7 Example of Power-On Reset Circuit and Operation
× 32
Vdet1
(3)
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R8C/20 Group, R8C/21 Group 5. Resets
5.3 Voltage Monitor 1 Reset
A reset is applied using the on-chip voltage detection 1 ci rcuit. The voltage det ection 1 circuit monito rs the input
voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches to the Vdet1 level or below, the pins, CPU, and SFR are reset.
And when the input voltage to the VCC pin reaches to the Vdet1 level or above, count operation of the low-speed
on-chip oscillator clock starts. When the operation counts the low-speed on-chip oscillator clock for 32 times, the
internal reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed onchip oscillator clock divide-by-8 is automatically selected for the CPU after reset.
The LVD1ON bit in the OFS register can select to enable or disable voltage monitor 1 reset after a reset.
To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register
to 0, bits VW1C0 and VW1C6 in the VW1C register to 1, the VCA bit in the VCA2 register to 1.
The LV D1ON bit cannot be changed by a program. When setting the LVD1ON bit, write 0 (voltage monitor 1
reset enabled after reset) or 1 (voltage monitor 1 reset disabled after reset) to the bit 6 of address 0FFFFh using a
flash programmer. Refer to Figure 5.4 OFS Register for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 1 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet1 level or below during
writing to the internal RAM, the internal RAM is in indeterminate state.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.4 Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 ci rcuit. The voltage det ection 2 circuit monito rs the input
voltage to the VCC pin. The voltage to monitor is Vdet2.
When the input voltage to the VCC pin drops to the Vdet2 level or below, the pins, CPU, and SFR are reset and the
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divide-by-8 is automatically selected for the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet2 level or below during
writing to the internal RAM, the internal RAM is in indeterminate state.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
5.5 Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its
pins, CPU, and SFR if the watchdog timer underflows. Then the program is executed beginning with the address
indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically
selected for the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the watchdog timer underflows, the internal RAM is in indeterminate state.
Refer to 13. Watchdog Timer for watchdog timer.
5.6 Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divide-by-8 is automatically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset.
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
6. Voltage Detection Circuit
The voltage detection circuit is a circuit to monitor the input voltage to the VCC pin. This circuit monitors the VCC
input voltage by the program. And the voltage monitor 1 reset, voltage monitor 2 interrupt and voltage monitor 2 reset
can be used.
Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.3 show the Block Diagrams.
Figures 6.4 to 6.6 show the Associated Registers.
Table 6.1 Specifications of Voltage Detection Circuit
Item Voltage Detection 1 Voltage Detection 2
VCC Monitor Voltage to monitor Vdet1 Vdet2
Detection target Whether passing
Monitor None VCA13 bit in VCA1
Process When Volt age Is
Detected
Digital Filter Switch
Reset Voltage monitor 1 reset Voltage monitor 2 reset
Interrupt None Voltage monitor 2
enabled/disabled
Sampling time (Divide-by-n of fOCO-S)
through Vdet1 by rising
or falling
Reset at Vdet1 > VCC;
Restart CPU operation at
VCC > Vdet1
Available Available
x 4
n: 1, 2, 4 and 8
Whether passing
through Vdet2 by rising
or falling
register
Whether VCC is higher
or lower than Vdet2
Reset at Vdet2 > VCC
Restart CPU operation
after a specified time
interrupt
Interrupt request at
Vdet2 > VCC and VCC >
Vdet2 when digital filter
is enabled;
Interrupt request at
Vdet2 > VCC or VCC >
Vdet2 when digital filter
is disabled
(Divide-by-n of fOCO-S)
x 4
n: 1, 2, 4 and 8
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
VCC
VCA27
+
Internal
reference
voltage
-
≥ Vdet2
VCA26
+
-
≥ Vdet1
Figure 6.1 Block Diagram of Voltage Detection Circuit
Voltage monitor 1 reset generation circuit
VW1F1 to VW1F0
= 00b
Voltage detection 1 circuit
VCA26
VCC
+
Internal
-
reference
voltage
fOCO-S
Voltage
detection 1
Voltage detection 1
signal is held “H” when
VCA26 bit is set to “0”
(disabled)
signal
1/2 1/2 1/2
VW1C7
= 01b
= 10b
= 11b
VW1C1
Noise filter
VW1C1
Digital
filter
VW1C0
VW1C6
Voltage detection 2
signal
VCA1 register
b3
VCA13 bit
Voltage detection 1
signal
Voltage
monitor 1
reset signal
VW1C0 to VW1C1, VW1F0 to VW1F1, VW1C6, VW1C7: Bits in VW 1C register
VCA26: Bit in VCA2 register
Figure 6.2 B lock Diagram of Voltage Monitor 1 Reset Generation Circuit
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
Voltage monitor 2 interrupt/reset generation c ircuit
VW2F1 to VW2F0
= 00b
Voltage detection 2 circuit
VCA27
VCC
+
(Filter width: 200ns)
Noise filter
Voltage detection 2 signal
is held “H” when VCA27 bit
is set to 0 (disabled)
Watchdog timer underflow
signal
Internal
reference
voltage
Watchdog timer block
VW2C0 to VW2C3, VW2F2, VW2F1, VW2C6, VW2C 7: Bit s in VW2C register
VCA13: Bit in V CA1 register
VCA27: Bit in V CA2 register
fOCO-S
VCA13
Voltage
detection
2 signal
1/2 1/2 1/2
VW2C3
VW2C7
This bit is set to 0 (not detected) by writing
“0” by program.
= 01b
= 10b
= 11b
VW2C1
VW2C2 bit is set to 0 (not detected) by
writing 0 by program.
When VCA27 bit is set to 0 (voltage
detection 2 circuit disabled), VW2C2
bit is set to 0
VW2C1
Digital
filter
VW2C0
VW2C6
VW2C2
Watchdog timer
interrupt signal
Voltage monitor 2
interrupt signal
Oscillation stop
detection
interrupt signal
Non-maskable
interrupt signal
Voltage
monitor 2
reset signal
Figure 6.3 B lock Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit
Rev.2.00 Aug 27, 2008 Page 30 of 458
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
)
Vol t ag e Det ect i on Regi st er 1
b7 b6 b5 b4 b3 b2 b1 b0
0000
NOTES:
1.2.The VCA13 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
The VCA13 bit is set to 1 (VCC ≥ Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2
circuit disabled
The software reset, watchdog timer reset and voltage monitor 2 reset do not affect the VCA1 register.
0
00
Symbol Address After Reset
VCA1
0031h 00001000b
(2)
Bit Symbol Bit Name Function RW
—
Reserved bits
Set to 0
(b2-b0)
VCA13
Voltage detection 2 signal monitor
(1)
flag
0 : VCC < Vdet2
1 : VCC ≥ Vdet2 or voltage detection 2
circuit disabled
—
Reserved bits Set to 0
(b7-b4)
.
RW
RO
RW
Voltage Detec tion Regis ter 2
b7 b6 b5 b4 b3 b2 b1
00
b0
000
(1)
Symbol Address
VCA2 0032h
After Reset
The LVD1ON bit in the OF S regis ter is s et to 1: 00h
Power-on reset , v oltag e m onit or 1 reset or t he LVD1ON
bit in t he OF S regis t er is se t t o 0: 0100000 0b
Bit Symb o l Bit Name Fun ction RW
VCA20
—
Internal power low consumption
enable bit
(5)
Res erved bits
0 : Disables low consumption
1 : Enables low consumption
Set to 0
(b5-b1)
VCA26
VCA27
Voltage detection 1 enable bit
Voltage detection 2 enable bit
(2)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled
(3)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled
NOTES:
1.
Set the PRC3 bit in the PRCR register to 1 (enables w riting) before w riting to the VCA2 register.
2.
When using the voltage monitor 1 reset, set the VCA26 bit to 1.
After the VCA26 bit is set from 0 to 1, the voltage detection circuit elapses for td(E-A) before starting operation.
3.
When using the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is from 0 to 1, the voltage detection circuit elapses for td(E-A) before starting operation.
4.
The VCA27 bit remains unchanged after software reset, watchdog timer reset, and voltage monitor 2 reset.
5. Use the VCA20 bit only when entering to w ait mode. To set the VCA20 bit, follow the procedure shown in
10.10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
(4)
RW
RW
RW
RW
Figure
.
Figure 6.4 Registers VCA1 and VCA2
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
Vol tage M oni tor 1 Circui t Cont rol Regi st er
b3 b2
b1 b0b7 b6 b5 b4
0
NOTES:
Set the PRC 3 bit in the PRCR register to 1 (w rite enable) before writing to the VW1C register.
1.
The value other than the VW1CO and VW1C6 bits remains unchanged after softw are reset, w atchdog timer reset,
2.
and voltage m onitor 2 reset.
3.
The VW1C 0 bit is enabled when the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit
enabled). Set the VW1C0 bit to 0 (disable), w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
The VW1C7 bit is enabled when the VW1C1 bit is set to 1 (digital filter disabled mode).
4.
Symbol Address
VW1C 0036h
Bit Symbol Bit Name Function RW
VW1C0 RW
Voltage moni tor 1 reset enable
(3)
bit
Voltage moni tor 1 digi tal filter
VW1C1
disable mode select bit
VW1C2 Reserved bit
—
Reserved bit
(b3)
Sampling clock select bits
VW1F0 RW
VW1F1 RW
VW1C6
VW1C7
Voltage moni tor 1 circuit mode
select bit
Voltage moni tor 1 reset generation
condition select bit
(1)
After Reset
The LVD1ON bit in t he OFS regis ter is s et t o 1: 0000X000b
Power-on reset, v oltage m onit or 1 res et or t he LVD 1ON bit
in the OF S regis t er is s et t o 0: 0100X001b
(2)
0 : Disable
1 : Enable
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled m ode
RW
(digital filter circuit disabled)
Set to 0 R W
When read, the content is undefined.
b5 b4
RO
0 0 : fOCO-S divide-by-1
0 1 : fOCO-S divide-by-2
1 0 : fOCO-S divide-by-4
1 1 : fOCO-S divide-by-8
When the VW1C0 bit is set to 1 (enables
voltage monitor 1 reset), set to 1.
(4)
When the VW1C1 bit is set to 1 (digital filter
disabled mode), set to 1.
RW
RW
Figure 6.5 VW1C Register
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
Voltage Moni t or 2 Circui t Cont rol Register
b3 b2
b1 b0b7 b6 b5 b4
Symbol Address After Reset
VW2C 0037h 00h
Bit Symbol Bit Name Function RW
VW2C0 RW
VW2C1
VW2C2
VW2C3
VW2F0 RW
VW2F1 RW
VW2C6
VW2C7
NOTES:
1.
Set the PRC3 bit in the PRCR register to 1 (enables w riting) before w riting to the VW2C register. When w riting the
VW2C register, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after w riting the VW2C register.
2.
When the voltage monitor 2 interrupt is used to exit stop mode and to return again, write 0 to the VW2C1 bit before
writing 1.
3.
This bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
4.
Set this bit to 0 by a program. When writing 0 by a program, it is set to 0 (it remains unchanged even if it is set to 1).
5.
This bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enables reset).
6.
The VW2C 0 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
7.
The VW2C7 bit is enabled when the VW2C1 bit is set to 1 (digital filter disabled mode).
8.
The VW2C 2 and VW2C3 bits remain unchanged in the softw are reset, w atchdog timer reset and voltage monitor 2
reset.
9.
When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (when VCC reaches to Vdet2
or below) (do not set to 0).
Voltage moni tor 2 interrupt/reset
enable bit
(6)
Voltage moni tor 2 digi tal filter
disabled mode select bit
Voltage change detection
(3,4,8)
flag
WDT detection flag
Sampling clock select bits
Voltage moni tor 2 circuit mode
select bit
(5)
Voltage moni tor 2 interrupt/reset
generation condition select
(7,9)
bit
(1)
(4,8)
(8)
0 : Disable
1 : Enable
(2)
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled m ode
RW
(digital filter circuit disabled)
0 : Not detected
1 : Vdet2 pass detected
0 : Not detected
1 : Detected
b5 b4
RW
RW
0 0 : fOCO-S divide-by-1
0 1 : fOCO-S divide-by-2
1 0 : fOCO-S divide-by-4
1 1 : fOCO-S divide-by-8
0 : Voltage monitor 2 interrupt mode
1 : Voltage monitor 2 reset mode
RW
0 : When VCC reaches Vdet2 or above
1 : When VCC reaches Vdet2 or below
RW
Figure 6.6 VW2C Register
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
6.1 VCC Input Voltage
6.1.1 Monitoring Vdet1
Vdet1 cannot be monitored.
6.1.2 Monitoring Vdet2
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed
(refer to 20. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register.
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
6.2 Voltage Monitor 1 Reset
Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Mo nitor 1 Reset and Figure 6.7 sh ows an
Example of Voltage Monitor 1 Reset Operation. To use the voltage monitor 1 reset to exit stop mod e, set the
VW1C1 bit in the VW1C register to 1 (digital filter disabled).
Table 6.2 Procedure for Setting Bits Associated with Voltage Monitor 1 Reset
Step When Using Digital Filter When Not Using Digital Filter
1 Set th e VCA2 6 bit in the VCA2 reg iste r to 1 (voltage detection 1 circuit enabled)
2 Wait for td(E-A)
Select the sampling clock of the digital filter
3
by the VW1F0 to VW1F1 bits in the VW1C
register
(1)
4
(1)
5
Set the VW1C1 bit in the VW1C register to
“0” (digital filter enabled)
Set the VW1C6 bit in the VW1C register to 1 (voltage monitor 1 reset mode)
6 Set the VW1C2 bit in the VW1C register to 0
7 Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
8 Wait for the sampling clock of the digital
filter x 4 cycles
9 Set the VW1C0 bit in the VW1C register to 1 (enables voltage monitor 1 reset)
Set the VW1C7 bit in the VW1C register to
1
Set the VW1C1 bit in the VW1C register to
1 (digital filter disabled)
−
− (no wait time)
NOTE:
1. When the VW1C0 bit is set to 0, procedures 3, 4 and 5 can be executed simultaneously (with 1
instruction).
VCC
Vdet1
1
fOCO-S
1
fOCO-S
x 32
x 32
When the VW1C1 bit is se t
to 0 (digital filter enabled)
When the VW1C1 bit is se t
to 1 (digital filter disabl ed )
and the VW1C7 bit is set
to 1
VW1C1 and VW1C7: Bits in VW1C register
Internal reset signal
Internal reset signal
The above applies to the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (enables voltage monitor 1 reset )
• VW1C6 bit in VW1C register = 1 (voltage monitor 1 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal is changed from “L” to “H”, the pr ogram is executed beginning with the address indicat ed by the
reset vector.
Refer to
Sampling clock of
digital filter x 4 cycles
4. Special Function Registers (SFRs) for the SFR status after reset.
Figure 6.7 Example of Voltage Monitor 1 Reset Operation
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
6.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.8
shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage
monitor 2 interrupt or voltage monitor 2 r eset to exit stop mode, set the VW2C1 bit in the VW2C register to 1
(digital filter disabled).
Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset
When Using Digital Filter When Not Using Digital Filter
Step
1 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled)
2 Wait for td(E-A)
3
(2)
4
(2)
5
6 Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected)
7 Set the CM14 bit in the CM1 register to 0
8 W ait for the samplin g clock of the digital filter
9 Set the VW2C0 bit in the VW2C register to 1 (enables voltage monitor 2 interrupt/reset)
NOTES:
1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.
2. When the VW2C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
Voltage Monitor 2
Interrupt
Voltage Monitor 2
Reset
Select the sampling clock of the digital filter
by the VW2F0 to VW2F1 bits in the VW2C
register
Set the VW2C1 bit in the VW2C register to 0
(digital filter enabled)
Set the VW2C6 bit in
the VW2C register to
0 (voltage monitor 2
interrupt mode)
Set the VW2C6 bit in
the VW2C register to
1 (voltage monitor 2
reset mode)
(low-speed on-chip oscillator on)
x 4 cycles
Voltage Monitor 2
Interrupt
Voltage Monitor 2
Reset
Select the timing of the interrupt and reset
request by the VW2C7 bit in the VW2C
register
(1)
Set the VW2C1 bit in the VW2C register to 1
(digital filter disabled)
Set the VW2C6 bit in
the VW2C register to
0 (voltage monitor 2
interrupt mode)
Set the VW2C6 bit in
the VW2C register to
1 (voltage monitor 2
reset mode)
−
− (no wait time)
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R8C/20 Group, R8C/21 Group 6. V oltage Detection Circuit
When the VW2C1 bit is set
to 0 (digital filter enabled)
When the VW2C1 bit is
set to 1 (digital filter
disabled) and the
VW2C7 bit is set to 0
(Vdet2 or above)
When the VW2C1 bit is
set to 1 (digital filter
disabled) and the
VW2C7 bit is set to 1
(Vdet2 or below)
Vdet2
(1)
2.7 V
VCA13 bit
VW2C2 bit
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
VW2C2 bit
Voltage monitor 2
interrupt request
(VW2C6 = 0)
VW2C2 bit
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
VCC
1
0
Sampling clock of digital filter
x 4 cycles
1
0
1
0
1
0
Sampling clock of digital filter
x 4 cycles
Set to 0 by a program
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Set to 0 by interrupt
request acknowledgement
Set to 0 by a program
Set to 0 by interrupt
request
acknowledgement
VCA13 : Bit in VCA1 register
VW2C1, VW2C2, VW2C6, VW2C7 : Bit in VW2C register
The above applies to the following conditions.
• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (enables voltage monitor 2 interrupt and voltage monitor 2 reset)
NOTE:
1. When the voltage monitor 1 reset is not used, set the power supply to VCC
≥ 2.7.
Figure 6.8 Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
7. Programmable I/O Ports
There are 41 programmable Input/Output ports (I/O ports) P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5,
and P6. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used, and the
P4_2 can be used as an input-only port if the A/D converter is not used.
Table 7.1 Overview of Programmable I/O Ports
Ports I/O Type of Output I/O Setting Internal Pull-Up Resister
P0 to P2, P6 I/O CMOS3 state Set every bit
P3_0, P3_1, P3_3 to
I/O CMOS3 state Set every bit
Set every 4 bits
Set every 3 bits
P3_5, P3_7
P4_3 I/O CMOS3 state Set every bit
P4_4, P4_5 I/O CMOS3 state Set every bit
(2)
P4_2
P4_6, P4_7
(3)
I (No output function) None None
Set every bit
Set every 2 bits
NOTES:
1. In input mode, whether the internal pull-up resistor is connected or not can be sel ected by the PUR0
and PUR1 registers.
2. When the A/D converter is not used, these ports can be used as the inp ut port only.
3. When the XIN clock oscillation circuit is not used, these ports can be used as the input port only.
(1)
(1)
(1)
(1)
7.1 Functions of Programmable I/O Ports
The PDi_j (i = 0 to 4, 6, j = 0 to 7) bit in the PDi register controls I/O of the ports P0 to P2, P3_0, P3_1, P3_3 to
P3_5, P3_7, P4_3 to P4_5, and P6. The Pi register consists of a port latch to hold output data and a circuit to read
pin state.
Figures 7.1 to 7.7 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of
Programmable I/O Ports. Also, Figure 7.9 shows the PDi (i = 0 to 4 and 6) Registers. Figure 7.10 shows the Pi (i =
0 to 4 and 6) Registers, Figure 7.11 shows the Registers PUR0 and PUR1 and Figure 7.12 shows the PMR Register.
Table 7.2 Functions of Programmable I/O Ports
Operation When
Accessing
Pi Register
When PDi_j bit is set to 0 (input mode) When PDi_j bit is set to 1 (output mode)
Value of PDi_j Bit in PDi Register
Reading Read pin input level Read the port latch
Writing Write to the port latch Write to the port latch. The value written in
the port latch, it is output from the pin.
i = 0 to 4, 6, j = 0 to 7
NOTE:
1. Nothing is assigned to bits PD3_2, PD3_6, PD4_0 to PD4_2, PD4_6, and PD4_7.
(1)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
7.2 Effect on Peripheral Functions
Programmable I/O ports function as I/O of peripheral functions (refer to Table 1.6 Pin Name Information by Pin
Number).
Ta ble 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4, 6 j = 0 to
7). Refer to descriptions of each function for how to set peripheral functions.
T able 7.3 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4, 6 j = 0 to 7)
I/O of Peripheral Functions PDi_j Bit Setting of Port shared with Pin
Input Set this bit to 0 (input mode).
Output This bit can be set to both 0 or 1 (output regardless of the port setting)
7.3 Pins Other than Programmable I/O Ports
Figure 7.8 shows the Configuration of I/O Pins.
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
P0
Data bus
P1_0 to P1_3
Pull-up selection
Direction
register
(1)
Port latch
(1)
Analog input
Pull-up selection
Direction
register
1
(1)
Output from each periph eral fu nct io n
Port latchData bus
(1)
Input to each peripheral function
Analog input
P1_4
Direction
Output from each periph eral fu nct io n
Port latchData bus
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage on each port will not exceed VCC.
Pull-up selection
register
1
Figure 7.1 Configuration of Programmable I/O Ports (1)
(1)
(1)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
P1_5 and P1_7
Output from each periph eral fu nct io n
INT1 input
Input to each peripheral function
P1_6 and P2
Output from each periph eral fu nct io n
Pull-up selection
Direction
register
1
(1)
Port latchData bus
(1)
Digital
filter
Pull-up selection
Direction
register
1
(1)
Port latchData bus
(1)
Input to each peripheral function
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage on each port will not exceed VCC.
Figure 7.2 Configuration of Programmable I/O Ports (2)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
P3_0 and P3_1
Output from each peripheral function
P3_3 to P3_5 and P3_7
Output from each peripheral function
Data bus
Pull-up selection
Direction
register
1
(1)
Port latchData bus
(1)
Pull-up selection
Direction
register
1
(1)
Port latch
(1)
Input to each peripheral function
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage on each port will not exceed VCC.
Figure 7.3 Configuration of Programmable I/O Ports (3)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
P4_2/VREF
P4_3 and P4_4
NOTE:
1. symbolizes a parasitic diode.
(1)
Data bus
(1)
Pull-up selection
Direction
register
(1)
Port latchData bus
(1)
Ensure the input voltage on each port will not exceed VCC.
Figure 7.4 Configuration of Programmable I/O Ports (4)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
P4_5
INT0 and input to each peripheral function
P4_6/XIN
Pull-up selection
Direction
register
(1)
Port latchData bus
(1)
Digital
filter
(1)
Data bus
Clocked inverter
(2)
P4_7/XOUT
Data bus
NOTES:
1. symbolizes a parasitic diode.
Ensure the input voltage on each port will not exceed VCC.
2. When CM05 = 1, CM10 = 1, or CM13 = 0, the clocked inverter is cutoff.
3. When CM10 = 1 or CM13 = 0, the feedback resistor is unconnected.
4. When CM05 = CM13 = 1 or CM10 = CM13 = 1, this pin is pulled up.
Figure 7.5 Configuration of Programmable I/O Ports (5)
(1)
(3)
(1)
(4)
(1)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
P6_0
Data bus
P6_1 to P6_5
Pull-up selection
Direction
register
Output from each peripheral function
Port latch
Pull-up selection
Direction
register
Port latchData bus
1
(1)
(1)
(1)
(1)
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage on each port will not exceed VCC.
Figure 7.6 Configuration of Programmable I/O Ports (6)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
P6_6
P6_7
Pull-up selection
Direction
register
Output from each peripheral function
Port latchData bus
INT2 input
Pull-up selection
Direction
register
Port latchData bus
1
(1)
(1)
Digital
filter
(1)
(1)
INT3 input
Input to each peripheral function
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage on each port will not exceed VCC.
Digital
filter
Figure 7.7 Configuration of Programmable I/O Ports (7)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
MODE
MODE signal input
(1)
RESET
RESET signal input
(1)
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage on each port will not exceed VCC.
Figure 7.8 C onfiguration of I/O Pins
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Port Pi Directio n Regi st er (i = 0 t o 4, 6)
b7 b6 b5 b4 b3 b2
NOTES:
1.
Nothing is assigned to the PD3_2 and PD3_6 bits in the PD3 register.
When writing to the PD3_2 and PD3_6 bits , w rite 0 (input mode). When read, its content is 0.
2.
Nothing is assigned to the PD4_0 to PD4_2, PD4_6 and PD4_7 bits in the PD4 register.
When writing to the PD4_0 to PD4_2, PD4_6 and PD4_7 bits in the PD4 register, w rite 0 (input mode). When read, its
content is 0.
3.
Write to the PD0 register w ith the next instruction after that used to set the PRC2 bit in the PRCR register to 1 (w rite
enabled).
b1 b0
Symbol Address After Reset
(3)
PD0
PD1
PD2
PD3
PD4
PD6
Bit Symbol Bit Name Function RW
PDi_0
PDi_1
PDi_2
Port Pi_0 direction bit
Port Pi_1 direction bit
Port Pi_2 direction bit
PDi_3 Port Pi_3 direction bit
PDi_4
PDi_5
PDi_6
Port Pi_4 direction bit
Port Pi_5 direction bit
Port Pi_6 direction bit RW
PDi_7 Port Pi_7 direction bit RW
(1,2)
00E2h 00h
00E3h 00h
00E6h 00h
00E7h 00h
00EAh 00h
00EEh 00h
(functions as an input port)
1 : Output mode
(functions as an output port)
RW0 : Input mode
RW
RW
RW
RW
RW
Figure 7.9 PDi (i = 0 to 4 and 6) Registers
P0
P1
P2
P3
P4
P6
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Pi_7
(1,2)
00E0h Indeterminate
00E1h Indeterminate
00E4h Indeterminate
00E5h Indeterminate
00E8h Indeterminate
00ECh Indeterminate
Port Pi_0 bit
Port Pi_1 bit
Port Pi_2 bit
Port Pi_3 bit
Port Pi_4 bit
Port Pi_5 bit
Port Pi_6 bit RW
Port Pi_7 bit
Port Pi Regi st er (i = 0 t o 4, 6)
b7 b6 b5 b4
NOTES:
b3 b2 b1 b0
Symbol Address After Reset
Bit Symbol Bit Name Function RW
Nothing is assigned to the P3_2 and P3_6 bits in the P3 register.
1.
When writing to the P3_2 and P3_6 bits, write 0 (“L” level). When read, its content is 0.
2. Nothi ng is assigned to the P4_0 and P4_1 bits in the P4 register.
When write to the P4_0 and P4_1 bits, w rite 0 (“L” level). When read, its content is 0.
The pi n level on any I/O port which is set
for input mode can be read by reading the
corresponding bit in thi s register. The pin
level on any I/O port which is set for
output m ode can be controlled by writing
to the corresponding bit in this register.
0 : “L” level
1 : “H” level
RW
RW
RW
RW
RW
RW
RW
Figure 7.10 Pi (i = 0 to 4 and 6) Registers
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r
Pull -Up Control Regis ter 0
b7 b6 b5 b4
NOTE:
b3 b2 b1 b0
Symbol Address After Reset
PUR0
00FCh 00h
Bit Symb o l Bit Name Function RW
PU00
PU01
PU02
P0_0 to P0_3 pull-up
P0_4 to P0_7 pull-up
P1_0 to P1_3 pull-up
PU03 P1_4 to P1_7 pull-up
PU04 RW
PU05
PU06
P2_0 to P2_3 pull-up
P2_4 to P2_7 pull-up
P3_0, P3_1, and P3_3 pull-up
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PU07
(1)
0 : Not pulled up
1 : Pulled up
0 : Not pulled up
1 : Pulled up
0 : Not pulled up
1 : Pulled up
0 : Not pulled up
1 : Pulled up
1. When this bit is set to 1 (pulled up), the pin whose direct bit is set to 0 (input mode) is pulled up.
RW
RW
RW
RW
RW
RW
RWP3_4 to P3_5, and P3_7 pull-up
Pul l -Up Cont rol Regi ster 1
b0
b7 b6 b5 b4
NOTE:
b3 b20b1
0
Symbol Address After Reset
PUR1
00FDh XX00XX00b
Bit Symbol Bit Name Function RW
PU10
PU11
—
P4_3 pull-up
(1)
P4_4 and P4_5 pull-up
Reserved bits
(1)
0 : Not pulled up
1 : Pull ed up
0 : Not pulled up
1 : Pull ed up
Set to 0
(b3-b2)
PU14 P6_0 to P6_3 pull-up
PU15 P6_4 to P6_7 pull-up
—
Nothing is assigned. If necessary, set to 0.
(b7-b6)
When this bit is set to 1 (pulled up) and the pin whose direct bit is set to 0 (input mode), the pin is pulled up.
1.
When read, the content is 0.
(1)
(1)
1 : Pull ed up
RW
RW
RW
RW0 : Not pulled up
RW
—
Figure 7.11 Registers PUR0 and PUR1
Port Mo de Regi st e
b0
00
b3 b20b1
0
00
Symbol Address After Reset
b7 b6 b5 b4
PMR
Bit Symbol Bit Name Function RW
Res erved bits
—
(b3-b0)
U1PINSEL
Port TXD1/RXD1 switch bit
—
Res erved bits
(b6-b5)
2
SSU/I
IICSEL RW
C bus sw itch bit
Figure 7.12 PMR Re gi st er
Rev.2.00 Aug 27, 2008 Page 49 of 458
REJ09B0250-0200
00F8h 00h
Set to 0
0 : I/O port P6_6 , P6_7
1 : TXD1, RXD1
Set to 0
0 : SSU function selects
2
1 : I
C bus function selects
—
RW
—
Page 66
R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
7.4 Port Settings
Table 7.4 to Table 7.47 list the port settings.
Table 7.4 Port P0_0/AN7
Register PD0 ADCON0
Bit PD0_0 CH2 CH1 CH0 ADGSEL0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
0XXXX
1 X X X X Output port
0 1 1 1 0 A/D converter input (AN7)
Table 7.5 Port P0_1/AN6
Register PD0 ADCON0
Bit PD0_1 CH2 CH1 CH0 ADGSEL0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
0XXXX
1 X X X X Output port
0 1 1 0 0 A/D converter input (AN6)
Input port
Input port
(1)
(1)
Function
Function
Table 7.6 Port P0_2/AN5
Register PD0 ADCON0
Bit PD0_2 CH2 CH1 CH0 ADGSEL0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
0XXXX
1 X X X X Output port
0 1 0 1 0 A/D converter input (AN5)
Table 7.7 Port P0_3/AN4
Register PD0 ADCON0
Bit PD0_3 CH2 CH1 CH0 ADGSEL0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
0XXXX
1 X X X X Output port
0 1 0 0 0 A/D converter input (AN4)
Table 7.8 Port P0_4/AN3
Register PD0 ADCON0
Bit PD0_4 CH2 CH1 CH0 ADGSEL0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
0XXXX
1 X X X X Output port
0 0 1 1 0 A/D converter input (AN3)
Input port
Input port
Input port
Function
(1)
Function
(1)
Function
(1)
Rev.2.00 Aug 27, 2008 Page 50 of 458
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.9 Port P0_5/AN2
Register PD0 ADCON0
Bit PD0_5 CH2 CH1 CH0 ADGSEL0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
0XXXX
1 X X X X Output port
0 0 1 0 0 A/D converter input (AN2)
Input port
(1)
Function
Table 7.10 Port P0_6/AN1
Register PD0 ADCON0
Bit PD0_6 CH2 CH1 CH0 ADGSEL0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
0XXXX
1 X X X X Output port
0 0 0 1 0 A/D converter input (AN1)
Input port
(1)
Function
Table 7.11 Port P0_7/AN0
Register PD0 ADCON0
Bit PD0_7 CH2 CH1 CH0 ADGSEL0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
0XXXX
1 X X X X Output port
0 0 0 0 0 A/D converter input (AN0)
Input port
(1)
Function
Table 7.12 Port P1_0/KI0/AN8
Register PD1 KIEN ADCON0
Bit PD1_0 KI0EN CH2 CH1 CH0 ADGSEL0
0XXXXX
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
1 X X X X X Output port
01XXXX
0 X 1 0 0 1 A/D converter input (AN8)
Table 7.13 Port P1_1/KI1/AN9
Register PD1 KIEN ADCON0
Bit PD1_1 KI1EN CH2 CH1 CH0 ADGSEL0
0XXXXX
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
1 X X X X X Output port
01XXXX
0 X 1 0 1 1 A/D converter input (AN9)
Input port
KI
0 input
Input port
1 input
KI
Function
(1)
Function
(1)
Rev.2.00 Aug 27, 2008 Page 51 of 458
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.14 Port P1_2/KI2/AN10
Register PD1 KIEN ADCON0
Bit PD1_2 KI2EN CH2 CH1 CH0 ADGSEL0
0XXXXX
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
1 X X X X X Output port
01XXXX
0 X 1 1 0 1 A/D converter input (AN10)
Input port
2 input
KI
Function
(1)
Table 7.15 Port P1_3/KI3/AN11
Register PD1 KIEN ADCON0
Bit PD1_3 KI3EN CH2 CH1 CH0 ADGSEL0
0XXXXX
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
1 X X X X X Output port
01XXXX
0 X 1 1 1 1 A/D converter input (AN11)
Input port
input
KI3
Function
(1)
Table 7.16 Port P1_4/TXD0
Register PD1 U0MR
Bit PD1_4 SMD2 SMD1 SMD0
0000
1 0 0 0 Output port
Setting
value
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the NCH bit in the U0C0 register to 1.
X
001
100
101
110
Input port
TXD0 output
(1)
(2)
Table 7.17 Port P1_5/RXD0/(TRAIO)/(INT1)
Register PD1 TRAIOC TRAMR INTEN
Bit PD1_5 TIOSEL TOPCR TMOD2 TMOD1 TMOD0 INT1EN
0XXXX
0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
1
0
0 1 X Other than 001b X TRAIO input
0 1 X Other than 001b 1
X 1 0 0 0 1 X TRAIO pulse output
X1XXX
X X Other than 001b
0XXXX
X X Other than 001b
X X Other than 001b
0X001
Function
X
Input port
X Output portX1XXX
X RXD0 input
TRAIO/INT1
Function
(1)
input
Rev.2.00 Aug 27, 2008 Page 52 of 458
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.18 Port P1_6/CLK0
Register PD1 U0MR
Bit PD1_6 SMD2 SMD1 SMD0 CKDIR
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
0
1 Other than 001b X Output port
0 X X X 1 CLK0 (external clock) input
X 0 0 1 0 CLK0 (internal clock) output
Other than 001b X
XXX1
Input port
(1)
Function
Table 7.19 Port P1_7/TRAIO/INT1
Register PD1 TRAIOC TRAMR INTEN
Bit PD1_7 TIOSEL TOPCR TMOD2 TMOD1 TMOD0 INT1EN
0XXXX
0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
1
0 0 X Other than 001b X TRAIO input
0 0 X Other than 001b 1
X 0 0 0 0 1 X TRAIO pulse output
X1XXX
X X Other than 001b
1XXXX
X X Other than 001b
X
X Output portX1XXX
Input port
TRAIO/INT1
Function
(1)
input
Table 7.20 Port P2_0/TRDIOA0/TRDCLK
Register PD2 TRDOER1 TRDFCR TRDIORA0
Bit PD2_0 EA0 CMD1 CMD0 STCLK PWM3 IOA2 IOA1 IOA0
0 1 XXXXXXX
1 1 X X X X X X X Output port
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
0 X 0 0 0 1 1 X X Timer mode (input capture function)
0 X XX1 1000External clock input (TRDCLK)
X 0 0 0 0 0 X X X PWM3 mode waveform output
X00001
001
01X
Function
Input port
Timer mode waveform output
(output compare function)
(1)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.21 Port P2_1/TRDIOB0
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORA0
Bit PD2_1 EB0 CMD1 CMD0 PWM3 PWMB0 IOB2 IOB1 IOB0
01XXXXXXX
1 1 X X X X X X X Output port
0 X 0 0 1 0 1 X X Timer mode (input capture function)
10
11
X X X X X Complementary PWM mode waveform output
001
01X
Setting
value
X0
X001XXXXX
X 0 0 0 0 X X X X PWM3 mode waveform output
X 0 0 0 1 1 X X X PWM mode waveform output
X00010
X: 0 or 1
NOTE:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
Input port
Reset synchronous PWM mode waveform output
Timer mode waveform output (out put comp are
function)
(1)
Function
Table 7.22 Port P2_2/TRDIOC0
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC0
Bit PD2_2 EC0 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC0
0 1 XXX X XXX
1 1 XXX X XXXOutput port
0 X 0 0 1 0 1 X X Timer mode (input capture function)
10
11
XXXXX
001
01X
Setting
value
X0
X001XXXXX
X 0 0 0 1 1 X X X PWM mode waveform output
X 0 001 0
X: 0 or 1
NOTE:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
Input port
Complementary PWM mode waveform
output
Reset synchronous PWM mode waveform
output
Timer mode waveform output (output
compare function)
Function
(1)
Table 7.23 Port P2_3/TRDIOD0
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC0
Bit PD2_3 ED0 CMD1 CMD0 PWM3 PWMD0 IOD2 IOD1 IOD0
0 1 XXX X XXX
1 1 XXX X XXXOutput port
0 X 0 0 1 0 1 X X Timer mode (input capture function)
Setting
value
X0
X001XXXXX
X 0 0 0 1 1 X X X PWM mode waveform output
X 0 001 0
X: 0 or 1
NOTE:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
10
11
XXXXX
001
01X
Function
Input port
Complementary PWM mode waveform
output
Reset synchronous PWM mode waveform
output
Timer mode waveform output (output
compare function)
(1)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.24 Port P2_4/TRDIOA1
Register PD2 TRDOER1 TRDFCR TRDIORA1
Bit PD2_4 EA1 CMD1 CMD0 PWM3 IOA2 IOA1 IOA0
0 1 XXXXXX
1 1 XXXXXXOutput port
0 X 0 0 1 1 X X Timer mode (input capture function)
Setting
value
X0
X 0 0 1 X X X X Reset synchronous PWM mode waveform output
X 0 001
10
11
X X X X Complementary PWM mode waveform output
001
01X
X: 0 or 1
NOTE:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
Input port
Timer mode wavefor m outp ut
(output compare function)
(1)
Function
Table 7.25 Port P2_5/TRDIOB1
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORA1
Bit PD2_5 EB1 CMD1 CMD0 PWM3 PWMB1 IOB2 IOB1 IOB0
0 1 XXX X XXX
1 1 X X X X X X X Output port
0 X 0 0 1 0 1 X X Timer mode (input capture function)
10
11
X X X X X Complementary PWM mode waveform output
001
01X
Setting
value
X0
X001XXXXX
X 0 0 0 1 1 X X X PWM mode waveform output
X 0 001 0
X: 0 or 1
NOTE:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
Input port
Reset synchronous PWM mode waveform
output
Timer mode waveform output (out pu t
compare function)
Function
(1)
Table 7.26 Port P2_6/TRDIOC1
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC1
Bit PD2_6 EC1 CMD1 CMD0 PWM3 PWMC1 IOC2 IOC1 IOC0
0 1 XXX X XXX
1 1 X X X X X X X Output port
0 X 0 0 1 0 1 X X Timer mode (input capture function)
Setting
value
X0
X001XXXXX
X 0 0 0 1 1 X X X PWM mode waveform output
X 0 001 0
X: 0 or 1
NOTE:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
10
11
X X X X X Complementary PWM mode waveform output
001
01X
Function
Input port
Reset synchronous PWM mode waveform
output
Timer mode waveform output (out pu t
compare function)
(1)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.27 Port P2_7/TRDIOD1
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC1
Bit PD2_7 ED1 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD0
0 1 XXX X XXX
1 1 X X X X X X X Output port
0 X 0 0 1 0 1 X X Timer mode (input capture function)
10
11
X X X X X Complementary PWM mode waveform output
001
01X
Setting
value
X0
X001XXXXX
X 0 0 0 1 1 X X X PWM mode waveform output
X 0 001 0
X: 0 or 1
NOTE:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
Input port
Reset synchronous PWM mode waveform
output
Timer mode waveform output
(output compare function)
Function
(1)
Table 7.28 Port P3_0/TRAO
Register PD3 TRAIOC
Bit PD3_0 TOENA
Setting
value
00
1 0 Output port
X 1 TRAO output
Input port
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
(1)
Function
Table 7.29 Port P3_1/TRBO
Register PD3 TRBMR TRBIOC
Bit PD3_1 TMOD1 TMOD0 TOCNT
000X
Setting
value
100X
X 01b 1
X Other than 00b 0 TRBO output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
Input port
Output port
(1)
Function
Table 7.30 Port P3_3/SSI
Clock Synchronous Serial I/O with Chip Select
Register PD3
Bit PD3_3 SSI output control SSI input control IICSEL
00 00
0X X1
Setting
value
10 00
1X X1
X 0 1 0 SSI input
X1 00
X: 0 or 1
NOTES:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the SOOS bit in the SSMR2 register to 1 when this pin functions as output.
(Refer to Table 16.4 Association between
Communication Modes and I/O Pins.)
PMR
Input port
Output port
SSI output
Function
(1)
(2)
(2)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.31 Port P3_4/SDA/SCS
Register PD3 SSMR2 PMR ICCR1
Bit PD3_4 CSS1 CSS0 IICSEL ICE
0000X
000X0
1000X
Setting
value
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
100X0
X010X
X
X X X 1 1 SDA input/output
10
11
0X
Input port
Output port
SCS
SCS
input
output
(1)
(2)
(2)
Function
Table 7.32 Port P3_5/SCL/SSCK
Register PD3
Bit PD3_5 SSCK output control SSCK input control IICSEL ICE
Setting
value
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
Clock Synchronous Serial I/O with Chip Select
(Refer to Table 16.4 Association between
Communication Modes and I/O Pins.)
00 00X
00 0X0
10 00X
10 0X0
X 0 1 0 0 SSCK input
X1 000
X 1 0 1 1 SCL input/output
PMR ICCR1
Input port
Output port
SSCK output
(1)
(2)
(2)
Function
Table 7.33 Port P3_7/SSO
Clock Synchronous Serial I/O with Chip Select
Register PD3
Bit PD3_7 SSO output control SSO input control SOOS IICSEL
00 0X0
0X XX1
10 000
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
1X X 01
X 0 1 0 0 SSO input
X 1 0 0 0 SSO output (CMOS output)
X1 0 10
(Refer to Table 16.4 Association between
Communication Modes and I/O Pins.)
SSMR2 PMR
Table 7.34 Port P4_2/VREF
Register ADCON1
Bit VCUT
Setting
value
0 Input port
1 Input port/VREF input
Function
Function
Input port
Output port
SSO output (N-channel open-drain
output)
(1)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.35 Port P4_3
Register PD4
Bit PD4_3
Setting
value
NOTE:
1. Pulled up by setting the PU10 bit in the PUR0 register to 1.
0
1 Output port
Input port
(1)
Function
Table 7.36 Port P4_4
Register PD4
Bit PD4_4
Setting
value
NOTE:
1. Pulled up by setting the PU11 bit in the PUR0 register to 1.
0
1 Output port
Input port
(1)
Function
Table 7.37 Port P4_5/INT0
Register PD4 INTEN
Bit PD4_5 INT0EN
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU11 bit in the PUR0 register to 1.
0X
1 X Output port
01
Input port
INT0
(1)
input
Function
Table 7.38 Port P4_6/XIN
Register CM1 CM0 Circuit specifications
Bit CM13 CM10 CM05
0 X X OFF OFF Input port
Setting
value
X: 0 or 1
1 0 0 ON ON XIN-XOUT oscillation
1 0 1 OFF ON External XIN input
1 1 0 OFF OFF XIN-XOUT oscillation stop
1 1 1 OFF OFF XIN-XOUT oscillation stop
Oscillation
buffer
Feedback
Table 7.39 Port P4_7/XOUT
Register CM1 CM0 Circuit specifications
Bit CM13 CM10 CM05
0 X X OFF OFF Input port
Setting
value
X: 0 or 1
1 0 0 ON ON XIN-XOUT oscillation
1 0 1 OFF ON XOUT is “H” pull-up
1 1 0 OFF OFF XIN-XOUT oscillation stop
1 1 1 OFF OFF XIN-XOUT oscillation stop
Oscillation
buffer
Feedback
Function
resistor
Function
resistor
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.40 Port P6_0/TREO
Register PD6 TRECR1
Bit PD6_0 TOENA
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR0 register to 1.
00
1 0 Output port
X 1 TREO output
Input port
(1)
Function
Table 7.41 Port P6_1
Register PD6
Bit PD6_1
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR0 register to 1.
0
1 Output port
Input port
(1)
Function
Table 7.42 Port P6_2
Register PD6
Bit PD6_2
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR0 register to 1.
0
1 Output port
Input port
(1)
Function
Table 7.43 Port P6_3
Register PD6
Bit PD6_3
Setting
value
NOTE:
1. Pulled up by setting the PU14 bit in the PUR0 register to 1.
0
1 Output port
Input port
Table 7.44 Port P6_4
Register PD6
Bit PD6_4
Setting
value
NOTE:
1. Pulled up by setting the PU15 bit in the PUR0 register to 1.
0
1 Output port
Input port
Table 7.45 Port P6_5
Register PD6
Bit PD6_5
Setting
value
NOTE:
1. Pulled up by setting the PU15 bit in the PUR0 register to 1.
0
1 Output port
Input port
Function
(1)
Function
(1)
Function
(1)
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
Table 7.46 Port P6_6/INT2/TXD1
Register PD6 PMR U1MR U1C0 INTEN
Bit PD6_6 U1PINSEL SMD2 SMD1 SMD0 NCH INT2EN
0
1
0XXXXX1
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR0 register to 1.
X1
X1
X 000
0XXX
X 000
0XXX
001
100
101
110
001
100
101
110
XX
X X Output port
0 X TXD1 output (CMOS output)
1 X TXD1 output (N-channel open-drain output)
Input port
input
INT2
Function
(1)
Table 7.47 Port P6_7/INT3/RXD1
Register PD6 PMR INTEN
Bit PD6_7 U1PINSEL INT3EN
0XX
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR0 register to 1.
1 X X Output port
0X1
0 1 X RXD1 input
Input port
input
INT3
(1)
Function
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports
7.5 Unassigned Pin Handling
Table 7.48 lists Unassigned Pin Handling.
Table 7.48 Unassigned Pin Handling
Pin Name Connection
Ports P0 to P2, P3_0,
P3_1, P3_3 to P3_7,
P4_3 to P4_5, P6
Ports P4_6, P4_7
Port P4_2/VREF Connect to VCC
RESET
(3)
NOTES:
1. If these ports are set to output mode and left open, th ey remain input mode un til they are switched to
output mode by a program. The voltage level of these pins may be undefined and the power current
may increase while the ports remain input mode.
The content of the direction registers may change due to noise or program runaway caused by
noise. In order to enhance program reliability, the program should periodically repeat the setting of
the direction registers.
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) as
possible.
3. When power-on reset function is in use.
• After setting to input mode, connect every pin to VSS via a resistor (pulldown) or connect every pin to VCC via a resistor (pull-up).
• After setting to output mode, leave these pins open.
Connect to VCC via a resistor (pull-up)
Connect to VCC via a resistor (pull-up)
(2)
(2)
(2)
(1, 2)
MCU
Port P0 to P2, P3_0,
P3_1, P3_3 to P3_7,
P4_3 to P4_5, P6
NOTE:
1. When power-on reset function is in use.
Figure 7.13 Unassigned Pin Handling
(Input mode )
:
:
(Input mode)
(Output mode)
Port P4_6, P4_7
RESET
Port P4_2/VREF
:
:
Open
(1)
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R8C/20 Group, R8C/21 Group 8. Processor Mode
y
8. Processor Mode
8.1 Processor Modes
Single-chip mode can be selected as processor mode.
Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1
Register.
Table 8.1 Features of Processor Mode
Processor Mode Accessible Areas Pins Assignable as I/O Port Pins
Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
function I/O pins
Proces sor M ode Regi st er 0
b7 b6 b5 b4 b3 b2—b1 b0
000
NOTE:
1.
Set the PRC 1 bit in the PRCR register to 1 (enables w riting) before rew riting to the PM0 register.
Symbol Address After Reset
PM0 0004h 00h
Bit Symbol Bit Name Function RW
—
(b2-b0)
PM03
—
(b7-b4)
Figure 8.1 PM0 Register
Proces sor M ode Regi st er 1
b7 b6 b5 b4 b3 b2—b1 b0
0
NOTES :
Set the PRC 1 bit in the PRCR register to 1 (enables w riting) before rewriting to the P M1 register.
1.
The PM12 bit is set to 1 by a program (it remains unchanged even if it is set to 0).
2.
When the CSPRO bit in the CSPR register is set to 1 (selects count source protect mode), the PM12 bit is
automaticall
00
Symbol Address After Reset
PM1 0005h 00h
Bit Symbol Bit Name Function RW
—
(b1-b0)
PM12
—
(b6-b3)
—
(b7)
set to 1.
(1)
Reserved bits Set to 0
Softw are reset bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
(1)
Reserved bits Set to 0
WDT interrupt/reset sw itch bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Reserved bit Set to 0
The MCU is reset w hen this bit is set to 1.
When read, its content is 0.
0 : Watchdog timer interrupt
1 : Watchdog timer reset
(2)
RW
RW
RW
RW
RW
Figure 8.2 PM1 Register
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R8C/20 Group, R8C/21 Group 9. Bus
9. Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/20 Group and Table 9.2 lists Bus Cycles by Access Space of
the R8C/21 Group.
The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word-(16 bits) unit, these
area are accessed twice in 8-bit unit.
Table 9.3 lists Access Unit and Bus Operations.
Table 9.1 Bus Cycles by Access Space of the R8C/20 Group
Access Area Bus Cycle
SFR 2 cycles of CPU clock
ROM/RAM 1 cycle of CPU clock
Table 9.2 Bus Cycles by Access Space of the R8C/21 Group
Access Area Bus Cycle
SFR/Data flash 2 cycles of CPU clock
Program ROM/RAM 1 cycle of CPU clock
Table 9.3 Access Unit an d Bu s Op e ra t ions
Area
Even address
byte access
Odd address
byte access
Even address
word access
Odd address
word access
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
SFR, data flash
Even
Odd
Data
Data
Even + 1Even
Odd + 1Odd
Data
Data
Data
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
ROM (program ROM), RAM
Even
Data
Odd
Data
Even
Data
Odd
Data
Even + 1
Odd + 1
Data
Data
However, only following SFRs are connected with the 16-bit bus:
Timer RD: registers TRDi (i = 0, 1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi
Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, data flash, even address
byte access” in Table 9.3 Access Unit and Bus Operations, and 16-bit data is accessed at a time.
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
10. Clock Generation Circuit
The clock generation circuit has:
• XIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
Table 10.1 lists Specifications of Clock Generation Circ uit. Figure 10.1 shows a Cl ock Generation Circuit. Figu res
10.2 to 10.7 show clock-associated registers.
Table 10.1 Specifications of Clock Generation Circuit
Item
XIN Clock
Oscillation Circuit
Use of Clock • CPU clock source
• Peripheral
function clock
source
Clock Frequency 0 to 20 MHz
Connectable
Oscillator
•Ceramic
resonator
• Crystal oscillator
Oscillator
XIN, XOUT
(1)
Connect Pins
Oscillation Stop,
Usable Usable Usable
Restart Function
Oscillator Status
Stop Stop Oscillate
After Reset
Others Externally
generated clock
can be input
(2)
High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator
• CPU clock source
• Peripheral function clock
source
• CPU and peripheral function
clock sources when XIN clock
stops oscillating
Approx. 40 MHz
(3)
−−
(1)
−
−−
On-Chip Oscillator
• CPU clock source
• Peripheral function clock
source
• CPU and peripheral function
clock sources when XIN clock
stops oscillating
Approx. 125 kHz
(1)
−
NOTES:
1. These pins can be used as P4_6 and P4_7 when using the on-chip oscillator clock as the CPU
clock while the XIN clock oscillation circuit is not used.
2. Set the CM05 bit in the CM0 register to 1 (main clock stops) and the CM13 bit in the CM1 register to
1 (XIN-XOUT pin) when the external clock is input.
3. The clock frequency is automatically set to up to 20 MHz by a driver when using the high-speed onchip oscillator as the CPU clock source.
Rev.2.00 Aug 27, 2008 Page 64 of 458
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
RESET
Power-on reset
Software reset
Interrupt request
CM05
CM10 = 1 (stop mode)
WAIT
instruction
XIN
CM13
CM13
S
R
S
R
XOUT
a
FRA1 register
High-speed
on-chip
oscillator
FRA01 = 1
FRA01 = 0
Low-speed
on-chip
oscillator
Oscillation
stop
detection
System clock
b
1/2 1/2
Divider
fOCO-S
OCD2 = 1
OCD2 = 0
c
FRA2 register
fOCO
On-chip oscillator
clock
fOCO40M
Divider
(1/128)
fOCO-F
INT0
Power-on
reset
Voltage
detection
circuit
b
c
a
Divider
d
f1
f2
f4
d
f8
e
g
f32
h
e
1/2 1/2 1/2
fOCO128
Watchdog
timer
CPU clock
SSU/IIC
A/D
converter
Timer RDTimer RBTimer RA
Timer RE
UART0
UART1
g
Frequency adjustable
FRA00
CM14
Q
Q
XIN clock
CM02
CM02, CM05, CM06: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
OCD0, OCD1, OCD2: Bits in OCD register
FRA00, FRA01: Bits in FRA0 register
CM06 = 0
CM17 to CM16 = 00b
Oscillation stop detection circuit
Forcible discharge when OCD0 = 0
XIN clock
Pulse generation
circuit for clock edge
detection and
charge, discharge
control circuit
Charge,
discharge
circuit
OCD1
Figure 10.1 Clock Generation Circuit
CM06 = 0
CM06 = 0
CM17 to CM16 = 01b
Oscillation stop detection
interrupt generation
circuit detection
CM17 to CM16 = 10b
Watchdog
timer interrupt
Voltage watch
2 interrupt
OCD2 bit switch signal
CM14 bit switch signal
CM06 = 1
CM06 = 0
CM17 to CM16 = 11b
h
Details of divider
Oscillation stop
detection,
watchdog timer, voltage
monitor 2 interrupt
Rev.2.00 Aug 27, 2008 Page 65 of 458
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
Sys tem Clo ck Control Regi s ter 0
b7 b6 b5 b4 b3 b2 b1 b0
00100
NOTES:
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the CM0 register.
1.
The CM05 bit is to stop the XIN clock w hen the high-speed on-chip oscillator mode, low-speed on-chip oscillator
2.
mode is selected. Do not use this bit for w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the
following orders:
(a) Set the OCD0 and OCD1 bits in the OCD register to 00b.
(b) Set the OCD 2 bit to 1 (selects on-chip oscillator clock).
During external clock input, only the clock oscillation buffer is turned off and clock input is acknowledged.
3.
P4_6 and P4_7 can be used as input ports w hen the CM05 bit is set to 1 (XIN clock stops) and the CM13 bit in the
4.
CM1 register is set to 0 (P4_6, P4_7).
When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
5.
Symbol Address After Reset
CM0
Bit Symbol Bit Name Function RW
—
(b1-b0)
CM02
—
(b3)
—
(b4)
CM05
CM06
—
(b7)
(1)
0006h 01101000b
Reserved bits Set to 0
WAIT peripheral function clock stop
bit
0 : Peripheral function clock does not stop
in w ait mode
1 : Peripheral function clock stops in wait
mode
Reserved bit Set to 1
Reserved bit Set to 0
XIN clock (XIN-XOUT) stop bit
(2,4)
0 : XIN clock oscillates
1 : XIN clock stops
(5)
System clock division select bit 0
0 : Enables CM16, CM17
1 : Divide-by-8 mode
Reserved bit Set to 0
RW
RW
RW
RW
(3)
RW
RW
RW
Figure 10.2 CM0 Register
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
Sys tem Clo ck Control Regi s ter 1
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol Address After Reset
CM1
(1)
0007h 00100000b
Bit Symbol Bit Name Function RW
CM10
All clock stop control bit
—
Reserved bits Set to 0
(b2-b1)
CM13
CM14
CM15
Port XIN-XOUT sw itch bit
Low-speed on-chip oscillation stop
(5,6,8)
bit
XIN-XOUT drive capacity select bit
System clock division select bits 1
CM16 RW
CM17 RW
NOTES:
1.
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the CM1 register.
2.
When entering stop mode, the CM15 bit is set to 1 (drive capacity high).
When the CM06 bit is set to 0 (CM16, CM17 bits enabled), the CM16 to CM17 bits become enabled.
3.
I f the CM10 bit is 1 (stop mode), the internal feedback resistor becom es disabled.
4.
When the OCD2 bit is set to 0 (selects XIN clock), the CM14 bit is set to 1 (stops low-speed on-chip oscillator). When
5.
the OCD2 bit is set to 1 (selects on-chip oscill ator clock), the CM14 bit is set to 0 (low-speed on-chip oscillator on). It
remains unchanged even if it is set to 1.
6.
When using the low voltage 2 detection interrupt (when using the digital filter), set the CM14 bit to 0 (low -speed onchip oscillator on).
When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT
7.
(P4_7) pin becomes “H”. When the CM13 bit is set to 0 (input ports, P4_6, P4_7), the P4_7 (XOUT) enters
input mode.
I n count source protect mode (Refer to
8.
13.2 Count Source Protection Mode Enabled
unchanged even if the CM10 and CM14 bits are set.
9. Once the CM13 bit is set to 1, it can not to 0 in a program.
(4,7,8)
(7,9)
0 : Oscillates clock
1 : Stops all clocks (stop mode)
0 : Input ports P4_6, P4_7
1 : XIN-XOUT pin
0 : Low-speed on-chip oscillator on
1 : Low-speed on-chip oscillator off
(2)
0 : Low
1 : High
(3)
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
), the value remains
RW
RW
RW
RW
RW
Figure 10.3 CM1 Register
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
Os c i l l ati on S top Det ect i on Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
NOTES:
1.
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the OCD register.
2.
Set the OCD1 to OCD0 bits to 00b before entering stop and high-speed on-chip oscillator mode, low-speed on-chip
oscillator mode (XIN clock stops). Set the OCD1 to OCD0 bits to 00b when the FRA01 bit in the FRA0 register is set to
1 (selects high-speed on-chip oscillator).
3.
The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (selects on-chip oscillator clock).
4.
The OCD2 bit is automatically set to 1 (selects on-chip oscillator clock) if a XIN clock oscillation stop is detected w hile
the OCD1 to OCD0 bits are set to 11b. If the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains unchanged
when w riting 0 (selects XIN clock).
5.
The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled).
6.
The OCD3 bit remains 0 (XIN clock oscillates) if the OCD1 to OCD0 bits are set to 00b.
7.
Ref er to
Clock
Figure 10. 13 Procedure for Switch ing Clock Source from Low-Speed On-Chip Oscillator to XIN
for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.
Symbol Address After Reset
OCD
Bit Symbol Bit Name Function RW
Oscillation stop detection enable
(7)
OCD0 RW
OCD1 RW
OCD2
OCD3
—
bit
Oscillation stop detection
interrupt enable bit
System clock select bit
Clock monitor bit
R e served bits Set to 0
(b7-b4)
(1)
000Ch 00000100b
0 : Oscillation stop detection function
disabled
(2)
1 : Oscillation stop detection function enabled
0 : Disable
(2)
1 : Enable
(4)
0 : Selects XIN clock
(7)
1 : Selects on-chip oscillator clock
(5,6)
0 : XIN clock oscillates
1 : XIN clock stops
(3)
RW
RO
RW
Figure 10.4 O CD Re gi st er
Rev.2.00 Aug 27, 2008 Page 68 of 458
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
High-Spe ed On-Chi p Oscil l ator Cont rol Regi st er 0
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol Address After Reset
FRA0
0023h 00h
Bit Symbol Bit Name Function RW
FRA00 RW
FRA01 RW
—
High-speed on-chip oscillator enable
bit
High-speed on-chip oscillator select
(2)
bit
Reserved bits Set to 0
(b7-b2)
NOTES:
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the FRA0 register.
1.
2.
Change the FRA01 bit under the following conditions.
• FRA00 = 1 (high-speed on-chip oscillation)
• The CM14 bit in the CM1 register = 0 (low-speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register
All divide ratio mode settings are supported when VCC = 3.0 V to 5.5 V (J version) 000b to 111b
Divide ratio of 4 or more w hen VCC = 2.7 V to 5.5 V and K version 010b to 111b
When setting the FRA01 bit to 0 (selects low -speed on-chip oscillator), do not set the FRA00 bit to 0 (40MHz on-chip
3.
oscillator off) at the same time.
Set the FRA00 bit to 0 after setting the FRA01 bit to 0.
High-Spe ed On-Chi p Oscil l ator Cont rol Regi st e r 1
b7 b0
Symbol Address After Reset
FRA1
The frequency of high-speed on-chip oscillator is adjusted w ith bits 0 to 7.
High-speed on-chip oscillator frequency = 40 MHz (FRA1 register = value when shipping)
Set the value of the FRA1 register to smaller, the frequency w ill be higher
Set the value of the FRA1 register to larger, the frequency w ill be low er
NOTES:
1.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rewriting to the FRA1 register.
When adjusting the FRA1 register, set the value of the FRA1 register to 40 MHz and below.
2.
When changing the values of the FRA1 register, adjust the FRA1 register so that the frequency of the high-speed
on-chip oscillator clock w ill be 40 MHz or less.
0024h
(1)
(1)
Function
0 : High-speed on-chip oscillator off
1 : High-speed on-chip oscillator on
0 : Selects low -speed on-chip oscillator
1 : Selects high-speed on-chip oscillator
When Shipping
(2)
(3)
RW
RW
RW
Figure 10.5 Registers FRA0 and FRA1
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
High-Sp eed On-Chi p Oscil l ator Cont rol Regi st er 2
b3 b2 b1 b0b7 b6 b5 b4
0000
NOTES:
0
Symbol Address After Reset
FRA2
0025h 00h
Bit Symbol Bit Name Function RW
High-speed on-chip oscillator
FRA20
frequency sw itching bits
FRA21
FRA22 RW
—
Reserved bits Set to 0
(b7-b3)
Set the PRC 0 bit in the PRCR register to 1 (enables writing) before rew riting to the FRA2 register.
1.
Since the value after reset is 000b, set 010b to 111b on the K version products.
2.
Do not set on the K version products.
3.
(1)
(2)
The di vision of high-speed on-chip
oscillator clock can be selected.
b2 b1 b0
0 0 0 : Divide-by-2 mode
0 0 1 : Divide-by-3 mode
(3)
(3)
RW
0 1 0 : Divide-by-4 mode
0 1 1 : Divide-by-5 mode
RW
1 0 0 : Divide-by-6 mode
1 0 1 : Divide-by-7 mode
1 1 0 : Divide-by-8 mode
1 1 1 : Divide-by-9 mode
RW
Figure 10.6 FRA2 Register
Vol tage Det ect i on Regi st er 2
b7 b6 b5 b4 b3 b2 b1
00
NOTES:
Set the PRC 3 bit in the PRCR register to 1 (enables writing) before w riting to the VCA2 register.
1.
When using the voltage monitor 1 reset, set the VCA26 bit to 1.
2.
After the VCA26 bit is set from 0 to 1, the voltage detection circuit elapses for td(E-A) before starting operation.
When using the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
3.
After the VCA27 bit is from 0 to 1, the voltage detection circuit elapses for td(E-A) before starting operation.
The VCA27 bit remains unchanged after softw are reset, w atchdog timer reset, and voltage monitor 2 reset.
4.
5. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure shown in
10.10 Procedure for Enabling Reduced Internal Power Consumption U sing VCA20 bit
b0
000
Bit Symbol Bit Name Function RW
(1)
Symbol Address
VCA2 0032h
VCA20
I nternal power low consumption
enable bit
—
Reserved bits
(5)
(b5-b1)
VCA26
VCA27
Voltage detection 1 enable bit
Voltage detection 2 enable bit
After Reset
The LVD1ON bit in t he OF S regis t er is s et to 1: 00h
Power-on reset, v olt age m onit or 1 res et or t he LVD 1ON
bit in t he OF S regis t er is s et t o 0: 01 000000b
0 : Disables low consum ption
1 : Enables low consumption
Set to 0
(2)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled
(3)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled
(4)
RW
RW
RW
RW
Figure
.
Figure 10.7 VCA2 Register
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
The following describes the clocks generated by the clock generation circuit.
10.1 XIN Clock
This clock is supplied by a XIN clock oscillation circuit. This clock is used as the clock source for the CPU and
peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator b etween the
XIN and XOUT pins. The XIN clock oscillation circuit contains a feedback resistor, which is disconnected from
the oscillation circuit in stop mode in order to reduce the amount of power consumed in the chip. The XIN clock
oscillation circuit may also be configured by feeding an externally generated clock to the XIN pin.
Figure 10.8 shows Examples of XIN Clock Connection Circuit. During or after reset, the XIN clock stops.
The XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock on) after setting the
CM13 bit in the CM1 register to 1 (XIN- XOUT pin).
To use the XIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (select XIN clock) after
the XIN clock is oscillating stably.
The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (stop XIN clock) if the
OCD2 bit is set to 1 (select on-chip oscillator clock).
When the clocks externally generated to the XIN pin are input, a XIN clock does not stop if setting the CM05 bit
to 1. If necessary, use an external circuit to stop the clock.
In stop mode, all clocks including the XIN clock stop. Refer to 10.4 Power Control for details.
MCU
(built-in feedback resistor)
XIN
Rf
(1)
XOUT
Rd
(1)
COUTCIN
Ceramic resonator external circuit
NOTE:
1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so after
oscillation stabilizes.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 10.8 Examples of XIN Clock Connection Circuit
MCU
(built-in feedback resistor)
XIN
Externally derived clock
VCC
VSS
External clock inpu t clock
XOUT
Open
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
10.2 On-Chip Oscillator Clocks
This clock is supplied by an on-chip oscillator. The on-chip oscillator contains a high-speed on-chip oscillator and
a low-speed on-chip oscillator. Either an on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.
10.2.1 Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-S.
After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator by divide-by-8 is
selected for the CPU clock.
If the XIN clock stops oscillating when the OCD1 to OCD0 bits in the OCD register are set to 11b, the lowspeed on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU.
The frequency of the low-speed on-chip oscil lator varies depending o n the supply volt age and the operating
ambient temperature. The application products must be designed with sufficient margin to accommodate the
frequency range.
10.2.2 High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, fOCO-F and fOCO40M.
To use the high-speed on-chip oscillator clock as the clock source of the CPU clock, peripheral clock, fOCO,
and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows;
All divide ratio mode settings are supported when VCC = 3.0 V to 5.5 V (J version)000b to 111b
Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V and K version 010b to 111b
After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. The oscillation
starts by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can
be adjusted by the FRA1 and FRA2 registers.
Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make
adjustments by changing the settings of individual bits.
Adjust the amount of high-speed on-chip oscillator frequency to 40 MHz and below by setting the FRA1
register.
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
10.3 CPU Clock and Peripheral Function Clock
There are two type clocks: a CPU clock to operate the CPU and a peripheral function clock to operate the
peripheral functions. Refer to Figure 10.1 Clock Generation Circuit.
10.3.1 System Clock
The system clock is a clock source for the CPU and peripheral function clocks. The XIN clock or on-chip
oscillator clock can be selected.
10.3.2 CPU Clock
The CPU clock is an operating clock for the CPU and watchdog timer.
The system clock can be the divide-by-1 (no divi sion), 2, 4, 8 or 16 to produce th e CPU clock. Use the CM06
bit in the CM0 register and the CM16 to CM17 bits in the CM1 register to select the value of the division.
After reset, the low-speed on-chip oscillator clock divided-by-8 provides the CPU clock.
When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
10.3.3 Peripheral Function Clock (f1, f2, f4, f8 and f32)
The peripheral function clock is operating clock for the peripheral functions.
The clock fi (i = 1, 2, 4, 8, 32) is generated by the system clock divided-by-i. The clock fi is used for timers
RA, RB, RD, RE, serial interface and A/D converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function
clock stops in wait mode), the clock fi stop.
10.3.4 fOCO
fOCO is operating clocks for the peripheral functions.
The fOCO run at the same frequency as the on-chip oscillator clock and can be used as the source for the timer
RA.
When the WAIT instruction is executed, the clocks fOCO does not stop.
10.3.5 fOCO40M
fOCO40M is used as the count source for the timer RD. The fOCO40M is generated by the high-speed on-chip
oscillator and provided by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO40M does not stop.
fOCO40M can be used with supply voltage VCC = 3.0 to 5.5V.
10.3.6 fOCO-F
fOCO-F is used as the count source for the AD converter. The fOCO-F is generated by th e high-speed on -chip
oscillator and provided by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO-F does no t st op.
10.3.7 fOCO-S
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. When setting the CM14 bit
to 0 (low-speed on-chip oscillator on) using the clock generated by the low-speed on-chip oscillator, the fOCOS can be provided. When the WAIT instruction is executed or in cou nt source protect mode of the watchdog
timer, the clock fOCO-S does not stop.
10.3.8 fOCO128
fOCO128 is generated by fOCO divided-by-128. The clock fOCO128 is used for capture signal of timer RD
(channel 0).
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10.4 Power Control
There are three power control modes. All modes other than wait and stop modes are referred to as standard
operating mode.
10.4.1 Standard Operating Mode
Standard operating mode is further separated into three modes.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock s ource after switching needs to
be stabilized and oscillated. If the new clock source is the XIN clock, allow s ufficient wait ti me in a pro gram
until an oscillation is stabilized before exiting.
Table 10.2 Settings and Modes of Clock Associated Bits
Modes
High-speed
clock mode
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
−: can be 0 or 1, no change in outcome.
No division 0 00b
Divide-by-2 0 01b − 100−−
Divide-by-4 0 10b − 100−−
Divide-by-8 0 −−110−−
Divide-by-16 0 11b − 100−−
No division 1 00b −−0 − 11
Divide-by-2 1 01b
Divide-by-4 1 10b
Divide-by-8 1
Divide-by-16 1 11b
No division 1 00b 0
Divide-by-2 1 01b 0 − 0 − 0 −
Divide-by-4 1 10b 0 − 0 − 0 −
Divide-by-8 1 − 0 − 1 − 0 −
Divide-by-16 1 11b 0 − 0 − 0 −
OCD Register CM1 Register CM0 Register FRA0 Register
OCD2 CM17, CM16 CM14 CM13 CM06 CM05 FRA01 FRA00
− 100−−
−−0 − 11
−−0 − 11
−−−1 − 11
−−0 − 11
− 0 − 0 −
10.4.1.1 High-Speed Clock Mode
The XIN clock divided-by-1 (no division), -2, -4, -8, or -16 provides the CPU clock. Set the CM06 bit to 1
(divide-by-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode.
If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1
(high-speed on-chip oscillator on), the fOCO can be used for timers RA.
When the FRA00 bit is set to 1, fOCO40M can be used for timer RD.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the watchdo g timer
and voltage detection circuit.
10.4.1.2 High-Speed On-Chip Oscillator Mode
The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0
register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The onchip oscillator divided-by-1 (no division), -2, -4, -8 or -16 provides the CPU clock. Set the CM06 bit to 1
(divide-by-8) when transiting to high-speed clock mode.
If the FRA00 bit is set to 1, fOCO40M can be used for timer RD.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the watchdo g timer
and voltage detection circuit.
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10.4.1.3 Low-Speed On-Chip Oscillator Mode
If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the FRA01bit in the FRA0
register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock.
The on-chip oscillator clock divided-by-1 (no division), -2, -4, -8 or -16 provides the CPU clock. The on-chi p
oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8
mode) when transiting to high-speed cl ock mode. When the FRA00 bit is set to 1, fOCO40M c an be used for
timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the
watchdog timer and voltage detection circuit.
In this mode, stopping the XIN clock and high-speed on-chip oscillat or, and setting the FMR47 bit in the
FMR4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption
operation.
To enter wait mode from low-speed clock mode, settin g the VCA20 bit in the VCA2 register to 1 (internal
power low consumption enabled) enables lower consumption current in wait mode.
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.10 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
10.4.2 Wait Mode
Since the CPU clock stops in wait mode, the CPU operated in the CPU clock and the watchdog timer when
count source protection mode is disabled stops. The XIN clock and on-chip oscillator clock do not stop and the
peripheral functions using these clocks maintain operating.
10.4.2.1 Peripheral Function Clock Stop Function
If the CM02 bit is set to 1 (peripheral function cl ock stops in wait mode), the f1, f2, f4, f8 and f32 clocks stop
in wait mode. The power consumption can be reduced.
10.4.2.2 Entering Wait Mode
The MCU enters wait mode when the WAIT instruction is executed.
When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the
OCD1bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT
instruction.
If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled),
current consumption is not reduced because the CPU clock does not stop.
10.4.2.3 Pin Status in Wait Mode
The I/O port is the status before wait mode was entered is maintained.
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10.4.2.4 Exiting Wait Mode
The MCU exits wait mode by a hardware reset or peripheral function interrupt. When using a hardware reset to
exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral functi on interrup ts to 000b (int errupts d isabled )
before executing the WAIT instructio n.
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (per ipheral
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode.
When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the
peripheral function clock stop operating and the peripheral fu nctions operated by exte rnal signals can be used
to exit wait mode.
Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions.
Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions
Interrupt CM02 = 0 CM02 = 1
Serial Interface Interrupt Usable when operating with
internal or external clock
Clock Synchronous Serial I/O
with Chip Select Interrupt /
2
I
C Bus Interface Interrupt
Key Input Interrupt Usable Usable
A/D Conversion Interrupt Usable in one-shot mode − (Do not use)
Timer RA Interrupt Usable in all modes Can be used if there is no filter in event
Timer RB Interrupt Usable in all modes − (Do not use)
Timer RD Interrupt Usable in all modes Usable by selecting fOCO40M as
Timer RE Interrupt Usable in all modes − (Do not use )
INT
Interrupt
Voltage Monitor 2 Interrupt Usable Usable
Oscillation Stop Detection
Interrupt
Usable in all modes − (Do not use)
Usable
Usable − (Do not use)
Usable when operating with external
clock
counter mode.
Usable by selecting fOCO as count
source.
count source
Usable (INT0 to INT3 can be used if
there is no filter.)
Figure 10.9 shows the Time from Wait Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level to the ILVL2 to ILVL0 bits in the interrupt control register of the
peripheral function interrupts to use for exiting wait mode. Set the ILVL2 to ILVL0 bits of the
peripheral function interrupts not to use for exiting wait mode to 000b (disables interrupt).
(2) Set the I flag to 1.
(3) Operate the peripheral function to use for exiting wait mode.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register
as described in Figure 10.9.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
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FMR0 Register
FMSTP Bit
0
(flash memory
operates)
1
(flash memory
stops)
Wait mode
Time until Flash Memory is
Activated (T1)
Period of system clock
× 12 cycles + 30 µs (max.)
Period of system clock
× 12 cycles
T1 T2 T3
Flash memory activation
sequence
Interrupt request generated
Time until CPU Clock is
Supplied (T2)
Period of CPU clock
× 6 cycles
Same as above Same as above
CPU clock restart
sequence
Time for Interrupt
Period of CPU clock
Interrupt sequence
Figure 10.9 Time from Wait Mode to Interrupt Routine Execution
Sequence (T3)
× 20 cycles
Remarks
Following total
time is the time
from wait mode
until an interrupt
routine is
executed.
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10.4.2.5 Reducing Internal Power Consumption
Internal power consumption can be reduced by using low-speed on-chip oscillator mode.
Figure 10.10 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.10 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (8)
Handling procedure of internal power
low consumption enabled by VCA20 bit
Enter low-speed on-chip oscillator mode
Stop XIN clock and high-speed on-chip
VCA20 ← 1 (internal power low consumption
VCA20 ← 0 (internal power low consumption
Start XIN clock or high-speed on-chip
(Wait until XIN clock os ci llation stabilizes)
Enter high-speed clock mode or high-speed
oscillator clock
(2)
enabled)
Enter wait mode
disabled)
oscillator clock
on-chip oscillator mode
(4)
(2)
Exit wait mode by
interrupt
Step (5)
Step (6)
Step (7)
Step (8)
Step (1)
Step (2)
Step (3)
VCA20 ← 0 (internal power low consumption
(Wait until XIN clock oscillation stabilizes)
Enter high-speed clock mode or high-speed
Enter low-speed on-chip oscillator mode
Stop XIN clock and high-speed on- c h ip
VCA20 ← 1 (internal power low consumption
(Note 1)
In interrupt handling routine
(2)
disabled)
Start XIN clock or high-speed on-chip
oscillator clock
on-chip oscillator mode
Interrupt handling
oscillator clock
(2,3)
enabled)
If it is necessary to start
the high-speed clock or
the high-speed on-chip
oscillator in the interrupt
handling routine, execute
steps (5) to (7) in the
interrupt routine.
If the high-speed clock or
high-speed on-chip
oscillator is started in the
interrupt handling routine,
execute steps (1) to (3) at
the last of the interrupt
routine.
Interrupt handling completed
NOTES:
1. Execute this handling to all interrupt handlings generated around the WAIT instruction. If it is not necessary to start the high-speed
clock or the high-speed on-chip oscillator in the interrupt handling, it does not need to be started.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.6.2 Wait Mode.
VCA20: Bit in VCA2 register
Figure 10.10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
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10.4.3 Stop Mode
Since the oscillator circuits stop in wait mode, the CP U clock and perip heral function cl ock stop and the CPU
and peripheral functions clocked by these clocks stop operati ng. The least power required to operate the MCU
is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the internal RAM is maintained.
The peripheral functions clocked by external signals maintain operating.
Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions.
Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions
Interrupt Usage Conditions
Key Input Interrupt −
INT0
to INT3 Interrupt Can be used if there is no filter
Timer RA Interrupt When there is no filter and external pulse is counted in event
counter mode
Serial Interface Interrupt When external clock is selected
Volt age Monitor 2 Interrupt Usable in digital filter disabled mode (VW2C1 bit in VW2C register
is set to 1)
10.4.3.1 Entering Stop Mode
The MCU enters stop mode by setting the CM10 bit in the CM1 register to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM10 register is
set to 1 (drive capability HIGH of XIN clock oscillator circuit).
When using stop mode, set the OCD1 to OCD0 bits to 00b before entering stop mode.
10.4.3.2 Pin Status in Stop Mode
The status before entering wait mode is maintained.
However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held
“H”. When the CM13 bit is set to 0 (input port P4_6 and P4_7), the P4_7(XOUT) is held in input status.
10.4.3.3 Exiting Stop Mode
The MCU exits stop mode by a reset or peripheral function interrupt.
When using a reset to exit stop mode, set the IL VL2 to ILVL0 bits for the peripheral function interrupts to 000b
(disables interrupts) before setting the CM10 bit to 1.
Figure 10.11 shows the Time from Stop Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exi t st op m ode, set up t he fol lowing be fore setting the CM10 bi t
to 1.
(1) Set the interrupt priority level to the ILVL2 to ILVL0 bits of the peripheral function interrupts to use for
exiting stop mode. Set the ILVL2 to ILVL0 bits of the peripheral function interrupts not to use for
exiting stop mode to 000b (disables interrupt).
(2) Set the I flag to 1.
(3) Operates the peripheral function to use for exiting stop mode.
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt
request is generated and the CPU clock supply is started.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the previous system clock divided by 8.
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FMR0 Register
FMSTP Bit
0
(flash memory
operates)
1
(flash memory
stops)
Stop
mode
Time until Flash Memory is
Activated (T2)
Period of system clock
× 12 cycles + 30 µs (max.)
Period of system clock
× 12 cycles
T0
Internal
power
stability time
Oscillation period of the CPU
clock source used immediately
T1
before stop mode
Time until CPU Clock is
Supplied (T3)
Period of CPU clock
× 6 cycles
Time for Interrupt
Sequence (T4)
Period of CPU clock
× 20 cycles
Same as above Same as above
T2 T3 T4
Flash memory activation
CPU clock restart
sequence
sequence
150 µs
request
(max.)
Interrupt
generated
Figure 10.11 Time from Stop Mode to Interrupt Routine Execution
Remarks
Following total
time of T0 to T4 is
the time from wait
mode until an
interrupt routine is
executed.
Interrupt sequence
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Figure 10.12 shows the State Transitions in Power Control Mode.
State Transition in Power Control Mode
Reset
Standard operating mode
Low-speed on-chip oscillator mode
CM14 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
OCD2 = 1
FRA01 = 0
High-speed clock mode
CM05 = 0
CM13 = 1
OCD2 = 0
Interrupt
Wait mode
CPU operation stops
CM05 = 0
CM13 = 1
OCD2 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
CM14 = 0
FRA01 = 0
High-speed on-chip oscillator mode
OCD2 = 1
FRA00 = 1
FRA01 = 1
InterruptWAIT instruction
Stop mode
All oscillators stop
FRA00 = 1
FRA01 = 1
CM10 = 1
CM05 : CM0 register
CM13, CM14 : CM1 register
OCD2 : OCD register
FRA00, FRA01 : FRA0 register
Figure 10.12 State Transitions in Power Control Mode
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10.5 Oscillation Stop Detection Function
The oscillation stop detection function is a function to detect the stop of the XIN clock oscillating circuit. The
oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register.
Table 10.5 lists the Specifications of Oscillation Stop Detection Function.
When the XIN clock is the CPU clock source and the OCD1 to OCD0 bits are set to 11b, the system is placed in
the following state if the XIN clock stops.
• OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
• OCD3 bit in OCD register = 1 (XIN clock stops)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
• Oscillation stop detection interrupt request is generated
Table 10.5 Specifications of Oscillation Stop Detection Function
Item Specification
Oscillation Stop Detection Clock and
Frequency Bandwidth
Enabled Condition for Oscillation Stop
Detection Function
Operation at Oscillation Stop Detection Oscillation stop detection interrupt is generated
f(XIN) ≥ 2 MHz
Set OCD1 to OCD0 bits to 11b
10.5.1 How to Use Oscillation Stop Detection Function
• The oscillation stop detection interrupt shares the vector with the voltage monitor 2 interrupt and the
watchdog timer interrupt. When using the oscillation stop detection interrupt and watchdog timer interrupt,
the interrupt cause needs to be determined.
Table 10.6 lists the Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage
Monitor 1, and Voltage Monitor 2 Interrupts.
Figure 10.14 shows an Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt.
• When the XIN clock is re-oscillated after oscillat ion stop, switch the XIN clock to the clock source of the
CPU clock and peripheral functions by a program.
Figure 10.13 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to
XIN Clock.
• To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral
function clock does not stop in wait mode).
• Since the oscillation stop detection function is a function preparing to stop the XIN clock by the external
cause, set the OCD1 to OCD0 bits to 00b when the XIN clock stops or oscillates in the program, that is stop
mode is selected or the CM05 bit is changed.
• This function cannot be used when the XIN clock frequency is less than 2 MHz. Set the OCD1 to OCD0
bits to 00b.
• When using the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral
functions after detecting the oscillation stop, set the FRA 01 bit in the FRA0 register to 0 (l ow-speed onchip oscillator selected) and the OCD1 to OCD0 bits to 11b.
When using the high-speed on-chip oscillator clock for the CPU clock and clock sources of periph eral
functions after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-ch ip oscillator on ) and
the FRA01 bit to 1 (high-speed on-chip oscillator selected) and the OCD1 to OCD0 bits to 11b.
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Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer,
Voltage Monitor 1, and Voltage Monitor 2 Interrupts
Generated Interrupt Source Bit Showing Interrupt Cause
Oscillation Stop Detection
((a) or (b))
(a) OCD3 bit in OCD register = 1
(b) OCD1 to OCD0 bits in OCD register = 11b and the OCD2 bit = 1
Watchdog Timer VW2C3 bit in VW2C register = 1
Voltage Monitor 2 VW2C2 bit in VW2C register = 1
Switch to XIN clock
No
Determine several times
that the OCD bit is 0 (X IN clo ck
Set OCD1 to OCD0 bits to 00b
oscillates)
Yes
Set OCD2 bit to 0
(select XIN Clock)
End
OCD3 to OCD0 bits: Bits in OCD register
Figure 10.13 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock
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Interrupt sources judgment
OCD3 = 1?
(XIN clock stops)
YES
OCD1 = 0 (Oscillation stop detection
interrupt disable)
Jump to oscillation stop detection
interrupt process routine.
NOTE:
1. This disables multiple oscillation stop detection interrupts.
OCD1 to OCD3: Bits in OCD register
VW2C3: Bit in VW2C register
(1)
NO
OCD1 = 1 (Oscillation
stop detection interrupt enable),
and OCD2=1 (Selects on-chip
oscillator clock)?
YES
NO
VW2C3 = 1?
(Watchdog time underflows)
YES
Jump to watchdog timer interru pt
process routine.
NO
Jump to voltage monitor 2 Interrupt
process routine.
Figure 10.14 Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt
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