RENESAS R8C-2K, R8C-2L User Manual

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PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

R8C/2K Group, R8C/2L Group

REJ03B0219-0010

RENESAS MCU

1. Overview

1.1 Features

The R8C/2K Group and R8C/2L Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core,
employing sophisticated instructions for a high level of efficiency. Wi th 1 Mbyte of address space and is capable of
executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation
processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
Furthermore, the R8C/2L Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/2K Group and R8C/2L Group is only the presence or absence of data flash. Their
peripheral functions are the same.

1.1.1 Applications

Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.

Rev.0.10

Jul 20, 2007

Rev.0.10 Jul 20, 2007 Page 1 of 44
REJ03B0219-0010

Under development

Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

1.1.2 Specifications

Tables 1.1 and 1.2 outlines the Specifications for R8C/2K Group and Tables 1.3 and 1.4 outlines the
Specifications for R8C/2L Group

Table 1.1 Specifications for R8C/2K Group (1)

Item Function Specification

CPU Central processing

unit

Memory ROM, RAM Refer to T able 1.5 Product List for R8C/2K Group.
Power Supply
Voltage
Detection
I/O Ports Programmable I/O

Clock Clock generation

Interrupts • External: 4 sources, Internal: 15 sources, Software: 4 sources
Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable

Timer Timer RA 8 bits × 1 (with 8-bit prescaler)

Voltage detection
circuit

ports

circuits

Timer RB 8 bits × 1 (with 8-bit prescaler)

Timer RC 16 bits × 1 (with 4 capture/compare registers)

Timer RD 16 bits × 2 (with 4 capture/compare registers)

R8C/Tiny series core

• Number of fundamental instructions: 89

• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operation mode: Single-chip mode (address space: 1 Mbyte)

• Power-on reset

• Voltage detection 3

• Input-only: 3 pins

• CMOS I/O ports: 25, selectable pull-up resistor

• High current drive ports: 8

2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),

On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function)

• Oscillation stop detection: XIN clock oscillation stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode

• Priority levels: 7 levels

Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode

Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait on e­shot generation mode

Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)

Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)

Rev.0.10 Jul 20, 2007 Page 2 of 44
REJ03B0219-0010

Under development

Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

Table 1.2 Specifications for R8C/2K Group (2)

Item Function Specification
Serial
Interface
LIN Module Hardware LIN: 1 (timer RA, UART0)
A/D Converter 10-bit resolution × 9 channels, includes sample and hold function
Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V

Operating Frequency/Supply
Voltage

Current consumption TBD (VCC = 5.0 V, f(XIN) = 20 MHz)

Operating Ambient Temperature -20 to 85°C (N version)
Package 32-pin LQFP

NOTE:

1. Specify the D version if D version functions are to be used.

UART0, UART2 Clock synchronous serial I/O/UART × 2

• Programming and erasure endurance: 100 times

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)

f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V) (VCC = 2.7 to 5.5 V for A/D converter only)

TBD (VCC = 3.0 V, f(XIN) = 10 MHz)
TBD (VCC = 3.0 V, wait mode)
TBD (VCC = 3.0 V, stop mode)

-40 to 85°C (D version)

(1)

• Package code: PLQP0032GB-A (previous code: 32P6U-A)

Rev.0.10 Jul 20, 2007 Page 3 of 44
REJ03B0219-0010

Under development

Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

Table 1.3 Specifications for R8C/2L Group (1)

Item Function Specification
CPU Central processing

unit

Memory ROM, RAM Refer to T able 1.6 Product List for R8C/2L Group.
Power Supply
Voltage

Voltage detection

circuit
Detection
I/O Ports Programmable I/O

ports
Clock Clock generation

circuits

Interrupts • External: 4 sources, Internal: 15 sources, Software: 4 sources
Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable

Timer Timer RA 8 bits × 1 (with 8-bit prescaler)

Timer RB 8 bits × 1 (with 8-bit prescaler)

Timer RC 16 bits × 1 (with 4 capture/compare registers)

Timer RD 16 bits × 2 (with 4 capture/compare registers)

R8C/Tiny series core

• Number of fundamental instructions: 89

• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operation mode: Single-chip mode (address space: 1 Mbyte)

• Power-on reset

• Voltage detection 3

• Input-only: 3 pins

• CMOS I/O ports: 25, selectable pull-up resistor

• High current drive ports: 8

2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),

On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function)

• Oscillation stop detection: XIN clock oscillation stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode

• Priority levels: 7 levels

Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode

Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait on e­shot generation mode

Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)

Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)

Rev.0.10 Jul 20, 2007 Page 4 of 44
REJ03B0219-0010

Under development

Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

Table 1.4 Specifications for R8C/2L Group (2)

Item Function Specification
Serial
Interface
LIN Module Hardware LIN: 1 (timer RA, UART0)
A/D Converter 10-bit resolution × 9 channels, includes sample and hold function
Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V

Operating Frequency/Supply
Voltage

Current consumption TBD (VCC = 5.0 V, f(XIN) = 20 MHz)

Operating Ambient Temperature -20 to 85°C (N version)
Package 32-pin LQFP

NOTE:

1. Specify the D version if D version functions are to be used.

UART0, UART2 Clock synchronous serial I/O/UART × 2

• Programming and erasure endurance: 10,000 times (data flash)

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)

f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V) (VCC = 2.7 to 5.5 V for A/D converter only)

TBD (VCC = 3.0 V, f(XIN) = 10 MHz)
TBD (VCC = 3.0 V, wait mode)
TBD (VCC = 3.0 V, stop mode)

-40 to 85°C (D version)

(1)

• Package code: PLQP0032GB-A (previous code: 32P6U-A)

1,000 times (program ROM)

Rev.0.10 Jul 20, 2007 Page 5 of 44
REJ03B0219-0010

Under development

Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

1.2 Product List

Table 1.5 lists Product List for R8C/2K Group, Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/2K Group, Table 1.6 lists Product List for R8C/2L Group, and Figure 1.2 shows a Part Number, Memory Size,
and Package of R8C/2L Group.

Table 1.5 Product List for R8C/2K Group Current of Jul. 2007

Part No. ROM Capacity RAM Capacity Package Type Remarks
R5F212K2SNFP (D) 8 Kbytes 1 Kbyte PLQP0032GB- A N versio n
R5F212K4SNFP (D) 16 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F212K2SDFP (D) 8 Kbytes 1 Kbyte PLQP0032GB- A D versio n
R5F212K4SDFP (D) 16 Kbytes 1.5 Kbytes PLQP0032GB-A

(D): Under development

Part No. R 5 F 21 2K 2 S N FP

Package type:

FP: PLQP0032GB-A

Classification

N: Operating ambient temperature -20°C to 85°C

D: Operating ambient temperature -40°C to 85°C
S: Low-voltage version
ROM capacity

2: 8 KB

4: 16 KB
R8C/2K Group
R8C/Tiny Series
Memory type

F: Flash memory
Renesas MCU
Renesas semiconductor

Figure 1.1 Part Number, Memory Size, and Package of R8C/2K Group

Rev.0.10 Jul 20, 2007 Page 6 of 44
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Under development

Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

Table 1.6 Product List for R8C/2L Group Current of Jul. 2007

Part No.

ROM Capacity

Pr o g r a m RO M Data flash

RAM

Capacity

Package Ty pe Remarks

R5F212L2SNFP (D) 8 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A N version
R5F212L4SNFP (D) 16 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F212L2SDFP (D) 8 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A D version
R5F212L4SDFP (D) 16 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

(D): Under development

Part No. R 5 F 21 2L 2 S N FP

Package type:

FP: PLQP0032GB-A
Classification

N: Operating ambient temperature -20°C to 85°C

D: Operating ambient temperature -40°C to 85°C
S: Low-voltage version
ROM capacity

2: 8 KB

4: 16 KB
R8C/2L Group
R8C/Tiny Series
Memory type

F: Flash memory
Renesas MCU
Renesas semiconductor

Figure 1.2 Part Number, Memory Size, and Package of R8C/2L Group

Rev.0.10 Jul 20, 2007 Page 7 of 44
REJ03B0219-0010

Under development

Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

1.3 Block Diagram

Figure 1.3 shows a Block Diagram.

I/O ports

Peripheral functions

Timers

Timer RA (8 bits × 1)
Timer RB (8 bits × 1)

Timer RC (16 bits × 1)

Timer RD (16 bits × 2)

Watchdog timer

(15 bits)

A/D converter

× 9 channels)

(10 bits

Port P0

5

8

Port P1

clock synchronous serial I/O

(8 bits × 2)

LIN module

Port P2

UART or

R8C/Tiny Series CPU core

R0H R0L

R1L

R1H

R2
R3

A0
A1

FB

8

3

Port P3

High-speed on-chip oscillator

Low-speed on-chip oscillator

1 3

Port P4

System clock

generation circuit

XIN-XOUT

Memory

SB

USP

ISP

INTB

PC

FLG

(1)

ROM

(2)

RAM

Multiplier

Figure 1.3 Block Diagram

Rev.0.10 Jul 20, 2007 Page 8 of 44
REJ03B0219-0010

NOTES:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

Under development

Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

1.4 Pin Assignment

Figure 1.4 shows Pin Assignment (Top View). Table 1.7 outlines the Pin Name Information by Pin Number.

(2)

P4_5/INT0

P1_5/RXD0/(TRAIO)/(INT1)

5781234 6

P1_6/CLK0

P1_7/TRAIO/INT1

16
15
14
13
12

11
10

9

P2_0/TRDIOA0/TRDCLK
P2_2/TRDIOC0
P2_1/TRDIOB0
P2_3/TRDIOD0
P2_4/TRDIOA1
P2_5/TRDIOB1
P2_6/TRDIOC1
P2_7/TRDIOD1

P1_0/KI0/AN8

P3_4/TRCIOC
P3_5/TRCIOD

P0_5/AN2

P0_3/AN4/CLK2

P0_2/AN5/RXD2

P0_1/AN6/TXD2

P0_0/AN7

P1_4/TXD0

P1_3/KI3/AN11/TRBO

P1_1/KI1/AN9/TRCIOA/TRCTRG

P1_2/KI2/AN10/TRCIOB

24 23 22 21 20 19 18 17

25
26
27

R8C/2K Group

28

R8C/2L Group

29
30

PLQP0032GB-A

31
32

(32P6U-A)
(top view)

MODE

VREF/P4_2

NOTES:

1. P4_7 are an input-only port.

2. Can be assigned to the pin in parentheses by a program.

3. Confirm the pin 1 position on the package by referring to the package dimensions.

Figure 1.4 Pin Assignment (Top View)

(1)

RESET

XOUT/P4_7

VSS/AVSS

XIN/P4_6

VCC/AVCC

P3_3/INT3/TRCCLK

Rev.0.10 Jul 20, 2007 Page 9 of 44
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Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

Table 1.7 Pin Name Information by Pin Number

Pin

Number

Control Pin Port

Interrupt Timer Serial Interface
1VREFP4_2
2MODE
3

RESET

4XOUTP4_7
5 VSS/AVSS
6XINP4_6
7 VCC/AVCC
8P3_3

INT3

9 P2_7 TRDIOD1

10 P2_6 TRDIOC1

11 P2_5 TRDIOB1
12 P2_4 TRDIOA1
13 P2_3 TRDIOD0
14 P2_1 TRDIOB0
15 P2_2 TRDIOC0
16 P2_0 TRDIOA0/TRDCLK
17 P4_5
18 P1_7

INT0
INT1

19 P1_6 CLK0
20 P1_5

(INT1

(1)

)
21 P1_4 TXD0
22 P1_3
23 P1_2
24 P1_1

25 P1_0

KI3
KI2
KI1

KI0

26 P3_4 TRCIOC
27 P3_5 TRCIOD
28 P0_5 AN2
29 P0_3 CLK2 AN4
30 P0_2 RXD2 AN5
31 P0_1 TXD2 AN6
32 P0_0 AN7

NOTE:

1. Can be assigned to the pin in parentheses by a program.

I/O Pin Functions for of Peripheral Modules

A/D Converter

TRCCLK

TRAIO

(TRAIO)

(1)

RXD0

TRBO AN11

TRCIOB AN10

TRCIOA/TRCTRG AN9

AN8

Rev.0.10 Jul 20, 2007 Page 10 of 44
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Under development

Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 1. Overview

1.5 Pin Functions

Table 1.8 lists Pin Functions.

Table 1.8 Pin Functions

Item Pin Name
Power supply input VCC, VSS − Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power

supply input
Reset input

MODE MODE I Connect this pin to VCC via a resistor.
XIN clock input XIN I These pins are provided for XIN clock ge neration circuit I/O.

XIN clock output XOUT O

interrupt input INT0, INT1, INT3 IINT interrupt input pins.

INT

Key input interrupt
Timer RA TRAIO I/O Timer RA I/O pin

Timer RB TRBO O Timer RB output pin
Timer RC TRCCLK I External clock input pin

Timer RD TRDIOA0, TRDIOA1,

Serial interface CLK0, CLK2 I/O Transfer clock I/O pins

Reference voltage
input

A/D converter AN2, AN4 to AN11 I Analog input pins to A/D converter
I/O port P0_0 to P0_3, P0_5,

Input port P4_2, P4_6, P4_7 I Input-only ports

I: Input O: Output I/O: Input and output
NOTE:

1. Refer to the oscillator manufacturer for oscillation characteristics.

AVCC, AVSS − Power supply for the A/D converter.

RESET

KI0 to KI3

TRCTRG I External trigger input pin
TRCIOA, TRCIOB,

TRCIOC, TRCIOD

TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1

TRDCLK I External clock input pin

RXD0, RXD2 I Serial data input pins
TXD0, TXD2 O Serial data output pins
VREF I Reference voltage input pin to A/D converter

P1_0 to P1_7,
P2_0 to P2_7,
P3_3 to P3_5,
P4_5,

I/O Type

Connect a capacitor between AVCC and AVSS.

I Input “L” on this pin resets the MCU.

Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins
the XIN pin and leave the XOUT pin open.

INT0 is timer RB, timer RC and timer RD input pins.

I Key input interrupt input pins

I/O Timer RC I/O pins

I/O Timer RD I/O pins

I/O CMOS I/O ports. Each port has an I/ O select direction

register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P2_0 to P2_7 also function as LED drive ports.

Description

(1)

. To use an external clock, input it to

Rev.0.10 Jul 20, 2007 Page 11 of 44
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Preliminary specification
Specications in this manual are tentative and subject to change

R8C/2K Group, R8C/2L Group 2. Central Processing Unit (CPU)

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.

b31

R2
R3

b15 b8b7

R0H (high-order of R0)
R1H (high-order of R1)

R0L (low-order of R0)
R1L (low-order of R1)

R2
R3

A0
A1

FB

b15b19

INTBH

The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.

b19

INTBL

PC

b15

USP

ISP

SB

b0

Data registers

Address registers

Frame base register

b0

Interrupt table register

b0

Program counter

b0

User stack pointer
Interrupt stack pointer
Static base register

(1)

(1)

(1)

b15

IPL

NOTE:

1. These registers comprise a register bank. There are two register banks.

Figure 2.1 CPU Registers

b15

b0

FLG

b8

b7

b0

C

DZSBOIU

Flag register

Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit

Rev.0.10 Jul 20, 2007 Page 12 of 44
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R8C/2K Group, R8C/2L Group 2. Central Processing Unit (CPU)

Preliminary specification
Specications in this manual are tentative and subject to change

2.1 Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separatel y as 8-bit data regi sters. R1H and R 1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data regi ster (R2R0). R3R1 is
analogous to R2R0.

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32­bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.

2.8.2 Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.

2.8.5 Register Bank Select Flag (B)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.

2.8.6 Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

Rev.0.10 Jul 20, 2007 Page 13 of 44
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R8C/2K Group, R8C/2L Group 2. Central Processing Unit (CPU)

Preliminary specification
Specications in this manual are tentative and subject to change

2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

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