The R8C/2K Group and R8C/2L Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core,
employing sophisticated instructions for a high level of efficiency. Wi th 1 Mbyte of address space and is capable of
executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation
processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
Furthermore, the R8C/2L Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/2K Group and R8C/2L Group is only the presence or absence of data flash. Their
peripheral functions are the same.
1.1.1Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
Rev.0.10
Jul 20, 2007
Rev.0.10Jul 20, 2007Page 1 of 44
REJ03B0219-0010
Under development
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group1. Overview
1.1.2Specifications
Tables 1.1 and 1.2 outlines the Specifications for R8C/2K Group and Tables 1.3 and 1.4 outlines the
Specifications for R8C/2L Group
Table 1.1Specifications for R8C/2K Group (1)
ItemFunctionSpecification
CPUCentral processing
unit
MemoryROM, RAMRefer to T able 1.5 Product List for R8C/2K Group.
Power Supply
Voltage
Detection
I/O PortsProgrammable I/O
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group1. Overview
Table 1.2Specifications for R8C/2K Group (2)
ItemFunctionSpecification
Serial
Interface
LIN ModuleHardware LIN: 1 (timer RA, UART0)
A/D Converter10-bit resolution × 9 channels, includes sample and hold function
Flash Memory• Programming and erasure voltage: VCC = 2.7 to 5.5 V
Operating Frequency/Supply
Voltage
Current consumptionTBD (VCC = 5.0 V, f(XIN) = 20 MHz)
Operating Ambient Temperature-20 to 85°C (N version)
Package32-pin LQFP
NOTE:
1. Specify the D version if D version functions are to be used.
UART0, UART2Clock synchronous serial I/O/UART × 2
• Programming and erasure endurance: 100 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V) (VCC = 2.7 to 5.5 V for A/D converter only)
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group1. Overview
Table 1.4Specifications for R8C/2L Group (2)
ItemFunctionSpecification
Serial
Interface
LIN ModuleHardware LIN: 1 (timer RA, UART0)
A/D Converter10-bit resolution × 9 channels, includes sample and hold function
Flash Memory• Programming and erasure voltage: VCC = 2.7 to 5.5 V
Operating Frequency/Supply
Voltage
Current consumptionTBD (VCC = 5.0 V, f(XIN) = 20 MHz)
Operating Ambient Temperature-20 to 85°C (N version)
Package32-pin LQFP
NOTE:
1. Specify the D version if D version functions are to be used.
UART0, UART2Clock synchronous serial I/O/UART × 2
• Programming and erasure endurance: 10,000 times (data flash)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V) (VCC = 2.7 to 5.5 V for A/D converter only)
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group1. Overview
1.2Product List
Table 1.5 lists Product List for R8C/2K Group, Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/2K Group, Table 1.6 lists Product List for R8C/2L Group, and Figure 1.2 shows a Part Number, Memory Size,
and Package of R8C/2L Group.
Table 1.5Product List for R8C/2K GroupCurrent of Jul. 2007
Part No.ROM CapacityRAM CapacityPackage TypeRemarks
R5F212K2SNFP (D)8 Kbytes1 KbytePLQP0032GB- AN versio n
R5F212K4SNFP (D)16 Kbytes1.5 KbytesPLQP0032GB-A
R5F212K2SDFP (D)8 Kbytes1 KbytePLQP0032GB- AD versio n
R5F212K4SDFP (D)16 Kbytes1.5 KbytesPLQP0032GB-A
(D): Under development
Part No. R 5 F 21 2K 2 S N FP
Package type:
FP: PLQP0032GB-A
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
S: Low-voltage version
ROM capacity
2: 8 KB
4: 16 KB
R8C/2K Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1Part Number, Memory Size, and Package of R8C/2K Group
Rev.0.10Jul 20, 2007Page 6 of 44
REJ03B0219-0010
Under development
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group1. Overview
Table 1.6Product List for R8C/2L GroupCurrent of Jul. 2007
Part No.
ROM Capacity
Pr o g r a m RO MData flash
RAM
Capacity
Package Ty peRemarks
R5F212L2SNFP (D)8 Kbytes1 Kbyte × 21 KbytePLQP0032GB-A N version
R5F212L4SNFP (D)16 Kbytes1 Kbyte × 21.5 KbytesPLQP0032GB-A
R5F212L2SDFP (D)8 Kbytes1 Kbyte × 21 KbytePLQP0032GB-A D version
R5F212L4SDFP (D)16 Kbytes1 Kbyte × 21.5 KbytesPLQP0032GB-A
(D): Under development
Part No. R 5 F 21 2L 2 S N FP
Package type:
FP: PLQP0032GB-A
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
S: Low-voltage version
ROM capacity
2: 8 KB
4: 16 KB
R8C/2L Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2Part Number, Memory Size, and Package of R8C/2L Group
Rev.0.10Jul 20, 2007Page 7 of 44
REJ03B0219-0010
Under development
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group1. Overview
1.3 Block Diagram
Figure 1.3 shows a Block Diagram.
I/O ports
Peripheral functions
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Watchdog timer
(15 bits)
A/D converter
× 9 channels)
(10 bits
Port P0
5
8
Port P1
clock synchronous serial I/O
(8 bits × 2)
LIN module
Port P2
UART or
R8C/Tiny Series CPU core
R0HR0L
R1L
R1H
R2
R3
A0
A1
FB
8
3
Port P3
High-speed on-chip oscillator
Low-speed on-chip oscillator
1 3
Port P4
System clock
generation circuit
XIN-XOUT
Memory
SB
USP
ISP
INTB
PC
FLG
(1)
ROM
(2)
RAM
Multiplier
Figure 1.3Block Diagram
Rev.0.10Jul 20, 2007Page 8 of 44
REJ03B0219-0010
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Under development
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group1. Overview
1.4Pin Assignment
Figure 1.4 shows Pin Assignment (Top View). Table 1.7 outlines the Pin Name Information by Pin Number.
RXD0, RXD2ISerial data input pins
TXD0, TXD2OSerial data output pins
VREFIReference voltage input pin to A/D converter
P1_0 to P1_7,
P2_0 to P2_7,
P3_3 to P3_5,
P4_5,
I/O Type
Connect a capacitor between AVCC and AVSS.
IInput “L” on this pin resets the MCU.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins
the XIN pin and leave the XOUT pin open.
INT0 is timer RB, timer RC and timer RD input pins.
IKey input interrupt input pins
I/OTimer RC I/O pins
I/OTimer RD I/O pins
I/OCMOS I/O ports. Each port has an I/ O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P2_0 to P2_7 also function as LED drive ports.
Description
(1)
. To use an external clock, input it to
Rev.0.10Jul 20, 2007Page 11 of 44
REJ03B0219-0010
Under development
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group2. Central Processing Unit (CPU)
2.Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
R2
R3
b15b8b7
R0H (high-order of R0)
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
R2
R3
A0
A1
FB
b15b19
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
INTBL
PC
b15
USP
ISP
SB
b0
Data registers
Address registers
Frame base register
b0
Interrupt table register
b0
Program counter
b0
User stack pointer
Interrupt stack pointer
Static base register
(1)
(1)
(1)
b15
IPL
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1CPU Registers
b15
b0
FLG
b8
b7
b0
C
DZSBOIU
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Rev.0.10Jul 20, 2007Page 12 of 44
REJ03B0219-0010
Under development
R8C/2K Group, R8C/2L Group2. Central Processing Unit (CPU)
Preliminary specification
Specications in this manual are tentative and subject to change
2.1Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separatel y as 8-bit data regi sters. R1H and R 1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data regi ster (R2R0). R3R1 is
analogous to R2R0.
2.2Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Rev.0.10Jul 20, 2007Page 13 of 44
REJ03B0219-0010
Under development
R8C/2K Group, R8C/2L Group2. Central Processing Unit (CPU)
Preliminary specification
Specications in this manual are tentative and subject to change
2.8.7Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.0.10Jul 20, 2007Page 14 of 44
REJ03B0219-0010
Under development
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group3. Memory
3.Memory
3.1R8C/2K Group
Figure 3.1 is a Memory Map of R8C/2K Group. The R8C/2K Group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal
ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1.5-Kbyte internal
RAM area is allocated addresses 00400h to 009FFh. The internal RAM is used not only for storing data but also for
calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
002FFh
00400h
0XXXh
0YYYYh
0FFFFh
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group3. Memory
3.2R8C/2L Group
Figure 3.2 is a Memory Map of R8C/2L Group. The R8C/2L Group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1.5-Kbyte
internal RAM is allocated addresses 00400h to 009FFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
002FFh
00400h
0XXXXh
02400h
02BFFh
0YYYYh
0FFFFh
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
Ta ble 5.4Flash Memory (Program ROM) Electrical Characteristics
SymbolParameterConditions
−
Program/erase endurance
(2)
R8C/2K Group
R8C/2L Group
Min.Typ.Max.
100
1,000
−Byte program time−50400µs
−Block erase time−0.49s
d(SR-SUS)Time delay from suspend request until
t
−−97+CPU clock
suspend
−Interval from erase start/restart until
650−−µs
following suspend request
−Interval from program start/restart until
0−−ns
following suspend request
−Time from suspend until program/erase
−−3+CPU clock
restart
−Program, erase voltage2.7−5.5V
−Read voltage2.2−5.5V
−Program, erase temperature0−60 °C
−
Data hold time
(7)
Ambient temperature = 55°C20−−year
NOTES:
1. V
CC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Standard
(3)
−−times
(3)
−−times
Unit
µs
× 6 cycles
µs
× 4 cycles
Rev.0.10Jul 20, 2007Page 26 of 44
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Under development
Preliminary specification
Specications in this manual are tentat ive and subject to change
Table 5.5Flash Memory (Data flash Block A, Block B) Electrical Characteristics
SymbolParameterConditions
−
Program/erase endurance
(2)
−Byte program time
Min.Typ.Max.
10,000
Standard
(3)
−50400µs
(4)
−−times
(program/erase endurance ≤ 1,000 times)
−Byte program time
−65−µs
(program/erase endurance > 1,000 times)
−Block erase time
−0.29s
(program/erase endurance ≤ 1,000 times)
−Block erase time
−0.3−s
(program/erase endurance > 1,000 times)
t
d(SR-SUS)Time delay from suspend request until
suspend
−Interval from erase start/restart until
−−97+CPU clock
× 6 cycles
650−−µs
following suspend request
−Interval from program start/restart until
0−−ns
following suspend request
−Time from suspend until program/erase
restart
−−3+CPU clock
× 4 cycles
−Program, erase voltage2.7−5.5V
−Read voltage2.2−5.5V
(8)
−Program, erase temperature
−
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Data hold time
(9)
Ambient temperature = 55 °C20 −−year
−20
−85 °C
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. −40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Unit
µs
µs
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Preliminary specification
Specications in this manual are tentat ive and subject to change
Voltage detection level
Voltage monitor 1 interrupt request generation time
−Voltage detection circuit self power consumptionVCA26 = 1, V
d(E-A)Waiting time until voltage detection circuit operation
t
starts
(3)
(4)
(2)
CC = 5.0 V−0.6−µA
NOTES:
1. The measurement condition is V
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes V
CC = 2.2 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
det1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
Table 5.9Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics
SymbolParameterCondition
por1
V
por2Power-on reset or voltage monitor 0 reset valid
V
Power-on reset valid voltage
(4)
Standard
Min.Typ.Max.
−−0.1V
0−Vdet0V
(3)
voltage
rth
t
External power VCC rise gradient
(2)
20−−mV/msec
NOTES:
1. The measurement condition is T
2. This condition (external power V
opr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
CC rise gradient) does not apply if VCC≥ 1.0 V.
3. To use the power- on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. t
w(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain t
3,000 s or more if −40°C ≤ T
(3)
Vdet0
External
Power V
CC
opr < −20°C.
trth
w(por1) for 30 s or more if −20°C ≤ Topr≤ 85°C, maintain tw(por1) for
(3)
2.2V
trth
Vdet0
Vpor2
Vpor1
w(por1)
t
Sampling time
(1, 2)
Unit
Internal
reset signal
(“L” valid)
1
f
OCO-S
× 32
f
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
det0 indicates the voltage detection level of the voltage detectio n 0 circuit. Refer to 6. Voltage Detection
opr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
SymbolParameterCondition
CCPower supply
I
current
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are V
SS
Wait mode
Stop mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Standard
Min.Typ.Max.
−TBDTBDµA
−TBDTBDµA
−TBDTBDµA
−TBD−µA
Unit
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Preliminary specification
Specications in this manual are tentative and subject to change
opr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
SymbolParameterCondition
CCPower supply current
I
(V
CC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are V
SS
High-speed
clock mode
High-speed
on-chip
oscillator
mode
XIN= 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
= 10 MHz (square wave)
XIN
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
Low-speed
on-chip
oscillator
mode
Wait modeXIN clock off
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Stop modeXIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
, Topr = 25°C
, Topr = 85°C
Standard
Min.Typ.Max.
−TBD−mA
−TBD−mA
−TBDTBDmA
−TBD−mA
−TBDTBDµA
−TBDTBDµA
−TBDTBDµA
−TBDTBDµA
−TBD−µA
Unit
Rev.0.10Jul 20, 2007Page 37 of 44
REJ03B0219-0010
Under development
Preliminary specification
Specications in this manual are tentative and subject to change
opr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
SymbolParameterCondition
CCPower supply current
I
(V
CC = 2.2 to 2.7 V)
Single-chip mode,
output pins are open,
other pins are V
SS
High-speed
clock mode
High-speed
on-chip
oscillator
mode
XIN= 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
= 5 MHz (square wave)
XIN
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
Low-speed
on-chip
oscillator
mode
Wait modeXIN clock off
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Stop modeXIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
, Topr = 25°C
, Topr = 85°C
Standard
Min.Typ.Max.
−TBD−mA
−TBD−mA
−TBD−mA
−TBD−mA
−TBDTBDµA
−TBDTBDµA
−TBDTBDµA
−TBDTBDµA
−TBD−µA
Unit
Rev.0.10Jul 20, 2007Page 41 of 44
REJ03B0219-0010
Under development
Preliminary specification
Specications in this manual are tentative and subject to change
Figure 5.14Serial Interface Timing Diagram when VCC = 2.2 V
Table 5.31External Interrupt INTi (i = 0, 1, 3) Input
SymbolParameter
W(INH)
t
W(INL)
t
NOTES:
1. When selecting the digital filter by the INTi
2. When selecting the digital filter by the INTi
INTi input “H” width
INTi input “L” width
input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
th(C-D)
Standard
Min.Max.
(1)
1000
(2)
1000
VCC = 2.2 V
th(C-Q)
Unit
−ns
−ns
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.15External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.0.10Jul 20, 2007Page 43 of 44
REJ03B0219-0010
VCC = 2.2 V
Under development
Preliminary specification
Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
2417
25
32
Z
D
PLQP0032GB-A32P6U-A
H
D
*1
D
Index mark
y
e
Previous CodeJEITA Package CodeRENESAS Code
16
9
81
*3
b
p
MASS[Typ.]
0.2gP-LQFP32-7x7-0.80
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b
E
E
H
*2
E
Z
F
x
1
Terminal cross section
2
A
A
1
A
Detail F
1
c
c
c
L
L
1
Dimension in Millimeters
Reference
Symbol
D
E
A
2
H
D
H
E
A
A
1
b
p
b
1
c
0.09
c
1
e
x
y
Z
D
Z
E
L
L
1
MaxNomMin
7.17.06.9
7.17.06.9
1.4
9.29.08.8
9.29.08.8
1.7
0.35
0.145
0.125
0.8
0.7
0.7
1.0
0.20.1
0.420.370.32
0.20
0.20
0.10
0.70.50.3
8°0°
0
Rev.0.10Jul 20, 2007Page 44 of 44
REJ03B0219-0010
REVISION HISTORYR8C/2K Group, R8C/2L Group Datasheet
REVISION HISTORY
R8C/2K Group, R8C/2L Group Datasheet
Rev.Date
0.10Jul 20, 2007
Description
PageSummary
−First Edition issued
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