Renesas R8C/20, R8C/21, R8C FAMILY, R8C/2x SERIES Hardware Manual
REJ09B0250-0200
R8C/20 Group, R8C/21 Group
16
Hardware Manual
RENESAS MCU
R8C FAMILY / R8C/2x SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev.2.00
Revision Date: Aug 27, 2008
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/20 Group and R8C/21 Group. Make sure to refer to the latest versions of
these documents. The newest versions of the documents li sted may be obtained fro m the Renesas Technology Web
site.
Document Type Description Document Title Document No.
Datasheet Hardware overview and electrical characteristics R8C/20 Group,
R8C/21 Group
Datasheet
Hardware manual Hardware specifications (pin assignments,
memory maps, peripheral function
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
Software manual Description of CPU instruction set R8C/Tiny Series
Application note Information on using peripheral functions and
application examples
Sample programs
Information on writing programs in assembly
language and C
Renesas
technical update
Product specifications, updates on documents,
etc.
R8C/20 Group,
R8C/21 Group
Hardware Manual
Software Manual
Available from Renesas
Technology Web site.
REJ03B0120
This hardware
manual
REJ09B0001
2. Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “b” is appended to numeric valu es given i n binary format. However, nothing is appended to the
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
3. Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
0
XXX0
XXX1
(b2)
(b3)
XXX4
XXX5
XXX6
XXX7
*1
Symbol Address After Reset
XXX XXX 00h
Bit NameBit Symbol
XXX bits
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Reserved bits
XXX bits
XXX bit
b1 b0
1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
Set to 0.
Function varies according to the operating
mode.
0: XXX
1: XXX
Function
RW
RW
RW
RW
RW
WO
RW
RO
*2
*3
*4
*1
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2
RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
4. List of Abbreviations and Acronyms
Abbreviation Full Form
ACIA Asynchronous Communication Interface Adapter
bps bits per second
CRC Cyclic Redundancy Check
DMA Direct Memory Access
DMAC Direct Memory Access Controller
GSM Global System for Mobile Communications
Hi-Z High Impedance
IEBus Inter Equipment Bus
I/O Input / Output
IrDA Infrared Data Association
LSB Least Significant Bit
MSB Most Significant Bit
NC Non-Connect
PLL Phase Locked Loop
PWM Pulse Width Modulation
SIM Subscriber Identity Module
UART Universal Asynchronous Receiver / Transmitter
VCO Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
SFR Page Reference ........................................................................................................................... B - 1
1. Overview ......................... ............................................. .............................................................. ... .. 1
1.1 Applications ............................................................................................................................................... 1
1.2 Performance Overview .............................................................................................................................. 2
1.3 Block Diagram ......................................... .................................. ............................................................... 4
1.4 Product Information .................................................................................................................................. 5
1.5 Pin Assignments ........................................................................................................................................ 7
1.6 Pin Functions ............................................................................................................................................. 8
2. Central Processing Unit (CPU) ........................................ ... ... ... .......................................... ... ....... 10
2.1 Data Registers (R0, R1, R2 and R3) ....................................................................................................... 11
2.2 Address Registers (A0 and A1) ............................................................................................................... 11
2.3 Frame Base Register (FB) ....................................................................................................................... 11
2.4 Interrupt Table Register (INTB) .............................................................................................................. 11
2.5 Program Counter (PC) ................................................................... .......................................................... 11
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................. 11
2.7 Static Base Register (SB) ....................................................................................... ................................. 11
2.8 Flag Register (FLG) ................................................................................................................................ 11
2.8.1 Carry Flag (C) ..................................................................................................................................... 11
2.8.2 Debug Flag (D) ................................................................................................................................... 11
2.8.3 Zero Flag (Z) ....................................................................................................................................... 11
2.8.4 Sign Flag (S) ....................................................................................................................................... 11
2.8.5 Register Bank Select Flag (B) ............................................................................................................ 11
2.8.6 Overflow Flag (O) .............................................................................................................................. 11
2.8.7 Interrupt Enable Flag (I) ................................................................... .................................................. 12
2.8.8 Stack Pointer Select Flag (U) .............................................................................................................. 12
2.8.9 Processor Interrupt Priority Level (IPL) ........................................... .................................. ................ 12
2.8.10 Reserved Bit ................................................................ ........................................................................ 12
3. Memory ..................................... ............................................. ....................................................... 13
3.1 R8C/20 Group ......................................................................................................................................... 13
3.2 R8C/21 Group ......................................................................................................................................... 14
4. Special Function Registers (SFRs) ............................................................................................... 15
5. Resets ....................................... .......................... .......................... ......................... ....................... 21
5.1 Hardware Reset ....................................................................................................................................... 24
5.1.1 When Power Supply is Stable .................................................................... ......................................... 24
5.1.2 Power On ............................................................................................................................................ 24
5.2 Power-On Reset Function ....................................................................................................................... 26
5.3 Voltage Monitor 1 Reset ......................................................................................................................... 27
5.4 Voltage Monitor 2 Reset ......................................................................................................................... 27
5.5 Watchdog Timer Reset ............................................................................................................................ 27
5.6 Software Reset ......................................................................................................................................... 27
6. Voltage Detection Circuit .............................................................................................................. 28
6.1 VCC Input Voltage .................................................................................................................................. 34
6.1.1 Monitoring Vdet1 ............................................................ .................................. ................................. 34
A - 1
6.1.2 Monitoring Vdet2 ............................................................ .................................. ................................. 34
6.2 Voltage Monitor 1 Reset ......................................................................................................................... 35
6.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..................................................................... 36
7. Programmable I/O Ports ............................................................................................................... 38
7.1 Functions of Programmable I/O Ports ..................................................................................................... 38
7.2 Effect on Peripheral Functions ................................................................................................................ 39
7.3 Pins Other than Programmable I/O Ports ................................................................................................ 39
7.4 Port Settings ..................................... ................................. .................................. .................................... 50
7.5 Unassigned Pin Handling ........................................................................................................................ 61
8. Processor Mode ............................................................................................................................ 62
8.1 Processor Modes .................................... .................................. .................................. .............................. 62
9. Bus ..................................... ................. ................ ................ ................ ................ .......................... 63
10. Clock Generation Circuit ............................................................................................................... 64
10.1 XIN Clock ..................................... .................................. ................................. ....................................... 71
10.2 On-Chip Oscillator Clocks ...................................................................................................................... 72
10.2.1 Low-Speed On-Chip Oscillator Clock ................................................................................................ 72
10.2.2 High-Speed On-Chip Oscillator Clock ............................................................................................... 72
10.3 CPU Clock and Peripheral Function Clock ............................................................................................. 73
10.3.1 System Clock ...................................................................................................................................... 73
10.3.2 CPU Clock ........................................................................................ .................................................. 73
10.3.3 Peripheral Function Clock (f1, f2, f4, f8 and f32) .............................................................................. 73
10.3.4 fOCO ................................................................................................................................................... 73
10.3.5 fOCO40M ........................................................................................................................................... 73
10.3.6 fOCO-F ............................................................................................................................................... 73
10.3.7 fOCO-S ............................................................................................................................................... 73
10.3.8 fOCO128 ............................................................................................................................................. 73
10.4 Power Control .......................................................................................................................................... 74
10.4.1 Standard Operating Mode ................................................................................................................... 74
10.4.2 Wait Mode ................................................................................ .......................................................... 75
10.4.3 Stop Mode ........................................................................................................................................... 79
10.5 Oscillation Stop Detection Function ....................................................................................................... 82
10.5.1 How to Use Oscillation Stop Detection Function ............................................................................... 82
10.6 Notes on Clock Generation Circuit ......................................................................................................... 85
10.6.1 Stop Mode ........................................................................................................................................... 85
10.6.2 Wait Mode ................................................................................ .......................................................... 85
10.6.3 Oscillation Stop Detection Function ................................................................................................... 85
10.6.4 Oscillation Circuit Constants .............................................................................................................. 85
11. Protection ........................ ................ ................ ................. ................ ................ ............................. 86
12. I nterrupts ...................... ....................... ...................... .......................... .......................................... 87
12.1 Interrupt Overview .................................................................................................................................. 87
12.1.1 Types of Interrupts .............................................................................................................................. 87
12.1.2 Software Interrupts ............................................................................................................................. 88
12.1.3 Special Interrupts ................................................................................................................................ 89
A - 2
12.1.4 Peripheral Function Interrupt .............................................................................................................. 89
12.1.5 Interrupts and Interrupt Vector ........................................................................................................... 90
12.1.6 Interrupt Control ........................................ .. .................................. ..................................................... 92
12.2 INT
12.2.1 INTi
12.2.2 INTi
Interrupt ......................................................................................................................................... 101
Interrupt (i = 0 to 3) .................................................................................................................. 101
Input Filter (i = 0 to 3) ................................................... .................................. ... ...................... 103
12.3 Key Input Interrupt ............................................................................................................ .................... 104
12.4 Address Match Interrupt ........................... ............................................................................................. 106
12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts and I
2
C bus Interface
Interrupts (Interrupts with Multiple Interrupt Request Sources) ........................................................... 108
12.6 Notes on Interrupts ................................................................................................................................ 110
12.6.1 Reading Address 00000h .................................................................................................................. 110
12.6.2 SP Setting .......................................................................................................................................... 110
12.6.3 External Interrupt and Key Input Interrupt ....................................................................................... 110
12.6.4 Changing Interrupt Sources .............................................................................................................. 111
12.6.5 Changing Interrupt Control Register Contents ................................................................................. 112
13. Watchdog Timer ........................................................................................................................... 113
13.1 Count Source Protection Mode Disabled .............................................................................................. 116
13.2 Count Source Protection Mode Enabled ............................................................................................... 117
14. Timers ....................... .................................................................... ............................................... 118
14.1 Timer RA ............................................................................................................................................... 120
14.1.1 Timer Mode ...................................................................................................................................... 124
14.1.2 Pulse Output Mode ..................................................... ................................. ..................................... 126
14.1.3 Event Counter Mode ......................................................................................................................... 128
14.1.4 Pulse Width Measurement Mode .............................................................................................. ........ 130
14.1.5 Pulse Period Measurement Mode ..................................................................................................... 133
14.1.6 Notes on Timer RA ........................................................................................................................... 136
14.2 Timer RB ......................................................................................................................................... ...... 137
14.2.1 Timer Mode ...................................................................................................................................... 141
14.2.2 Programmable Waveform Generation Mode ....................................... .................................. ........... 144
14.2.3 Programmable One-shot Generation Mode ...................................................................................... 147
14.2.4 Programmable Wait One-shot Generation Mode ............................................................................. 151
14.2.5 Notes on Timer RB ........................................................................................................................... 155
14.3 Timer RD ............................................................................................................................................... 159
14.3.1 Count Source .................................................................................................................... ................. 164
14.3.2 Buffer Operation .............................................................................................................. ................. 165
14.3.3 Synchronous Operation ........................ .................................. ........................................................... 167
14.3.4 Pulse Output Forced Cutoff .............................................................................................................. 168
14.3.5 Input Capture Function ............................................................................................................... ...... 170
14.3.6 Output Compare Function ......................... ................................................................... .................... 184
14.3.7 PWM Mode ........................................................... .................................. .................................. ........ 200
14.3.8 Reset Synchronous PWM Mode ....................................................................................................... 213
14.3.9 Complementary PWM Mode ............................................................................................................ 223
14.3.10 PWM3 Mode ....................................................................................................................... .............. 237
14.3.11 Timer RD Interrupt ........................................................................................................................... 249
14.3.12 Notes on Timer RD ................................................................................................................... ........ 251
14.4 Timer RE .................................................................................................................................... ........... 257
A - 3
14.4.1 Output Compare Mode ...................................................................................... ... ............................ 258
14.4.2 Notes on Timer RE ........................................................................................................................... 264
15. Serial Interface ............................................................................................................................ 265
15.1 Clock Synchronous Serial I/O Mode .............. ....................................................................................... 271
15.1.1 Polarity Select Function .................................................................................................................... 274
15.1.2 LSB First/MSB First Select Function ............................................................................................... 274
15.1.3 Continuous Receive Mode ................................................................................................................ 275
15.2 Clock Asynchronous Serial I/O (UART) Mode .......................................... .......................................... 276
15.2.1 Bit Rate .................................................................... .................................. ....................................... 280
15.3 Notes on Serial Interface ....................................................................................................................... 281
16. Cloc k Synchronous Serial Interface ............................................................................................ 282
16.1 Mode Selection ...................................................................................................................................... 282
16.2 Clock Synchronous Serial I/O with Chip Select (SSU) ........................................................................ 283
16.2.1 Transfer Clock .................................................................................................................................. 292
16.2.2 SS Shift Register (SSTRSR) ............................................................................................................. 294
16.2.3 Interrupt Requests ............................................................................. ............................... ................. 295
16.2.4 Communicatio n Modes and Pin Functions ....................................................................................... 296
16.2.5 Clock Synchronous Communication Mode ...................................................................................... 297
16.2.6 Operation in 4-Wire Bus Communication Mode .............................................................................. 304
16.2.7 SCS
Pin Control and Arbitration ...................................................................................................... 310
16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 311
16.3 I
2
C Bus Interface ................................................................................................................................... 312
16.3.1 Transfer Clock .................................................................................................................................. 322
16.3.2 Interrupt Requests ............................................................................. ............................... ................. 323
16.3.3 I
2
C Bus Interface Mode .................................................................................................................... 324
16.3.4 Clock Synchronous Serial Mode ...................................................................................................... 335
16.3.5 Noise Canceller ................................................................................................................................. 338
16.3.6 Bit Synchronization Circuit .............................................................................................................. 339
16.3.7 Examples of Register Setting ............................................................................................................ 340
16.3.8 Notes on I
2
C Bus Interface ............................................................................................................... 344
17. H ardw are LI N ......................... ... ... ... .... ... ... ... ... ....................................... ... .... ... ... ... .... ................. 345
17.1 Features ............................................................................................................................. .................... 345
17.2 I nput/Output Pins .................................................................................. ................................................ 346
17.3 Register Configuration .................................................................................................................. ........ 347
17.4 Functional Description .......................................................................................................................... 349
17.4.1 Master Mode ..................................................................................................................................... 349
17.4.2 Slave Mode ....................................................................................................................................... 352
17.4.3 Bus Collision Detection Function ..................................................................................................... 356
17.4.4 Hardware LIN End Processing ...................................................................................................... ... 357
17.5 I nterrupt Requests ......... .................................. .................................. ..................................................... 358
17.6 Notes on Hardware LIN ................................................................................................................ ........ 359
18. A/D Converter ............................................................................................................................. 360
18.1 One-Shot Mode ..................................................................................................................................... 364
18.2 Repeat Mode .................................................................................................................................. ........ 367
18.3 S ample and Hold .................................................... .................................. ............................................. 370
A - 4
18.4 A/D Conversion Cycles .................................... ..................................................................................... 371
18.5 Internal Equivalent Circuit of Analog Input .......................................................................................... 372
18.6 Output Impedance of Sensor Under A/D Conversion ........................................................................... 373
18.7 Notes on A/D Converter ........................................................................................................................ 374
19. Flash Memory ............................................................................................................................. 375
19.1 Overview ................................................................................................................................. .............. 375
19.2 Memory Map ............................................... .......................................................................................... 377
19.3 Functions to Prevent Rewriting of Flash Memory ................................................................................ 380
19.3.1 ID Code Check Function .................................................................................................................. 380
19.3.2 ROM Code Protect Function ............................................................................................................ 381
19.4 CPU Rewrite Mode ........................................................... .................................. .................................. 382
19.4.1 EW0 Mode .......................................................................................................................... .............. 383
19.4.2 EW1 Mode .......................................................................................................................... .............. 383
19.4.3 Software Commands ......................................................................................................................... 392
19.4.4 Status Registers ................................................................................................................................. 397
19.4.5 Full Status Check .............................................................................................................................. 398
19.5 Standard Serial I/O Mode ...................................................................................................................... 400
19.5.1 ID Code Check Function .................................................................................................................. 400
19.6 P arallel I/O Mode .................................................................................................................................. 404
19.6.1 ROM Code Protect Function ............................................................................................................ 404
19.7 Notes on Flash Memory ........................................................................................................................ 405
19.7.1 CPU Rewrite Mode ......................................... .................................................................................. 405
20. Electrical Characteristics ............................................................................................................ 408
21. Usage Notes ............................................................................................................................... 428
21.1 Notes on Clock Generation Circuit ....................................................................................................... 428
21.1.1 Stop Mode ......................................................................................................................................... 428
21.1.2 Wait Mode ................................................................................ ........................................................ 428
21.1.3 Oscillation Stop Detection Function ...................................................................................... ........... 428
21.1.4 Oscillation Circuit Constants ............................................................................................................ 428
21.2 Notes on Interrupts ................................................................................................................................ 429
21.2.1 Reading Address 00000h .................................................................................................................. 429
21.2.2 SP Setting .......................................................................................................................................... 429
21.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 429
21.2.4 Changing Interrupt Sources .............................................................................................................. 430
21.2.5 Changing Interrupt Control Register Contents ................................................................................. 431
21.3 Notes on Timers ......................................................................................................................... ........... 432
21.3.1 Notes on Timer RA ........................................................................................................................... 432
21.3.2 Notes on Timer RB ........................................................................................................................... 433
21.3.3 Notes on Timer RD ........................................................................................................................... 437
21.3.4 Notes on Timer RE ........................................................................................................................... 443
21.4 Notes on Serial Interface ....................................................................................................................... 444
21.5 Clock Synchronous Serial Interface ...................................................................................................... 445
21.5.1 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 445
21.5.2 Notes on I
2
C Bus Interface ............................................................................................................... 445
21.6 Notes on Hardware LIN ................................................................................................................ ........ 446
21.7 Notes on A/D Converter ........................................................................................................................ 447
A - 5
21.8 Notes on Flash Memory ........................................................................................................................ 448
21.8.1 CPU Rewrite Mode ......................................... .................................................................................. 448
21.9 Notes on Noise ...................................................................................................................................... 451
21.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ............................................................................................................................................ 451
21.9.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 451
22. Notes on On-Chip Debugger ...................................................................................................... 452
23. Notes on Emulator Debugger ..................................................................................................... 453
Appendix 1. Package Dimensions ........................................................................................................ 454
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 455
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 456
Index ..................................................................................................................................................... 457
A - 6
SFR Page Reference
Address
0000h
0001h
0002h
0003h
0004h
Processor Mode Register 0 PM0 62
0005h
Processor Mode Register 1 PM1 62
0006h
System Clock Control Register 0 CM0 66
0007h
System Clock Control Register 1 CM1 67
0008h
0009h
000Ah
Protect Register PRCR 86
000Bh
000Ch
Oscillation Stop Detection Register OCD 68
000Dh
Watchdog Timer Reset Register WDTR 115
000Eh
Watchdog Timer Start Register WDTS 115
000Fh
Watchdog Timer Control Register WDC 114
0010h
Address Match Interrupt Register 0 RMAD0 107
0011h
0012h
0013h
Address Match Interrupt Enable Register AIER 107
0014h
Address Match Interrupt Register 1 RMAD1 107
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Count Source Protect Mode Regist er CSPR 115
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
High-Speed On-Chip O s cillator Co ntro l Reg ister 0
0024h
High-Speed On-Chip O s cillator Co ntro l Reg ister 1
0025h
High-Speed On-Chip O s cillator Co ntro l Reg ister 2
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
Voltage Detection Register 1 VCA1 31
0032h
Voltage Detection Register 2 VCA2 31, 70
0033h
0034h
0035h
0036h
Voltage Monitor 1 Circuit Control Register VW1C 32
0037h
Voltage Monitor 2 Circuit Control Register VW2C 33
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Register Symbol Page
FRA0 69
FRA1 69
FRA2 70
NOTE:
1. Blank columns are all reserved space. No access is allowed.
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h Timer RD0 Interrupt Control Register TRD0IC
0049h Timer RD1 Interrupt Control Register TRD1IC
004Ah Timer RE Interrupt Control Register TREIC
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC
004Eh A/D Conversion Interrupt Control Register ADIC
004Fh SSU Interrupt Control Register/IIC Bus
Interrupt Control Register
0050h
0051h UART0 Transmit Interrupt Control Register S0TIC
0052h UART0 Receive Interrupt Control Regist er S0RIC
0053h UART1 Transmit Interrupt Control Register S1TIC
0054h UART1 Receive Interrupt Control Regist er S1RIC
0055h INT2 Interrupt Control Register INT2IC
0056h Timer RA Interrupt Control Register TRAIC
0057h
0058h Timer RB Interrupt Control Register TRBIC
0059h INT1 Interrupt Control Register INT1IC
005Ah INT3 Interrupt Control Register INT3IC
005Bh
005Ch
005Dh INT0 Interrupt Control Register INT0IC
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Register Symbol Page
SSUIC/IICIC
93
93
92
92
92
93
92
92
92
92
94
92
92
94
94
94
B - 1
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
UART0 Transmit/Receive Mode Register U0MR 268
00A1h
UART0 Bit Rate Register U0BRG 267
00A2h
UART0 Transmit Buffer Register U0TB 267
00A3h
00A4h
UART0 Transmit/Receive Control Register 0 U0C0 269
00A5h
UART0 Transmit/Receive Control Register 1 U0C1 269
00A6h
UART0 Receive Buffer Register U0RB 267
00A7h
00A8h
UART1 Transmit/Receive Mode Register U1MR 268
00A9h
UART1 Bit Rate Register U1BRG 267
00AAh
UART1 Transmit Buffer Register U1TB 267
00ABh
00ACh
UART1 Transmit/Receive Control Register 0 U1C0 269
00ADh
UART1 Transmit/Receive Control Register 1 U1C1 269
00AEh
UART1 Receive Buffer Register U1RB 267
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
SS Control Register H/IIC Bus Contr ol Regis ter 1
00B9h
SS Control Register L/IIC Bus Control Register 2
00BAh SS Mode Register/IIC Bus Mode Register 1 SSMR/ICMR
00BBh SS Enable Register/IIC Bus Interrupt Enable
Register
00BCh SS Status Register/IIC Bus Status Register SSSR/ICSR
00BDh SS Mode Register 2/Slave Address Register SSMR2/SAR
00BEh SS Transmit Data Register/IIC Bus Transmit
Data Register
00BFh SS Receive Data Register/IIC Bus Receive
Data Register
Register Symbol Page
SSCRH/ICCR1
SSCRL/ICCR2
SSER/ICIER
SSTDR/ICDRT
SSRDR/
ICDRR
NOTE:
1. Blank columns are all reserved space. No access is allowed.
285, 315
286, 316
287, 317
288, 318
289, 319
290, 320
291, 320
291, 321
Address
00C0h
A/D Register AD 363
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
A/D Control Register 2 ADCON2 363
00D5h
00D6h
A/D Control Register 0 ADCON0 362, 365, 368
00D7h
A/D Control Register 1 ADCON1 363, 366, 369
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
Port P0 Register P0 48
00E1h
Port P1 Register P1 48
00E2h
Port P0 Direction Register PD0 48
00E3h
Port P1 Direction Register PD1 48
00E4h
Port P2 Register P2 48
00E5h
Port P3 Register P3 48
00E6h
Port P2 Direction Register PD2 48
00E7h
Port P3 Direction Register PD3 48
00E8h
Port P4 Register P4 48
00E9h
00EAh
Port P4 Direction Register PD4 48
00EBh
00ECh
Port P6 Register P6 48
00EDh
00EEh
Port P6 Direction Register PD6 48
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
UART1 Function Select Register U1SR 270
00F6h
00F7h
00F8h Port Mode Register PMR
00F9h External Input Enable Register INTEN
00FAh INT Input Filter Select Register INTF
00FBh Key Input Enable Register KIEN
00FCh Pull-Up Control Register 0 PUR0
00FDh Pull-Up Control Register 1 PUR1
00FEh
00FFh
Register Symbol Page
49, 270, 291,
321
101
102
105
49
49
B - 2
Address
0100h Timer RA Control Register TRACR
0101h Timer RA I/O Control Register TRAIOC
0102h Timer RA Mode Register TRAMR
0103h Timer RA Prescaler Register TRAPRE
0104h Timer RA Register TRA
0105h
0106h LIN Control Register LINCR
0107h LIN Status Register LINST
0108h Timer RB Control Register TRBCR
0109h Timer RB One-Shot Control Register TRBOCR
010Ah Timer RB I/O Control Register TRBIOC
010Bh Timer RB Mode Register TRBMR
010Ch Timer RB Prescaler Register TRBPRE
010Dh Timer RB Secondary Register TRBSC
010Eh Timer RB Primary TRBPR
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Counter Data Register TRESEC
0119h Timer RE Compare Data Register TREMIN
011Ah
011Bh
011Ch Timer RE Control Register 1 TRECR1
011Dh Timer RE Control Register 2 TRECR2
011Eh Timer RE Count Source Select Register TRECSR
011Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h Timer RD Start Register TRDSTR
0138h Timer RD Mode Register TRDMR
0139h Timer RD PWM Mode Register TRDPMR
013Ah Timer RD Function Control Register TRDFCR
013Bh Timer RD Output Master Enable Register 1 TRDOER1
013Ch Timer RD Output Master Enable Register 2 TRDOER2
013Dh Timer RD Output Control Register TRDOCR
013Eh Timer RD Digital Filter Function Select
Register 0
013Fh Timer RD Digital Filter Function Select
Register 1
Register Symbol Page
TRDDF0
TRDDF1
NOTE:
1. Blank columns are all reserved space. No access is allowed.
121
121, 124, 127,
129, 131, 134
122
122
123
347
348
138
138
139, 141, 145,
148, 153
139
140
140
140
260
260
261
261
262
172, 186, 202,
215, 225, 239
172, 186, 203,
216, 226, 240
173, 187, 203
174, 188, 204,
216, 227, 240
189, 205, 217,
228, 241
189, 205, 217,
228, 241
190, 206, 242
175
175
Address
0140h Timer RD Control Register 0 TRDCR0
0141h Timer RD I/O Control Register A0 TRDIORA0
0142h Timer RD I/O Control Register C0 TRDIORC0
0143h Timer RD Status Register 0 TRDSR0
0144h Timer RD Interrupt Enable Register 0 TRDIER0
0145h Timer RD PWM Mode Output Level Control
Register 0
0146h Timer RD Counter 0 TRD0
0148h Timer RD General Register A0 TRDGRA0
014Ah Timer RD General Register B0 TRDGRB0
014Ch Timer RD General Register C0 TRDGRC0
014Eh Timer RD General Register D0 TRDGRD0
0150h Timer RD Control Register 1 TRDCR1
0151h Timer RD I/O Control Register A1 TRDIORA1
0152h Timer RD I/O Control Register C1 TRDIORC1
0153h Timer RD Status Register 1 TRDSR1
0154h Timer RD Interrupt Enable Register 1 TRDIER1
0155h Timer RD PWM Mode Output Level Control
Register 1
0156h Timer RD Counter 1 TRD1
0158h Timer RD General Register A1 TRDGRA1
015Ah Timer RD General Register B1 TRDGRB1
015Ch Timer RD General Register C1 TRDGRC1
015Eh Timer RD General Register D1 TRDGRD1
01B0h
01B1h
01B2h
01B3h Flash Memory Co ntrol Register 4 FMR4
01B4h
01B5h Flash Memory Co ntrol Register 1 FMR1
01B6h
01B7h Flash Memory Co ntrol Register 0 FMR0
01B8h
01B9h
01BAh
01BBh
FFFFh Option Function Select Register OFS
Register Symbol Page
TRDPOCR0
TRDPOCR1
176, 191, 206,
218, 229, 243
177, 192
178, 193
179, 194, 207,
219, 230, 244
180, 195, 208,
220, 231, 245
209
180, 195, 209,
220, 232, 2450147h
181, 196, 210,
221, 232, 2460149h
181, 196, 210,
221, 232, 246014Bh
181, 196, 210,
221, 246014Dh
181, 196, 210,
221, 232, 246014Fh
176, 191, 206,
229
177, 192
178, 193
179, 194, 207,
219, 230, 244
180, 195, 208,
220, 231, 245
209
180, 195, 209,
2320157h
181, 196, 210,
221, 232, 2460159h
181, 196, 210,
221, 232, 246015Bh
181, 196, 210,
221, 232, 246015Dh ,
181, 196, 210,
221, 232, 246015Fh
388
387
386
23, 114, 381
B - 3
R8C/20 Group, R8C/21 Group
REJ09B0250-0200
RENESAS MCU
Aug 27, 2008
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using the R8C CPU core and is packaged
in a 48-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of
instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed. This
Furthermore, the data flash (1 KB x 2 blocks) is embedded in the R8C/21 Group.
The difference between R8C/20 and R8C/21 Groups is only the existence of the data flash. Their peripheral functi ons
are the same.
1.1 Applications
Automotive, etc.
Rev.2.00
Rev.2.00 Aug 27, 2008 Page 1 of 458
REJ09B0250-0200
R8C/20 Group, R8C/21 Group 1. Overview
1.2 Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/20 Group and Table 1.2 outlines the Functions and
Specifications for R8C/21 Group.
Table 1.1 Functions and Specifications for R8C/20 Group
Item Specification
CPU Number of fundamental instructions 89 instructions
Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.3 Product Information for R8C/20 Group
Peripheral
Function
Electric
Characteristics
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Operating Ambient Temperature -40 to 85°C
Package 48-pin mold-plastic LQFP
NOTES:
1. When using options, be sure to inquire about the specification .
2
2. I
C bus is a registered trademark of Koninklijke Philips Electronics N.V.
Ports I/O ports: 41 pins, Input port: 3 pins
Timers Timer RA: 8 bits x 1 channel,
Timer RB: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits x 2 channel
(Circuits of input capture and output compare)
Timer RE: With compare match function
Serial interface 1 channel (UART0)
Clock synchronous I/O, UART
1 channel (UART1)
UART
Clock synchronous serial interface
LIN module
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 1 1 sources, Extern al: 5 sources, Software: 4 sources,
Clock generation circuits 2 circuits
Oscillation stop detection
function
Voltage detection circuit On-chip
Power-on reset circuit include On-chip
Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version)
Current consumption Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on-
Programming and erasure
endurance
1 channel
I2C bus interface
select
Hardware LIN: 1 channel
(timer RA, UART0)
Reset start selectable
Priority level: 7 levels
XIN clock generation circuit (with on-chip feedback resistor)
On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency adjustment
function.
Stop detection of XIN clock oscillation
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
chip oscillator stopping)
Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip
oscillator stopping)
100 times
-40 to 125°C (option
(2)
, Clock synchronous serial I/O with chip
(1)
)
Rev.2.00 Aug 27, 2008 Page 2 of 458
REJ09B0250-0200
R8C/20 Group, R8C/21 Group 1. Overview
Table 1.2 Functions and Specifications for R8C/21 Group
Item Specification
CPU Number of fundamental instructions 89 instructions
Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.4 Product Information for R8C/21 Group
Peripheral
Function
Electric
Characteristics
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Operating Ambient Temperature -40 to 85°C
Package 48-pin mold-plastic LQFP
Ports I/O ports: 41 pins, Input port: 3 pins
Timers Timer RA: 8 bits x 1 channel,
Timer RB: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits x 2 channel
(Circuits of input capture and output compare)
Timer RE: With compare match function
Serial interface 1 channel (UART0)
Clock synchronous I/O, UART
1 channel (UART1)
UART
Clock synchronous serial interface
LIN module
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits x 1 channel (with prescaler)
Interrupts Internal: 11 sources, External: 5 sources, Software: 4 sources,
Clock generation circuits 2 circuits
Oscillation stop detection
function
Voltage detection circuit On-chip
Power-on reset circuit include On-chip
Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version)
Current consumption Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on-
Programming and erasure
endurance
1 channel
I2C bus interface
select
Hardware LIN: 1 channel
(Timer RA, UART0)
Reset start selectable
Priority level: 7 levels
XIN clock generation circuit (with on-chip feedback resistor)
On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency adjustment
function.
Stop detection of XIN clock oscillation
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
chip oscillator stopping)
Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip
oscillator stopping)
10,000 times (data flash)
1,000 times (program ROM)
-40 to 125°C (option
(2)
, Clock synchronous serial I/O with chip
(1)
)
NOTES:
1. When using options, be sure to inquire about the specification .
2
2. I
C bus is a registered trademark of Koninklijke Philips Electronics N.V.
Rev.2.00 Aug 27, 2008 Page 3 of 458
REJ09B0250-0200
R8C/20 Group, R8C/21 Group 1. Overview
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
I/O port
Timer
Timer RA (8 bits)
Timer RB (8 bits)
Timer RD (16 bits
Timer RE (8 bits)
Watchdog timer
(15 bits)
Port P0
× 2 channels)
8
8
Port P1
A/D converter
(10 bits
× 12 channels)
UART or
clock synchronous serial I/O
(8 bits × 1 channel)
(8 bits
I2C bus interface or
clock synchronous serial I/O
with chip select
(8 bits × 1 channel)
LIN module
(1 channel)
R8C CPU core
R0H R0L
R1H
R2
R3
A0
A1
FB
Port P2
UART
× 1 channel)
R1L
8
6
Port P3
3 3
Port P4
8
Port P6
System clock
generation circuit
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
Memory
SB
USP
ISP
INTB
PC
FLG
(1)
ROM
(2)
RAM
Multiplier
Figure 1.1 Block Diagram
Rev.2.00 Aug 27, 2008 Page 4 of 458
REJ09B0250-0200
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
R8C/20 Group, R8C/21 Group 1. Overview
1.4 Product Information
Table 1.3 lists Product Information for R8C/20 Group and Table 1.4 lists Product Information for R8C/21 Group.
Table 1.3 Product Information for R8C/20 Group Current of Aug. 2008
Type No. ROM Capacity RAM Capacity Package Type Remarks
R5F21206JFP 32 Kbytes 2 Kbytes PLQP0048KB-A J version Flash memory
R5F21207JFP 48 Kbytes 2.5 Kbytes PLQP0048KB-A
R5F21208JFP 64 Kbytes 3 Kbytes PLQP0048KB-A
R5F2120AJFP 96 Kbytes 5 Kbytes PLQP0048KB-A
R5F2120CJFP
128 Kbytes
(1)
6 Kbytes PLQP0048KB-A
R5F21206KFP 32 Kbytes 2 Kbytes PLQP0048KB-A K version
R5F21207KFP 48 Kbytes 2.5 Kbytes PLQP0048KB-A
R5F21208KFP 64 Kbytes 3 Kbytes PLQP0048KB-A
R5F2120AKFP 96 Kbytes 5 Kbytes PLQP0048KB-A
R5F2120CKFP
128 Kbytes
(1)
6 Kbytes PLQP0048KB-A
NOTE:
1. Do not use addresses 20000h to 23FFFh because these area s are used for the emulator debu gger .
Refer to 23. Notes on Emulator Debugger.
version
Part number R 5 F 21 20 6 J XXX FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin-pitch, 7 mm square body)
ROM number
Classification
J: Operating ambient temperature -40°C to 85°C (J version)
K: Operating ambient temperature -40°C to 125°C (K version)
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/20 Group
R8C/2x Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group
Rev.2.00 Aug 27, 2008 Page 5 of 458
REJ09B0250-0200
R8C/20 Group, R8C/21 Group 1. Overview
Table 1.4 Product Information for R8C/21 Group Current of Aug. 2008
Type No.
ROM Capacity
Program ROM
Data Flash
RAM Capacity Package T ype Remarks
R5F21216JFP 32 Kbytes 1 Kbyte X 2 2 Kbytes PLQP0048KB-A J version Flash
R5F21217JFP 48 Kbytes 1 Kbyte X 2 2.5 Kbytes PLQP0048KB-A
R5F21218JFP 64 Kbytes 1 Kbyte X 2 3 Kbytes PLQP0048KB-A
memory
version
R5F2121AJFP 96 Kbytes 1 Kbyte X 2 5 Kbytes PLQP0048KB-A
R5F2121CJFP
128 Kbytes
(1)
1 Kbyte X 2 6 Kbytes PLQP0048KB-A
R5F21216KFP 32 Kbytes 1 Kbyte X 2 2 Kbytes PLQP0048KB-A K version
R5F21217KFP 48 Kbytes 1 Kbyte X 2 2.5 Kbytes PLQP0048KB-A
R5F21218KFP 64 Kbytes 1 Kbyte X 2 3 Kbytes PLQP0048KB-A
R5F2121AKFP 96 Kbytes 1 Kbyte X 2 5 Kbytes PLQP0048KB-A
R5F2121CKFP
128 Kbytes
(1)
1 Kbyte X 2 6 Kbytes PLQP0048KB-A
NOTE:
1. Do not use addresses 20000h to 23FFFh because these area s are used for the emulator debu gger .
Refer to 23. Notes on Emulator Debugger.
Part number R 5 F 21 21 6 J XXX FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin-pitch, 7 mm square body)
ROM number
Classification
J: Operating ambient temperature -40°C to 85°C (J version)
K: Operating ambient temperature -40°C to 125°C (K version)
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/21 Group
R8C/2x Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.3 Type Number, Memory Size, and Package of R8C/21 Group
Rev.2.00 Aug 27, 2008 Page 6 of 458
REJ09B0250-0200
R8C/20 Group, R8C/21 Group 1. Overview
1.5 Pin Assignments
Figure 1.4 shows Pin Assignments (Top View).
Pin assignments (top view)
P4_5/INT0
P6_6/INT2/TXD1
P6_7/INT3/RXD1
P1_2/KI2 /AN10
P1_1/KI1 /AN9
P1_0/KI0 /AN8
P3_1/TRBO
P3_0/TRAO
P6_5
P6_4
P6_3
P0_7/AN0
25
26
27
28
29
30
31
32
33
34
35
36
P3_7/SSO
37P0_6/AN1
38P0_5/AN2
39P0_4/AN3
40P4_2/VREF
41P6_0/TREO
42P6_2
43P6_1
44P0_3/AN4
45P0_2/AN5
46P0_1/AN6
47P0_0/AN7
48
R8C/20 Group,
R8C/21 Group
9VSS/AVSS
8
7RESET
6P4_4
5P4_3
4MODE
3P3_4/SDA/SCS
2P3_3/SSI
1P3_5/SCL/SSCK
10P4_6/XIN
24
23
22
21
20
19
18
17
16
15
14
13
12
11VCC/AVCC
P1_3/KI3/AN11
P1_4/TXD0
P1_5/RXD0/(TRAIO)/(INT1)
P1_6/CLK0
P1_7/TRAIO/INT1
P2_0/TRDIOA0/TRDCLK
P2_1/TRDIOB0
P2_2/TRDIOC0
P2_3/TRDIOD0
P2_4/TRDIOA1
P2_5/TRDIOB1
P2_6/TRDIOC1
(2)
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a program.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.4 Pin Assignments (Top View)
P4_7/XOUT
(1)
P2_7/TRDIOD1
Package: PLQP0048KB-A
0.5 mm pin pitch, 7 mm square body
Rev.2.00 Aug 27, 2008 Page 7 of 458
REJ09B0250-0200
R8C/20 Group, R8C/21 Group 1. Overview
1.6 Pin Functions
Table 1.5 lists the Pin Functions and Table 1.6 lists the Pin Name Information by Pin Number.
Table 1.5 Pin Functions
Type Symbol I/O Type Description
Power Supply Input VCC
VSS
Analog Power Supply
Input
Reset Input RESET
MODE MODE I Connect this pin to VCC via a resistor.
XIN Clock Input XIN I These pins are provided for the XIN clock generation
XIN Clock Output XOUT O
Interrupt Input INT0 to INT3 IINT interrupt input pins.
INT
Key Input Interrupt KI0
Timer RA TRAIO I/O Timer RA I/O pin.
Timer RB TRBO O Timer RB output pin.
Timer RD TRDIOA0, TRDIOA1,
Timer RE TREO O Divided clock output pin.
Serial Interface CLK0 I/O Transfer clock I/O pin.
2
C Bus Interface
I
Clock Synchronous
Serial I/O with Chip
Select
Reference Voltage Input VREF I Reference voltage input pin to A/D converter.
A/D Converter AN0 to AN11 I Analog input pins to A/D converter.
I/O Port P0_0 to P0_7,
Input Port P4_2, P4_6, P4_7 I Input only ports.
A VCC, AVSS I Applies the power supply for the A/D converter. Connect
to KI3 I Key input interrupt input pins.
TRAO O Timer RA output pin.
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
TRDCLK I External clock input pin.
RXD0, RXD1 I Serial data input pins.
TXD0, TXD1 O Serial data output pins.
SCL I/O Clock I/O pin.
SDA I/O Data I/O pin.
SSI I/O Data I/O pin.
SCS
SSCK I/O Clock I/O pin.
SSO I/O Data I/O pin.
P1_0 to P1_7,
P2_0 to P2_7,
P3_0, P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_5,
P6_0 to P6_7
I: Input O: Output I/O: Input and output
I Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the
VSS pin.
a capacitor between A VCC and AVSS.
I Input “L” on this pin resets the MCU.
circuit I/O. Connect a ceramic resonator or a crystal
oscillator between the XIN and XOUT pins. To use an
externally derived clock, input it to the XIN pin and leave
the XOUT pin open.
Timer RD input pins.
INT0
Timer RA input pins.
INT1
I/O Timer RD I/O ports.
I/O Chip-select signal I/O pin.
I/O CMOS I/O ports. Each port contains an input/output
select direction register, allowing each pin in that port to
be directed for input or output individually.
Any port set to input can select whether to use a pull-up
resistor or not by a program.
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R8C/20 Group, R8C/21 Group 1. Overview
Table 1.6 Pin Name Information by Pin Number
I/O Pin Functions for of Peripheral Modules
Pin
Number
Control Pin Port
Interrupt Timer
Serial
Interface
1 P3_5 SSCK SCL
2 P3_3 SSI
3P3_4
4MODE
5P4_3
6P4_4
7
RESET
8XOUTP4_7
9 VSS/AVSS
10 XIN P4_6
11 VCC/AVCC
12 P2_7 TRDIOD1
13 P2_6 TRDIOC1
14 P2_5 TRDIOB1
15 P2_4 TRDIOA1
16 P2_3 TRDIOD0
17 P2_2 TRDIOC0
18 P2_1 TRDIOB0
19 P2_0 TRDIOA0/TRDCLK
20 P1_7
INT1
TRAIO
21 P1_6 CLK0
22 P1_5
(INT1
(1)
)
(TRAIO)
(1)
RXD0
23 P1_4 TXD0
24 P1_3
25 P4_5
26 P6_6
27 P6_7
28 P1_2
29 P1_1
30 P1_0
KI3
INT0
INT2
INT3
KI2
KI1
KI0
INT0
TXD1
RXD1
31 P3_1 TRBO
32 P3_0 TRAO
33 P6_5
34 P6_4
35 P6_3
36 P0_7 AN0
37 P0_6 AN1
38 P0_5 AN2
39 P0_4 AN3
40 VREF P4_2
41 P6_0 TREO
42 P6_2
43 P6_1
44 P0_3 AN4
45 P0_2 AN5
46 P0_1 AN6
47 P0_0 AN7
48 P3_7 SSO
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Clock Synchronous
Serial I/O
with Chip Select
SCS
2
I
C Bus
Interface
SDA
A/D
Converter
AN1 1
AN10
AN9
AN8
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R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB
comprise a register bank. Two sets of register banks are provided.
b31
R2
R3
b15 b8b7
R0H (high-order of R0)
R0 L (low -ord er o f R0 )
R1H (high-order of R1) R1L (low-order of R1)
R2
R3
A0
A1
FB
b15b19
INTBH
The 4-high order bits of INTB are INTBH and
the 16-low order bits of INTB are INTBL.
b19
INTBL
PC
b15
USP
ISP
SB
b0
Data registers
Address registers
Frame base registers
b0
Interrupt table register
b0
Program counter
b0
User stack pointer
Interrupt stack pointer
Static base register
(1)
(1)
(1)
b15
IPL
NOTE:
1. A register bank comprises these registers. Two sets of register banks are provided.
Figure 2.1 C PU Registers
b15
b0
FLG
b8
b7
b0
C
DZSBOIU
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
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R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU)
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3.
R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The
same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register
(R2R0). The same applies R3R1 as R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also
are used for transfer, arithmetic and logic operations. The same applies to A1 as A0.
A1 can be combined with A0 to be used a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB, a 20-bit register, indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU status.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is 0. The register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when the operation resulted in an overflow; otherwise, 0.
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R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU)
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to
0 when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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R8C/20 Group, R8C/21 Group 3. Memory
3. Memory
3.1 R8C/20 Group
Figure 3.1 shows a Memory Map of R8C/20 Group. The R8C/20 Group has 1 Mbyte of address space from
address 00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal
ROM is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future
user and cannot be accessed by users.
00000h
002FFh
00400h
0XXXXh
01300h
02000h
03000h
0SSSSh
0YYYYh
0FFFFh
ZZZZZh
FFFFFh
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Do not use addresses 20000h to 23FFFh because these areas are used for the emul ator debugger. Refer to 23. Notes on
Emulator Debugger.
Part Number
R5F21206JFP, R5F21206KFP
R5F21207JFP, R5F21207KFP
R5F21208JFP, R5F21208KFP
R5F2120AJFP, R5F2120AKFP
R5F2120CJFP, R5F2120CKFP
SFR
(Refer to 4. Special
Function Registers
(SFRs))
Internal RAM
Reserved area
Internal RAM
Internal ROM
(program ROM)
Internal ROM
(program ROM)
(2)
Size Address 0YYYYh Address ZZZZZh
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Internal ROM
08000h
04000h
04000h
04000h
04000h
0FFDCh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Watchdog timer•oscillation stop detection•voltage detection
-
13FFFh
1BFFFh
23FFFh
Address break
Size
2 Kbytes
2.5 Kbytes
3 Kbytes
5 Kbytes
6 Kbytes
Single step
(Reserved)
Reset
Internal RAM
Address 0XXXXh
00BFFh
00DFFh
00FFFh
00FFFh
00FFFh
Address 0SSSSh
037FFh
03BFFh
-
-
-
Figure 3.1 Memory Map of R8C/20 Group
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R8C/20 Group, R8C/21 Group 3. Memory
3.2 R8C/21 Group
Figure 3.2 shows a Memory Map of R8C/21 Group. The R8C/21 Group has 1 Mbyte of address space from
address 00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated them. All addresses within the SFR, which have nothing allocated are reserved for future
use and cannot be accessed by users.
00000h
002FFh
00400h
0XXXXh
01300h
02000h
02400h
02BFFh
03000h
0SSSSh
0YYYYh
0FFFFh
ZZZZZh
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locati ons in these regions.
3. Do not use addresses 20000h to 23FFFh because these areas are used for t he emulator debugger. Refer to 23. Notes on
Emulator Debugger.
Part Number
R5F21216JFP, R5F21216KFP
R5F21217JFP, R5F21217KFP
R5F21218JFP, R5F21218KFP
R5F2121AJFP, R5F2121AKFP
R5F2121CJFP, R5F2121CKFP
SFR
(Refer to 4. Special
Function Registers
(SFRs))
Internal RAM
Reserved area
Internal ROM
(data flash)
Internal RAM
Internal ROM
(program ROM)
Internal ROM
(program ROM)
(1)
(3)
Size Address 0YYYYh Address ZZZZZh
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Internal ROM
08000h
04000h
04000h
04000h
04000h
0FFDCh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Watchdog timer•oscillation stop detection•voltage detection
-
-
13FFFh
1BFFFh
23FFFh
Address break
Size
2 Kbytes
2.5 Kbytes
3 Kbytes
5 Kbytes
6 Kbytes
Single step
(Reserved)
Reset
Internal RAM
Address 0XXXXh
00BFFh
00DFFh
00FFFh
00FFFh
00FFFh
Address 0SSSSh
037FFh
03BFFh
-
-
-
Figure 3.2 Memory Map of R8C/21 Group
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