RENESAS R8C-13 User Manual

R8C/13 Group

REJ03B0069-0100Z

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

1. Overview

This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU
core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing
instructions at high speed.
The data flash ROM (2 KB X 2 blocks) is embedded.

1.1 Applications

Electric household appliance, office equipment, housing equipment (sensor, security), general industrial
equipment, audio, etc.

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Sep 30, 2004

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R8C/13 Group 1. Overview

1.2 Performance Outline

Table 1.1. lists the performance outline of this MCU.

Table 1.1 Performance outline

Item Performance

CPU Number of basic instructions 89 instructions

Shortest instruction execution time

Operating mode Single-chip
Address space 1M bytes

Memory capacity See Table 1.2.
Peripheral Interrupt Internal: 11 factors, External: 5 factors,
function Software: 4 factors, Priority level: 7 levels

Watchdog timer 15 bits x 1 (with prescaler)

Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,

Serial Interface •1 channel

A/D converter 10-bit A/D converter: 1 circuit, 12 channels

Clock generation circuit 2 circuits

Oscillation stop detection function

Voltage detection circuit Included

Power on reset circuit Included

Port Input/Output: 22 (including LED drive port), Input: 2

Electrical Power supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ)
characteristics

Power consumption Typ. 9 mA (VCC = 5.0 V, (f(XIN) = 20 MHZ, High-speed mode)

Flash memory

Operating ambient temperature -20 to 85 °C

Package 32-pin plastic mold LQFP

Program/erase voltage VCC = 2.7 to 5.5 V

Number of program/erase 10,000 times (Data area)

50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)

Reset start function selectable

Timer Z: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel

Circuits of input capture and output compare.

Clock synchronous, UART

•1 channel
UART

•Main clock generation circuit (Equipped with a built-in

feedback resistor)

•On-chip oscillator (high speed, low speed)

On High-speed on-chip oscillator the frequency adjust­ment function is usable.

Stop detection of main clock oscillation

(LED drive I/O port: 8)

VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ)

Typ. 5 mA (VCC = 3.0 V, (f(XIN) = 10 MHZ, High-speed mode)
Typ. 35µA(VCC = 3.0 V, Wait mode, Peripheral clock stops)
Typ. 0.7µA(VCC = 3.0 V, Stop mode)

1,000 times (Program area)

-40 to 85 °C (D-version)

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R8C/13 Group 1. Overview

1.3 Block Diagram

Figure 1.1 shows this MCU block diagram.

I/O port

P o r t P 0

Pe r i p h e r a l f u n c t i o n s

T i m e r

Timer X (8 bits)
Timer Y (8 bits)
Timer Z (8 bits)

Timer C (16 bits)

Watchdog timer

(15 bits)

8

8

Port P1

A/D converter

(10 bits ✕ 12 channels)

UART or Clock synchronous

serial I/O

(8 bits ✕ 1 channel)

UART

(8 bits ✕ 1 channel)

R8C Series CPU c or e

R0LR 0 H

R 1 HR1L

R2
R3

A0
A1
FB

5

Port P3

System clock generator

X

High-speed on-chip oscillator

Low-speed on-chip oscillator

SB

USP

ISP

INTB

PC

FLG

IN-XOUT

M e m o r y

M u l t i p l i e r

1 2

P o r t P 4

R O M

( N o t e 1 )

RAM

(Note 2)

Figure 1.1 Block Diagram

N o t e 1 : R O M s i z e d e p e n d s o n M C U t y p e .
N o t e 2 : R A M s i z e d e p e n d s o n M C U t y p e .

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R8C/13 Group 1. Overview

1.4 Product Information

Table 1.2 lists the products.

Table 1.2 Product List

Type No.

R5F21132FP
R5F21133FP
R5F21134FP

R5F21132DFP
R5F21133DFP
R5F21134DFP

ROM capacity

Program area

8K bytes
12K bytes
16K bytes

8K bytes

12K bytes
16K bytes

Type No. R 5 F 21 13 4 D FP

Data area

2K bytes x 2
2K bytes x 2
2K bytes x 2
2K bytes x 2
2K bytes x 2
2K bytes x 2

Package type:
FP : 32P6U

Shows characteristics and others.
D: Operating ambient temperature –40 °C to 85 °C
No symbol: Operating ambient temperature –20 °C to 85 °C

RAM capacity

512 bytes
768 bytes

1K bytes

512 bytes
768 bytes

1K bytes

Package type

32P6U-A
32P6U-A

32P6U-A
32P6U-A

32P6U-A
32P6U-A

As of September 2004

Remarks

Flash memory version

D version

ROM capacity:
2 : 8 KBytes.
3 : 12 KBytes.
4 : 16 KBytes.

R8C/13 group

R8C/Tiny series

Memory type:
F: Flash memory version

Renesas MCU

Renesas semiconductors

Figure 1.2 Type No., Memory Size, and Package

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R8C/13 Group 1. Overview

1.5 Pin Assignments

Figure 1.3 shows the pin configuration (top view).

PIN CONFIGURATION (top view)

2

1

0

1

P 06/ A N
P 05/ A N

P 04/ A N

M O D E
P 03/ A N
P 02/ A N

P 01/ A N

P00/AN7/TxD

1

/

0

R

0

N

3

S

/

/

C

S

0

7

C

3

0

A

P

V

V

C N T

C M P

P

I

U

T

A

C M P

2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7

2 5

1

2 6

2

2 7

3

2 8
2 9

4

3 0

5

3 1

6

11

3 2

R 8 C / 1 3 G r o u p

1 2 3 4 5 6 7 8

/

1

1

R

N

I

/

T
O

Z
/

1

3

E

P

C

F

T

/

/

3

2

R

T

T

V

/

C

/

/

C

3

2

3

3

V

I N

I N

C N T

P

P

C M P

A

1 6
1 5
1 4
1 3
1 2
1 1
1 0

P 45/ I N T
P 10/ K I0/ A N8/ C M P 0
P 11/ K I1/ A N9/ C M P 0
P 12/ K I2/ A N
P 13/ K I3/ A N
P 14/ T x D
P 15/ R x D

9

P16/CLK

0

0
1

1 0

/ C M P 0

2

1 1

0

0
0

1

D
/

0

1

D

N

/

7

3
P

R x

T x

N o t e s :
1 . P 4

7

f u n c t i o n s o n l y a s a n i n p u t p o r t .

2. W h e n u s i n g O n - c h i p d e b u g g e r , d o n o t u s e p i n s P 0
a n d P 37/ T x D

1 0

/ R x D1.

3 . D o n o t c o n n e c t I V c c t o V c c .

Figure 1.3 Pin Configuration (Top View)

)

6

S
S

V
C

E S E

S

T

S

V

P

R

7

4
/

T
O

X

(N o t e 1

U

P

0

C

4

C

R

V

/

N

I

X

/

1

T
/

7

1
P

I N

C N T

0

/ A N7/ T x D

1 1

Package: 32P6U-A

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R8C/13 Group 1. Overview

1.6 Pin Description

Table 1.3 shows the pin description

Table 1.3 Pin description

Signal name Pin name I/O type
Power supply Vcc, I
input Vss
IVcc IVcc O

Analog power AVcc, AVss I
supply input

Reset input

___________

RESET I
CNVss CNVss I
MODE MODE I
Main clock input XIN I

Main clock output XOUT O

_____

INT interrupt input
Key input interrupt
Timer X CNTR0 I/O

_______ _______

INT0 to INT3 I

_____ _____

KI0 to KI3 I

__________

CNTR0 O
Timer Y CNTR1 I/O
Timer Z TZOUT O
Timer C TCIN I

CMP00 to CMP03,

O

CMP10 to CMP13
Serial interface CLK0 I/O

RxD0, RxD1 I

TxD0, TxD10,O

TxD11
Reference voltage VREF I
input
A/D converter AN0 to AN11 I
I/O port P00 to P07, I/O

P10 to P17,

P30 to P33, P37,

P45

Input port P46, P47 I

Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
This pin is to stabilize internal power supply.
Connect this pin to Vss via a capacitor (0.1 µF).
Do not connect to Vcc.
These are power supply input pins for A/D converter.
Connect the AVss pin to Vss. Connect a capacitor
between pins AVcc and AVss.
“L” on this input resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generat­ing circuit I/O. Connect a ceramic resonator or a crys­tal oscillator between the XIN and XOUT pins. To use
an externally derived clock, input it to the XIN pin and
leave the XOUT pin open.

______

These are INT interrupt input pins.
These are key input interrupt pins.
This is the timer X I/O pin.
This is the timer X output pin.
This is the timer Y I/O pin.
This is the timer Z output pin.
This is the timer C input pin.
These are the timer C output pins.

This is a transfer clock I/O pin.
These are serial data input pins.
These are serial data output pins.

This is a reference voltage input pin for A/D con­verter.
These are analog input pins for A/D converter.
These are 8-bit CMOS I/O ports. Each port has an I/O
select direction register, allowing each pin in that port
to be directed for input or output individually.
Any port set to input can select whether to use a pull­up resistor or not by program.
P10 to P17 also function as LED drive ports.
These are input only pins.

Function

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R8C/13 Group 2. Central Processing Unit (CPU)

g

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.

b31

R2
R3

b15

R0H(R0's high bits)
R1H(R1's high bits)

b19

b15

INTBH

The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.

b19

PC

b15

b15

b15

b7 b8

IPL

b8 b7 b0

R0L(R0's low bits)
R1L(R1's low bits)

R2
R3
A0

A1

FB

INTBL

USP

ISP

SB

FLG

Data registers (Note 1)

Address registers (Note 1)
Frame base registers (Note 1)

b0

Interrupt table register

b0

Program counter

b0

User stack pointer
Interrupt stack pointer

Static base register

b0

Flag register

b0

CDZSBOIU

Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area

Note 1: These re

isters comprise a register bank. There are two register banks.

Figure 2.1 Central Processing Unit Register

2.1 Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32­bit data register (R2R0). R3R1 is the same as R2R0.

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R8C/13 Group 2. Central Processing Unit (CPU)

2.2 Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3 Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4 Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5 Register Bank Select Flag (B Flag)

Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.

2.8.6 Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.

2.8.10 Reserved Area

When write to this bit, write "0". When read, its content is indeterminate.

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R8C/13 Group 3. Memory

3. Memory

Figure 3.1 is a memory map of this MCU. The address space extends the 1M bytes from address 0000016
to FFFFF16.
The internal ROM (program area) is allocated in a lower address direction beginning with address 0FFFF16.
For example, a 16-Kbyte internal ROM is allocated to the addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated to the addresses from 0FFDC
the start address of each interrupt routine here.
The internal ROM (data area) is allocated to the addresses from 0200016 to 02FFF16.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 1-Kbyte internal RAM is allocated to the addresses from 0040016 to 007FF16. In addition to storing data,
the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
Special function registers (SFR) are allocated to the addresses from 0000016 to 002FF16. Peripheral func­tion control registers are located here. Of the SFR, any space which has no functions allocated is reserved
for future use and cannot be used by users.

16 to 0FFFF16. Therefore, store

00000

002FF

00400

0XXXX

02000

02FFF

0YYYY

0FFFF

FFFFF

16

16

16

16

16

16

16

16

16

SFR

(See Chapter 4 for details.)

Internal RAM

Internal ROM

(data area)

Internal ROM

(program area)

Expanding area

1

0FFDC

0FFFF

16

Watchdog timer,Oscillation stop detection,Voltage detection

16

Undefined instruction

NOTES:

1. The data flash ROM block A (2K bytes) and block B (2K bytes) are shown.

2. Blank spaces are reserved. No access is allowed.

Type name

R5F21134FP, R5F21134DFP

R5F21133FP, R5F21133DFP
R5F21132FP, R5F21132DFP

Internal ROM

Size

16K bytes
12K bytes

8K bytes

Address 0YYYY

0C000

16
16

0D000

0E000

16

16

Internal RAM

Size

1K bytes
768 bytes
512 bytes

Overflow

BRK instruction

Address match

Single step

(Reserved)
(Reserved)

Reset

Address 0XXXX

007FF
006FF
005FF

16
16
16
16

Figure 3.1 Memory Map

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