Renesas M16C Series, R8C/11 Series, R8C/Tiny Series Hardware Manual
REJ09B0062-0120
R8C/11 Group
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY/R8C/Tiny SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev. 1.20
Revision date: Jan 27, 2006
www.renesas.com
Keep safety first in your circuit designs!
1.
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better and more reliable, but there is always the possibility that trouble may occur with
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
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Renesas Technology Corp. or a third party.
2.
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any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
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How to Use This Manual
0
1. Introduction
This hardware manual provides detailed information on the R8C/11 Group of microcomputers.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
X X X r e g i s t e r
b 7b 6b 5b 4b 3b2b 1b 0
0
d d r e s
f t e r r e s e
X
S y m b o lA
X X XX
X X X
XXX1
(b2)
( b 3 )
XXX4
XXX5
X X X 6
X X X 7
Bit NameBit symbol
X X X B i t
N o t h i n g i s a s s i g n e d .
W h e n w r i t e , s h o u l d s e t t o " 0 " . W h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e .
R e s e r v e d B i t
X X X B i t
XXX Bit
sA
X0
b 1 b 0
1 0 : X X X
0 1 : X X X
1 0 : A v o i d t h i s s e t t i n g
1 1 : X X X
Must set to “0”
Function varies depending on each
operation mode
0: XXX
1: XXX
0
h
t
Function
*5
*1
Blank:Set to “0” or “1” according to the application
0: Set to “0”
1: Set to “1”
X: Nothing is assigned
*2
RW: Read and write
RO: Read only
WO: Write only
−: Nothing is assigned
*3
•Reserved bit
Reserved bit. Set to specified value.
*4
•Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to “0” when writing to this bit.
•Do not set to this value
The operation is not guaranteed when a value is set.
•Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
*5
Follow the text in each manual for binary and hexadecimal notations.
*1
RW
RW
RW
RW
R W
W O
R W
RO
*2
*3
*4
3. M16C Family Documents
The following documents were prepared for the M16C family.
(1)
Document
Short Sheet
Data Sheet
Hardware Manual
Software Manual
Application Note
RENESAS TECHNICAL UPDATE
NOTES:
1. Before using this material, please visit the our website to verify that this is the most updated
document available.
Hardware overview
Hardware overview and electrical characteristics
Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts).
*Refer to the application note for how to use peripheral functions.
Detailed description of assembly instructions and microcomputer
performance of each instruction
• Usage and application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
Preliminary report about the specification of a product, a document,
etc.
Contents
Table of Contents
SFR Page Reference
Chapter 1. Overview..............................................................1
1.1 Applications ....................................................................................................................1
1.2 Performance Overview...................................................................................................2
1.3 Block Diagram ................................................................................................................ 3
1.4 Product Information .......................................................................................................4
1.5 Pin Assignments.............................................................................................................5
1.6 Pin Description ...............................................................................................................6
Chapter 2. Central Processing Unit (CPU)..........................7
2.1 Data Registers (R0, R1, R2 and R3) ..............................................................................7
2.2 Address Registers (A0 and A1) .....................................................................................8
2.3 Frame Base Register (FB)..............................................................................................8
2.4 Interrupt Table Register (INTB)......................................................................................8
2.5 Program Counter (PC)....................................................................................................8
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ...................................... 8
2.7 Static Base Register (SB) .............................................................................................. 8
2.8 Flag Register (FLG) ........................................................................................................8
2.8.1 Carry Flag (C Flag) .................................................................................................... 8
2.8.2 Debug Flag (D Flag)...................................................................................................8
2.8.3 Zero Flag (Z Flag) ......................................................................................................8
2.8.4 Sign Flag (S Flag) ......................................................................................................8
2.8.5 Register Bank Select Flag (B Flag) ..........................................................................8
2.8.6 Overflow Flag (O Flag) .............................................................................................. 8
2.8.7 Interrupt Enable Flag (I Flag)....................................................................................8
2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 8
2.8.9 Processor Interrupt Priority Level (IPL) .................................................................. 8
2.8.10 Reserved Area..........................................................................................................8
Chapter 3. Memory................................................................ 9
Chapter 4. Special Function Registers (SFR)................... 10
Chapter 5. Reset.................................................................. 14
5.1 Hardware Reset ............................................................................................................ 14
5.1.1 Hardware Reset 1.................................................................................................................................. 14
5.1.2 Hardware Reset 2.................................................................................................................................. 17
5.1.3 Power-on Reset Function.....................................................................................................................18
5.2 Software Reset..............................................................................................................20
5.3 Watchdog Timer Reset.................................................................................................20
A-1
5.4 Voltage Detection Circuit .............................................................................................21
5.4.1 Voltage Detection Interrupt ..................................................................................................................26
5.4.2 Exiting Stop Mode on a Voltage Detection Interrupt .........................................................................28
Chapter 6. Clock Generation Circuit..................................29
6.1 Main Clock.....................................................................................................................34
6.2 On-Chip Oscillator Clock ............................................................................................. 35
6.2.1 Low-Speed On-Chip Oscillator ............................................................................................................35
6.2.2 High-Speed On-Chip Oscillator ...........................................................................................................35
6.3 CPU Clock and Peripheral Function Clock ................................................................ 36
6.3.1 CPU Clock..............................................................................................................................................36
6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO) .......................................................36
6.3.3 fRING and fRING128 ...................................................................................................................................................................36
6.3.4 fRING-fast ......................................................................................................................................................................................36
6.4 Power Control ...............................................................................................................37
6.4.1 Normal Operation Mode .......................................................................................................................37
6.4.2 Wait Mode ..............................................................................................................................................39
6.4.3 Stop Mode..............................................................................................................................................40
6.5 Oscillation Stop Detection Function...........................................................................42
6.5.1 How to Use Oscillation Stop Detection Function ..............................................................................42
Chapter 7. Protection.......................................................... 44
Chapter 8. Processor Mode................................................ 45
8.1 Types of Processor Mode ............................................................................................45
Chapter 9. Bus..................................................................... 46
Chapter 10. Interrupt........................................................... 47
10.1 Interrupt Overview......................................................................................................47
10.1.1 Type of Interrupts................................................................................................................................47
10.1.2 Software Interrupts .............................................................................................................................48
10.1.3 Hardware Interrupts............................................................................................................................49
10.1.4 Interrupts and Interrupt Vector.......................................................................................................... 50
10.1.5 Interrupt Control .................................................................................................................................52
______
10.2 INT Interrupt ................................................................................................................60
10.2.1 INT0 Interrupt ......................................................................................................................................60
10.2.2 INT0 Input Filter...................................................................................................................................61
10.2.3 INT1 Interrupt and INT2 Interrupt ......................................................................................................62
10.2.4 INT3 Interrupt ......................................................................................................................................63
________
_______
______ ______
______
10.3 Key Input Interrupt ..................................................................................................... 65
10.4 Address Match Interrupt ............................................................................................66
Chapter 11. Watchdog Timer.............................................. 68
Chapter 12. Timers.............................................................. 70
12.1 Timer X ........................................................................................................................ 71
12.1.1 Timer Mode ..........................................................................................................................................73
A-2
12.1.2 Pulse Output Mode .............................................................................................................................74
12.1.3 Event Counter Mode ...........................................................................................................................75
12.1.4 Pulse Width Measurement Mode....................................................................................................... 76
12.1.5 Pulse Period Measurement Mode.....................................................................................................78
12.2 Timer Y.........................................................................................................................80
12.2.1 Timer Mode.......................................................................................................................................... 83
12.2.2 Programmable Waveform Generation Mode ....................................................................................85
12.3 Timer Z.........................................................................................................................88
12.3.1 Timer Mode.......................................................................................................................................... 91
12.3.2 Programmable Waveform Generation Mode ....................................................................................93
12.3.3 Programmable One-shot Generation Mode......................................................................................95
12.3.4 Programmable Wait One-shot Generation Mode .............................................................................98
12.4 Timer C ...................................................................................................................... 101
12.4.1 Input Capture Mode .........................................................................................................................105
12.4.2 Output Compare Mode ....................................................................................................................107
Chapter 13. Serial Interface.............................................. 109
13.1 Clock Synchronous Serial I/O Mode....................................................................... 114
13.1.1 Polarity Select Function ................................................................................................................... 117
13.1.2 LSB First/MSB First Select Function ..............................................................................................117
13.1.3 Continuous Receive Mode ............................................................................................................... 118
13.2 Clock Asynchronous Serial I/O (UART) Mode ....................................................... 119
13.2.1 TxD10/RxD1 Select Function (UART1)............................................................................................ 122
13.2.2 TxD11 Select Function (UART1) ......................................................................................................122
13.2.3 Bit Rate ..............................................................................................................................................123
Chapter 14. A/D Converter................................................ 124
14.1 One-shot Mode ......................................................................................................... 128
14.2 Repeat Mode ............................................................................................................. 130
14.3 Sample and Hold ......................................................................................................132
14.4 A/D conversion cycles ........................................................................................... 132
14.5 Internal Equivalent Circuit of Analog Input...........................................................133
14.6 Inflow Current Bypass Circuit ................................................................................134
14.7 Output Impedance of Sensor under A/D Conversion...........................................135
Chapter 15. Programmable I/O Ports .............................. 137
15.1 Description................................................................................................................137
15.1.1 Port Pi Direction Register (PDi Register, i=0,1,3,4)........................................................................137
15.1.2 Port Pi Register (Pi Register, i=0 to 4).............................................................................................137
15.1.3 Pull-up Control Register 0, Pull-up Control Register 1 (PUR0 and PUR1 Registers)................. 137
15.1.4 Port P1 Drive Capacity Control Register (DRR Register)..............................................................137
15.2 Port setting................................................................................................................145
15.3 Unassigned Pin Handling ........................................................................................151
Chapter 16. Electrical Characteristics............................. 152
Chapter 17. Flash Memory Version ................................. 164
A-3
17.1 Overview....................................................................................................................164
17.2 Memory Map..............................................................................................................165
17.3 Functions To Prevent Flash Memory from Rewriting............................................166
17.3.1 ID Code Check Function ..................................................................................................................166
17.4 CPU Rewrite Mode....................................................................................................167
17.4.1 EW0 Mode..........................................................................................................................................168
17.4.2 EW1 Mode..........................................................................................................................................168
17.4.3 Software Commands ........................................................................................................................174
17.4.4 Status Register..................................................................................................................................178
17.4.5 Full Status Check..............................................................................................................................179
17.5 Standard Serial I/O Mode .........................................................................................181
17.5.1 ID Code Check Function ..................................................................................................................181
Chapter 18. On-chip Debugger ........................................ 185
18.1 Address Match Interrupt ..........................................................................................185
18.2 Single Step Interrupt ................................................................................................185
18.3 UART1........................................................................................................................185
18.4 BRK Instruction ........................................................................................................188
Chapter 19. Usage Notes.................................................. 186
19.1 Stop Mode and Wait Mode.......................................................................................186
19.1.1 Stop Mode..........................................................................................................................................186
19.1.2 Wait Mode ..........................................................................................................................................186
19.2 Interrupts...................................................................................................................187
19.2.1 Reading Address 0000016 ............................................................................................................................................ 187
19.2.2 SP Setting ..........................................................................................................................................187
19.2.3 External Interrupt and Key Input Interrupt .....................................................................................187
19.2.4 Watchdog Timer Interrupt ................................................................................................................187
19.2.5 Changing Interrupt Factor................................................................................................................188
19.2.6 Changing Interrupt Control Register ..............................................................................................189
19.3 Clock Generation Circuit ......................................................................................... 190
19.3.1 Oscillation Stop Detection Function ...............................................................................................190
19.3.2 Oscillation Circuit Constants...........................................................................................................190
19.4 Timers........................................................................................................................191
19.3.1 Timers X, Y and Z..............................................................................................................................191
19.3.2 Timer X.................................................................................................................................................19
19.3.3 Timer Y ...............................................................................................................................................191
19.3.4 Timer Z ...............................................................................................................................................191
19.3.5 Timer C...............................................................................................................................................191
19.5 Serial Interface..........................................................................................................192
19.6 A/D Converter............................................................................................................193
19.7 Flash Memory Version .............................................................................................194
19.7.1 CPU Rewrite Mode ............................................................................................................................194
19.8 Noise..........................................................................................................................197
Chapter 20. Usage Notes for On-chip Debugger............ 198
A-4
Appendix 1 Package Dimensions.................................... 199
Appendix 2 Connecting Examples for Serial Writer and
On-chip Debugging Emulator .......................................... 200
Appendix 3 Example of Oscillation Evaluation Circuit.. 202
Register Index ................................................................... 203
A-5
SFR Page Reference
A d d r e s s R
0 0 0 01
6
0 0 0 11
6
0 0 0 21
6
0 0 0 31
6
M
P r o c e s s o r m o d e r e g i s t e r 0P
0 0 0 41
6
M
0 0 0 51
6
P r o c e s s o r m o d e r e g i s t e r 1P
M
0 0 0 61
6
S y s t e m c l o c k c o n t r o l r e g i s t e r 0C
M
0 0 0 71
6
S y s t e m c l o c k c o n t r o l r e g i s t e r 1C
H R
0 0 0 81
6
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 0
0 0 0 91
6
A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e rA I E R6 7
R C
0 0 0 A1
6
P r o t e c t r e g i s t e rP
R
0 0 0 B1
6
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 1 H
C
0 0 0 C1
6
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO
D T
0 0 0 D1
6
W a t c h d o g t i m e r r e s e t r e g i s t e rW
D T
0 0 0 E1
6
W a t c h d o g t i m e r s t a r t r e g i s t e rW
D
0 0 0 F1
6
W a t c h d o g t i m e r c o n t r o l r e g i s t e rW
M A D
0 0 1 01
6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0R
0 0 1 11
6
0 0 1 21
6
0 0 1 31
6
M A D
0 0 1 41
6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R
0 0 1 51
6
0 0 1 61
6
0 0 1 71
6
0 0 1 81
6
C R
0 0 1 91
6
V o l t a g e d e t e c t i o n r e g i s t e r 1V
C R
0 0 1 A1
6
V o l t a g e d e t e c t i o n r e g i s t e r 2V
0 0 1 B1
6
0 0 1 C1
6
0 0 1 D1
6
N T 0
0 0 1 E1
6
I N T 0 i n p u t f i l t e r s e l e c t r e g i s t e rI
4 I N
0 0 1 F1
6
V o l t a g e d e t e c t i o n i n t e r r u p t r e g i s t e rD
0 0 2 01
6
0 0 2 11
6
0 0 2 21
6
0 0 2 31
6
0 0 2 41
6
0 0 2 51
6
0 0 2 61
6
0 0 2 71
6
0 0 2 81
6
0 0 2 91
6
0 0 2 A1
6
0 0 2 B1
6
0 0 2 C1
6
0 0 2 D1
6
0 0 2 E1
6
0 0 2 F1
6
0 0 3 01
6
0 0 3 11
6
0 0 3 21
6
0 0 3 31
6
0 0 3 41
6
0 0 3 51
6
0 0 3 61
6
0 0 3 71
6
0 0 3 81
6
0 0 3 91
6
0 0 3 A1
6
0 0 3 B1
6
0 0 3 C1
6
0 0 3 D1
6
0 0 3 E1
6
0 0 3 F1
6
e g i s t e
rS
y m b o l
P a g e
04 5
14 5
03 1
13 1
0 3 3
R4 4
1 3 3
D3 2
R6 9
S6 9
C6 9
06 7
16 7
12 2
22 2
F6 0
T2 3
Blank columns are all reserved space. No use is allowed.
A d d r e s s R
0 0 4 01
6
0 0 4 11
6
0 0 4 21
6
0 0 4 31
6
0 0 4 41
6
0 0 4 51
6
0 0 4 61
6
0 0 4 71
6
0 0 4 81
6
0 0 4 91
6
0 0 4 A1
6
0 0 4 B1
6
0 0 4 C1
6
U P I
0 0 4 D1
6
K e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e rK
0 0 4 E1
6
A D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e rA D I C5 3
0 0 4 F1
6
M P 1 I
0 0 5 01
6
C o m p a r e 1 i n t e r r u p t c o n t r o l r e g i s t e r C
0 T I
0 0 5 11
6
U A R T 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S
0 R I
0 0 5 21
6
U A R T 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S
1 T I
0 0 5 31
6
U A R T 1 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S
1 R I
0 0 5 41
6
U A R T 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S
N T 2 I
0 0 5 51
6
I N T 2 i n t e r r u p t c o n t r o l r e g i s t e rI
X I
0 0 5 61
6
T i m e r X i n t e r r u p t c o n t r o l r e g i s t e rT
Y I
0 0 5 71
6
T i m e r Y i n t e r r u p t c o n t r o l r e g i s t e rT
Z I
0 0 5 81
6
T i m e r Z i n t e r r u p t c o n t r o l r e g i s t e rT
N T 1 I
0 0 5 91
6
I N T 1 i n t e r r u p t c o n t r o l r e g i s t e rI
N T 3 I
0 0 5 A1
6
I N T 3 i n t e r r u p t c o n t r o l r e g i s t e rI
C I
0 0 5 B1
6
T i m e r C i n t e r r u p t c o n t r o l r e g i s t e rT
M P 0 I
0 0 5 C1
6
C o m p a r e 0 i n t e r r u p t c o n t r o l r e g i s t e r C
N T 0 I
0 0 5 D1
6
I N T 0 i n t e r r u p t c o n t r o l r e g i s t e rI
0 0 5 E1
6
0 0 5 F1
6
0 0 6 01
6
0 0 6 11
6
0 0 6 21
6
0 0 6 31
6
0 0 6 41
6
0 0 6 51
6
0 0 6 61
6
0 0 6 71
6
0 0 6 81
6
0 0 6 91
6
0 0 6 A1
6
0 0 6 B1
6
0 0 6 C1
6
0 0 6 D1
6
0 0 6 E1
6
0 0 6 F1
6
0 0 7 01
6
0 0 7 11
6
0 0 7 21
6
0 0 7 31
6
0 0 7 41
6
0 0 7 51
6
0 0 7 61
6
0 0 7 71
6
0 0 7 81
6
0 0 7 91
6
0 0 7 A1
6
0 0 7 B1
6
0 0 7 C1
6
0 0 7 D1
6
0 0 7 E1
6
0 0 7 F1
6
e g i s t e
rS
y m b o l
P a g e
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
B-1
SFR Page Reference
A d d r e s s R
Y Z M
0 0 8 01
6
T i m e r Y , Z m o d e r e g i s t e rT
R E
Pr e s c a l e r YP
0 0 8 11
6
Y S
T i m e r Y s e c o n d a r yT
0 0 8 21
6
Y P
T i m e r Y p r i m a r yT
0 0 8 31
6
U
T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r P
0 0 8 41
6
R E
Pr e s c a l e r ZP
0 0 8 51
6
Z S
T i m e r Z s e c o n d a r yT
0 0 8 61
6
Z P
T i m e r Z p r i m a r yT
0 0 8 71
6
0 0 8 81
6
0 0 8 91
6
Y Z O
T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e rT
0 0 8 A1
6
X M
T i m e r X m o d e r e g i s t e rT
0 0 8 B1
6
R E
Pr e s c a l e r XP
0 0 8 C1
6
T i m e r X r e g i s t e rT
0 0 8 D1
6
C S S
T i m e r c o u n t s o u r c e s e t t i n g r e g i s t e rT
0 0 8 E1
6
0 0 8 F1
6
0
0 0 9 01
6
T i m e r C r e g i s t e rT
0 0 9 11
6
0 0 9 21
6
0 0 9 31
6
0 0 9 41
6
0 0 9 51
6
N T E
E x t e r n a l i n p u t e n a b l e r e g i s t e rI
0 0 9 61
6
0 0 9 71
6
I E
K e y i n p u t e n a b l e r e g i s t e rK
0 0 9 81
6
0 0 9 91
6
C C
T i m e r C c o n t r o l r e g i s t e r 0T
0 0 9 A1
6
C C
T i m e r C c o n t r o l r e g i s t e r 1T
0 0 9 B1
6
M
0 0 9 C1
6
C a p t u r e a n d c o m p a r e 0 r e g i s t e rT
0 0 9 D1
6
M
0 0 9 E1
6
C o m p a r e 1 r e g i s t e rT
0 0 9 F1
6
0 M
0 0 A 01
6
U A R T 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r U
0 B R
0 0 A 11
6
U A R T 0 b i t r a t e r e g i s t e rU
0 T
0 0 A 21
6
U A R T 0 t r a n s m i t b u f f e r r e g i s t e rU
0 0 A 31
6
0 C
0 0 A 41
6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 U
0 C
0 0 A 51
6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 U
0 R
0 0 A 61
6
U A R T 0 r e c e i v e b u f f e r r e g i s t e r U
0 0 A 71
6
1 M
0 0 A 81
6
U A R T 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r U
1 B R
0 0 A 91
6
U A R T 1 b i t r a t e r e g i s t e rU
1 T
0 0 A A1
6
U A R T 1 t r a n s m i t b u f f e r r e g i s t e rU
0 0 A B1
6
1 C
0 0 A C1
6
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 U
1 C
0 0 A D1
6
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 U
1 R
0 0 A E1
6
U A R T 1 r e c e i v e b u f f e r r e g i s t e r U
0 0 A F1
6
r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r
C O
0 0 B 01
6
U A R T t
0 0 B 11
6
0 0 B 21
6
0 0 B 31
6
0 0 B 41
6
0 0 B 51
6
0 0 B 61
6
0 0 B 71
6
0 0 B 81
6
0 0 B 91
6
0 0 B A1
6
0 0 B B1
6
0 0 B C1
6
0 0 B D1
6
0 0 B E1
6
0 0 B F1
6
e g i s t e
rS
y m b o l
2 U
P a g e
R8 0 / 8 8
Y8 1
C8 1
R8 1
M8 2 / 9 0
Z8 9
C8 9
R8 9
C8 1 / 8 9
R7 1
X7 2
X7 2
7 2 / 8 2 / 9 0
C1
3
N6 0
N6 5
01 0 3
11 0 4
01 0 3
11 0 3
R1 1 2
G1 1 1
B1 1 1
01 1 2
11 1 3
B1 1 1
R1 1 2
G1 1 1
B1 1 1
01 1 2
11 1 3
B1 1 1
N1 1 3
Blank columns are all reserved space. No use is allowed.
A d d r e s s
0 0 C 0
0 0 C 1
0 0 C 2
0 0 C 3
0 0 C 4
0 0 C 5
0 0 C 6
0 0 C 7
0 0 C 8
0 0 C 9
0 0 C A
0 0 C B
0 0 C C
0 0 C D
0 0 C E
0 0 C F
0 0 D 0
0 0 D 1
0 0 D 2
0 0 D 3
0 0 D 4
0 0 D 5
0 0 D 6
0 0 D 7
0 0 D 8
0 0 D 9
0 0 D A
0 0 D B
0 0 D C
0 0 D D
0 0 D E
0 0 D F
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
00E9
00EA
00EB
00EC
00ED
00EE
00EF
00F0
00F1
00F2
00F3
00F4
00F5
00F6
00F7
00F8
00F9
03FA
00FB
00FC
00FD
00FE
00FF
01B3
01B4
01B5
01B6
01B7
1 6
A D r e g i s t e rA
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
D C O N 21 2
A D c o n t r o l r e g i s t e r 2A
1 6
1 6
AD control register 0 ADCON0 126
1 6
D C O N 11 2
A D c o n t r o l r e g i s t e r 1 A
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
Port P0 register P0 143
16
16
P o r t P 1 r e g i s t e rP
16
Port P0 direction register PD0 143
16
Port P1 direction register PD1 143
16
16
Port P3 register P3 143
16
D
P o r t P 3 d i r e c t i o n r e g i s t e rP
16
P o r t P 4 r e g i s t e rP
16
16
16
Port P4 direction register PD4 143
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
U R
16
P u l l - u p c o n t r o l r e g i s t e r 0 P
16
Pull-up control register 1 PUR1 144
P o r t P 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r D R R1 4 4
16
C O U
16
T i m e r C o u t p u t c o n t r o l r e g i s t e r T
M R
16
F l a s h m e m o r y c o n t r o l r e g i s t e r 4 F
16
M R
16
F l a s h m e m o r y c o n t r o l r e g i s t e r 1 F
16
M R
16
F l a s h m e m o r y c o n t r o l r e g i s t e r 0 F
Register Symbol
P a g e
D1 2 7
7
6
11 4 3
31 4 3
41 4 3
01 4 4
T1 0 6
41 7 1
11 7 1
01 7 0
B-2
R8C/11 Group
REJ09B0062-0120
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU
core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing
instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial
equipment, audio, etc.
Rev.1.20
Jan 27, 2006
Rev.1.20 Jan 27, 2006 page 1 of 204
REJ09B0062-0120
R8C/11 Group
1.2 Performance Overview
Table 1.1. lists the performance outline of this MCU.
Table 1.1 Performance outline
Item Performance
CPU Number of basic instructions 89 instructions
Minimum instruction execution time
Operating mode Single-chip
Address space 1M bytes
Memory capacity See Table 1.2.
Peripheral Port Input/Output: 22 (including LED drive port), Input: 2
function LED drive port I/O port: 8
Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Serial Interface •1 channel
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt Internal: 11 factors, External: 5 factors,
Clock generation circuit 2 circuits
Oscillation stop detection function
Voltage detection circuit Included
Power on reset circuit Included
Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ)
characteristics
Power consumption Typ. 9 mA (VCC = 5.0 V, (f(XIN) = 20 MHZ)
Flash memory Program/erase supply voltage
Program/erase endurance 100 times
Operating ambient temperature -20 to 85 °C
Package 32-pin plastic mold LQFP
50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)
Timer Z: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel
(Circuits of input capture and output compare)
Clock synchronous, UART
•1 channel
UART
Software: 4 factors, Priority level: 7 levels
•Main clock generation circuit (Equipped with a built-in
feedback resistor)
•On-chip oscillator (high speed, low speed)
On High-speed on-chip oscillator the frequency adjustment function is usable.
Main clock oscillation stop detection function
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ)
Typ. 5 mA (VCC = 3.0 V, (f(XIN) = 10 MHZ)
Typ. 35 µA (VCC = 3.0 V, Wait mode, Peripheral clock off)
Typ. 0.7 µA (VCC = 3.0 V, Stop mode)
VCC = 2.7 to 5.5 V
-40 to 85 °C (D-version)
1. Overview
Rev.1.20 Jan 27, 2006 page 2 of 204
REJ09B0062-0120
R8C/11 Group
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
1. Overview
I / O p o r t
P o r t P 0
Pe r i p h e r a l f u n c t i o n s
T i m e r
T i m e r X ( 8 b i t s )
T i m e r Y ( 8 b i t s )
T i m e r Z ( 8 b i t s )
T i m e r C ( 1 6 b i t s )
W a t c h d o g t i m e r
( 1 5 b i t s )
ROM
RAM
1 2
Port P4
(1)
(2)
8
8
Port P1
A / D c o n v e r t e r
( 1 0 b i t s ✕ 1 2 c h a n n e l s )
U A R T o r C l o c k s y n c h r o n o u s
s e r i a l I / O
( 8 b i t s ✕ 1 c h a n n e l )
U A R T
( 8 b i t s ✕ 1 c h a n n e l )
R 8 C / T i n y S e r i e s C P U c o r e
R 0 LR 0 H
R1H R1L
R 2
R 3
A 0
A1
FB
5
P o r t P 3
System clock generator
X
H i g h - s p e e d o n - c h i p o s c i l l a t o r
L o w - s p e e d o n - c h i p o s c i l l a t o r
SB
USP
I S P
INTB
P C
FLG
I N
- X
O U T
M e m o r y
M u l t i p l i e r
Figure 1.1 Block Diagram
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Rev.1.20 Jan 27, 2006 page 3 of 204
REJ09B0062-0120
R8C/11 Group
1.4 Product Information
Table 1.2 lists the product information.
1. Overview
Table 1.2 Product Information
Type No.
R5F21112FP
R5F21113FP
R5F21114FP
R5F21112DFP
R5F21113DFP
R5F21114DFP
ROM capacity
12K bytes
16K bytes
12K bytes
16K bytes
Type No. R 5 F 21 11 4 D FP
8K bytes
8K bytes
As of January 2006
RAM capacity
512 bytes
768 bytes
1K bytes
512 bytes
768 bytes
1K bytes
Package type:
FP : PLQP0032GB-A
Classification:
D: Operating ambient temperature –40 °C to 85 °C
No symbol: Operating ambient temperature –20 °C to 85 °C
Package type
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
Flash memory version
D version
Remarks
ROM capacity:
2 : 8 KBytes.
3 : 12 KBytes.
4 : 16 KBytes.
R8C/11 group
R8C/Tiny series
Memory type:
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.1.20 Jan 27, 2006 page 4 of 204
REJ09B0062-0120
R8C/11 Group
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
A
2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7
P 06/ A N
P05/AN
P 04/ A N
MODE
P03/AN
P02/AN
P01/AN
P 00/ A N7/T x D
2 5
1
2 6
2
2 7
3
2 8
2 9
4
3 0
5
3 1
6
1 1
3 2
1 2 3 4 5 6 7 8
0
1
/
0
R
0
N
/
/
C
0
7
C
3
0
V
C N T
P
C M P
I
P
R8C/11 Group
1. Overview
2
1
1
/
1
1
R
N
I
/
T
O
Z
S
/
S
1
V
3
C M P
T
A
P
U
C
F
T
/
/
3
2
R
T
T
V
/
C
/
/
C
3
2
3
3
V
C N T
I N
I N
C M P
P
P
E
A
P45/INT
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
0
P10/KI0/AN8/CMP0
P11/KI1/AN9/CMP0
P12/KI2/AN10/CMP0
P13/KI3/AN
P14/TxD
P15/RxD
P16/CLK
11
0
0
0
0
1
2
1
D
/
0
1
D
N
/
7
3
P
R x
T x
N O T E S :
1 . P 4
7
f u n c t i o n s o n l y a s a n i n p u t p o r t .
2. W h e n u s i n g O n - c h i p d e b u g g e r , d o n o t u s e p i n s P 0
a n d P 37/ T x D
3 . D o n o t c o n n e c t I V c c t o V c c .
Figure 1.3 Pin Assignments (Top View)
)
6
S
S
V
C
S
T
(
1
S
7
V
4
/
T
R
E S E
O
X
U
P
1 0
/ R x D1.
0
C
4
C
R
V
/
N
I
X
P
/
1
T
/
7
1
P
I N
C N T
0
/ A N7/ T x D
1 1
Package: PLQP0032GB-A (32P6U-A)
Rev.1.20 Jan 27, 2006 page 5 of 204
REJ09B0062-0120
R8C/11 Group
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
Signal name Pin name I/O type
Power supply Vcc, I
input Vss
IVcc IVcc O
Analog power AVcc, AVss I
supply input
Reset input
___________
RESET I
CNVss CNVss I
MODE MODE I
Main clock input XIN I
Main clock output XOUT O
_____
INT interrupt input
Key input interrupt
Timer X CNTR0 I/O
_______ _______
INT0 to INT3 I
_____ _____
KI0 to KI3 I
____________
CNTR0 O
Timer Y CNTR1 I/O
Timer Z TZOUT O
Timer C TCIN I
CMP00 to CMP02,
O
CMP10 to CMP12
Serial interface CLK0 I/O
RxD0, RxD1 I
TxD0, TxD10,O
TxD11
Reference voltage VREF I
input
A/D converter AN0 to AN11 I
I/O port P00 to P07, I/O
P10 to P17,
P30 to P33, P37,
P45
Input port P46, P47 I
NOTES :
1. Refer to "19.8 Noise" for the connecting reference resistor value.
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
This pin is to stabilize internal power supply.
Connect this pin to Vss via a capacitor (0.1 µF).
Do not connect to Vcc.
Power supply input pins for A/D converter. Connect the
AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a
capacitor between pins AVcc and AVss.
Input “L” on this pin resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generating circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use
an externally derived clock, input it to the XIN pin and
leave the XOUT pin open.
______
INT interrupt input pins.
Key input interrupt pins.
Timer X I/O pin
Timer X output pin
Timer Y I/O pin
Timer Z output pin
Timer C input pin
Timer C output pins
Transfer clock I/O pin.
Serial data input pins.
Serial data output pins.
Reference voltage input pin for A/D converter. Connect the VREF pin to Vcc.
Analog input pins for A/D converter
These are 8-bit CMOS I/O ports. Each port has an I/O
select direction register, allowing each pin in that port
to be directed for input or output individually.
Any port set to input can select whether to use a pullup resistor or not by program.
P10 to P17 also function as LED drive ports.
Port for input-only
1. Overview
Function
(1)
Rev.1.20 Jan 27, 2006 page 6 of 204
REJ09B0062-0120
R8C/11 Group 2. Central Processing Unit (CPU)
g
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
b 3 1
R 2
R 3
b 1 9
I N T B H
T h e 4 - h i g h o r d e r b i t s o f I N T B a r e I N T B H a n d
t h e 1 6 - l o w b i t s o f I N T B a r e I N T B L .
b19
b 1 5 b 0 b7 b 8
I P L
i s t e r b a n k c o m p r i s e s t h e s e r e g i s t e r s . T w o s e t s o f r e g i s t e r b a n k s a r e p r o v i d e
N O T E S :
A r e
1 .
b 1 5 b
R0H (high-order of R0)
R1H (high-order of R1)
8
b7 b 0
R0L (low-order of R0)
R1L (low-order of R1)
R2
D a t a r e g i s t e r s
( 1 )
R3
A0
A1
F B
b 1 5 b
I N T B L
PC
b 1 5 b
U S P
ISP
SB
b15 b0
F L G
A d d r e s s r e g i s t e r s
F r a m e b a s e r e g i s t e r s
0
I n t e r r u p t t a b l e r e g i s t e r
b 0
P r o g r a m c o u n t e r
0
U s e r s t a c k p o i n t e r
Interrupt stack pointer
Static base register
Flag register
( 1 )
( 1 )
CDZSBOIU
Carry flag
D e b u g f l a g
Z e r o f l a g
Sign flag
Register bank select flag
O v e r f l o w f l a g
I n t e r r u p t e n a b l e f l a g
S t a c k p o i n t e r s e l e c t f l a g
R e s e r v e d b i t
Processor interrupt priority level
Reserved bit
d
Figure 2.1 CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0
can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit
data register (R2R0). The same applies to R3R1 as R2R0.
Rev.1.20 Jan 27, 2006 page 7 of 204
REJ09B0062-0120
R8C/11 Group 2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be
combined with A0 to be used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to “0”.
2.8.3 Zero Flag (Z)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4 Sign Flag (S)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is
set to “1”.
2.8.6 Overflow Flag (O)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The
I flag is set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
When write to this bit, set to “0”. When read, its content is indeterminate.
Rev.1.20 Jan 27, 2006 page 8 of 204
REJ09B0062-0120
R8C/11 Group 3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses
0000016 to FFFFF16.
The internal ROM is allocated lower addresses beginning with address 0FFFF16. For example, a 16-Kbyte
internal ROM is allocated addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte
internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing
data, but for calling subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function
control registers are located them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users.
00000
002FF
00400
0YYYY
0FFFF
16
16
16
16
16
(See Chapter 4 for details.)
SFR
Internal ROM
Figure 3.1 Memory Map
Rev.1.20 Jan 27, 2006 page 9 of 204
REJ09B0062-0120
R8C/11 Group 4. Special Function Register (SFR)
(
)
(4)
(3)
(
)
(2)
(4)
(3)
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR
information
Table 4.1 SFR Information(1)
Address
0 0 0 0
1 6
0 0 0 1
1 6
0 0 0 2
1 6
0 0 0 3
1 6
M
P r o c e s s o r m o d e r e g i s t e r 0P
0 0 0 4
1 6
M
0 0 0 5
1 6
P r o c e s s o r m o d e r e g i s t e r 1P
M
1 1 0 1 0 0
0 0 0 6
1 6
S y s t e m c l o c k c o n t r o l r e g i s t e r 0C
M
0 1 0 0 0 0
0 0 0 7
1 6
S y s t e m c l o c k c o n t r o l r e g i s t e r 1C
R
0 0 0 8
1 6
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 0H
I E
X X X X X 0
0 0 0 9
1 6
A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e rA
R C
0 X X X 0 0
0 0 0 A
1 6
P r o t e c t r e g i s t e rP
R
0 0 0 B
1 6
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 1H
C
0 0 0 0 1 0
0 0 0 C
1 6
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO
D T
0 0 0 D
1 6
W a t c h d o g t i m e r r e s e t r e g i s t e rW
0 0 0 E
1 6
Watchdog timer start register WDTS XX
D
0 0 1 1 1 1
0 0 0 F
1 6
W a t c h d o g t i m e r c o n t r o l r e g i s t e rW
0 0 1 0
1 6
Address match interrupt register 0 RMAD0 00
0 0 1 1
1 6
0 0 1 2
1 6
0 0 1 3
1 6
M A D
0 0 1 4
1 6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R
0 0 1 5
1 6
0 0 1 6
1 6
0 0 1 7
1 6
0 0 1 8
1 6
0 0 1 9
1 6
Voltage detection register 1 VCR1 00001000
C R
0 0 1 A
1 6
V o l t a g e d e t e c t i o n r e g i s t e r 2V
0 0 1 B
1 6
0 0 1 C
1 6
0 0 1 D
1 6
0 0 1 E
1 6
INT0 input filter select register INT0F XXXXX000
0 0 1 F
1 6
Voltage detection interrupt register D4INT 00
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
X : U n d e f i n e d
N O T E S :
1 . B l a n k s p a c e s a r e r e s e r v e d . N o a c c e s s i s a l l o w e d .
2 . S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r .
3 . O w i n g t o R e s e t i n p u t .
4 . I n t h e c a s e o f
R E S E T
p i n = H r e t a i n i n g .
(1)
R e g i s t e r Symbol After reset
00
10
00
10
00
RX
R0
14
D0
RX
C0
10
2
2
20
0
1 6
0
1 6
0
1 6
0
1 6
X
1 6
16
16
00
16
X0
16
0
1 6
0 0
1 6
X 0
1 6
0
1 6
1 0 0 0 0 0 0 0
16
01000001
0
2
0
2
0
2
0
2
0
2
1
2
2
2
2
2
Rev.1.20 Jan 27, 2006 page 10 of 204
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R8C/11 Group 4. Special Function Register (SFR)
Table 4.2 SFR Information(2)
A d d r e s s
0 0 4 0
1 6
0 0 4 1
1 6
0 0 4 2
1 6
0 0 4 3
1 6
0 0 4 4
1 6
0 0 4 5
1 6
0 0 4 6
1 6
0 0 4 7
1 6
0 0 4 8
1 6
0 0 4 9
1 6
0 0 4 A
1 6
0 0 4 B
1 6
0 0 4 C
1 6
U P I
X X X X 0 0
0 0 4 D
1 6
K e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e rK
D I
X X X X 0 0
0 0 4 E
1 6
A D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e rA
0 0 4 F
1 6
X X X X 0 0
0 0 5 0
1 6
C o m p a r e 1 i n t e r r u p t c o n t r o l r e g i s t e r
X X X X 0 0
0 0 5 1
1 6
U A R T 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r
X X X X 0 0
0 0 5 2
1 6
U A R T 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r
0 0 5 3
1 6
UART1 transmit interrupt control register
X X X X 0 0
0 0 5 4
1 6
U A R T 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r
0 0 5 5
1 6
INT2 interrupt contro l register INT2IC XXXXX000
0 0 5 6
1 6
Timer X interrupt control register TXIC XXXXX000
0 0 5 7
1 6
Timer Y interrupt control register TYIC XXXXX000
Z I
X X X X 0 0
0 0 5 8
1 6
T i m e r Z i n t e r r u p t c o n t r o l r e g i s t e rT
0 0 5 9
1 6
INT1 interrupt contro l register INT1IC XXXXX000
0 0 5 A
1 6
INT3 interrupt contro l register INT3IC XXXXX000
C I
X X X X 0 0
0 0 5 B
1 6
T i m e r C i n t e r r u p t c o n t r o l r e g i s t e rT
X X X X 0 0
0 0 5 C
1 6
C o m p a r e 0 i n t e r r u p t c o n t r o l r e g i s t e r
0 0 5 D
1 6
INT0 interrupt contro l register INT0IC XX00X000
0 0 5 E
1 6
0 0 5 F
1 6
0 0 6 0
1 6
0 0 6 1
1 6
0 0 6 2
1 6
0 0 6 3
1 6
0 0 6 4
1 6
0 0 6 5
1 6
0 0 6 6
1 6
0 0 6 7
1 6
0 0 6 8
1 6
0 0 6 9
1 6
0 0 6 A
1 6
0 0 6 B
1 6
0 0 6 C
1 6
0 0 6 D
1 6
0 0 6 E
1 6
0 0 6 F
1 6
0 0 7 0
1 6
0 0 7 1
1 6
0 0 7 2
1 6
0 0 7 3
1 6
0 0 7 4
1 6
0 0 7 5
1 6
0 0 7 6
1 6
0 0 7 7
1 6
0 0 7 8
1 6
0 0 7 9
1 6
0 0 7 A
1 6
0 0 7 B
1 6
0 0 7 C
1 6
0 0 7 D
1 6
0 0 7 E
1 6
0 0 7 F
1 6
X : U n d e f i n e d
N O T E S :
1 . B l a n k s p a c e s a r e r e s e r v e d . N o a c c e s s i s a l l o w e d .
(1)
R e g i s t e r Symbol A f t e r r e s e t
CX
CX
C M P 1 I CX
S 0 T I CX
S 0 R I CX
0
0
0
0
0
S1TIC XXXXX000
S 1 R I CX
CX
CX
C M P 0 I CX
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev.1.20 Jan 27, 2006 page 11 of 204
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R8C/11 Group 4. Special Function Register (SFR)
(2)
Table 4.3 SFR Information(3)
A d d r e s s
X : U n d e f i n e d
N O T E S :
1 . B l a n k s p a c e s a r e r e s e r v e d . N o a c c e s s i s a l l o w e d .
2 . W h e n o u t p u t c o m p a r e m o d e ( t h e T C C 1 3 b i t i n t h e T C C 1 r e g i s t e r = 1 ) i s s e l e c t e d , t h e v a l u e a f t e r r e s e t i s s e t t o “ F F F F
Y Z M
0 0 8 0
1 6
T i m e r Y , Z m o d e r e g i s t e rT
R E
0 0 8 1
1 6
P r e s c a l e r Y r e g i s t e rP
Y S
T i m e r Y s e c o n d a r y r e g i s t e rT
0 0 8 2
1 6
Y P
T i m e r Y p r i m a r y r e g i s t e rT
0 0 8 3
1 6
U
T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e rP
0 0 8 4
1 6
R E
P r e s c a l e r Z r e g i s t e rP
0 0 8 5
1 6
Z S
T i m e r Z s e c o n d a r y r e g i s t e rT
0 0 8 6
1 6
Z P
T i m e r Z p r i m a r y r e g i s t e rT
0 0 8 7
1 6
0 0 8 8
1 6
0 0 8 9
1 6
Y Z O
T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e rT
0 0 8 A
1 6
X M
T i m e r X m o d e r e g i s t e rT
0 0 8 B
1 6
R E
P r e s c a l e r X r e g i s t e rP
0 0 8 C
1 6
T i m e r X r e g i s t e rT
0 0 8 D
1 6
C S
T i m e r c o u n t s o u r c e s e t r e g i s t e rT
0 0 8 E
1 6
0 0 8 F
1 6
0 0 9 0
1 6
T i m e r C r e g i s t e rT
0 0 9 1
1 6
0 0 9 2
1 6
0 0 9 3
1 6
0 0 9 4
1 6
0 0 9 5
1 6
N T E
0 0 9 6
1 6
E x t e r n a l i n p u t e n a b l e r e g i s t e rI
0 0 9 7
1 6
I E
K e y i n p u t e n a b l e r e g i s t e rK
0 0 9 8
1 6
0 0 9 9
1 6
Timer C contro l re gi st e r 0 TCC0 00
0 0 9 A
1 6
Timer C contro l re gi st e r 1 TCC1 00
0 0 9 B
1 6
M
0 0 9 C
1 6
C a p t u r e , c o m p a r e 0 r e g i s t e rT
0 0 9 D
1 6
0 0 9 E
1 6
Compare 1 reg ister TM1 FF
0 0 9 F
1 6
0 0 A 0
1 6
U A R T 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r
0 0 A 1
1 6
UART0 bit rate register U0BRG XX
0 0 A 2
1 6
UART0 transmit buffer register U0TB XX
0 0 A 3
1 6
0 0 A 4
1 6
UART0 transmit/receive control register 0
0 0 0 0 0 1
0 0 A 5
1 6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1
0 R
0 0 A 6
1 6
U A R T 0 r e c e i v e b u f f e r r e g i s t e r U
0 0 A 7
1 6
0 0 A 8
1 6
U A R T 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r
1 B R
0 0 A 9
1 6
U A R T 1 b i t r a t e r e g i s t e rU
1 T
0 0 A A
1 6
U A R T 1 t r a n s m i t b u f f e r r e g i s t e rU
0 0 A B
1 6
0 0 0 1 0 0
0 0 A C
1 6
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0
0 0 A D
1 6
UART1 transmit/receive control register 1
1 R
0 0 A E
1 6
U A R T 1 r e c e i v e b u f f e r r e g i s t e r U
0 0 A F
1 6
0 0 B 0
1 6
UART transmit/receive control register 2
0 0 B 1
1 6
0 0 B 2
1 6
0 0 B 3
1 6
0 0 B 4
1 6
0 0 B 5
1 6
0 0 B 6
1 6
0 0 B 7
1 6
0 0 B 8
1 6
0 0 B 9
1 6
0 0 B A
1 6
0 0 B B
1 6
0 0 B C
1 6
0 0 B D
1 6
0 0 B E
1 6
0 0 B F
1 6
(1)
R e g i s t e r Symbol A f t e r r e s e t
0 0
0 0
FF
XX
1 6
0
F
1 6
F
1 6
F
1 6
0
1 6
F
1 6
F
1 6
F
1 6
0
1 6
0
1 6
F
1 6
F
1 6
0
1 6
0
1 6
1 6
0
1 6
0
1 6
16
16
0
1 6
1 6
16
16
0
1 6
16
16
16
R0
YF
CF
RF
M0
ZF
CF
RF
C0
R0
XF
XF
S0
C0
N0
N0
00
U 0 M R0
U0C0 00001000
U 0 C 10
BX
U 1 M R0
GX
BX
X X
X X
X
1 6
1 6
0
1 6
X
1 6
X
1 6
1 6
U 1 C 00
U1C1 00000010
BX
UCON 00
X X
X
1 6
1 6
16
2
0
2
0
2
2
1 6
”.
Rev.1.20 Jan 27, 2006 page 12 of 204
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R8C/11 Group 4. Special Function Register (SFR)
A d d r e s s
0 0 C 01
0 0 C 11
0 0 C 21
0 0 C 31
0 0 C 41
0 0 C 51
0 0 C 61
0 0 C 71
0 0 C 81
0 0 C 91
0 0 C A1
0 0 C B1
0 0 C C1
0 0 C D1
0 0 C E1
0 0 C F1
0 0 D 01
0 0 D 11
0 0 D 21
0 0 D 31
0 0 D 41
0 0 D 51
0 0 D 61
0 0 D 71
0 0 D 81
0 0 D 91
0 0 D A1
0 0 D B1
0 0 D C1
0 0 D D1
0 0 D E1
0 0 D F1
0 0 E 01
0 0 E 11
0 0 E 21
0 0 E 31
0 0 E 41
0 0 E 51
0 0 E 61
0 0 E 71
0 0 E 81
0 0 E 91
0 0 E A1
0 0 E B1
0 0 E C1
0 0 E D1
0 0 E E1
0 0 E F1
0 0 F 01
0 0 F 11
0 0 F 21
0 0 F 31
0 0 F 41
0 0 F 51
0 0 F 61
0 0 F 71
0 0 F 81
0 0 F 91
0 3 F A1
0 0 F B1
0 0 F C1
0 0 F D1
0 0 F E1
0 0 F F1
6
A D r e g i s t e rA
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
D C O N
6
A D c o n t r o l r e g i s t e r 2A
6
D C O N
0 0 0 0 X X
6
A D c o n t r o l r e g i s t e r 0A
D C O N
6
A D c o n t r o l r e g i s t e r 1 A
6
6
6
6
6
6
6
6
6
Port P0 register P0 XX
6
P o r t P 1 r e g i s t e rP
6
Port P0 direction register PD0 00
D
6
P o r t P 1 d i r e c t i o n r e g i s t e rP
6
6
P o r t P 3 r e g i s t e rP
6
D
6
P o r t P 3 d i r e c t i o n r e g i s t e rP
6
P o r t P 4 r e g i s t e rP
6
D
6
P o r t P 4 d i r e c t i o n r e g i s t e rP
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
U R
0 X X 0 0 0
6
P u l l - u p c o n t r o l r e g i s t e r 0 P
U R
X X X X X 0
6
P u l l - u p c o n t r o l r e g i s t e r 1 P
R
6
P o r t P 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r D
C O U
6
T i m e r C o u t p u t c o n t r o l r e g i s t e r T
R e g i s t e r
Symbol After reset
DX
20
00
10
1X
10
3X
30
4X
40
00
1X
R0
T0
X X
X
1 6
1 6
0
1 6
X
0
2
1 6
16
X
1 6
16
0
1 6
X
1 6
0
1 6
X
1 6
0
1 6
0
2
X
0
1 6
0
1
2
0 1 B 31
6
0 1 B 41
6
M R
1 0 0 X X 0
0 1 B 51
6
F l a s h m e m o r y c o n t r o l r e g i s t e r 1 F
0 1 B 61
6
M R
0 0 0 0 0 0
0 1 B 71
6
F l a s h m e m o r y c o n t r o l r e g i s t e r 0 F
Rev.1.20 Jan 27, 2006 page 13 of 204
REJ09B0062-0120
10
00
1
X
2
2
R8C/11 Group
5. Reset
There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset.
5.1 Hardware Reset
There are three kinds of hardware reset: hardware reset 1, hardware reset 2, and power-on reset.
After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the
CPU.
5.1 Hardware Reset
5.1.1 Hardware Reset 1
____________ ____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while
the power supply voltage is within the recommended operating condition, the pins are initialized (see Table 5.1 “Pin Status When RESET Pin Level is 'L'”). When the input level at the
____________
____________
RESET pin is released from “L” to “H”, the CPU and SFR are initialized, and the program is
executed starting from the address indicated by the reset vector. Figure 5.1 shows the CPU
register status after reset and figure 5.2 shows the reset sequence. The internal RAM is not
____________
initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM
becomes indeterminate.
Figures 5.3 to 5.4 show the reset circuit example using the hardware reset 1. Refer to Chapter
4, “Special Function Register (SFR)” for the status of SFR after reset.
• When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin.
(2) Wait for 500 µs (1/fRING-S ✕ 20).
____________
(3) Apply an “H” signal to the RESET pin.
• Power on
____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condi-
tion.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Wait for 500 µs (1/fRING-S ✕ 20).
____________
(5) Apply an “H” signal to the RESET pin.
Table 5.1 Pin Status When RESET Pin Level is “L”
____________
Pin name
P0
P1
P3
0
to P33, P3
P45
to P47
Rev.1.20 Jan 27, 2006 page 14 of 204
REJ09B0062-0120
7
Input port
Input port
Input port
Input port
Status
R8C/11 Group
5.1 Hardware Reset
b15
0000
16
0000
16
0000
16
0000
16
0000
16
0000
16
0000
16
b19
00000
16
Content of addresses 0FFFE16 to 0FFFC
b15
16
0000
0000
16
0000
16
16
b0
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
b0
Interrupt table register(INTB)
Program counter(PC)
b0
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
b15
0000
b15
b7 b8
IPL
Figure 5.1 CPU Register Status After Reset
f
R I N G - S
I n t e r n a l o n - c h i p
o s c i l l a t i o n
C P U c l o c k
A d d r e s s
( I n t e r n a l a d d r e s s s i g n a l )
N O T E S :
1 . T h i s s h o w s h a r d w a r e r e s e t
M o r e t h a n 2 0 c y c l e s a r e n e e d e d
F l a s h m e m o r y a c t i v a t e d t i m e
( C P U c l o c k ✕ 6 4 c y c l e s )
( 1 )
16
C P U c l o c k ✕ 2 8 c y c l e s
b0
b0
CDZSBOIU
0FFFC16
Flag register(FLG)
0 F F F E1
6
1 6
0 F F F D
Content of reset vector
Figure 5.2 Reset Sequence
Rev.1.20 Jan 27, 2006 page 15 of 204
REJ09B0062-0120
R8C/11 Group
5.1 Hardware Reset
V
C C
2 . 7 V
0 V
V
R E S E T
C C
RESET
0 V
Figure 5.3 Example Reset Circuit Using The Hardware Reset 1
5V
2.7V
RESET
V
CC
Supply voltage
detection circuit
V
CC
0V
5V
Equal to or less
than 0.2V
CC
M o r e t h a n t d ( P - R ) + 5 0 0 µ s a r e
n e e d e d .
RESET
0V
More than td(P-R) + 500 µs
are needed.
Example when V
CC
= 5V
.
Figure 5.4 Example Reset Circuit Using The Hardware Reset 1 (Voltage Check Circuit)
Rev.1.20 Jan 27, 2006 page 16 of 204
REJ09B0062-0120
R8C/11 Group
5.1.2 Hardware Reset 2
This is the reset generated by the voltage detection circuit which is built-in to the microcomputer. The
voltage detection circuit monitors the input voltage at Vcc input pin. The microcomputer is reset when
the voltage at the VCC input pin drops below Vdet if all of the following conditions hold true.
• The VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled)
• The D40 bit in the D4INT register is set to “1” (voltage detection interrupt enabled)
• The D46 bit in the D4INT register is set to “1” (hardware reset 2 when going through Vdet)
When using a digital filter (D41 bit in the D4INT register is set to “1”), set the CM14 bit in the CM1
register to “0”(low-speed on-chip oscillator oscillates).
Conversely, when the input voltage at the VCC pin rises to Vdet or more, the pins, CPU, and SFR are
initialized and counting the low-speed on-chip oscillator starts. When counting the low-speed on-chip
oscillator clock 32 times, the internal reset is exited and the program is executed beginning with the
address indicated by the reset vector. The initialized pins and registers and the status thereof are the
same as in hardware reset 1. Refer to Section 5.4 “Voltage Detection Circuit.”
5.1 Hardware Reset
Rev.1.20 Jan 27, 2006 page 17 of 204
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R8C/11 Group
5.1.3 Power-on Reset Function
The power-on reset is the function which can reset the microcomputer without the external reset
circuit. The RESET pin should be connected to the VCC pin via about 5 kΩ pull-up resistance using the
power-on reset function, the function turns to active and the microcomputer has its pins, CPU and
SFR initialized. When a capacitor is connected to the RESET pin, always keep the voltage to the
____________
RESET pin 0.8 VCC or more.
When the input voltage at the VCC pin reaches to the Vdet level, count operation of the low-speed onchip oscillator clock starts. When the operation counts the low-speed on-chip oscillator clock for 32
times, the internal reset is released. Then the program is executed starting from the address indicated by the reset vector. The initialized pins and registers and the status thereof are the same as in
hardware reset 1 excluding the following bits.
• The D40 bit in the D4INT register turns to “1” automatically (voltage detection interrupt enabled)
• The D46 bit in the D4INT register turns to “1” automatically (hardware reset 2 when going through
Vdet)
Additionally, the hardware reset 2 turns to active after the power-on reset. This is because the VC27
bit in the VCR2 register is set to “1” (voltage detection circuit enabled) after the power-on reset same
as the hardware reset 1, so that hardware reset 2 active conditions are all satisfied including above
D40 and D46 bit conditions.
5.1 Hardware Reset
____________
____________
Figure 5.5 shows the power-on reset circuit. Figure 5.6 shows the power-on reset operation.
RESET
fRING-S
VCC ≥ Vdet detection
5-bit
counter
Figure 5.5 Power-on Reset Circuit
Trigger
Internal reset signal
Q
S
R
Rev.1.20 Jan 27, 2006 page 18 of 204
REJ09B0062-0120
R8C/11 Group
0.1V to 2.7VV
CC
RESET Vcc
about 5 kΩ
3
V
det
V
por1
t
w(por1)
Internal reset signal
(“L” effective)
t
w(Vpor1–Vdet)
1
f
RING-S
NOTES:
1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time.
2. A sampling clock is selectable. Refer to “5.4 Voltage Detection Circuit” for details.
det
shows the voltage detection level of the voltage detection circuit. Refer to “5.4 Voltage Detection Circuit” for details.
3. V
4. Refer to Table 16.6, 16.7 for electrical characteristics.
0V
RESET
0V
Sampling time
X 32
within td(P-R)
2)
(1,
t
w(por2)tw(Vpor2 –Vdet)
0.8VCC or above
V
cc min
V
por2
f
RING-S
(3)
V
det
1
X 32
Figure 5.6 Power-on Reset Operation
Rev.1.20 Jan 27, 2006 page 19 of 204
REJ09B0062-0120
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