RENESAS R8C-11 User Manual
REJ09B0062-0091Z
R8C/11 Group
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY/R8C/Tiny SERIES
Preliminary
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 0.91
Revision date: Sep 08, 2003
www.renesas.com
Keep safety first in your circuit designs!
•
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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programs, algorithms, or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
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How to Use This Manual
This hardware manual provides detailed information on features in the R8C/11 Group microcomputer.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputer.
Each register diagram contains bit functions with the following symbols and descriptions.
XXX register
b7 b6 b5 b4 b3 b2 b1 b0
0
*1
Symbol Address After reset
XXX XXX 00
Bit nameBit symbol
XXX0
XXX1
(b2)
(b3)
XXX4
XXX5
XXX6
XXX7
XXX bit
Nothing is assigned.
When write, should set to "0". When read, its content is indeterminate.
Reserved bit
XXX bit
XXX bit
*1
Blank:Set to "0" or "1" according to your intended use
0: Set to "0"
1: Set to "1"
X: Nothing is assigned
16
b1 b0
1 0: XXX
0 1: XXX
1 0: Avoid this setting
1 1: XXX
Must set to "0"
Function varies depending on each
operation mode
0: XXX
1: XXX
Function
RW
RW
RW
RW
RW
WO
RW
RO
*2
*3
*2
RW: Read and write
RO: Read only
WO: Write only
–: Nothing is assigned
*3
Terms to use here are explained as follows.
• Nothing is assigned
Nothing is assigned to the bit concerned. When write, set to "0" for new function
in future plan.
• Reserved bit
Reserved bit. Set the specified value.
• Avoid this setting
The operation at having selected is not guaranteed.
• Function varies depending on each operation mode
Bit function varies depending on peripheral function mode.
Refer to register diagrams in each mode.
M16C Family Documents
Document
Short Sheet
Data Sheet
Hardware Manual
Software Manual
Application Note
Contents
Hardware overview
Hardware overview and electrical characteristics
Hardware specifications (pin assignments,
memory maps, specifications of peripheral functions, electrical characteristics, timing charts)
Detailed description about instructions and microcomputer performance by each instruction
• Application examples of peripheral functions
• Sample programs
• Introductory description about basic functions in
M16C family
• Programming method with the assembly and C
languages
Table of Contents
SFR Page Reference
Chapter 1. Overview..............................................................1
1.1 Applications ....................................................................................................................1
1.2 Performance Outline ......................................................................................................2
1.3 Block Diagram ................................................................................................................ 3
1.4 Product Information .......................................................................................................4
1.5 Pin Assignments.............................................................................................................5
1.6 Pin Description ...............................................................................................................6
Chapter 2. Central Processing Unit (CPU)..........................7
2.1 Data Registers (R0, R1, R2 and R3) ..............................................................................7
2.2 Address Registers (A0 and A1) .....................................................................................8
2.3 Frame Base Register (FB).............................................................................................. 8
2.4 Interrupt Table Register (INTB)......................................................................................8
2.5 Program Counter (PC)....................................................................................................8
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ...................................... 8
2.7 Static Base Register (SB) .............................................................................................. 8
2.8 Flag Register (FLG) ........................................................................................................8
2.8.1 Carry Flag (C Flag) .................................................................................................... 8
2.8.2 Debug Flag (D Flag)...................................................................................................8
2.8.3 Zero Flag (Z Flag) ......................................................................................................8
2.8.4 Sign Flag (S Flag) ......................................................................................................8
2.8.5 Register Bank Select Flag (B Flag) ..........................................................................8
2.8.6 Overflow Flag (O Flag) .............................................................................................. 8
2.8.7 Interrupt Enable Flag (I Flag)....................................................................................8
2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 8
2.8.9 Processor Interrupt Priority Level (IPL) .................................................................. 8
2.8.10 Reserved Area..........................................................................................................8
Chapter 3. Memory................................................................ 9
Chapter 4. Special Function Registers (SFR)................... 10
Chapter 5. Reset.................................................................. 14
5.1 Hardware Reset ............................................................................................................ 14
5.1.1 Hardware Reset 1..................................................................................................................................14
5.1.2 Hardware Reset 2..................................................................................................................................17
5.1.3 Power-on Reset Function..................................................................................................................... 18
5.2 Software Reset..............................................................................................................19
5.3 Watchdog Timer Reset.................................................................................................19
A-1
5.4 Voltage Detection Circuit .............................................................................................20
5.4.1 Voltage Detection Interrupt ..................................................................................................................25
5.4.2 Get Out Of Stop Mode Due To The Voltage Detection Interrupt .......................................................27
Chapter 6. Clock Generating Circuit.................................. 28
6.1 Main Clock.....................................................................................................................33
6.2 Ring Oscillator Clock ...................................................................................................34
6.2.1 Low-speed Ring Oscillator................................................................................................................... 34
6.2.2 High-speed Ring Oscillator..................................................................................................................34
6.3 CPU Clock and Peripheral Function Clock ................................................................ 35
6.3.1 CPU Clock..............................................................................................................................................35
6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO, fRING, fRING128) ................35
6.3.3 fRING and fRING128 .............................................................................................................................35
6.3.4 fRING-fast ..............................................................................................................................................35
6.4 Power Control ...............................................................................................................36
6.4.1 Normal Operation Mode .......................................................................................................................36
6.4.2 Wait Mode ..............................................................................................................................................38
6.4.3 Stop Mode..............................................................................................................................................39
6.5 Oscillation Stop Detection Function...........................................................................42
6.5.1 How to Use Oscillation Stop Detection Function ..............................................................................42
Chapter 7. Protection.......................................................... 44
Chapter 8. Processor Mode................................................ 45
8.1 Types of Processor Mode ............................................................................................45
Chapter 9. Bus Control ....................................................... 46
Chapter 10. Interrupt........................................................... 47
10.1 Interrupt Overview......................................................................................................47
10.1.1 Type of Interrupts................................................................................................................................47
10.1.2 Software Interrupts .............................................................................................................................48
10.1.3 Hardware Interrupts............................................................................................................................49
10.1.4 Interrupts and Interrupt Vector..........................................................................................................50
10.1.5 Interrupt Control .................................................................................................................................52
______
10.2 INT Interrupt ................................................................................................................60
10.2.1 INT0 Interrupt ......................................................................................................................................60
10.2.2 INT0 Input Filter...................................................................................................................................61
10.2.3 INT1 Interrupt and INT2 Interrupt ......................................................................................................62
10.2.4 INT3 Interrupt ......................................................................................................................................63
________
_______
______ ______
______
10.3 Key Input Interrupt ..................................................................................................... 65
10.4 Address Match Interrupt ............................................................................................ 66
Chapter 11. Watchdog Timer.............................................. 68
Chapter 12. Timers.............................................................. 70
12.1 Timer X ........................................................................................................................ 71
A-2
12.1.1 Timer Mode..........................................................................................................................................73
12.1.2 Pulse Output Mode .............................................................................................................................74
12.1.3 Event Counter Mode ...........................................................................................................................75
12.1.4 Pulse Width Measurement Mode.......................................................................................................76
12.1.5 Pulse Period Measurement Mode..................................................................................................... 78
12.2 Timer Y.........................................................................................................................80
12.2.1 Timer Mode..........................................................................................................................................83
12.2.2 Programmable Waveform Generation Mode ....................................................................................85
12.3 Timer Z......................................................................................................................... 88
12.3.1Timer Mode...........................................................................................................................................91
12.3.2 Programmable Waveform Generation Mode ....................................................................................93
12.3.3 Programmable One-shot Generation Mode...................................................................................... 95
12.3.4 Programmable Wait One-shot Generation Mode .............................................................................98
12.4 Timer C ...................................................................................................................... 101
12.4.1 Input Capture Mode .........................................................................................................................105
12.4.2 Output Compare Mode ....................................................................................................................107
Chapter 13. Serial I/O ........................................................ 109
13.1 Clock Synchronous Serial I/O Mode....................................................................... 114
13.1.1 Polarity Select Function ................................................................................................................... 117
13.1.2 LSB First/MSB First Select Function ..............................................................................................117
13.1.3 Continuous Receive Mode ............................................................................................................... 118
13.2 Clock Asynchronous Serial I/O (UART) Mode ....................................................... 119
13.2.1 TxD10/RxD1 Select Function (UART1)............................................................................................122
13.2.2 TxD11 Select Function (UART1) ......................................................................................................122
Chapter 14. A-D Converter ............................................... 123
14.1 One-shot Mode ......................................................................................................... 127
14.2 Repeat Mode ............................................................................................................. 129
14.3 Sample and Hold ......................................................................................................131
Chapter 15. Programmable I/O Ports .............................. 132
15.1 Description................................................................................................................132
15.2 Unassigned Pin Handling ........................................................................................140
Chapter 16. Electrical Characteristics.............................141
Chapter 17. Flash Memory Version ................................. 148
17.1 Overview.................................................................................................................... 148
17.2 Memory Map.............................................................................................................. 149
17.3 Functions To Prevent Flash Memory from Rewriting............................................150
17.3.1 ID Code Check Function ..................................................................................................................150
17.4 CPU Rewrite Mode.................................................................................................... 151
17.4.1 EW0 Mode..........................................................................................................................................152
17.4.2 EW1 Mode..........................................................................................................................................152
A-3
17.4.3 Software Commands ........................................................................................................................158
17.4.4 Status Register..................................................................................................................................162
17.4.5 Full Status Check..............................................................................................................................163
17.5 Standard Serial I/O Mode .........................................................................................165
17.5.1 ID Code Check Function ..................................................................................................................165
Chapter 18. On-chip Debugger ........................................ 169
18.1 Address Match Interrupt .......................................................................................... 169
18.2 Single Step Interrupt ................................................................................................169
18.3 UART1........................................................................................................................169
18.4 BRK Instruction ........................................................................................................169
Chapter 19. Usage Notes.................................................. 170
19.1 Stop Mode and Wait Mode.......................................................................................170
19.2 Interrupts...................................................................................................................170
19.2.1 Reading Address 0000016................................................................................................................170
19.2.2 SP Setting ..........................................................................................................................................170
19.2.3 External Interrupt and Key Input Interrupt .....................................................................................170
19.2.4 Watchdog Timer Interrupt ................................................................................................................170
19.2.5 Changing Interrupt Source ..............................................................................................................170
19.2.6 Changing Interrupt Control Register ..............................................................................................172
19.3 Timers........................................................................................................................173
19.3.1 Timers X, Y and Z..............................................................................................................................173
19.3.2 Timer X...............................................................................................................................................173
19.3.3 Timer Z ...............................................................................................................................................173
19.3.4 Timer C...............................................................................................................................................173
19.4 Serial I/O ....................................................................................................................174
19.5 A-D Converter ...........................................................................................................175
19.6 Flash Memory Version .............................................................................................176
19.6.1 CPU Rewrite Mode ............................................................................................................................176
19.7 Noise..........................................................................................................................178
Chapter 20. Usage Notes for On-chip Debugger............ 179
Appendix 1 Package Dimensions.................................... 180
Appendix 2 Connecting Examples for Serial Writer and
On-chip Debugging Emulator .......................................... 181
Register Index ................................................................... 183
R8C/11 Group Usage Note Reference Book
For the most current Usage Note Reference Book, please visit our website.
A-4
SFR Page Reference
Address
000016
000116
000216
000316
000416
Processor mode register 0 PM0 45
000516
Processor mode register 1 PM1 45
000616
System clock control register 0 CM0 30
000716
System clock control register 1 CM1 30
000816
High-speed ring control register 0 HR0 32
000916
Address match interrupt enable register AIER 67
000A16
Protect register PRCR 44
000B16
High-speed ring control register 1 HR1 32
000C16
Oscillation stop detection register OCD 31
000D16
Watchdog timer reset register WDTR 69
000E16
Watchdog timer start register WDTS 69
000F16
Watchdog timer control register WDC 69
001016
Address match interrupt register 0 RMAD0 67
001116
001216
001316
001416
Address match interrupt register 1 RMAD1 67
001516
001616
001716
001816
001916
Voltage detection register 1 VCR1 21
001A16
Voltage detection register 2 VCR2 21
001B16
001C16
001D16
001E16
INT0 input filter select register INT0F 60
001F16
Voltage detection interrupt register D4INT 22
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Register Symbol
Page
Address
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
Key input interrupt control register KUPIC 53
004E
16
A-D conversion interrupt control register ADIC 53
004F
16
0050
16
Compare 2 interrupt control register
0051
16
UART0 transmit interrupt control register
0052
16
UART0 receive interrupt control register
0053
16
UART1 transmit interrupt control register
0054
16
UART1 receive interrupt control register
0055
16
INT2 interrupt control register INT2IC 53
0056
16
Timer X interrupt control register TXIC 53
0057
16
Timer Y interrupt control register TYIC 53
0058
16
Timer Z interrupt control register TZIC 53
0059
16
INT1 interrupt control register INT1IC 53
005A
16
INT3 interrupt control register INT3IC 53
005B
16
Timer C interrupt control register TCIC 53
005C
16
Compare 1 interrupt control register
005D
16
INT0 interrupt control register INT0IC 53
005E
16
005F
16
0060
16
0061
16
0062
16
0063
16
0064
16
0065
16
0066
16
0067
16
0068
16
0069
16
006A
16
006B
16
006C
16
006D
16
006E
16
006F
16
0070
16
0071
16
0072
16
0073
16
0074
16
0075
16
0076
16
0077
16
0078
16
0079
16
007A
16
007B
16
007C
16
007D
16
007E
16
007F
16
Register Symbol
Page
CMP2IC 53
S0TIC 53
S0RIC 53
S1TIC 53
S1RIC 53
CMP1IC 53
Blank columns are all reserved space. No use is allowed.
B-1
SFR Page Reference
Address
0080
16
Timer Y, Z mode register TYZMR 80/88
Prescaler Y PREY 81
0081
16
0082
16
Timer Y secondary TYSC 81
Timer Y primary TYPR 81
0083
16
0084
16
Timer Y, Z waveform output control register PUM 82/90
0085
16
Prescaler Z PREZ 89
Timer Z secondary TZSC 89
0086
16
Timer Z primary TZPR 89
0087
16
0088
16
0089
16
008A
16
Timer Y, Z output control register TYZOC 81/89
Timer X mode register TXMR 71
008B
16
008C
16
Prescaler X PREX 72
Timer X register TX 72
008D
16
Count source set register TCSS
008E
16
008F
16
0090
16
Timer C register TC 103
0091
16
0092
16
0093
16
0094
16
0095
16
0096
16
External input enable register INTEN 60
0097
16
Key input enable register KIEN 65
0098
16
0099
16
Timer C control register 0 TCC0 103
009A
16
Timer C control register 1 TCC1 104
009B
16
009C
16
Capture and compare 0 register TM0 103
009D
16
009E
16
Compare 1 register TM1 103
009F
16
00A0
16
UART0 transmit/receive mode register U0MR 112
00A1
16
UART0 bit rate generator U0BRG 111
00A2
16
UART0 transmit buffer register U0TB 111
00A3
16
00A4
16
UART0 transmit/receive control register 0 U0C0 112
00A5
16
UART0 transmit/receive control register 1 U0C1 111
00A6
16
UART0 receive buffer register U0RB 111
00A7
16
UART1 transmit/receive mode register U1MR 112
00A8
16
UART1 bit rate generator U1BRG 111
00A9
16
00AA
16
UART1 transmit buffer register U1TB 111
00AB
16
UART1 transmit/receive control register 0 U1C0 112
00AC
16
UART1 transmit/receive control register 1 U1C1 113
00AD
16
00AE
16
UART1 receive buffer register U1RB 111
00AF
16
00B0
16
UART
00B1
00B2
00B3
00B4
00B5
00B6
00B7
00B8
00B9
00BA
00BB
00BC
00BD
00BE
00BF
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
transmit/receive control register 2 UCON 113
Register Symbol
Page
72/82/90
Blank columns are all reserved space. No use is allowed.
Address
00C0
00C1
00C2
00C3
00C4
00C5
00C6
00C7
00C8
00C9
00CA
00CB
00CC
00CD
00CE
00CF
00D0
00D1
00D2
00D3
00D4
00D5
00D6
00D7
00D8
00D9
00DA
00DB
00DC
00DD
00DE
00DF
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
00E9
00EA
00EB
00EC
00ED
00EE
00EF
00F0
00F1
00F2
00F3
00F4
00F5
00F6
00F7
00F8
00F9
03FA
00FB
00FC
00FD
00FE
00FF
01B3
01B4
01B5
01B6
01B7
16
Register Symbol
A-D register AD 126
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
A-D control register 2 ADCON2 126
16
16
A-D control register 0 ADCON0 125
16
A-D control register 1 ADCON1 125
16
16
16
16
16
16
16
16
16
Port P0 register P0 138
16
Port P1 register P1 138
16
Port P0 direction register PD0 138
16
Port P1 direction register PD1 138
16
16
Port P3 register P3 138
16
16
Port P3 direction register PD3 138
16
Port P4 register P4 138
16
16
Port P4 direction register PD4 138
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Pull-up control register 0 PUR0 139
16
Pull-up control register 1 PUR1 139
16
Port P1 drivability control register DRR 139
16
Timer C output control register TCOUT 104
16
Flash memory control register 4 FMR4 144
16
16
Flash memory control register 1 FMR1 144
16
16
Flash memory control register 0 FMR0 143
Page
B-2
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU
core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing
instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial
equipment, audio, etc.
1. Overview
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.0.91 2003 Sep 08 page 1 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
1.2 Performance Outline
Table 1.1. lists the performance outline of this MCU.
Table 1.1 Performance outline
Item Performance
CPU Number of basic instructions 89 instructions
Shortest instruction execution time
Operating mode Single-chip
Address space 1M bytes
Memory capacity See Table 1.2.
Peripheral Interrupt Internal: 10 sources, External: 5 sources,
function Software: 4 sources, Priority level: 7 levels
Watchdog timer 15 bits x 1 (with prescaler)
Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Serial I/O •1 channel
A-D converter 10-bit A-D converter: 1 circuit, 12 channels
Clock generation circuit 2 circuits
Oscillation stop detection function
Voltage detection circuit Included
Power on reset circuit Included
Port Input/Output: 22 (including LED drive port), Input: 2
Electrical Power supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ)
characteristics
Power consumption TBD (VCC = 5.0 V, (f(XIN) = 20 MHZ)
Flash memory
Program/erase voltage VCC = 2.7 to 5.5 V
Number of program/erase 100 times
Operating ambient temperature -20 to 85 °C
Package 32-pin plastic mold LQFP
Option: If you require this option, please specify so.
50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)
Timer Z: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel
Circuits of input capture and output compare.
Clock synchronous, UART
•1 channel
UART
•Main clock generation circuit (Equipped with a built-in
feedback resistor)
•Ring oscillator (high speed, low speed)
On High-speed ring oscillator the frequency adjustment
function is usable.
Stop detection of main clock oscillation
(LED drive I/O port: 8, max. 20 mA)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ)
TBD (VCC = 3.0 V, (f(XIN) = 10 MHZ)
TBD (VCC = 3.0 V, Wait mode)
TBD (VCC = 3.0 V, Stop mode)
-40 to 85 °C (option)
1. Overview
Rev.0.91 2003 Sep 08 page 2 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
1. Overview
I/O port
Port P0
Peripheral functions
T i m e r
T i m e r X ( 8 b i t s )
T i m e r Y ( 8 b i t s )
T i m e r Z ( 8 b i t s )
T i m e r C ( 1 6 b i t s )
W a t c h d o g t i m e r
( 1 5 b i t s )
8
8
Port P1
A-D converter
(10 bits ✕ 12 channels)
UART or Clock synchronous
serial I/O
(8 bits ✕ 1 channel)
UART
(8 bits ✕ 1 channel)
R 8 C S e r i e s C P U c o r e
R0LR0H
R 1 HR1L
R2
R3
A0
A 1
FB
5
P o r t P 3
System clock generator
High-speed ring oscillator
Low-speed ring oscilla tor
S B
USP
I S P
INTB
PC
FLG
X
IN-XOUT
M e m o r y
M u l t i p l i e r
1 2
Port P4
ROM
(Note 1)
RAM
(Note 2)
Figure 1.1 Block Diagram
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Rev.0.91 2003 Sep 08 page 3 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.4 Product Information
Table 1.2 lists the products.
1. Overview
Table 1.2 Product List
RAM capacityR O M c a p a c i t yP
R 5 F 2 1 1 1 2 F P
R 5 F 2 1 1 1 3F P
R 5 F 2 1 1 1 4 F P
* *
* *
6 8 b y t e
K b y t e
* *
R 5 F 2 1 1 1 2 D F P3
R 5 F 2 1 1 1 3 DF P
R5F21114DFP
: U n d e r d e v e l o p m e n t
* *
* *
* *
8K byt es 5 1 2 b y t e s
6 8 b y t e
K b y t e
a c k a g e t y p
3 2P 6 U - A8K byt es 5 1 2 b y t e s
3 2P 6 U - A1 2 K b y t e s7
s
3 2P 6 U - A1 6 K b y t e s1
s
2P 6 U -
3 2P 6 U - A1 2 K b y t e s7
s
3 2P 6 U - A1 6 K b y t e s1
s
A
e m a r k
eR
F l a s h m e m o r y v e r s i o n
D v e r s i o n
A s o f S e p t e m b e r 2 0 0 3
sT y p e N o .
* *
Type No. R 5 F 21 11 4 D FP
Package type:
FP : 32P6U
Shows characteristics and others.
D: Operating ambient temperature –40 °C to 85 °C
No symbol: Operating ambient temperature –20 °C to 85 °C
ROM capacity:
2 : 8 KBytes.
3 : 12 KBytes.
4 : 16 KBytes.
R8C/11 group
R8C/Tiny series
Memory type:
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.0.91 2003 Sep 08 page 4 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
N0
07/
P
A
1. Overview
12
10
11
R1/
N
CI
F
T
T/
R0/
ZO
S
C
VC
I
1/
30/
VS
3
C N T
P
C M P
U
C M P
A
E
T
P
T3/
T2/
VR
C/
33/
32/
VC
I N
I N
C N T
P
P
C M P
A
P 06/ A N1
P 05/ A N2
P04/AN3
P 03/ A N4
P 02/ A N5
P01/AN6
P 00/ A N7/T x D1
MODE
2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7
2 5
2 6
2 7
2 8
R8C/11 Group
2 9
3 0
3 1
3 2
1
1 6
1 5
1 4
1 3
1 2
1 1
1 0
P45/INT0
P10/KI0/AN8/CMP00
P11/KI1/AN9/CMP01
P12/KI2/AN10/CMP02
P13/KI3/AN11
P14/TxD0
P 15/ R x D0
9
P16/CLK0
1 2 3 4 5 6 7 8
)
S
S
T
D1
VS
0/
C
D1
N
37/
P
R x
T x
R
E S E
47
T/
XO
U
P
(N o t e 1
C
46
C
VS
P
R0
V
N/
XI
T1/
17/
P
I N
C N T
N o t e s :
1 . P 4
7
f u n c t i o n s o n l y a s a n i n p u t p o r t .
2. W h e n u s i n g O n - c h i p d e b u g g e r , d o n o t u s e p i n s P 0
a n d P 37/ T x D
1 0
/ R x D1.
0
/ A N7/ T x D
1 1
Package: 32P6U-A
Figure 1.3 Pin Configuration (Top View)
Rev.0.91 2003 Sep 08 page 5 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
Signal name Pin name I/O type
Power supply Vcc, Input
input Vss
IVcc IVcc Output
Analog power AVcc, AVss Input
supply input
Reset input
CNVss CNVss Input
MODE MODE Input
Main clock input XIN Input
Main clock output XOUT Output
_____
INT interrupt input
Key input interrupt
input
Timer X CNTR0 Input/Output
Timer Y CNTR1 Input/Output
Timer Z TZOUT Output
Timer C TCIN Input
Serial interface CLK0 Input/Output
Reference voltage VREF Input
input
A-D converter AN0 to AN11 Input
I/O port P00 to P07, Input/Output
Input port P46, P47 Input
___________
RESET Input
_______ _______
INT0 to INT3 Input
_____ _____
KI0 to KI3 Input
__________
CNTR0 Output
CMP00 to CMP03,
Output
CMP10 to CMP13
RxD0, RxD1 Input
TxD0, TxD10, Output
TxD11
P10 to P17,
P30 to P33, P37,
P45
1. Overview
Function
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
Connect this pin to Vss via a capacitor (0.1 µF).
These are power supply input pins for A-D converter.
Connect the AVss pin to Vss. Connect a capacitor
between pins AVcc and AVss.
“L” on this input resets the MCU.
Connect this pin to Vss via a resistor (approximately 5 kΩ).
Connect this pin to Vcc via a resistor (approximately 5 kΩ).
These pins are provided for the main clock generating circuit input/output. Connect a ceramic resonator
or a crystal oscillator between the XIN and XOUT pins.
To use an externally derived clock, input it to the XIN
pin and leave the XOUT pin open.
______
These are INT interrupt input pins.
These are key input interrupt input pins.
This is the timer X I/O pin.
This is the timer X output pin.
This is the timer Y I/O pin.
This is the timer Z output pin.
This is the timer C input pin.
These are the timer C output pins.
This is a transfer clock I/O pin.
These are serial data input pins.
These are serial data output pins.
This is a reference voltage input pin for A-D converter.
These are analog input pins for A-D converter.
These are 8-bit CMOS I/O ports. Each port has an
input/output select direction register, allowing each
pin in that port to be directed for input or output individually.
Any port set to input can select whether to use a pullup resistor or not by program.
P10 to P17 also function as LED drive ports.
These are input only pins.
Rev.0.91 2003 Sep 08 page 6 of 184
Under development
g
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
R2
R3
b15
R0H(R0's high bits)
R1H(R1's high bits)
b19
b15
INTBH
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
PC
b15
b15
b15
b7 b8
IPL
b8 b7 b0
R0L(R0's low bits)
R1L(R1's low bits)
R2
R3
A0
A1
FB
INTBL
USP
ISP
SB
FLG
Data registers (Note 1)
Address registers (Note 1)
Frame base registers (Note 1)
b0
Interrupt table register
b0
Program counter
b0
User stack pointer
Interrupt stack pointer
Static base register
b0
Flag register
b0
CDZSBOIU
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note 1: These re
isters comprise a register bank. There are two register banks.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
Rev.0.91 2003 Sep 08 page 7 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
Rev.0.91 2003 Sep 08 page 8 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
3. Memory
Figure 3.1 is a memory map of this MCU. The address space extends the 1M bytes from address 0000016
to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address 0FFFF16. For example,
a 16-Kbyte internal ROM is allocated to the addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated to the addresses from 0FFDC16 to 0FFFF16. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 1-Kbyte internal RAM is allocated to the addresses from 0040016 to 007FF16. In addition to storing data,
the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
Special function registers (SFR) are allocated to the addresses from 0000016 to 002FF16. Peripheral function control registers are located here. Of the SFR, any space which has no functions allocated is reserved
for future use and cannot be used by users.
3. Memory
0000016
SFR
(See Chapter 4 for details.)
002FF16
0040016
Internal RAM
0XXXX16
0YYYY16
Internal ROM
0FFFF16
Expanding area
FFFFF16
Type name
R5F21114FP, R5F21114DFP
R5F21113FP, R5F21113DFP
R5F21112FP, R5F21112DFP
Size
16K bytes
12K bytes
8K bytes
0FFDC16
0FFFF16
Internal ROM
Address 0YYYY
0C00016
0D000
0E00016
Undefined instruction
Overflow
BRK instruction
Address match
Watchdog timer,Oscillation stop detection,Voltage detection
Single step
(Reserved)
(Reserved)
Reset
Internal RAM
16
Size
1K bytes
16
768 bytes
512 bytes
Address 0XXXX16
007FF16
006FF
16
005FF16
Figure 3.1 Memory Map
Rev.0.91 2003 Sep 08 page 9 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
4. Special Function Register (SFR)
4. Special Function Register (SFR)
A d d r e s s
0 0 0 0
1 6
0 0 0 1
1 6
0 0 0 2
1 6
0 0 0 3
1 6
M
P r o c e s s o r m o d e r e g i s t e r 0P
0 0 0 4
1 6
M
0 0 0 5
1 6
P r o c e s s o r m o d e r e g i s t e r 1P
M
1 1 0 1 0 0
0 0 0 6
1 6
S y s t e m c l o c k c o n t r o l r e g i s t e r 0C
M
0 1 0 0 0 0
0 0 0 7
1 6
S y s t e m c l o c k c o n t r o l r e g i s t e r 1C
R
0 0 0 8
1 6
H i g h - s p e e d r i n g c o n t r o l r e g i s t e r 0H
I E
X X X X X 0
0 0 0 9
1 6
A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e rA
R C
0 X X X 0 0
0 0 0 A
1 6
P r o t e c t r e g i s t e rP
R
0 0 0 B
1 6
H i g h - s p e e d r i n g c o n t r o l r e g i s t e r 1H
C
0 0 0 0 1 0
0 0 0 C
1 6
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO
D T
0 0 0 D
1 6
W a t c h d o g t i m e r r e s e t r e g i s t e rW
D T
0 0 0 E
1 6
W a t c h d o g t i m e r s t a r t r e g i s t e rW
D
0 0 X X X X
0 0 0 F
1 6
W a t c h d o g t i m e r c o n t r o l r e g i s t e rW
M A D
0 0 1 0
1 6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0R
0 0 1 1
1 6
0 0 1 2
1 6
0 0 1 3
1 6
M A D
0 0 1 4
1 6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R
0 0 1 5
1 6
0 0 1 6
1 6
0 0 1 7
1 6
0 0 1 8
1 6
C R
0 0 1 9
1 6
V o l t a g e d e t e c t i o n r e g i s t e r 1V
0 0 1 A
1 6
Voltage detection register 2 VCR2 10000000
0 0 1 B
1 6
0 0 1 C
1 6
0 0 1 D
1 6
0 0 1 E
1 6
INT0 input filter select register INT0F XXXXX000
0 0 1 F
1 6
Voltage detection interrupt register D4INT 00
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
X : U n d e f i n e d
B l a n k c o l u m n s a r e a l l r e s e r v e d s p a c e . N o a c c e s s i s a l l o w e d .
N o t e s :
1. S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t b i t s 0 t o 1 o f P M 0 r e g i s t e r .
2 . S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r .
3 . O w i n g t o R e s e t i n p u t .
4 . I n t h e c a s e o f
R E S E T
p i n = “ H ” r e t a i n i n g .
Register Symbol After reset
1
2
2
2
00
10
00
10
00
RX
R0
14
D0
RX
SX
C0
00
10
10
0 0
X 0
0 0
X 0
0
1 6
0
1 6
0
2
0
2
0
1 6
0
2
0
0
0
2
1 6
0
2
X
1 6
X
1 6
X
2
1 6
1 6
1 6
0
1 6
1 6
1 6
0
1 6
16
2
3
16
01000001
4
2
Rev.0.91 2003 Sep 08 page 10 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR)
Address
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
004A
004B
004C
004D
004E
004F
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005A
005B
005C
005D
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
006A
006B
006C
006D
006E
006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007C
007D
007E
007F
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Key input interrupt control register KUPIC XXXXX000
16
A-D conversion interrupt control register ADIC XXXXX000
16
16
Compare 2 interrupt control register
16
UART0 transmit interrupt control register
16
UART0 receive interrupt control register
16
UART1 transmit interrupt control register
16
UART1 receive interrupt control register
16
INT2 interrupt control register INT2IC XXXXX000
16
Timer X interrupt control register TXIC XXXXX000
16
Timer Y interrupt control register TYIC XXXXX000
16
Timer Z interrupt control register TZIC XXXXX000
16
INT1 interrupt control register INT1IC XXXXX000
16
INT3 interrupt control register INT3IC XXXXX000
16
Timer C interrupt control register TCIC XXXXX000
16
Compare 1 interrupt control register
16
INT0 interrupt control register INT0IC XX00X000
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Register Symbol After reset
X : Undefined
Blank columns are all reserved space. No access is allowed.
CMP2IC XXXXX000
S0TIC XXXXX000
S0RIC XXXXX000
S1TIC XXXXX000
S1RIC XXXXX000
CMP1IC XXXXX000
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev.0.91 2003 Sep 08 page 11 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR)
Address
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
008A
008B
008C
008D
008E
008F
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
009A
009B
009C
009D
009E
009F
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
00A8
00A9
00AA
00AB
00AC
00AD
00AE
00AF
00B0
00B1
00B2
00B3
00B4
00B5
00B6
00B7
00B8
00B9
00BA
00BB
00BC
00BD
00BE
00BF
16
Timer Y, Z mode register TYZMR 00
16
Prescaler Y PREY FF
16
Timer Y secondary TYSC FF
Timer Y primary TYPR FF
16
Timer Y, Z waveform output control register PUM 00
16
16
Prescaler Z PREZ FF
Timer Z secondary TZSC FF
16
Timer Z primary TZPR FF
16
16
16
Timer Y, Z output control register TYZOC 00
16
Timer X mode register TXMR 00
16
16
Prescaler X PREX FF
Timer X register TX FF
16
Count source set register TCSS 00
16
16
16
Timer C register TC 00
16
16
16
16
16
16
External input enable register INTEN 00
16
Key input enable register KIEN 00
16
16
16
Timer C control register 0 TCC0 00
16
Timer C control register 1 TCC1 00
16
Capture, compare 0 register TM0 XX
16
16
Compare 1 register TM1 XX
16
16
UART0 transmit/receive mode register
16
UART0 bit rate generator U0BRG XX
16
UART0 transmit buffer register U0TB XX
16
16
UART0 transmit/receive control register 0
16
UART0 transmit/receive control register 1
16
UART0 receive buffer register U0RB XX
16
16
UART1 transmit/receive mode register
16
UART1 bit rate generator U1BRG XX
16
UART1 transmit buffer register U1TB XX
16
16
UART1 transmit/receive control register 0
16
UART1 transmit/receive control register 1
16
UART1 receive buffer register U1RB XX
16
16
UART transmit/receive control register 2
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Register Symbol After reset
X : Undefined
Blank columns are all reserved space. No access is allowed.
16
16
16
16
16
16
16
16
16
16
16
16
16
16
00
16
16
16
16
16
16
XX
16
16
XX
U0MR 00
16
16
16
16
XX
16
U0C0 00001000
U0C1 00000010
16
XX
U1MR 00
16
16
16
16
XX
16
U1C0 00001000
U1C1 00000010
16
XX
16
UCON 00
16
2
2
2
2
Rev.0.91 2003 Sep 08 page 12 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR)
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
03FA16
00FB16
00FC16
00FD16
00FE16
00FF16
Register
A-D register AD XX
A-D control register 2 ADCON2 00
Symbol After reset
16
XX
16
16
A-D control register 0 ADCON0 00000XXX
A-D control register 1 ADCON1 00
Port P0 register P0 XX
Port P1 register P1 XX
Port P0 direction register PD0 00
Port P1 direction register PD1 00
Port P3 register P3 XX
Port P3 direction register PD3 00
Port P4 register P4 XX
Port P4 direction register PD4 00
16
16
16
16
16
16
16
16
16
Pull-up control register 0 PUR0 00XX0000
Pull-up control register 1 PUR1 XXXXXX0X
Port P1 drivability control register DRR 00
Timer C output control register TCOUT 00
16
16
2
2
2
Flash memory control register 4 FMR4 0100000X
01B316
01B416
01B516
Flash memory control register 1 FMR1 0100XX0X
01B616
01B716
Flash memory control register 0 FMR0 XX000001
X : Undefined
Blank columns are all reserved space. No access is allowed.
Rev.0.91 2003 Sep 08 page 13 of 184
2
2
2
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Reset
There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset.
5.1 Hardware Reset
There are three kinds of hardware reset: hardware reset 1, hardware reset 2, and power-on reset.
5.1 Hardware Reset
5.1.1 Hardware Reset 1
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the
power supply voltage is within the recommended operating condition, the pins are initialized (see
Table 5.1 “Pin Status When RESET Pin Level is 'L'”). When the input level at the RESET pin is
released from “L” to “H”, the CPU and SFR are initialized, and the program is executed starting
from the address indicated by the reset vector. Figure 5.1 shows the CPU register status after
reset and figure 5.2 shows the reset sequence. The internal RAM is not initialized. If the RESET
pin is pulled “L” while writing to the internal RAM, the internal RAM becomes indeterminate.
Figures 5.3 to 5.4 show the reset circuit example using the hardware reset 1. Refer to Chapter 4,
“Special Function Register (SFR)” for the status of SFR after reset.
• When the power supply is stable
(1) Apply an “L” signal to the RESET pin.
(2) Wait 500 µs.
(3) Apply an “H” signal to the RESET pin.
• Power on
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condi-
tion.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Wait 500 µs.
(5) Apply an “H” signal to the RESET pin.
____________ ____________
____________ ____________
____________
____________
____________
____________
____________
detection circuit monitors the voltage supplied to the VCC pin.
Table 5.1 Pin Status When RESET Pin Level is “L”
____________
Pin name
P0
P1
P3
0 to P33, P37
P45 to P47
Rev.0.91 2003 Sep 08 page 14 of 184
Input port
Input port
Input port
Input port
Status
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.1 Hardware Reset
b15
0000
16
0000
16
0000
16
0000
16
0000
16
0000
16
0000
16
b19
00000
16
Content of addresses 0FFFE16 to 0FFFC
b15
16
0000
0000
16
0000
16
16
b0
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
b0
Interrupt table register(INTB)
Program counter(PC)
b0
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
b15
0000
b15
b7 b8
IPL
Figure 5.1 CPU Register Status After Reset
Internal ring
oscillation
RESET
CPU clock
Address
(Internal address
signal)
More than 20 cycles are needed
CPU clock: 28cycles
16
0FFFC
16
0FFFD
b0
Flag register(FLG)
b0
CDZSBOIU
0FFFE
16
16
Content of reset vector
Figure 5.2 Reset Sequence
Rev.0.91 2003 Sep 08 page 15 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.1 Hardware Reset
V
CC
2.7V
0 V
V
R E S E T
CC
R E S E T
0V
Figure 5.3 Example Reset Circuit Using The Hardware Reset 1
5V
2.7V
RESET
V
CC
V
CC
Supply voltage
detection circuit
0V
5V
Equal to or less
than 0.2V
CC
M o r e t h a n t d ( P - R ) + 5 0 0 µ s a r e
n e e d e d .
RESET
0V
More than td(P-R) + 500 µs
are needed.
Example when V
CC
= 5V
.
Figure 5.4 Example Reset Circuit Using The Hardware Reset 1 (Voltage Check Circuit)
Rev.0.91 2003 Sep 08 page 16 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.1.2 Hardware Reset 2
The microcomputer is reset when the voltage at the VCC input pin drops below Vdet if all of the
following conditions hold true.
• The VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled)
• The D40 bit in the D4INT register is set to “1” (voltage detection interrupt enabled)
• The D46 bit in the D4INT register is set to “1” (hardware reset 2 when going through Vdet)
Conversely, when the input voltage at the VCC pin rises to Vdet or more, the pins, CPU, and SFR are
initialized, and the program is executed starting from the address indicated by the reset vector. The
initialized pins and registers and the status thereof are the same as in hardware reset 1. Refer to
Section 5.4 “Voltage Detection Circuit.”
5.1 Hardware Reset
Rev.0.91 2003 Sep 08 page 17 of 184
Under development
R8C/11 Group
5.1.3 Power-on Reset Function
The power-on reset is the function which can reset the microcomputer without the external reset
circuit. The RESET pin should be connected to the VCC pin via about 5 kΩ pull-up resistance using
the power-on reset function, the function turns to active.
When the input voltage at the VCC pin reaches to the Vdet level, count operation of the low-speed
ring oscillator clock starts. When the operation counts the low-speed ring oscillator clock for 32 times,
the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting
from the address indicated by the reset vector. The initialized pins and registers and the status
thereof are the same as in hardware reset 1.
• The D40 bit in the D4INT register turns to “1” automatically (voltage detection interrupt enabled)
• The D46 bit in the D4INT register turns to “1” automatically (hardware reset 2 when going through
Vdet)
Additionally, the hardware reset 2 turns to active after the power-on reset. This is because the VC27
bit in the VCR2 register is set to “1” (voltage detection circuit enabled) after the power-on reset same
as the hardware reset 1, so that hardware reset 2 active conditions are all satisfied including above
D40 and D46 bit conditions.
Preliminary specification
Specifications in this manual are tentative and subject to change.
____________
5.1 Hardware Reset
Figure 5.5 shows the power-on reset circuit. Figure 5.6 shows the power-on reset operation.
RESET
5 bit
counter
V
CC ≥
f
RING-S
Vdet detection
Figure 5.5 Power-on Reset Circuit
Trigger
Internal reset signal
Q
S
R
V
C C
a b o u t
5 kΩ
c
c
I n t e r n a l r e s e t s i g n a l
R E S E TV
Figure 5.6 Power-on Reset Operation
Rev.0.91 2003 Sep 08 page 18 of 184
0.5 V
0 V
1 m s o r m o r e
2 . 7 V
Less than100 µs
1
f
R I N G - S
V d e t
x 3 2
Under development
R8C/11 Group
5.2 Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its
pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by
the reset vector.
Some SFRs are not initialized by the software reset. Refer to Chapter 4, “SFR.”
5.3 Watchdog Timer Reset
Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed starting from the address indicated by the reset vector.
Some SFRs are not initialized by the watchdog timer reset. Refer to Chapter 4, “SFR.”
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.2 Software Reset, 5.3 Watchdog Timer Reset
Rev.0.91 2003 Sep 08 page 19 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.4 Voltage Detection Circuit
5.4 Voltage Detection Circuit
The voltage detection circuit has a circuit to monitor the input voltage at the VCC pin with Vdet. Besides
the program, the hardware reset 2 and voltage detection interrupt can be used to check the input voltage
at the VCC pin.
Figure 5.7 shows the voltage detection circuit. Figure 5.8 shows VCR1 and VCR2 registers. Figure 5.9
shows the D4INT register. Figure 5.10 shows an operation example of the voltage detection circuit. Figure 5.11 to 5.12 show the operation example of the voltage detection circuit to get out of stop mode.
VC27
CC1
+
V
Noise canceller
V
REF
-
Figure 5.7 Voltage Detection Circuit Block
Voltage detection
interrupt signal
VCR1 register
b3
VC13 bit
Rev.0.91 2003 Sep 08 page 20 of 184
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