REJ09B0062-0091Z
R8C/11 Group
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY/R8C/Tiny SERIES
Preliminary
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 0.91
Revision date: Sep 08, 2003
www.renesas.com
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•
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programs, algorithms, or circuit application examples contained in these materials.
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How to Use This Manual
This hardware manual provides detailed information on features in the R8C/11 Group microcomputer.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputer.
Each register diagram contains bit functions with the following symbols and descriptions.
XXX register
b7 b6 b5 b4 b3 b2 b1 b0
0
*1
Symbol Address After reset
XXX XXX 00
Bit nameBit symbol
XXX0
XXX1
(b2)
(b3)
XXX4
XXX5
XXX6
XXX7
XXX bit
Nothing is assigned.
When write, should set to "0". When read, its content is indeterminate.
Reserved bit
XXX bit
XXX bit
*1
Blank:Set to "0" or "1" according to your intended use
0: Set to "0"
1: Set to "1"
X: Nothing is assigned
16
b1 b0
1 0: XXX
0 1: XXX
1 0: Avoid this setting
1 1: XXX
Must set to "0"
Function varies depending on each
operation mode
0: XXX
1: XXX
Function
RW
RW
RW
RW
RW
WO
RW
RO
*2
*3
*2
RW: Read and write
RO: Read only
WO: Write only
–: Nothing is assigned
*3
Terms to use here are explained as follows.
• Nothing is assigned
Nothing is assigned to the bit concerned. When write, set to "0" for new function
in future plan.
• Reserved bit
Reserved bit. Set the specified value.
• Avoid this setting
The operation at having selected is not guaranteed.
• Function varies depending on each operation mode
Bit function varies depending on peripheral function mode.
Refer to register diagrams in each mode.
M16C Family Documents
Document
Short Sheet
Data Sheet
Hardware Manual
Software Manual
Application Note
Contents
Hardware overview
Hardware overview and electrical characteristics
Hardware specifications (pin assignments,
memory maps, specifications of peripheral functions, electrical characteristics, timing charts)
Detailed description about instructions and microcomputer performance by each instruction
• Application examples of peripheral functions
• Sample programs
• Introductory description about basic functions in
M16C family
• Programming method with the assembly and C
languages
Table of Contents
SFR Page Reference
Chapter 1. Overview..............................................................1
1.1 Applications ....................................................................................................................1
1.2 Performance Outline ......................................................................................................2
1.3 Block Diagram ................................................................................................................ 3
1.4 Product Information .......................................................................................................4
1.5 Pin Assignments.............................................................................................................5
1.6 Pin Description ...............................................................................................................6
Chapter 2. Central Processing Unit (CPU)..........................7
2.1 Data Registers (R0, R1, R2 and R3) ..............................................................................7
2.2 Address Registers (A0 and A1) .....................................................................................8
2.3 Frame Base Register (FB).............................................................................................. 8
2.4 Interrupt Table Register (INTB)......................................................................................8
2.5 Program Counter (PC)....................................................................................................8
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ...................................... 8
2.7 Static Base Register (SB) .............................................................................................. 8
2.8 Flag Register (FLG) ........................................................................................................8
2.8.1 Carry Flag (C Flag) .................................................................................................... 8
2.8.2 Debug Flag (D Flag)...................................................................................................8
2.8.3 Zero Flag (Z Flag) ......................................................................................................8
2.8.4 Sign Flag (S Flag) ......................................................................................................8
2.8.5 Register Bank Select Flag (B Flag) ..........................................................................8
2.8.6 Overflow Flag (O Flag) .............................................................................................. 8
2.8.7 Interrupt Enable Flag (I Flag)....................................................................................8
2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 8
2.8.9 Processor Interrupt Priority Level (IPL) .................................................................. 8
2.8.10 Reserved Area..........................................................................................................8
Chapter 3. Memory................................................................ 9
Chapter 4. Special Function Registers (SFR)................... 10
Chapter 5. Reset.................................................................. 14
5.1 Hardware Reset ............................................................................................................ 14
5.1.1 Hardware Reset 1..................................................................................................................................14
5.1.2 Hardware Reset 2..................................................................................................................................17
5.1.3 Power-on Reset Function..................................................................................................................... 18
5.2 Software Reset..............................................................................................................19
5.3 Watchdog Timer Reset.................................................................................................19
A-1
5.4 Voltage Detection Circuit .............................................................................................20
5.4.1 Voltage Detection Interrupt ..................................................................................................................25
5.4.2 Get Out Of Stop Mode Due To The Voltage Detection Interrupt .......................................................27
Chapter 6. Clock Generating Circuit.................................. 28
6.1 Main Clock.....................................................................................................................33
6.2 Ring Oscillator Clock ...................................................................................................34
6.2.1 Low-speed Ring Oscillator................................................................................................................... 34
6.2.2 High-speed Ring Oscillator..................................................................................................................34
6.3 CPU Clock and Peripheral Function Clock ................................................................ 35
6.3.1 CPU Clock..............................................................................................................................................35
6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO, fRING, fRING128) ................35
6.3.3 fRING and fRING128 .............................................................................................................................35
6.3.4 fRING-fast ..............................................................................................................................................35
6.4 Power Control ...............................................................................................................36
6.4.1 Normal Operation Mode .......................................................................................................................36
6.4.2 Wait Mode ..............................................................................................................................................38
6.4.3 Stop Mode..............................................................................................................................................39
6.5 Oscillation Stop Detection Function...........................................................................42
6.5.1 How to Use Oscillation Stop Detection Function ..............................................................................42
Chapter 7. Protection.......................................................... 44
Chapter 8. Processor Mode................................................ 45
8.1 Types of Processor Mode ............................................................................................45
Chapter 9. Bus Control ....................................................... 46
Chapter 10. Interrupt........................................................... 47
10.1 Interrupt Overview......................................................................................................47
10.1.1 Type of Interrupts................................................................................................................................47
10.1.2 Software Interrupts .............................................................................................................................48
10.1.3 Hardware Interrupts............................................................................................................................49
10.1.4 Interrupts and Interrupt Vector..........................................................................................................50
10.1.5 Interrupt Control .................................................................................................................................52
______
10.2 INT Interrupt ................................................................................................................60
10.2.1 INT0 Interrupt ......................................................................................................................................60
10.2.2 INT0 Input Filter...................................................................................................................................61
10.2.3 INT1 Interrupt and INT2 Interrupt ......................................................................................................62
10.2.4 INT3 Interrupt ......................................................................................................................................63
________
_______
______ ______
______
10.3 Key Input Interrupt ..................................................................................................... 65
10.4 Address Match Interrupt ............................................................................................ 66
Chapter 11. Watchdog Timer.............................................. 68
Chapter 12. Timers.............................................................. 70
12.1 Timer X ........................................................................................................................ 71
A-2
12.1.1 Timer Mode..........................................................................................................................................73
12.1.2 Pulse Output Mode .............................................................................................................................74
12.1.3 Event Counter Mode ...........................................................................................................................75
12.1.4 Pulse Width Measurement Mode.......................................................................................................76
12.1.5 Pulse Period Measurement Mode..................................................................................................... 78
12.2 Timer Y.........................................................................................................................80
12.2.1 Timer Mode..........................................................................................................................................83
12.2.2 Programmable Waveform Generation Mode ....................................................................................85
12.3 Timer Z......................................................................................................................... 88
12.3.1Timer Mode...........................................................................................................................................91
12.3.2 Programmable Waveform Generation Mode ....................................................................................93
12.3.3 Programmable One-shot Generation Mode...................................................................................... 95
12.3.4 Programmable Wait One-shot Generation Mode .............................................................................98
12.4 Timer C ...................................................................................................................... 101
12.4.1 Input Capture Mode .........................................................................................................................105
12.4.2 Output Compare Mode ....................................................................................................................107
Chapter 13. Serial I/O ........................................................ 109
13.1 Clock Synchronous Serial I/O Mode....................................................................... 114
13.1.1 Polarity Select Function ................................................................................................................... 117
13.1.2 LSB First/MSB First Select Function ..............................................................................................117
13.1.3 Continuous Receive Mode ............................................................................................................... 118
13.2 Clock Asynchronous Serial I/O (UART) Mode ....................................................... 119
13.2.1 TxD10/RxD1 Select Function (UART1)............................................................................................122
13.2.2 TxD11 Select Function (UART1) ......................................................................................................122
Chapter 14. A-D Converter ............................................... 123
14.1 One-shot Mode ......................................................................................................... 127
14.2 Repeat Mode ............................................................................................................. 129
14.3 Sample and Hold ......................................................................................................131
Chapter 15. Programmable I/O Ports .............................. 132
15.1 Description................................................................................................................132
15.2 Unassigned Pin Handling ........................................................................................140
Chapter 16. Electrical Characteristics.............................141
Chapter 17. Flash Memory Version ................................. 148
17.1 Overview.................................................................................................................... 148
17.2 Memory Map.............................................................................................................. 149
17.3 Functions To Prevent Flash Memory from Rewriting............................................150
17.3.1 ID Code Check Function ..................................................................................................................150
17.4 CPU Rewrite Mode.................................................................................................... 151
17.4.1 EW0 Mode..........................................................................................................................................152
17.4.2 EW1 Mode..........................................................................................................................................152
A-3
17.4.3 Software Commands ........................................................................................................................158
17.4.4 Status Register..................................................................................................................................162
17.4.5 Full Status Check..............................................................................................................................163
17.5 Standard Serial I/O Mode .........................................................................................165
17.5.1 ID Code Check Function ..................................................................................................................165
Chapter 18. On-chip Debugger ........................................ 169
18.1 Address Match Interrupt .......................................................................................... 169
18.2 Single Step Interrupt ................................................................................................169
18.3 UART1........................................................................................................................169
18.4 BRK Instruction ........................................................................................................169
Chapter 19. Usage Notes.................................................. 170
19.1 Stop Mode and Wait Mode.......................................................................................170
19.2 Interrupts...................................................................................................................170
19.2.1 Reading Address 0000016................................................................................................................170
19.2.2 SP Setting ..........................................................................................................................................170
19.2.3 External Interrupt and Key Input Interrupt .....................................................................................170
19.2.4 Watchdog Timer Interrupt ................................................................................................................170
19.2.5 Changing Interrupt Source ..............................................................................................................170
19.2.6 Changing Interrupt Control Register ..............................................................................................172
19.3 Timers........................................................................................................................173
19.3.1 Timers X, Y and Z..............................................................................................................................173
19.3.2 Timer X...............................................................................................................................................173
19.3.3 Timer Z ...............................................................................................................................................173
19.3.4 Timer C...............................................................................................................................................173
19.4 Serial I/O ....................................................................................................................174
19.5 A-D Converter ...........................................................................................................175
19.6 Flash Memory Version .............................................................................................176
19.6.1 CPU Rewrite Mode ............................................................................................................................176
19.7 Noise..........................................................................................................................178
Chapter 20. Usage Notes for On-chip Debugger............ 179
Appendix 1 Package Dimensions.................................... 180
Appendix 2 Connecting Examples for Serial Writer and
On-chip Debugging Emulator .......................................... 181
Register Index ................................................................... 183
R8C/11 Group Usage Note Reference Book
For the most current Usage Note Reference Book, please visit our website.
A-4
SFR Page Reference
Address
000016
000116
000216
000316
000416
Processor mode register 0 PM0 45
000516
Processor mode register 1 PM1 45
000616
System clock control register 0 CM0 30
000716
System clock control register 1 CM1 30
000816
High-speed ring control register 0 HR0 32
000916
Address match interrupt enable register AIER 67
000A16
Protect register PRCR 44
000B16
High-speed ring control register 1 HR1 32
000C16
Oscillation stop detection register OCD 31
000D16
Watchdog timer reset register WDTR 69
000E16
Watchdog timer start register WDTS 69
000F16
Watchdog timer control register WDC 69
001016
Address match interrupt register 0 RMAD0 67
001116
001216
001316
001416
Address match interrupt register 1 RMAD1 67
001516
001616
001716
001816
001916
Voltage detection register 1 VCR1 21
001A16
Voltage detection register 2 VCR2 21
001B16
001C16
001D16
001E16
INT0 input filter select register INT0F 60
001F16
Voltage detection interrupt register D4INT 22
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Register Symbol
Page
Address
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
Key input interrupt control register KUPIC 53
004E
16
A-D conversion interrupt control register ADIC 53
004F
16
0050
16
Compare 2 interrupt control register
0051
16
UART0 transmit interrupt control register
0052
16
UART0 receive interrupt control register
0053
16
UART1 transmit interrupt control register
0054
16
UART1 receive interrupt control register
0055
16
INT2 interrupt control register INT2IC 53
0056
16
Timer X interrupt control register TXIC 53
0057
16
Timer Y interrupt control register TYIC 53
0058
16
Timer Z interrupt control register TZIC 53
0059
16
INT1 interrupt control register INT1IC 53
005A
16
INT3 interrupt control register INT3IC 53
005B
16
Timer C interrupt control register TCIC 53
005C
16
Compare 1 interrupt control register
005D
16
INT0 interrupt control register INT0IC 53
005E
16
005F
16
0060
16
0061
16
0062
16
0063
16
0064
16
0065
16
0066
16
0067
16
0068
16
0069
16
006A
16
006B
16
006C
16
006D
16
006E
16
006F
16
0070
16
0071
16
0072
16
0073
16
0074
16
0075
16
0076
16
0077
16
0078
16
0079
16
007A
16
007B
16
007C
16
007D
16
007E
16
007F
16
Register Symbol
Page
CMP2IC 53
S0TIC 53
S0RIC 53
S1TIC 53
S1RIC 53
CMP1IC 53
Blank columns are all reserved space. No use is allowed.
B-1
SFR Page Reference
Address
0080
16
Timer Y, Z mode register TYZMR 80/88
Prescaler Y PREY 81
0081
16
0082
16
Timer Y secondary TYSC 81
Timer Y primary TYPR 81
0083
16
0084
16
Timer Y, Z waveform output control register PUM 82/90
0085
16
Prescaler Z PREZ 89
Timer Z secondary TZSC 89
0086
16
Timer Z primary TZPR 89
0087
16
0088
16
0089
16
008A
16
Timer Y, Z output control register TYZOC 81/89
Timer X mode register TXMR 71
008B
16
008C
16
Prescaler X PREX 72
Timer X register TX 72
008D
16
Count source set register TCSS
008E
16
008F
16
0090
16
Timer C register TC 103
0091
16
0092
16
0093
16
0094
16
0095
16
0096
16
External input enable register INTEN 60
0097
16
Key input enable register KIEN 65
0098
16
0099
16
Timer C control register 0 TCC0 103
009A
16
Timer C control register 1 TCC1 104
009B
16
009C
16
Capture and compare 0 register TM0 103
009D
16
009E
16
Compare 1 register TM1 103
009F
16
00A0
16
UART0 transmit/receive mode register U0MR 112
00A1
16
UART0 bit rate generator U0BRG 111
00A2
16
UART0 transmit buffer register U0TB 111
00A3
16
00A4
16
UART0 transmit/receive control register 0 U0C0 112
00A5
16
UART0 transmit/receive control register 1 U0C1 111
00A6
16
UART0 receive buffer register U0RB 111
00A7
16
UART1 transmit/receive mode register U1MR 112
00A8
16
UART1 bit rate generator U1BRG 111
00A9
16
00AA
16
UART1 transmit buffer register U1TB 111
00AB
16
UART1 transmit/receive control register 0 U1C0 112
00AC
16
UART1 transmit/receive control register 1 U1C1 113
00AD
16
00AE
16
UART1 receive buffer register U1RB 111
00AF
16
00B0
16
UART
00B1
00B2
00B3
00B4
00B5
00B6
00B7
00B8
00B9
00BA
00BB
00BC
00BD
00BE
00BF
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
transmit/receive control register 2 UCON 113
Register Symbol
Page
72/82/90
Blank columns are all reserved space. No use is allowed.
Address
00C0
00C1
00C2
00C3
00C4
00C5
00C6
00C7
00C8
00C9
00CA
00CB
00CC
00CD
00CE
00CF
00D0
00D1
00D2
00D3
00D4
00D5
00D6
00D7
00D8
00D9
00DA
00DB
00DC
00DD
00DE
00DF
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
00E9
00EA
00EB
00EC
00ED
00EE
00EF
00F0
00F1
00F2
00F3
00F4
00F5
00F6
00F7
00F8
00F9
03FA
00FB
00FC
00FD
00FE
00FF
01B3
01B4
01B5
01B6
01B7
16
Register Symbol
A-D register AD 126
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
A-D control register 2 ADCON2 126
16
16
A-D control register 0 ADCON0 125
16
A-D control register 1 ADCON1 125
16
16
16
16
16
16
16
16
16
Port P0 register P0 138
16
Port P1 register P1 138
16
Port P0 direction register PD0 138
16
Port P1 direction register PD1 138
16
16
Port P3 register P3 138
16
16
Port P3 direction register PD3 138
16
Port P4 register P4 138
16
16
Port P4 direction register PD4 138
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Pull-up control register 0 PUR0 139
16
Pull-up control register 1 PUR1 139
16
Port P1 drivability control register DRR 139
16
Timer C output control register TCOUT 104
16
Flash memory control register 4 FMR4 144
16
16
Flash memory control register 1 FMR1 144
16
16
Flash memory control register 0 FMR0 143
Page
B-2
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU
core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing
instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial
equipment, audio, etc.
1. Overview
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.0.91 2003 Sep 08 page 1 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
1.2 Performance Outline
Table 1.1. lists the performance outline of this MCU.
Table 1.1 Performance outline
Item Performance
CPU Number of basic instructions 89 instructions
Shortest instruction execution time
Operating mode Single-chip
Address space 1M bytes
Memory capacity See Table 1.2.
Peripheral Interrupt Internal: 10 sources, External: 5 sources,
function Software: 4 sources, Priority level: 7 levels
Watchdog timer 15 bits x 1 (with prescaler)
Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Serial I/O •1 channel
A-D converter 10-bit A-D converter: 1 circuit, 12 channels
Clock generation circuit 2 circuits
Oscillation stop detection function
Voltage detection circuit Included
Power on reset circuit Included
Port Input/Output: 22 (including LED drive port), Input: 2
Electrical Power supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ)
characteristics
Power consumption TBD (VCC = 5.0 V, (f(XIN) = 20 MHZ)
Flash memory
Program/erase voltage VCC = 2.7 to 5.5 V
Number of program/erase 100 times
Operating ambient temperature -20 to 85 °C
Package 32-pin plastic mold LQFP
Option: If you require this option, please specify so.
50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)
Timer Z: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel
Circuits of input capture and output compare.
Clock synchronous, UART
•1 channel
UART
•Main clock generation circuit (Equipped with a built-in
feedback resistor)
•Ring oscillator (high speed, low speed)
On High-speed ring oscillator the frequency adjustment
function is usable.
Stop detection of main clock oscillation
(LED drive I/O port: 8, max. 20 mA)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ)
TBD (VCC = 3.0 V, (f(XIN) = 10 MHZ)
TBD (VCC = 3.0 V, Wait mode)
TBD (VCC = 3.0 V, Stop mode)
-40 to 85 °C (option)
1. Overview
Rev.0.91 2003 Sep 08 page 2 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
1. Overview
I/O port
Port P0
Peripheral functions
T i m e r
T i m e r X ( 8 b i t s )
T i m e r Y ( 8 b i t s )
T i m e r Z ( 8 b i t s )
T i m e r C ( 1 6 b i t s )
W a t c h d o g t i m e r
( 1 5 b i t s )
8
8
Port P1
A-D converter
(10 bits ✕ 12 channels)
UART or Clock synchronous
serial I/O
(8 bits ✕ 1 channel)
UART
(8 bits ✕ 1 channel)
R 8 C S e r i e s C P U c o r e
R0LR0H
R 1 HR1L
R2
R3
A0
A 1
FB
5
P o r t P 3
System clock generator
High-speed ring oscillator
Low-speed ring oscilla tor
S B
USP
I S P
INTB
PC
FLG
X
IN-XOUT
M e m o r y
M u l t i p l i e r
1 2
Port P4
ROM
(Note 1)
RAM
(Note 2)
Figure 1.1 Block Diagram
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Rev.0.91 2003 Sep 08 page 3 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.4 Product Information
Table 1.2 lists the products.
1. Overview
Table 1.2 Product List
RAM capacityR O M c a p a c i t yP
R 5 F 2 1 1 1 2 F P
R 5 F 2 1 1 1 3F P
R 5 F 2 1 1 1 4 F P
* *
* *
6 8 b y t e
K b y t e
* *
R 5 F 2 1 1 1 2 D F P3
R 5 F 2 1 1 1 3 DF P
R5F21114DFP
: U n d e r d e v e l o p m e n t
* *
* *
* *
8K byt es 5 1 2 b y t e s
6 8 b y t e
K b y t e
a c k a g e t y p
3 2P 6 U - A8K byt es 5 1 2 b y t e s
3 2P 6 U - A1 2 K b y t e s7
s
3 2P 6 U - A1 6 K b y t e s1
s
2P 6 U -
3 2P 6 U - A1 2 K b y t e s7
s
3 2P 6 U - A1 6 K b y t e s1
s
A
e m a r k
eR
F l a s h m e m o r y v e r s i o n
D v e r s i o n
A s o f S e p t e m b e r 2 0 0 3
sT y p e N o .
* *
Type No. R 5 F 21 11 4 D FP
Package type:
FP : 32P6U
Shows characteristics and others.
D: Operating ambient temperature –40 °C to 85 °C
No symbol: Operating ambient temperature –20 °C to 85 °C
ROM capacity:
2 : 8 KBytes.
3 : 12 KBytes.
4 : 16 KBytes.
R8C/11 group
R8C/Tiny series
Memory type:
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.0.91 2003 Sep 08 page 4 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
N0
07/
P
A
1. Overview
12
10
11
R1/
N
CI
F
T
T/
R0/
ZO
S
C
VC
I
1/
30/
VS
3
C N T
P
C M P
U
C M P
A
E
T
P
T3/
T2/
VR
C/
33/
32/
VC
I N
I N
C N T
P
P
C M P
A
P 06/ A N1
P 05/ A N2
P04/AN3
P 03/ A N4
P 02/ A N5
P01/AN6
P 00/ A N7/T x D1
MODE
2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7
2 5
2 6
2 7
2 8
R8C/11 Group
2 9
3 0
3 1
3 2
1
1 6
1 5
1 4
1 3
1 2
1 1
1 0
P45/INT0
P10/KI0/AN8/CMP00
P11/KI1/AN9/CMP01
P12/KI2/AN10/CMP02
P13/KI3/AN11
P14/TxD0
P 15/ R x D0
9
P16/CLK0
1 2 3 4 5 6 7 8
)
S
S
T
D1
VS
0/
C
D1
N
37/
P
R x
T x
R
E S E
47
T/
XO
U
P
(N o t e 1
C
46
C
VS
P
R0
V
N/
XI
T1/
17/
P
I N
C N T
N o t e s :
1 . P 4
7
f u n c t i o n s o n l y a s a n i n p u t p o r t .
2. W h e n u s i n g O n - c h i p d e b u g g e r , d o n o t u s e p i n s P 0
a n d P 37/ T x D
1 0
/ R x D1.
0
/ A N7/ T x D
1 1
Package: 32P6U-A
Figure 1.3 Pin Configuration (Top View)
Rev.0.91 2003 Sep 08 page 5 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
Signal name Pin name I/O type
Power supply Vcc, Input
input Vss
IVcc IVcc Output
Analog power AVcc, AVss Input
supply input
Reset input
CNVss CNVss Input
MODE MODE Input
Main clock input XIN Input
Main clock output XOUT Output
_____
INT interrupt input
Key input interrupt
input
Timer X CNTR0 Input/Output
Timer Y CNTR1 Input/Output
Timer Z TZOUT Output
Timer C TCIN Input
Serial interface CLK0 Input/Output
Reference voltage VREF Input
input
A-D converter AN0 to AN11 Input
I/O port P00 to P07, Input/Output
Input port P46, P47 Input
___________
RESET Input
_______ _______
INT0 to INT3 Input
_____ _____
KI0 to KI3 Input
__________
CNTR0 Output
CMP00 to CMP03,
Output
CMP10 to CMP13
RxD0, RxD1 Input
TxD0, TxD10, Output
TxD11
P10 to P17,
P30 to P33, P37,
P45
1. Overview
Function
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
Connect this pin to Vss via a capacitor (0.1 µF).
These are power supply input pins for A-D converter.
Connect the AVss pin to Vss. Connect a capacitor
between pins AVcc and AVss.
“L” on this input resets the MCU.
Connect this pin to Vss via a resistor (approximately 5 kΩ).
Connect this pin to Vcc via a resistor (approximately 5 kΩ).
These pins are provided for the main clock generating circuit input/output. Connect a ceramic resonator
or a crystal oscillator between the XIN and XOUT pins.
To use an externally derived clock, input it to the XIN
pin and leave the XOUT pin open.
______
These are INT interrupt input pins.
These are key input interrupt input pins.
This is the timer X I/O pin.
This is the timer X output pin.
This is the timer Y I/O pin.
This is the timer Z output pin.
This is the timer C input pin.
These are the timer C output pins.
This is a transfer clock I/O pin.
These are serial data input pins.
These are serial data output pins.
This is a reference voltage input pin for A-D converter.
These are analog input pins for A-D converter.
These are 8-bit CMOS I/O ports. Each port has an
input/output select direction register, allowing each
pin in that port to be directed for input or output individually.
Any port set to input can select whether to use a pullup resistor or not by program.
P10 to P17 also function as LED drive ports.
These are input only pins.
Rev.0.91 2003 Sep 08 page 6 of 184
Under development
g
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
R2
R3
b15
R0H(R0's high bits)
R1H(R1's high bits)
b19
b15
INTBH
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
PC
b15
b15
b15
b7 b8
IPL
b8 b7 b0
R0L(R0's low bits)
R1L(R1's low bits)
R2
R3
A0
A1
FB
INTBL
USP
ISP
SB
FLG
Data registers (Note 1)
Address registers (Note 1)
Frame base registers (Note 1)
b0
Interrupt table register
b0
Program counter
b0
User stack pointer
Interrupt stack pointer
Static base register
b0
Flag register
b0
CDZSBOIU
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note 1: These re
isters comprise a register bank. There are two register banks.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
Rev.0.91 2003 Sep 08 page 7 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
Rev.0.91 2003 Sep 08 page 8 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
3. Memory
Figure 3.1 is a memory map of this MCU. The address space extends the 1M bytes from address 0000016
to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address 0FFFF16. For example,
a 16-Kbyte internal ROM is allocated to the addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated to the addresses from 0FFDC16 to 0FFFF16. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 1-Kbyte internal RAM is allocated to the addresses from 0040016 to 007FF16. In addition to storing data,
the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
Special function registers (SFR) are allocated to the addresses from 0000016 to 002FF16. Peripheral function control registers are located here. Of the SFR, any space which has no functions allocated is reserved
for future use and cannot be used by users.
3. Memory
0000016
SFR
(See Chapter 4 for details.)
002FF16
0040016
Internal RAM
0XXXX16
0YYYY16
Internal ROM
0FFFF16
Expanding area
FFFFF16
Type name
R5F21114FP, R5F21114DFP
R5F21113FP, R5F21113DFP
R5F21112FP, R5F21112DFP
Size
16K bytes
12K bytes
8K bytes
0FFDC16
0FFFF16
Internal ROM
Address 0YYYY
0C00016
0D000
0E00016
Undefined instruction
Overflow
BRK instruction
Address match
Watchdog timer,Oscillation stop detection,Voltage detection
Single step
(Reserved)
(Reserved)
Reset
Internal RAM
16
Size
1K bytes
16
768 bytes
512 bytes
Address 0XXXX16
007FF16
006FF
16
005FF16
Figure 3.1 Memory Map
Rev.0.91 2003 Sep 08 page 9 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
4. Special Function Register (SFR)
4. Special Function Register (SFR)
A d d r e s s
0 0 0 0
1 6
0 0 0 1
1 6
0 0 0 2
1 6
0 0 0 3
1 6
M
P r o c e s s o r m o d e r e g i s t e r 0P
0 0 0 4
1 6
M
0 0 0 5
1 6
P r o c e s s o r m o d e r e g i s t e r 1P
M
1 1 0 1 0 0
0 0 0 6
1 6
S y s t e m c l o c k c o n t r o l r e g i s t e r 0C
M
0 1 0 0 0 0
0 0 0 7
1 6
S y s t e m c l o c k c o n t r o l r e g i s t e r 1C
R
0 0 0 8
1 6
H i g h - s p e e d r i n g c o n t r o l r e g i s t e r 0H
I E
X X X X X 0
0 0 0 9
1 6
A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e rA
R C
0 X X X 0 0
0 0 0 A
1 6
P r o t e c t r e g i s t e rP
R
0 0 0 B
1 6
H i g h - s p e e d r i n g c o n t r o l r e g i s t e r 1H
C
0 0 0 0 1 0
0 0 0 C
1 6
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO
D T
0 0 0 D
1 6
W a t c h d o g t i m e r r e s e t r e g i s t e rW
D T
0 0 0 E
1 6
W a t c h d o g t i m e r s t a r t r e g i s t e rW
D
0 0 X X X X
0 0 0 F
1 6
W a t c h d o g t i m e r c o n t r o l r e g i s t e rW
M A D
0 0 1 0
1 6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0R
0 0 1 1
1 6
0 0 1 2
1 6
0 0 1 3
1 6
M A D
0 0 1 4
1 6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R
0 0 1 5
1 6
0 0 1 6
1 6
0 0 1 7
1 6
0 0 1 8
1 6
C R
0 0 1 9
1 6
V o l t a g e d e t e c t i o n r e g i s t e r 1V
0 0 1 A
1 6
Voltage detection register 2 VCR2 10000000
0 0 1 B
1 6
0 0 1 C
1 6
0 0 1 D
1 6
0 0 1 E
1 6
INT0 input filter select register INT0F XXXXX000
0 0 1 F
1 6
Voltage detection interrupt register D4INT 00
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
X : U n d e f i n e d
B l a n k c o l u m n s a r e a l l r e s e r v e d s p a c e . N o a c c e s s i s a l l o w e d .
N o t e s :
1. S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t b i t s 0 t o 1 o f P M 0 r e g i s t e r .
2 . S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r .
3 . O w i n g t o R e s e t i n p u t .
4 . I n t h e c a s e o f
R E S E T
p i n = “ H ” r e t a i n i n g .
Register Symbol After reset
1
2
2
2
00
10
00
10
00
RX
R0
14
D0
RX
SX
C0
00
10
10
0 0
X 0
0 0
X 0
0
1 6
0
1 6
0
2
0
2
0
1 6
0
2
0
0
0
2
1 6
0
2
X
1 6
X
1 6
X
2
1 6
1 6
1 6
0
1 6
1 6
1 6
0
1 6
16
2
3
16
01000001
4
2
Rev.0.91 2003 Sep 08 page 10 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR)
Address
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
004A
004B
004C
004D
004E
004F
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005A
005B
005C
005D
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
006A
006B
006C
006D
006E
006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007C
007D
007E
007F
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Key input interrupt control register KUPIC XXXXX000
16
A-D conversion interrupt control register ADIC XXXXX000
16
16
Compare 2 interrupt control register
16
UART0 transmit interrupt control register
16
UART0 receive interrupt control register
16
UART1 transmit interrupt control register
16
UART1 receive interrupt control register
16
INT2 interrupt control register INT2IC XXXXX000
16
Timer X interrupt control register TXIC XXXXX000
16
Timer Y interrupt control register TYIC XXXXX000
16
Timer Z interrupt control register TZIC XXXXX000
16
INT1 interrupt control register INT1IC XXXXX000
16
INT3 interrupt control register INT3IC XXXXX000
16
Timer C interrupt control register TCIC XXXXX000
16
Compare 1 interrupt control register
16
INT0 interrupt control register INT0IC XX00X000
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Register Symbol After reset
X : Undefined
Blank columns are all reserved space. No access is allowed.
CMP2IC XXXXX000
S0TIC XXXXX000
S0RIC XXXXX000
S1TIC XXXXX000
S1RIC XXXXX000
CMP1IC XXXXX000
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev.0.91 2003 Sep 08 page 11 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR)
Address
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
008A
008B
008C
008D
008E
008F
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
009A
009B
009C
009D
009E
009F
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
00A8
00A9
00AA
00AB
00AC
00AD
00AE
00AF
00B0
00B1
00B2
00B3
00B4
00B5
00B6
00B7
00B8
00B9
00BA
00BB
00BC
00BD
00BE
00BF
16
Timer Y, Z mode register TYZMR 00
16
Prescaler Y PREY FF
16
Timer Y secondary TYSC FF
Timer Y primary TYPR FF
16
Timer Y, Z waveform output control register PUM 00
16
16
Prescaler Z PREZ FF
Timer Z secondary TZSC FF
16
Timer Z primary TZPR FF
16
16
16
Timer Y, Z output control register TYZOC 00
16
Timer X mode register TXMR 00
16
16
Prescaler X PREX FF
Timer X register TX FF
16
Count source set register TCSS 00
16
16
16
Timer C register TC 00
16
16
16
16
16
16
External input enable register INTEN 00
16
Key input enable register KIEN 00
16
16
16
Timer C control register 0 TCC0 00
16
Timer C control register 1 TCC1 00
16
Capture, compare 0 register TM0 XX
16
16
Compare 1 register TM1 XX
16
16
UART0 transmit/receive mode register
16
UART0 bit rate generator U0BRG XX
16
UART0 transmit buffer register U0TB XX
16
16
UART0 transmit/receive control register 0
16
UART0 transmit/receive control register 1
16
UART0 receive buffer register U0RB XX
16
16
UART1 transmit/receive mode register
16
UART1 bit rate generator U1BRG XX
16
UART1 transmit buffer register U1TB XX
16
16
UART1 transmit/receive control register 0
16
UART1 transmit/receive control register 1
16
UART1 receive buffer register U1RB XX
16
16
UART transmit/receive control register 2
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Register Symbol After reset
X : Undefined
Blank columns are all reserved space. No access is allowed.
16
16
16
16
16
16
16
16
16
16
16
16
16
16
00
16
16
16
16
16
16
XX
16
16
XX
U0MR 00
16
16
16
16
XX
16
U0C0 00001000
U0C1 00000010
16
XX
U1MR 00
16
16
16
16
XX
16
U1C0 00001000
U1C1 00000010
16
XX
16
UCON 00
16
2
2
2
2
Rev.0.91 2003 Sep 08 page 12 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR)
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
03FA16
00FB16
00FC16
00FD16
00FE16
00FF16
Register
A-D register AD XX
A-D control register 2 ADCON2 00
Symbol After reset
16
XX
16
16
A-D control register 0 ADCON0 00000XXX
A-D control register 1 ADCON1 00
Port P0 register P0 XX
Port P1 register P1 XX
Port P0 direction register PD0 00
Port P1 direction register PD1 00
Port P3 register P3 XX
Port P3 direction register PD3 00
Port P4 register P4 XX
Port P4 direction register PD4 00
16
16
16
16
16
16
16
16
16
Pull-up control register 0 PUR0 00XX0000
Pull-up control register 1 PUR1 XXXXXX0X
Port P1 drivability control register DRR 00
Timer C output control register TCOUT 00
16
16
2
2
2
Flash memory control register 4 FMR4 0100000X
01B316
01B416
01B516
Flash memory control register 1 FMR1 0100XX0X
01B616
01B716
Flash memory control register 0 FMR0 XX000001
X : Undefined
Blank columns are all reserved space. No access is allowed.
Rev.0.91 2003 Sep 08 page 13 of 184
2
2
2
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Reset
There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset.
5.1 Hardware Reset
There are three kinds of hardware reset: hardware reset 1, hardware reset 2, and power-on reset.
5.1 Hardware Reset
5.1.1 Hardware Reset 1
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the
power supply voltage is within the recommended operating condition, the pins are initialized (see
Table 5.1 “Pin Status When RESET Pin Level is 'L'”). When the input level at the RESET pin is
released from “L” to “H”, the CPU and SFR are initialized, and the program is executed starting
from the address indicated by the reset vector. Figure 5.1 shows the CPU register status after
reset and figure 5.2 shows the reset sequence. The internal RAM is not initialized. If the RESET
pin is pulled “L” while writing to the internal RAM, the internal RAM becomes indeterminate.
Figures 5.3 to 5.4 show the reset circuit example using the hardware reset 1. Refer to Chapter 4,
“Special Function Register (SFR)” for the status of SFR after reset.
• When the power supply is stable
(1) Apply an “L” signal to the RESET pin.
(2) Wait 500 µs.
(3) Apply an “H” signal to the RESET pin.
• Power on
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condi-
tion.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Wait 500 µs.
(5) Apply an “H” signal to the RESET pin.
____________ ____________
____________ ____________
____________
____________
____________
____________
____________
detection circuit monitors the voltage supplied to the VCC pin.
Table 5.1 Pin Status When RESET Pin Level is “L”
____________
Pin name
P0
P1
P3
0 to P33, P37
P45 to P47
Rev.0.91 2003 Sep 08 page 14 of 184
Input port
Input port
Input port
Input port
Status
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.1 Hardware Reset
b15
0000
16
0000
16
0000
16
0000
16
0000
16
0000
16
0000
16
b19
00000
16
Content of addresses 0FFFE16 to 0FFFC
b15
16
0000
0000
16
0000
16
16
b0
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
b0
Interrupt table register(INTB)
Program counter(PC)
b0
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
b15
0000
b15
b7 b8
IPL
Figure 5.1 CPU Register Status After Reset
Internal ring
oscillation
RESET
CPU clock
Address
(Internal address
signal)
More than 20 cycles are needed
CPU clock: 28cycles
16
0FFFC
16
0FFFD
b0
Flag register(FLG)
b0
CDZSBOIU
0FFFE
16
16
Content of reset vector
Figure 5.2 Reset Sequence
Rev.0.91 2003 Sep 08 page 15 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.1 Hardware Reset
V
CC
2.7V
0 V
V
R E S E T
CC
R E S E T
0V
Figure 5.3 Example Reset Circuit Using The Hardware Reset 1
5V
2.7V
RESET
V
CC
V
CC
Supply voltage
detection circuit
0V
5V
Equal to or less
than 0.2V
CC
M o r e t h a n t d ( P - R ) + 5 0 0 µ s a r e
n e e d e d .
RESET
0V
More than td(P-R) + 500 µs
are needed.
Example when V
CC
= 5V
.
Figure 5.4 Example Reset Circuit Using The Hardware Reset 1 (Voltage Check Circuit)
Rev.0.91 2003 Sep 08 page 16 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.1.2 Hardware Reset 2
The microcomputer is reset when the voltage at the VCC input pin drops below Vdet if all of the
following conditions hold true.
• The VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled)
• The D40 bit in the D4INT register is set to “1” (voltage detection interrupt enabled)
• The D46 bit in the D4INT register is set to “1” (hardware reset 2 when going through Vdet)
Conversely, when the input voltage at the VCC pin rises to Vdet or more, the pins, CPU, and SFR are
initialized, and the program is executed starting from the address indicated by the reset vector. The
initialized pins and registers and the status thereof are the same as in hardware reset 1. Refer to
Section 5.4 “Voltage Detection Circuit.”
5.1 Hardware Reset
Rev.0.91 2003 Sep 08 page 17 of 184
Under development
R8C/11 Group
5.1.3 Power-on Reset Function
The power-on reset is the function which can reset the microcomputer without the external reset
circuit. The RESET pin should be connected to the VCC pin via about 5 kΩ pull-up resistance using
the power-on reset function, the function turns to active.
When the input voltage at the VCC pin reaches to the Vdet level, count operation of the low-speed
ring oscillator clock starts. When the operation counts the low-speed ring oscillator clock for 32 times,
the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting
from the address indicated by the reset vector. The initialized pins and registers and the status
thereof are the same as in hardware reset 1.
• The D40 bit in the D4INT register turns to “1” automatically (voltage detection interrupt enabled)
• The D46 bit in the D4INT register turns to “1” automatically (hardware reset 2 when going through
Vdet)
Additionally, the hardware reset 2 turns to active after the power-on reset. This is because the VC27
bit in the VCR2 register is set to “1” (voltage detection circuit enabled) after the power-on reset same
as the hardware reset 1, so that hardware reset 2 active conditions are all satisfied including above
D40 and D46 bit conditions.
Preliminary specification
Specifications in this manual are tentative and subject to change.
____________
5.1 Hardware Reset
Figure 5.5 shows the power-on reset circuit. Figure 5.6 shows the power-on reset operation.
RESET
5 bit
counter
V
CC ≥
f
RING-S
Vdet detection
Figure 5.5 Power-on Reset Circuit
Trigger
Internal reset signal
Q
S
R
V
C C
a b o u t
5 kΩ
c
c
I n t e r n a l r e s e t s i g n a l
R E S E TV
Figure 5.6 Power-on Reset Operation
Rev.0.91 2003 Sep 08 page 18 of 184
0.5 V
0 V
1 m s o r m o r e
2 . 7 V
Less than100 µs
1
f
R I N G - S
V d e t
x 3 2
Under development
R8C/11 Group
5.2 Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its
pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by
the reset vector.
Some SFRs are not initialized by the software reset. Refer to Chapter 4, “SFR.”
5.3 Watchdog Timer Reset
Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed starting from the address indicated by the reset vector.
Some SFRs are not initialized by the watchdog timer reset. Refer to Chapter 4, “SFR.”
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.2 Software Reset, 5.3 Watchdog Timer Reset
Rev.0.91 2003 Sep 08 page 19 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.4 Voltage Detection Circuit
5.4 Voltage Detection Circuit
The voltage detection circuit has a circuit to monitor the input voltage at the VCC pin with Vdet. Besides
the program, the hardware reset 2 and voltage detection interrupt can be used to check the input voltage
at the VCC pin.
Figure 5.7 shows the voltage detection circuit. Figure 5.8 shows VCR1 and VCR2 registers. Figure 5.9
shows the D4INT register. Figure 5.10 shows an operation example of the voltage detection circuit. Figure 5.11 to 5.12 show the operation example of the voltage detection circuit to get out of stop mode.
VC27
CC1
+
V
Noise canceller
V
REF
-
Figure 5.7 Voltage Detection Circuit Block
Voltage detection
interrupt signal
VCR1 register
b3
VC13 bit
Rev.0.91 2003 Sep 08 page 20 of 184
Under development
( b
( b
(b6-b0)
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
V o l t a g e d e t e c t i o n r e g i s t e r 1
b 7b 6b 5b 4b 3b 2b 1b 0
0000 000
Symbol Address After reset
VCR1 001916 0016
5.4 Voltage Detection Circuit
2
Bit symbol
2 - b 0 )
V C 1 3
Bit name F u n c t i o n
Reserved bit
V o l t a g e m o n i t o r f l a g
S h o u l d se t t o “ 0 ”
V d e
0 : V
1 : V
C C <
C C
1
t
≥
V d e t o r v o l t a g e
R W
R W
R O
d e t e c t i o n c i r c u i t d i s a b l e d
V d e t o r v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d ) w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t
N o t e s :
7 - b 4 )
Reserved bit
S h o u l d s e t t o “ 0 ”
R W
1 . T h e V C 1 3 b i t i s v a l i d w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o “ 1 ” ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) . T h e
V C 1 3 b i t i s s e t t o “ 1 ” ( V
C C≥
t o “ 0 ” ( v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d ) .
2 . S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r .
V o l t a g e d e t e c t i o n r e g i s t e r 2
b 7b 6b 5b 4b 3b 2b 1b 0
00000
00
1
Symbol Address After reset
VCR2 001A16 100000002
B i t s y m b o l
VC27
Reserved bit Should set to “0”
Voltage monitor bit
Bit name
2
3
Function
0: Voltage detection circuit
disabled
R W
RW
RW
1: Voltage detection circuit
enabled
N o t e s :
1 . S e t t h e P R C 3 b i t i n t h e P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e d ) b e f o r e w r i t i n g t o t h i s r e g i s t e r .
2 . S e t t h e V C 2 7 b i t t o “ 1 ” ( v o l t a g e d e t e c t c i r c u i t e n a b l e d ) w h e n h a r d w a r e r e s e t 2 i s u s e d , o r t h e V C 1 3 b i t i n t h e
V C R 1 r e g i s t e r o r D 4 2 b i t i n t h e D 4 I N T r e g i s t e r i s u s e d , o r t h e D 4 0 b i t i s s e t t o “ 1 ” ( e n a b l e d ) .
3 . S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r .
Figure 5.8 VCR1 Register and VCR2 Register
Rev.0.91 2003 Sep 08 page 21 of 184
Under development
g
b5b
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.4 Voltage Detection Circuit
Voltage detection interrupt re gis ter
d d r e s
f t e r r e s e
b 7 b 6 b5 b 4 b 3 b 2 b 1 b 0
0 1
S y m b o lA
D 4 I N T0
R E S E T p i n = " H " r e t a i n i n g : 0 1 0 0 0 0 0 1
B i t s y m b o l
D40
D41
D42
D43
DF0
DF1
D46
1
sA
F
1 6
R e s e t i n p u t : 0 0
B i t n a m e
Voltage detection interrupt
enable bit
STOP mode deactivation
control bit
Voltage change detection
flag
WDT overflow detect flag
Sampling clock select bit
Voltage monitor mode select
bit
7
2
3, 4, 5
3, 4
6
1 0
t
1 6
F u n c t i o n
0 :
Disable
1 :
Enable
0 : D i s a b l e ( d o n o t u s e t h e v o l t a g e
d e t e c t i o n i n t e r r u p t t o g e t o u t o f
s t o p m o d e )
1 : E n a b l e ( u s e t h e v o l t a g e
d e t e c t i o n i n t e r r u p t t o g e t o u t o f
s t o p m o d e )
0: Not detected
1: Vdet passing detection
0 : N o t d e t e c t e d ( f l a g c l e a r )
1 : D e t e c t e d
4
00 : f
RING-S
RING-S
RING-S
RING-S
divided by 1
divided by 2
divided by 4
divided by 8
01 : f
10 : f
11 : f
0: Voltage detection interrupt
request is generated when
passing through Vdet
2
RW
RW
RW
RW
RW
R W
RW
RW
1: Hardware reset 2 when
passing through Vdet
D47
Stop mode exiting condition
select bit
8
I n s t o p m o d e , v o l t a g e d e t e c t i o n
i n t e r r u p t r e q u e s t i s g e n e r a t e d
o r h a r d w a r e r e s e t 2
w h e n V c c p a s s e s V d e t
9
R W
0 : O v e r V d e t
t i m e r r e s e t d o n o t a f f e c t t h i s r e g i s t e r
N o t e s :
1 : B e l o w V d e t
1 . S e t t h e P R C 3 b i t i n t h e P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r .
2 . I f t h e v o l t a g e d e t e c t i o n i n t e r r u p t n e e d s t o b e u s e d t o g e t o u t o f s t o p m o d e a g a i n a f t e r o n c e u s e d f o r t h a t
p u r p o s e , r e s e t t h e D 4 1 b i t b y w r i t i n g a “ 0 ” a n d t h e n a “ 1 ” .
3. V a l i d w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o “ 1 ” ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) .
4 . I f t h e V C 2 7 b i t i s s e t t o “ 0 ” ( v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d ) , t h e D 4 2 a n d D 4 3 b i t s a r e s e t t o “ 0 ” ( n o t d e t e c t e d ) .
5 . T h i s b i t i s s e t t o “ 0 ” b y w r i t i n g a “ 0 ” i n a p r o g r a m . ( w r i t i n g a “ 1 ” h a s n o e f f e c t . )
6 . V a l i d w h e n t h e D 4 0 b i t i s s e t t o “ 1 ” ( v o l t a g e d e t e c t i o n i n t e r r u p t e n a b l e d ) .
7 . T h e D 4 0 b i t i s v a l i d w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o " 1 " ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) .
W h e n s e t t i n g t h e D 4 0 b i t t o " 1 " , t h e f o l l o w i n g s e t t i n g i s r e q u i r e d .
( 1 ) S e t t h e V C 2 7 b i t " 1 " .
( 2 ) W a i t f o r t d ( E - A ) u n t i l t h e d e t e c t e r c i r c u i t o p e r a t e s .
( 3 ) W a i t f o r t h e s a m p l i n g t i m e ( t h e s a m p l i n g c l o c k w h i c h i s s e l e c t e d i n t h e D F 0 b i t t o D F 1 b i t t i m e s 4 c y c l e s . )
( 4 ) S e t t h e D 4 0 b i t t o " 1 " .
( 5 ) S e t t h e C M 1 4 b i t i n t h e C M 1 r e g i s t e r t o " 0 " ( l o w - s p e e d r i n g o s c i l l a t o r o n ) .
8 . V a l i d w h e n t h e D 4 1 b i t i s s e t t o " 1 " ( e n a b l e ) .
9 . T h e D 4 6 b i t c a n b e s e l e c t e d .
1 0 . T h e s o f t w a r e r e s e t o r t h e w a t c h d o
.
Figure 5.9 D4INT Register
Rev.0.91 2003 Sep 08 page 22 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.4 Voltage Detection Circuit
fRING
5.0 V
1
x 32
5.0 V
V
det
CC
V
Sampling time
(3 to 4 clock)
Internal reset signal
(D46 bit=1)
VC13 bit
Set to“1” by program (voltage
detection circuit enabled)
VC27 bit
Voltage detection
interrupt request
Interrupt acknowledged
Sampling time
(3 to 4 clock)
Interrupt acknowledged
(D46 bit=0)
The above applies to the following conditions.
• D4INT register D40 bit = 1 (voltage detection interrupt enabled)
• D4INT register D41 bit = 0 (do not use voltage detection interrupt to get out of stop mode)
Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
Figure 5.10 Operation Example of Voltage Detection Circuit
Rev.0.91 2003 Sep 08 page 23 of 184
Under development
R8C/11 Group
V
CC
Internal reset signal(D46 bit = 1)
VC13 bit
VC27 bit
CM 10 bit
Voltage detection
interrupt request
(D46 bit = 0)
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.0V
V
det
Set to "1" by program (voltage detection circuit enabled)
Interrupt acknowledged
5.4 Voltage Detection Circuit
The above applies to the following conditions.
D4INT register D40 = 1 (voltage detection interrupt enabled)
D4INT register D41 = 1 (use voltage deteciton interrupt to get out of stop mode)
D4INT register D47 = 1 ( Vcc is below Vdet)
CM10 : CM1 register bit
VC13 : VCR1 register bit
VC27 : VCR2 register bit
D46 : D4INT register bit
Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
Figure 5.11 Operation Example of Voltage Detection Circuit in use to get out of stop mode (1)
5.0V
V
det
CC
V
Internal reset signal
(D46 bit = 1)
VC13 bit
Set to "1" by program (voltage detection circuit enabled)
VC27 bit
CM10 bit
Voltage detection
interrupt request
(D46 bit = 0)
1
x 32
f
RING
Interrupt acknowledged
The above applies to the following conditions.
D4INT register D40 bit = 1 (voltage detection interrupt enabled)
D4INT register D41 bit = 1 (use voltage detection interrupt to get out of stop mode)
D4INT register D47 bit = 0 (Vcc is over Vdet)
Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
CM10 : CN1 register bit
VC13 : VCR1 register bit
VC27 : VCR2 register bit
D46 : D4INT register bit
Figure 5.12 Operation Example of Voltage Detection Circuit in use to get out of stop mode (2)
Rev.0.91 2003 Sep 08 page 24 of 184
Under development
R8C/11 Group
5.4.1 Voltage Detection Interrupt
Figure 5.13 shows the block diagram of voltage detection interrupt generation circuit.
Refer to 5.4.2, "Exiting Stop Mode on a Voltage Detection Circuit" for Getting out of stop mode due to
the voltage detection interrupt.
A voltage detection interrupt is generated when the input voltage at the VCC pin rises to Vdet or more
or drops below Vdet if all of the following conditions hold true in normal operation mode and wait
mode.
• The VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled)
• The D40 bit in the D4INT register is set to “1” (voltage detection interrupt enabled)
• The D46 bit in the D4INT register is set “0” (voltage detection interrupt selected)
To use the voltage detection interrupt , set the CM14 bit in the CM1 register to "0" (low-ring oscillator).
Figure 5.14 shows an operation example of voltage detection interrupt generation circuit.
The voltage detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscillation stop detection interrupt.
The D42 bit in the D4INT register becomes “1” when passing through Vdet is detected after the voltage inputted to the VCC pin is up or down.
A voltage detection interrupt request is generated when the D42 bit changes state from “0” to “1”. The
D42 bit needs to be set to “0” in a program.
Table 5.2 lists the voltage detection interrupt request generation conditions.
It takes 4 cycles of sampling clock until the D42 bit is set to "1" since the voltage which inputs to
Vcc pin passes Vdet.
It is possible to set the sampling clock detecting that the voltage applied to the VCC pin has passed
through Vdet with the DF0 to DF1 bits in the D4INT register.
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.4 Voltage Detection Circuit
Table 5.2 Voltage Detection Interrupt Request Generation Conditions
Operation mode
Normal operation
1
mode
Wait mode
Notes:
1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to Chapter 6, "Clock
Generation Circuit.")
2. Refer to Figure 5.14, "Operation Example of Voltage Detection Interrupt Generation Circuit" for interrupt generation
timing.
VC27 bit D40 bit D42 bitD41 bit VC13 bit
1
11
1
0 or 1 0
0 or 1 0 0 0
D46 bit
0
From 0 to 1
From 1 to 0
From 0 to 1
From 1 to 0
2
2
2
2
CM14 bit
0
Rev.0.91 2003 Sep 08 page 25 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.4 Voltage Detection Circuit
Voltage detection circuit
VC27
V
CC1
+
Noise
V
REF
Watchdog timer block
D40, D41, D42, D43, DF0, DF1, D46, D47: Bits in D4INT register CM02: Bit in CM0 register
VC13: Bit in VCR1 register CM10: Bit in CM1 register
VC27: Bit in VCR2 register
canceller
(Canceller width: 200 ns)
Watchdog timer
underflow signal
Voltage detection signal
is “H” when VC27 bit= 0
(disabled)
Voltage detection interrupt generation circuit
f
RING-S
VC13
Voltage
detection
signal
CM10
D43
This bit is set to “0”(not detected) by writing a “0” in a program.
1/21/2
D47
DF1 to DF0
=00
=01
=10
=11
1/2
Noise rejection
circuit
D41
2
2
2
2
Digital
filter
Figure 5.13 Operation Detection Interrupt Generation Block
D42 bit is set to “0”(not detected)
by writing a “0” in a program.
When VC27 bit is set to “0” (
voltage detection circuit
disabled), D42 bit is set to “0” .
D42
D40
D46
Watchdog
timer interrupt
signal
Voltage
detection
interrupt signal
Oscillation stop
detection
interrupt signal
Non-maskable
interrupt signal
Hardware reset 2
VCC
VC13 bit
sampling
Output of digital filter
2
D42 bit
Voltage detection
interrupt signal
Notes:
1. D40 is “1”(voltage detection interrupt enabled).
2. Output of the digital filter shown in Figure 5.11
sampling sampling sampling
No voltage detection interrupt
signals are generated when D42 bit
is “H”.
Set D42 bit to “0”
in a program (not
detected)
Set D42 bit to “0”
in a program (not
detected)
D42: Bit in D4INT register
VC13: Bit in VCR1 register
Figure 5.14 Voltage Detection Interrupt Generation Circuit Operation Example
Rev.0.91 2003 Sep 08 page 26 of 184
Under development
R8C/11 Group
5.4.2 Exiting Stop Mode on a Voltage Detection Interrupt
A voltage detection interrupt is generated when the input voltage at the VCC pin rises to Vdet or more
or drops below Vdet if all of the following conditions hold true in stop mode.
• The VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled)
• The D40 bit in the D4INT register is set to “1” (voltage detection interrupt enabled)
• The D41 bit in the D4INT register is set “1” (voltage detection used to get out of stop mode)
• The D46 bit in the D4INT register is set “0” (voltage detection interrupt selected)
To use the voltage detection interrupt , set the CM14 bit in the CM1 register to "0" (low-ring oscillator).
The voltage detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscillation stop detection interrupt.
The D42 bit in the D4INT register becomes “1” when passing through Vdet is detected after the voltage inputted to the VCC pin is up or down.
A voltage detection interrupt request is generated when the D42 bit changes state from “0” to “1”. The
D42 bit needs to be set to “0” in a program.
Table 5.3 lists the voltage detection interrupt request generation conditions in use to get out of stop
mode.
Preliminary specification
Specifications in this manual are tentative and subject to change.
5.4 Voltage Detection Circuit
Table 5.3 Voltage Detection Interrupt Request Generation Conditions in use to get out of
stop mode
Operation mode
Stop mode
Notes:
1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to Chapter 6, "Clock
Generation Circuit.")
2. Refer to Figure 5.14, "Operation Example of Voltage Detection Interrupt Generation Circuit" for interrupt generation
timing.
VC27 bit D40 bit D42 bitD41 bit VC13 bit
11
1
D46 bit
1
D47 bit
0 or 1
0
From 0 to 1
From 1 to 0
CM14 bit
0
Rev.0.91 2003 Sep 08 page 27 of 184
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R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Clock Generating Circuit
6. Clock Generation Circuit
The clock generation circuit contains two oscillator circuits as follows:
• Main clock oscillation circuit
• Ring oscillator (oscillation stop detect function)
Table 6.1 lists the clock generation circuit specifications. Figure 6.1 shows the clock generation circuit.
Figures 6.2 and 6.4 show the clock-related registers.
Table 6.1 Clock Generation Circuit Specifications
Item
Use of clock
Clock frequency 0 to 20 MHz
Usable oscillator
Pins to connect
oscillator
Oscillation stop,
restart function
Oscillator status
after reset
Other
Notes:
1. Can be used as P4
circuit is not used.
• CPU clock source
• Peripheral function
• Ceramic oscillator
• Crystal oscillator
X
Present
Stopped
Externally derived
clock can be input
Main clock
oscillation circuit
clock source
IN, XOUT
1
6 and P47 when the ring oscillator clock is used for CPU clock while the main clock oscillation
Ring oscillator
High-speed ring oscillator
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function
clock sources when the main
clock stops oscillating
Approx. 8 MHz
1
Note
Present
Stopped
Low-speed ring oscillator
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function
clock sources when the main
clock stops oscillating
Approx. 125 kHz
1
Note
Present
Oscillating
Rev.0.91 2003 Sep 08 page 28 of 184
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R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Clock Generating Circuit
f
RING-fast
RESET
Hardware reset2
Power on reset
Interrupt request level
judgment output
Voltage detective
interrupt
CM10=1(Stop mode)
WAIT instruction
Ring
oscillator
clock
1/128
Voltage
detection
circuit
fRING-S
Oscillation
stop
detection
e
OCD2=1
OCD2=0
a
e
b
Divider
b
f
1
f
AD
c
d
1/2 1/2 1/2 1/2
f
RING
f
RING128
f
1SIO
f
2
Peripheral
f
8SIO
f
32SIO
function clock
CPU clock
c
c
f
8
f
32
1/2
CM02
High-speed
ring oscillator
HR01=1
HR01=0
Low-speed
ring oscillator
Main
clock
X
OUT
CM13
HR00
CM14
QS
R
R
R
X
IN
CM05
QS
a
CM02, CM05, CM06: Bits in CM0
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
OCD0, OCD1, OCD2: Bits in OCD register
HR00, HR01: Bits in HR0 register
Oscillation stop detection circuit
Forcible discharge when OCD0
Pulse generation
circuit for clock
Main clock
edge detection
and charge,
discharge control
circuit
Notes:
1. Set the same value to the OCD1 bit and OCD0 bit.
Figure 6.1 Clock Generation Circuit
Charge,
discharge
circuit
OCD1
CM06=0
CM06=0
CM17 to CM16=00
CM06=0
CM17 to CM16=01
2
CM06=0
CM17 to CM16=10
2
CM06=1
CM17 to CM16=11
2
2
d
Details of divider
1
Oscillation stop
detection interrupt
1
generation circuit
Watchdog
timer
interrupt
OCD2 bit switch signal
CM14 bit switch signal
Oscillation stop
detection,
watchdog timer,
Voltage
detection
interrupt
Rev.0.91 2003 Sep 08 page 29 of 184
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g
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Clock Generating Circuit
System clock control register 0
b7 b6 b5 b4 b3 b2 b1 b0
00001
1
Symbol Address After reset
CM0 0006
16
68
16
Bit name FunctionBit symbol
(b1-b0)
CM02
(b3)
(b4)
CM05
CM06
(b7)
Reserved bit
WAIT peripheral function
clock stop bit
Reserved bit Must set to “1”
Reserved bit
Main clock (X
stop bit
Main clock division select
bit 0
CIN-XCOUT
2, 4
5
Reserved bit Must set to “0”
Notes
1: Set the PRC0 bit of PRCR register to “1” (write enable) before writing to this register.
2: The CM05 bit is provided to stop the main clock when the ring oscillator mode is selected. This bit cannot be used for detection as
to whether the main clock stopped or not. To stop the main clock, the following setting is required:
(1) Set the CM06 bit to “1” (divide-by-8 mode)
(2) Set the OCD0 and OCD1 bits in the OCD register to “00
(3) Set the OCD2 bit to “1” (selecting ring oscillator).
3: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted.
4: When the CM05 bit is set to “1” (main clock stop), P4
6
and P47 can be used as input ports.
5: When entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divide-by-8 mode).
6: Durin
ring oscillator mode, this bit must be set to “0” (peripheral clock turned on when in wait mode).
Must set to “0”
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode
Must set to “0”
)
0 : On
3
1 : Off
0 : CM16 and CM17 valid
1 : Divide-by-8 mode
2
” (disabling oscillation stop detection function).
6
RW
RW
RW
RW
RW
RW
RW
RW
System clock control register 1
b7 b6 b5 b4 b3 b2 b1 b0
00
1
Symbol Address After reset
CM1 0007
16
20
16
Bit name FunctionBit symbol
4
CM10
(b1)
(b2)
CM13
CM14
CM15
CM16
CM17
Notes:
1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
2: When entering stop mode from high or middle speed mode, the CM15 bit is set to “1” (drive capability high).
3: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
4: If the CM10 bit is “1” (stop mode), the internal feedback resistor becomes ineffective.
5: The CM14 bit can be set to “1” (low-speed ring oscillator off) if the OCD2 bit=0 (selecting main clock). When the OCD2 bit is set
to “1” (selecting ring oscillator clock), the CM14 bit is set to “0” (low-speed ring oscillator on). This bit remains unchanged when “
1” is written.
6: When using voltage detection interrupt circuit, CM14 bit is set to "0"
All clock stop control bit
Reserved bit
Reserved bit
Port XIN-X
Low-speed ring oscillation
stop bit
X
select bit
Main clock division
select bit 1
5,6
IN-XOUT
OUT
switch bit
drive capability
2
3
0 : Clock on
1 : All clocks off (stop mode)
Must set to
Must set to
0 : Input port P4
1 : X
0 : Low-speed ring oscillator on
1 : Low-speed ring oscillator off
0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
IN-XOUT
“0”
“0”
pin
6
, P47
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 6.2 CM0 Register and CM1 Register
Rev.0.91 2003 Sep 08 page 30 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Clock Generating Circuit
Oscillation stop detection register
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol Address After reset
OCD
Bit symbol
OCD0
OCD1
OCD2
OCD3
(b7-b4)
1
000C
Bit name
Oscillation stop
detection enable bit
System clock select bit
Clock monitor bit
Reserved bit
3, 5
16
0416
Function
b1 b0
0 0: The function is disabled
0 1: Avoid this setting
1 0: Avoid this setting
1 1: The function is enabled
0: Select main clock
6
1: Select ring oscillator clock
0: Main clock on
1: Main clock off
Must set to "0"
4
7
7
2
Notes:
1. Set the PRC0 bit in the PRCR register to “1” (write enable) before rewriting this register.
2. The OCD2 bit is set to “1” (selecting ring oscillator clock) automatically if a main clock oscillation stop is
detected while the OCD1 to OCD0 bits are set to “11
2
” (oscillation stop detection function enabled). If the
OCD3 bit is set to “1” (main clock stop), the OCD2 bit remains unchanged when trying to write “0”
(selecting main clock).
3. The OCD3 bit is enabled when the OCD1 to OCD0 bits are set to “11
2
” (oscillation stop detection function
enabled). Read the OCD3 bit several times with the oscillation stop detection interrupt processing program
to determine the main clock state.
4. The OCD1 to OCD0 bits should be set to “00
stop mode and ring oscillator (main clock stops). The OCD1 to OCD0 bits should be set to “00
2
” (oscillation stop detection function disabled)before entering
2
” when the
HR01 bit in the HR0 register is set to “1” (high-speed ring oscillator selected).
5. The OCD3 bit remains set to “0” (main clock on) if the OCD1 to OCD0 bits are set to “00
2
”.
6. The CM14 bit goes to “0” (low-speed ring oscillator on) if the OCD2 bit is set to “1” (selecting ring oscillator
clock).
7. Refer to Figure 6.9 “switching clock source from low-speed ring oscillator to main clock” for the switching
procedure when the main clock re-oscillates after detecting an oscillation stop.
RW
RW
RW
RO
RW
Figure 6.3 OCD Register
Rev.0.91 2003 Sep 08 page 31 of 184
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R8C/11 Group
High-speed ring control register 0
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Clock Generating Circuit
b7 b6 b5 b4 b3 b2 b1 b0
00
00000
Notes:
1. The HR01 bit should be changed under the following conditions.
• HR00 = 1 (high-speed ring oscillator on)
• CM1 register CM14 bit = 0 (low-speed ring oscillator on)
• CM0 register CM06 bit = 1 (divided-by-8 mode)
2. When OCD1 to OCD0 bits in the OCD register are set to "112"(the function is enabled), the HR01 bit should be set to "0".
High-speed ring control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol Address After reset
HR0 0008
16
00
16
Bit
HR00
HR01
(b7-b2)
High-speed ring enable bit
High-speed ring select bit
Reserved bit
name
0: High-speed ring oscillator off
1: High-speed ring oscillator on
1,2
0: Low-speed ring oscillator selected
1: High-speed ring oscillator selected
Should set to
1
Symbol Address After reset
HR1 000B
16
40
16
FunctionBit symbol
“0”
Function
The frequency of high-speed ring oscillator is adjusted with bits 0 to bits 6.
Period of high-speed ring oscillator
= td(HR offset) + (b6 + b5/2 + b4/4 + b3/8 + b2/16 + b1/32 + b0/64) x td(HR)
Bit 7 should be set to “0”.
RW
RW
RW
RW
RW
RW
Note:
1. Set the PRC0 bit in the PRCR register to “1” (write enable) before rewriting this register.
Figure 6.4 HR0 Register and HR1 Register
Rev.0.91 2003 Sep 08 page 32 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
The following describes the clocks generated by the clock generation circuit.
6.1 Main Clock
This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the
CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a
resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of
power consumed in the chip. The main clock oscillator circuit may also be configured by feeding an
externally generated clock to the XIN pin. Figure 6.5 shows examples of main clock connection circuit.
After reset, the main clock is turned off.
The main clock starts oscillating when the CM05 bit in the CM0 register is set to “0” (main clock on)
after setting the CM13 bit in the CM1 register to “1” (XIN- XOUT pin).
To use the main clock for the CPU clock, set the OCD2 bit in the OCD register to “0” (selecting main
clock) after the main clock becomes oscillating stably.
The power consumption can be reduced by setting the CM05 bit in the CM0 register to “1” (main clock
off) if the OCD2 bit is set to “1” (selecting ring oscillator clock).
Note that if an externally generated clock is fed into the XIN pin, the main clock cannot be turned off by
setting the CM05 bit to “1”. If necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to Section 6.4, “Power
Control.”
6.1 Main Clock
Microcomputer
(Built-in feedback resistor)
X
IN
C
IN
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
and X
OUT
following the instruction.
X
OUT
(Note)
R
d
C
OUT
Figure 6.5 Examples of Main Clock Connection Circuit
Microcomputer
(Built-in feedback resistor)
X
IN
Externally derived clock
Vcc
Vss
X
OUT
Open
IN
Rev.0.91 2003 Sep 08 page 33 of 184
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R8C/11 Group
6.2 Ring Oscillator Clock
This clock is supplied by a ring oscillator. There are two kinds of ring oscillator: high-speed ring oscillator and low-speed ring oscillator. These oscillators are selected by the bit HR01 bit in the HR0
register.
6.2.1 Low-speed Ring Oscillator
The clock derived from the low-speed ring oscillator is used as the clock source for the CPU clock,
peripheral function clock, fRING, fRING128 and fRING-S.
After reset, the ring oscillator clock derived from low-speed ring oscillator by divided by 8 is selected
for the CPU clock.
If the main clock stops oscillating when the OCD1 to OCD0 bits in the OCD register are “112” (oscillation stop detection function enabled), the low-speed ring oscillator automatically starts operating,
supplying the necessary clock for the microcomputer.
The frequency of the low-speed ring oscillator varies depending on the supply voltage and the operation ambient temperature. The application products must be designed with sufficient margin to accommodate the frequency range.
Preliminary specification
Specifications in this manual are tentative and subject to change.
6.2 Ring Oscillator Clock
6.2.2 High-speed Ring Oscillator
The clock derived from high-speed ring oscillator is used as the clock source for the CPU clock,
peripheral function clock, fRING, fRING128, and fRING1-fast.
After reset, the ring oscillator clock derived from high-speed ring oscillator is halted. The oscillation is
started by setting the HR00 bit in the HR0 register to “1” (high-speed ring oscillator on). The frequency can be adjusted by the HR1 register.
The relationship between the value of HR1 register and the period of high-speed ring oscillator is
shown below. It is noted that the difference in delay between the bits should be adjusted by changing
each bit. Bit 7 should be set be “0”.
Period of high-speed ring oscillator =
td(HR offset) + (b6 + b5/2 + b4/4 + b3/8 + b2/16 + b1/32 + b0/64)
b0 to b6 : Bits in HR1 register
Rev.0.91 2003 Sep 08 page 34 of 184
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R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6.3 CPU Clock and Peripheral Function Clock
6.3 CPU Clock and Peripheral Function Clock
There are two type clocks: CPU clock to operate the CPU and peripheral function clock to operate the
peripheral functions. Also refer to “Figure 6.1 Clock Generating Circuit”.
6.3.1 CPU Clock
This is an operating clock for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock or ring oscillator clock.
The selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use
the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to select the divideby-n value.
After reset, the ring oscillator clock divided by 8 provides the CPU clock. When the clock source for the
CPU clock is switched over, set the CM06 bit to “1” (divide-by-8 mode) before changing the OCD2 bit.
Note that when entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divideby-8 mode).
6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO, fRING, fRING128)
These are operating clocks for the peripheral functions.
Of these, fi (i=1, 2, 8, 32) is derived from the main clock or ring oscillator clock by dividing them by i.
The clock fi is used for timers X, Y, Z and C.
The clock fjSIO (j=1, 8, 32) is derived from the main clock or ring oscillator clock by dividing them by j.
The clock fjSIO is used for serial I/O.
The fAD clock is produced from the main clock or the ring oscillator clock and is used for the A-D
converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral
function clock turned off during wait mode), the clocks fi, fjSIO, and fAD are turned off.
6.3.3 fRING and fRING128
These are operating clocks for the peripheral functions.
The fRING runs at the same frequency as the ring oscillator, and can be used as the souce for the timer
Y. The fRING128 is derived from the fRING by dividing it by 128, and can be used for the timer C input
capture function.
When the WAIT instruction is executed, the clocks fRING and fRING128 are not turned off.
6.3.4 fRING-fast
This is used as the count source for the timer C. The fRING-fast is derived from the high-speed ring
oscillator and provided by setting the HR00 bit to “1” (high-speed ring oscillator on).
When the WAIT instruction is executed, the clock fRING-fast is not turned off.
Rev.0.91 2003 Sep 08 page 35 of 184
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R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6.4 Power Control
6.4 Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes
are referred to as normal operation mode here.
6.4.1 Normal Operation Mode
Normal operation mode is further classified into three modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU
clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower
the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator
circuits are turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which
switched must be oscillating stably. If the new clock source is the main clock, allow a sufficient wait
time in a program until it becomes oscillating stably.
• High-speed Mode
The main clock divided by 1 (undivided) provides the CPU clock. If the CM14 bit is set to “0” (lowspeed ring oscillator on) or the HR00 bit in the HR0 register is set to “1” (high-speed ring oscillator
on), the fRING and fRING128 can be used for timers Y and C. When the HR00 bit is set to “1”, fRING-fast
can be used for timer C.
• Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the CM14 bit is set to “0” (lowspeed ring oscillator on) or the HR00 bit in the HR0 register is set to “1” (high-speed ring oscillator
on), the fRING and fRING128 can be used for timers Y and C. When the HR00 bit is set to “1”, fRING-fast
can be used for timer C.
• Ring Oscillator Mode
The ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The ring
oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to “1”
(divided by 8 mode) when returning to high-speed and medium-speed. When the HR00 bit is set to
“1”, fRING-fast can be used for timer C.
Rev.0.91 2003 Sep 08 page 36 of 184
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R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6.4 Power Control
Table 6.2 Setting Clock Related Bit and Modes
Modes
OCD register
OCD2
High-speed mode 0 00
Medium-
speed
mode
Ring
oscillator
1
mode
divided by 2
divided by 4
divided by 8
divided by 16
no division
divided by 2
divided by 4
divided by 8
divided by 16
001
0102 00
010
0112 00
1002 0 0 or 1
1012 0 0 or 1
110
1 1 0 or 1
111
CM1 register
CM17, CM16
2
2
2
2
CM0 register
CM06 CM05
00
00
0 0 or 1
0 0 or 1
Notes:
1. The low-speed ring oscillator is used as the ring oscillator clock when the CM1 register CM14 bit=0 (low-speed
ring oscillator on) and HR0 register HR01 bit=0 (low-speed ring oscillator selected).
The high-speed ring oscillator is used as the ring oscillator clock when the HR0 register HR00 bit=1 (high-
speed ring oscillator on) and HR01 bit=1 (high-speed ring oscillator selected).
Rev.0.91 2003 Sep 08 page 37 of 184
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.4.2 Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU and the watchdog timer because both are
operated by the CPU clock. Because the main clock and ring oscillator clock both are on, the peripheral functions using these clocks keep operating.
• Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,
f8SIO, f32SIO, and fAD clocks are turned off when in wait mode, with the power consumption reduced
that much.
• Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
• Pin Status During Wait Mode
The status before wait mode is retained.
• Exiting Wait Mode
The microcomputer is moved out of wait mode by a hardware reset or peripheral function interrupt.
When using a hardware reset to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function
interrupts to “0002” (interrupts disabled) before executing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait
mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral
functions using the peripheral function clocks stop operating, so that only the peripheral functions
clocked by external signals can be used to exit from wait mode.
Table 6. 3 lists the interrupts to exit wait mode and the usage conditions.
When using a peripheral function interrupt to exit wait mode, set up the following before executing
the WAIT instruction.
1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the
peripheral function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt sequence is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.
Table 6.3 Interrupts to Exit Wait Mode and Usage Conditions
Interrupt CM02=0 CM02=1
Serial I/O interrupt
Key input interrupt Can be used Can be used
A-D conversion interrupt Can be used in one-shot mode
Timer X interrupt Can be used in all modes Can be used in event counter mode
Timer Y interrupt
INT interrupt Can be used
Voltage detection interrupt
Can be used when operating with
internal or external clock
Can be used in all modes
Can be used
Can be used when operating with
external clock
(Do not use)
Can be used when counting inputs from
CNTR1 pin in timer mode
Can be used (INT0 and INT3 can be used
if there is no filter.
Can be used
6.4 Power Control
Rev.0.91 2003 Sep 08 page 38 of 184
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R8C/11 Group
6.4.3 Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function
clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The
least amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the
internal RAM is retained.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
• Key interrupt
• INT interrupt (INT0 and INT3 can be used only when there is no filter.)
• Timer X interrupt (when counting external pulses in event counter mode)
• Timer Y interrupt (when counting inputs from CNTR1 pin in timer mode)
• Serial I/O interrupt (when external clock is selected)
• Voltage detection interrupt
• Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit of CM10 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the OCD1 to OCD0 bits to “002” (oscillation stop detection function
disable).
• Pin Status in Stop Mode
The status before wait mode is retained.
• Exiting Stop Mode
The microcomputer is moved out of stop mode by a hardware reset or peripheral function interrupt.
When using a hardware reset to exit stop mode, set the ILVL2 to ILVL0 bits for the peripheral function
interrupts to “0002” (interrupts disabled) before setting the CM10 bit to “1”.
When using a peripheral function interrupt to exit stop mode, set up the following before setting the
CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the
peripheral function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt sequence is executed.
Preliminary specification
Specifications in this manual are tentative and subject to change.
______ ______ ______
6.4 Power Control
The main clock divided by 8 of the clock which is used right before stop mode is used for the CPU
clock when exiting stop mode by a peripheral function interrupt.
Rev.0.91 2003 Sep 08 page 39 of 184
Under development
R8C/11 Group
Figure 6.6 shows the state transition from normal operation mode to stop mode and wait mode. Figure
6.7 shows the state transition in normal operation mode.
Preliminary specification
Specifications in this manual are tentative and subject to change.
Reset
6.4 Power Control
All oscillators stopped
Stop mode
All oscillators stopped
Stop mode
All oscillators stopped
Stop mode
All oscillators stopped
Stop mode
CM10: Bit in CM1 register
CM10=1
Interrupt
Interrupt
CM10=1
CM10=1
Interrupt
Interrupt
CM10=1
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
Ring oscillator mode
(divided-by-8 mode)
Ring oscillator mode
When
detecting an
oscillation stop
Medium-speed mode
(divided-by-8 mode)
detecting an
oscillation stop
High-speed mode,
medium-speed mode
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
When
WAIT
instruction
Interrupt
Normal mode
(Refer to the diagram of state transition in normal mode for details.)
Figure 6.6 State Transition to Stop Mode and Wait Mode
Rev.0.91 2003 Sep 08 page 40 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6.4 Power Control
Normal operation mode (Main clock is oscillating, ring oscillator
Medium-speed mode
(divided-by-8 mode)
CPU clock: f(XIN)/8
CM06=1
1, 2
CM06=1
High-speed mode
CPU clock: f(XIN)
CM06=0
CM17 to CM16=00
Medium-speed mode
(divided-by-4 mode)
CPU clock: f(XIN)/4
CM06=0
CM17 to CM16=10
Normal operation mode (main clock is
oscillating, ring oscillator is stopped)
2
2
Medium-speed mode
(divided-by-8 mode)
CPU clock: f(XIN)/8
CM06=1
High-speed mode
CPU clock: f(XIN)
CM06=0
CM17 to CM16=00
Medium-speed mode
(divided-by-4 mode)
CPU clock: f(XIN)/4
CM06=0
CM17 to CM16=10
2
2
CM06=0
Medium-speed mode
(divided-by-2 mode)
CPU clock: f(XIN)/2
CM06=0
CM17 to CM16=01
Medium-speed mode
(divided-by-16 mode)
CPU clock: f(XIN)/16
CM06=0
CM17 to CM16=11
CM14=0
Medium-speed mode
(divided-by-2 mode)
CPU clock: f(XIN)/2
CM06=0
CM17 to CM16=01
Medium-speed mode
(divided-by-16 mode)
CPU clock: f(XIN)/16
CM06=0
CM17 to CM16=11
3
is oscillating)
2
2
CM14=1
2
2
Ring oscillator mode (main clock is oscillating, ring oscillator3 is oscillating)
8-division mode
OCD2=1
1
OCD2=0
Ring oscillator mode (main clock is
stopped, ring oscillator is oscillating)
1-division mode
CPU clock: f(
CM17 to CM16=00
4-division mode
CPU clock: f(
CM17 to CM16=10
CM06=0
CM06=0
CPU clock: f(
CM06=1
2
RING
)
2
2
RING
)/4
2
CM06=1
CM05=0
3
RING
2-division mode
CPU clock: f(
CM17 to CM16=01
16-division mode
CPU clock: f(
CM17 to CM16=11
)/8
CM06=0
CM06=0
CM06=0
CM05=1
8-division mode
1-division mode
CPU clock: f(
CM17 to CM16=00
RING
CM06=0
4-division mode
CPU clock: f(
CM17 to CM16=10
RING
CM06=0
CPU clock: f(
2
)/4
)
2
2
2
CM06=1
RING
)/8
2-division mode
CPU clock: f(
CM06=0
CM17 to CM16=01
16-division mode
CPU clock: f(
CM06=0
CM17 to CM16=11
RING
RING
RING
RING
1, 2
2
)/2
2
2
)/16
2
2
)/2
2
2
)/16
2
Notes:
1. Switch clock after oscillation of main clock is sufficiently stable.
2. Change the CM17 to CM16 bits before changing CM06 bit.
3. Ring oscillator is selected by the HR01 bit in the HR0 register.
Figure 6.7 State Transition in Normal Operation Mode
CM05, CM06: Bits in CM0 register
CM14, CM16, CM17: Bits in CM1 register
OCD2: Bit in OCD register
Rev.0.91 2003 Sep 08 page 41 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6.5 Oscillation Stop Detection Function
6.5 Oscillation Stop Detection Function
The oscillation stop detection function is such that main clock oscillation circuit stop is detected. The
oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD
register.
Table 6.4 lists the specifications of the oscillation stop detection function.
Where the main clock corresponds to the CPU clock source and the OCD1 to OCD0 bits are “112”
(oscillation stop detection function enabled), the system is placed in the following state if the main clock
comes to a halt:
• The low-speed ring oscillator starts oscillation, and the low-speed ring oscillator clock becomes the
clock source for CPU clock and peripheral functions in place of the main clock
• OCD register OCD2 bit = 1 (selecting ring oscillator clock)
• OCD register OCD3 bit = 1 (main clock stopped)
• CM1 register CM14 bit = 0 (low-speed ring oscillator oscillating)
• Oscillation stop detection interrupt request occurs
Table 6.4 Oscillation Stop Detection Function Specifications
Item Specification
Oscillation stop detectable clock and f(XIN) ≥ 2 MHz
frequency bandwidth
Enabling condition for oscillation stop • Set OCD1 to OCD0 bits to “112” (oscillation stop detection
detection function function enabled)
• Set HR01 bit in HR0 register to “0” (low-speed ring oscillator
selected)
Operation at oscillation stop detection Oscillation stop detection interrupt occurs
6.5.1 How to Use Oscillation Stop Detection Function
• The oscillation stop detection interrupt shares the vector with the watchdog timer interrupt. If the
oscillation stop detection and watchdog timer interrupts both are used, the interrupt source must be
determined. Figure 6.5 shows how to determine the interrupt source with the oscillation stop detection interrupt processing program.
• Where the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and
peripheral functions must be switched to the main clock in the program.
Figure 6.8 shows the procedure for switching the clock source from the low-speed ring oscillator to
the main clock.
• To enter wait mode while using the oscillation stop detection function, set the CM02 bit to “0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop detection function is provided in preparation for main clock stop due to
external factors, set the OCD1 to OCD0 bits to “002” (oscillation stop detection function disabled)
where the main clock is stopped or oscillated in the program, that is where the stop mode is selected
or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the OCD1
to OCD0 bits to “002” (oscillation stop detection function disabled).
• The HR01 bit in the HR0 register should be set to “0” (low-speed ring oscillator selected) before
setting the OCD1 to OCD0 bits to “112” (oscillation stop detection function enabled). When the HR01
bit is set to “1” (high-speed ring oscillator selected), the OCD1 to OCD0 bits should be set to “002”
(oscillation stop detection function disabled).
Rev.0.91 2003 Sep 08 page 42 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
6.5 Oscillation Stop Detection Function
Table 6.5
Determination of Interrupt Source (Oscillation Stop Detection or Watchdog Timer Interrupt)
Generated Interrupt Source Bit showing interrupt source
Oscillation stop detection (a) The OCD3 bit in the OCD register = 1
( (a) or (b) ) (b) The OCD1 to OCD0 bits in the OCD register = 112 and the
OCD2 bit = 1
Watchdog timer The D43 bit in the D4INT register = 1
Voltage detection The D42 bit in the D4INT register = 1
Switch to Main clock
Verify OCD3 bit
0(main clock oscillating)
Determine several times
Determine several times that the main clock is supplied
1(main clock stop)
Figure 6.8
Set OCD1 to OCD0 bits to 002
(oscillation stop detection function disabled)
Set OCD2 bit to 0
(selecting main clock)
End
OCD3 to OCD0 bits: Bits in OCD register
Switching Clock Source From Low-speed Ring Oscillator to Main Clock
Rev.0.91 2003 Sep 08 page 43 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
7. Protection
In the event that a program runs out of control, this function protects the important registers so that they
will not be rewritten easily. Figure 7.1 shows the PRCR register. The following lists the registers protected
by the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1, and OCD, HR0, HR1 registers
• Registers protected by PRC1 bit: PM0 and PM1 registers
• Registers protected by PRC2 bit: PD0 register
• Registers protected by PRC3 bit: VCR2 and D4INT registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts will occur between the instruction in which the PRC2
bit is set to “1” and the next instruction. The PRC0 and PRC1 bits are not automatically set to “0” by writing
to any address. They can only be set to “0” in a program.
7. Protection
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol Address After reset
16
PRCR 000A
00XXX0002
Bit nameBit symbol
PRC0
PRC1
PRC2
(b5-b4)
Protect bit 0
Protect bit 1
Protect bit 2
Protect bit 3
Reserved bit When write, should set to “0”
Enable write to CM0, CM1, OCD,
HR0, HR1 registers
0 : Write protected
1 : Write enabled
Enable write to PM0, PM1
registers
0 : Write protected
1 : Write enabled
Enable write to PD0 register
0 : Write protected
1 : Write enabled
Enable write to VCR2, D4INT
registersPRC3
0 : Write protected
1 : Write enabled
Function
1
RW
RW
RW
RW
RW
RW
(b7-b6)
Notes:
1. The PRC2 bit is set to “0” by writing to any address after setting it to “1”. Other bits are not set to “0”
by writing to any address, and must therefore be set to “0” in a program.
Figure 7.1 PRCR Register
Rev.0.91 2003 Sep 08 page 44 of 184
Reserved bit
When read, its content is “0”.
RO
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
8. Processor Mode
8.1 Types of Processor Mode
The processor mode is single-chip mode. Table 8.1 shows the features of the processor mode. Figure
8.1 shows the PM0 and PM1 register.
Table 8.1 Features of Processor Mode
Processor mode
Single-chip mode SFR, internal RAM, internal ROM
Access space Pins which are assigned I/O ports
8. Processor Mode
All pins are I/O ports or peripheral
function I/O pins
Processor mode register 0
b7 b6 b5 b4 b3 b2 b1 b0
00
0
1
Symbol Address After reset
PM0 0004
16
00
Bit name FunctionBit symbol
(b2-b0)
PM03
(b7-b4)
Notes:
1. Set the PRC1 bit in the PRCR register to "1" (write enable) before writing to this register.
Processor mode register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol Address After reset
PM1 0005
0
Reserved bit
Software reset bit
Nothing is assigned. When write, set to “0”. When read, its
content is "0".
1
16
Must set to “0”
Setting this bit to “1” resets the
microcomputer. When read, its
content is “0”.
00
16
Bit name FunctionBit symbol
(b1-b0)
PM12
(b6-b3)
Reserved bit
WDT inerrupt/reset switch
bit
Nothing is assigned. When write, set to “0”. When read, its
content is "0".
Must set to “0”
0 : Watchdog timer interrupt
1 : Watchdog timer reset
16
RW
RW
RW
RW
RW
2
RW
(b7)
Notes:
1. Set the PRC1 bit in the PRCR register to "1" (write enable) before writing to this register.
2. PM12 bit is set to “1” by writing a “1” in a program. (Writing a “0” has no effect.)
Figure 8.1 PM0 Register and PM1 Register
Rev.0.91 2003 Sep 08 page 45 of 184
Reserved bit
Must set to “0”
RW
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
9. Bus
During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for
access space.
The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16
bits) units, these spaces are accessed twice in 8-bit units. Table 9.2 shows bus cycles in each access
space.
Table 9.1 Bus Cycles for Access Space
Access space Bus cycle
SFR 2 CPU clock cycles
ROM/RAM 1 CPU clock cycles
9. Bus
Table 9.2 Access Unit and Bus Operation
Space
Even address
byte access
CPU clock
Address
SFR
Even
Data
Add address
byte access
CPU clock
Address
Odd
Data
Even address
word access
Add address
word access
CPU clock
Address
Data
CPU clock
Address
Even
Data
Odd Odd+1 Odd Odd+1
Data
Data
Even+1
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
ROM/RAM
Even
Data
Odd
Data
Even
Data
Even+1
Data
Data
Rev.0.91 2003 Sep 08 page 46 of 184
Data
Data
Data
Data
Data
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
10. Interrupt
10.1 Interrupt Overview
10.1.1 Type of Interrupts
Figure 10.1 shows types of interrupts.
Software
(Non-maskable interrupt)
Interrupt
Hardware
Special
(Non-maskable interrupt)
Peripheral function
(Maskable interrupt)
1
10.1 Interrupt Overview
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Watchdog timer
Oscillation stop detection
Voltage detection
Single step
Address match
2
Notes:
1. Peripheral function interrupts are generated by the peripheral functions built in the microcomputer system.
2. Avoid using this interrupt because this is a dedicated interrupt for development support tools only.
Figure 10.1 Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Rev.0.91 2003 Sep 08 page 47 of 184
Under development
R8C/11 Group
10.1.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are nonmaskable interrupts.
• Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the
operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to
63 can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be
executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does
not change state during instruction execution, and the SP then selected is used.
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.1 Interrupt Overview
Rev.0.91 2003 Sep 08 page 48 of 184
Under development
R8C/11 Group
10.1.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
(1) Special Interrupts
Special interrupts are non-maskable interrupts.
• Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to Chapter 11, “Watchdog Timer.”
• Oscillation Stop Detection Interrupt
Generated by the oscillation stop detection function. For details about the oscillation stop detection
function, refer to Chapter 6, “Clock Generation Circuit.”
• Voltage Detection Interrupt
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to
Section 5.2, “Voltage Detection Circuit.”
• Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 to RMAD1 register that corresponds to one of the AIER register's AIER0 or
AIER1 bit which is "1" (address match interrupt enabled). For details about the address match interrupt, refer to Section 10.4, “Address Match Interrupt.”
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.1 Interrupt Overview
(2) Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in Table 10.2.
“Relocatable Vector Tables”. For details about the peripheral functions, refer to the description of
each peripheral function in this manual.
Rev.0.91 2003 Sep 08 page 49 of 184
Under development
R8C/11 Group
10.1.4 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in
the corresponding interrupt vector. Figure 10.2 shows the interrupt vector.
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.1 Interrupt Overview
Vector address (L)
Vector address (H)
MSB
Low address
Mid address
0 0 0 0 High address
0 0 0 0 0 0 0 0
LSB
Figure 10.2 Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from 0FFDC16 to 0FFFF16. Table 10.1 lists
the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of
fixed vectors are used by the ID code check function. For details, refer to Section 17.3, “Functions to
Prevent Flash Memory from Rewriting.”
Table 10.1 Fixed Vector Tables
Interrupt source Vector addresses Remarks Reference
Address (L) to address (H)
Undefined instruction 0FFDC16 to 0FFDF16 Interrupt on UND instruction R8C series software
Overflow 0FFE016 to 0FFE316 Interrupt on INTO instruction manual
BRK instruction 0FFE416 to 0FFE716
If the contents of address
0FFE716 is FF16, program execution starts from the address
shown by the vector in the
relocatable vector table.
Address match 0FFE816 to 0FFEB16
Single step
1
0FFEC16 to 0FFEF16
Address match interrupt
• Watchdog timer 0FFF016 to 0FFF316 •Watchdog timer
• Oscillation stop
detection •
•
Clock generation circuit
Voltage detection circuit
• Voltage detection
(Reserved) 0FFF416 to 0FFF716
(Reserved) 0FFF816 to 0FFFB16
Reset 0FFFC16 to 0FFFF16 Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development sup-
port tools.
Rev.0.91 2003 Sep 08 page 50 of 184
Under development
p
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
• Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable
vector table area. Table 10.2 lists interrupts and vector tables located in the relocatable vector table.
Table 10.2 Interrupt and Vector Tables in Relocatable Vector Tables
10.1 Interrupt Overview
Interrupt source
BRK instruction
(Reserved)
Key input interrupt
A-D
(Reserved)
Compare 2
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
INT2
Timer X
Timer Y
Timer Z
INT1
INT3
Timer C
Compare 1
INT0
(Reserved)
(Reserved)
Vector address
1
Address (L) to address (H)
2
+0 to +3 (0000
+52 to +55 (0034
+56 to +59 (0038
16
to 000316)
16
to 003716)
16
to 003B16)
Software interrupt
number
0
1 to 12
13
14
Reference
R8C/Tiny Series
software manual
Key input interrupt
A-D converter
15
16
+64 to +67 (0040
to 004316)
+68 to +71 (004416 to 004716)
+72 to +75 (0048
+76 to +79 (004C
+80 to +83 (0050
+84 to +87 (0054
+88 to +91 (0058
+92 to +95 (005C
+96 to +99 (0060
+100 to +103 (0064
+104 to +107 (0068
+108 to +111 (006C
+112 to +115 (0070
+116 to +119 (0074
16
to 004B16)
16
to 004F16)
16
to 005316)
16
to 005716)
16
to 005B16)
16
to 005F16)
16
to 006316)
16
to 006716)
16
to 006B16)
16
to 006F16)
16
to 007316)
16
to 007716)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Timer C
Serial I/O
INT interrupt
Timer X
Timer Y
Timer Z
INT interrupt
Timer C
Timer C
INT interrupt
30
31
Software interrupt2
Notes:
1. Address relative to address in INTB.
2. These interru
Rev.0.91 2003 Sep 08 page 51 of 184
ts cannot be disabled using the I flag.
+128 to +131 (0080
to
+252 to +255 (00FC
16
to 008316)
16
to 00FF16)
32
to
63
R8C/Tiny Series
software manual
Under development
R8C/11 Group
10.1.5 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in
which order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each
interrupt control register.
Figure 10.3 shows the interrupt control registers.
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.1 Interrupt Overview
Rev.0.91 2003 Sep 08 page 52 of 184
Under development
A
A
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.1 Interrupt Overview
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
2
Symbol Address After reset
KUPIC 004D
ADIC 004E
CMP2IC 0050
S0TIC, S1TIC 005116, 0053
S0RIC, S1RIC 005216, 0054
INT2IC 0055
TXIC 0056
TYIC 0057
TZIC 0058
INT1IC 0059
INT3IC 005A
TCIC 005B
CMP1IC 005C
Bit name FunctionBit symbol
ILVL0
ILVL1
ILVL2
IR
(b7-b4)
Interrupt priority level
select bit
Interrupt request bit
Nothing is assigned.
When write, set to “0”. When read, its content is indeterminate.
16
16
16
16
16
16
16
16
16
16
16
16
16
b2 b1b0
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
2
2
2
2
2
2
2
2
2
2
2
2
2
RW
RW
RW
RW
1
RW
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol Address After reset
INT0IC 005D
16
Bit name FunctionBit symbol
ILVL0
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
XX00X000
2
RW
RW
0 0 1 : Level 1
ILVL1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
RW
1 0 1 : Level 5
ILVL2
IR
POL
(b7-b6)
Interrupt request bit
Polarity select bit
3, 4
Reserved bit
Nothing is assigned.
When write, set to “0”. When read, its content is indeterminate.
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Must always be set to “0”
RW
RW
RW
RW
1
Notes:
1. Only "0" can be written to the IR bit. (Do not write "1").
2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
Refer to the paragraph 1.2.6 “Changing Interrupt Control Registers” in the Usage Notes Reference Book.
3. If the INTOPL bit in the INTEN register is set to “1” (both edges), set the POL bit to "0 " (selecting falling edge).
4. The IR bit may be set to “1” (interrupt requested) when the POL bit is rewritten. Refer to the paragraph 1.2.5
“Changing Interrupt Source” in the Usage Notes Reference Book.
Figure 10.3 Interrupt Control Registers
Rev.0.91 2003 Sep 08 page 53 of 184
Under development
R8C/11 Group
• I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the
maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
• IR Bit
The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit
is cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
• ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 10.3 shows the settings of interrupt priority levels and Table 10.4 shows the interrupt priority
levels enabled by the IPL.
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.1 Interrupt Overview
The following are conditions under which an interrupt is accepted:
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect
one another.
Table 10.4 Interrupt Priority Levels Enabled
Table 10.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 bits
0002
0012
0102
0112
1002
1012
1102
1112
Interrupt priority
level
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Priority
order
Lowest
Highest
by IPL
IPL
000
2
0012
0102
0112
1002
1012
1102
1112
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Enabled interrupt priority levels
Rev.0.91 2003 Sep 08 page 54 of 184
Under development
R8C/11 Group
• Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted
to the instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when
the execution of the instruction is completed, and transfers control to the interrupt sequence from the
next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA
instruction, the processor temporarily suspends the instruction being executed, and transfers control
to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 10.4 shows time required for executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by read-
ing the address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt
not requested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s inter-
nal temporary register
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63
is executed.
(4) The CPU’s internal temporary register
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
Preliminary specification
Specifications in this manual are tentative and subject to change.
(Note)
.
(Note)
is saved to the stack.
10.1 Interrupt Overview
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note: This register cannot be used by user.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CPU clock
Address bus
Data bus
RD
WR
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready
to accept instructions.
Address
0000
16
Interrupt
information
Indeterminate
Indeterminate
Indeterminate
SP-2 SP-4
SP-1 SP-3
SP-2
contents
SP-1
contents
contents
SP-4
SP-3
contents
VEC
VEC
contents
VEC+1
VEC+1
contents
VEC+2
VEC+2
contents
Figure 10.4 Time Required for Executing Interrupt Sequence
19
20
PC
Rev.0.91 2003 Sep 08 page 55 of 184
Under development
R8C/11 Group
• Interrupt Response Time
Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed (see #a in Figure 10.5) and a time during
which the interrupt sequence is executed (20 cycles, see #b in Figure 10.5).
Preliminary specification
Specifications in this manual are tentative and subject to change.
Interrupt request acknowledgedInterrupt request generated
10.1 Interrupt Overview
Time
Instruction Interrupt sequence
(a) 20 cycles (b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) 21 cycles for address match and single-step interrupts.
Figure 10.5 Interrupt Response Time
• Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is
set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels
listed in Table 10.5 is set in the IPL. Shown in Table 10.5 are the IPL values of software and special
interrupts when they are accepted.
Instruction in
interrupt routine
Table 10.5 IPL Level That Is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Watchdog timer, oscillation stop detection, voltage detection
Software, address match, single-step
Rev.0.91 2003 Sep 08 page 56 of 184
Level that is set to IPL
7
Not changed
Under development
R8C/11 Group
• Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits in the PC are saved.
Figure 10.6 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine.
Use the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.1 Interrupt Overview
Address
MSB LSB
m – 4
m – 3
m – 2
m – 1
m
m + 1
Stack
Content of previous stack
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
SPvalue before
interrupt occurs
Address
MSB LSB
m – 4
m – 3
m – 2
m – 1
m
m + 1
Stack status after interrupt request
is acknowledged
Stack
PC
L
PC
M
FLG
L
FLG
H
Content of previous stack
Content of previous stack
PC
H
[SP]
New SP value
Figure 10.6 Stack Status Before and After Acceptance of Interrupt Request
The registers are saved in four steps, 8 bits at a time. Figure 10.7 shows the operation of the saving
registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP
indicated by the U flag. Otherwise, it is the ISP.
Address
Stack
[SP] – 5
PC
[SP] – 4
[SP] – 3
[SP] – 2
[SP] – 1
FLG
L
PC
M
L
FLG
H
[SP]
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 10.7 Operation of Saving Register
Rev.0.91 2003 Sep 08 page 57 of 184
PC
Sequence in which order
registers are saved
(3)
(4)
Saved, 8 bits at a time
(1)
H
(2)
Finished saving registers
in four operations.
Under development
R8C/11 Group
• Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt
routine. Thereafter the CPU returns to the program which was being executed before accepting the
interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
• Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request
that has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the
ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their
interrupt priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 10.8
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control
branches invariably to the interrupt routine.
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.1 Interrupt Overview
Reset > WDT/Oscillation stop detection/Voltage detection > Peripheral function > Single step > Address match
Figure 10.8 Hardware Interrupt Priority
Rev.0.91 2003 Sep 08 page 58 of 184
Under development
R8C/11 Group
• Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among
those requested.
Figure 10.9 shows the circuit that judges the interrupt priority level.
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.1 Interrupt Overview
Priority level of each interrupt
Compare 1
INT3
Timer Z
Timer X
INT0
Timer C
INT1
Timer Y
UART1 reception
UART0 reception
Compare 2
A-D conversion
Level 0 (default value)
Highest
Priority of peripheral fucntion interrupts
(if priority levels are same)
INT2
UART1 transmission
UART0 transmission
Key input
IPL
I flag
Address match
Watchdog timer
Oscillation stop detection
Voltage detection
Notes:
1. For development support tool only
1
Figure 10.9 Interrupts Priority Select Circuit
Lowest
Interrupt request level
resolution output signal
Interrupt
request
accepted
Rev.0.91 2003 Sep 08 page 59 of 184
Under development
R8C/11 Group
______
10.2 INT Interrupt
10.2.1 INT0 Interrupt
________
_______
INT0 interrupt is triggered by an INT0 input. When using INT0 interrupts, the INT0EN bit in the INTEN
register must be set to “1” (enabling). The edge polarity is selected using the INT0PL bit in the INTEN
register and the POL bit in the INT0IC register. The IR bit may be set to “1” (interrupt requested) after
changing the INT0PL or POL bit. The IR bit must be set to “0” (interrupt not requested) after changing
the INT0PL and POL bits.
Inputs can be passed through a digital filter with three different sampling clocks.
Figure 10.10 shows the INTEN and INT0F registers.
External input enable register
b7 b6 b5 b4 b3 b2 b1 b0
0000
Preliminary specification
Specifications in this manual are tentative and subject to change.
00
Symbol Address After reset
INTEN 0096
16
00
______
10.2 INT Interrupt
16
Bit symbol
INT0EN
INT0 input enable bit
Bit name Function
1
0 : Disabled
1 : Enabled
2
INT0PL
INT0 input polarity select bit
0 : One edge
1 : Both edges
Reserved bit
Must set to “0”
(b7-b2)
Notes:
1. This bit must be set while the INT0STG bit in the PUM register is set to “0” (one-shot trigger disabled).
2. When setting the INT0PL bit to “1” (selecting both edges), the POL bit in the INT0IC must be set to “0”
(selecting falling edge).
3. The IR bit in the INT0IC register may be set to “1” (interrupt requested) when the INT0PL bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
INT0 input filter select register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol Address After reset
INT0F 001E
Bit symbol
INT0F0
INT0 input filter select bit
Bit name Function
16
XXXXX000
INT0F1
(b2)
2
b1 b0
0 0 : No filter
0 1 : Filter with f
1 0 : Filter with f
1 1 : Filter with f
Must set to “0”Reserved bit
1
sampling
8
sampling
32
sampling
RW
RW
RW
RW
RW
RW
RW
RW
(b7-b3)
Nothing is assigned.
When write, set to “0”. If read, it content is
Figure 10.10 INTEN Register and INT0F Register
Rev.0.91 2003 Sep 08 page 60 of 184
indeterminate.
Under development
R8C/11 Group
10.2.2 INT0 Input Filter
The INT0 input has a digital filter which can be sampled by one of three sampling clocks. The sampling
clock is selected using the INT0F1 to INT0F0 bits in the INT0F register. The IR bit in the INT0IC
register is set to “1” (interrupt requested) when the sampled input level matches three times. When the
INT0F1 to INT0F0 bits are set to “012”, “102”, or “112”, the P4_5 bit in the P4 register indicates the
filtered value.
Figure 10.11 shows the INT0 input filter configuration. Figure 10.12 shows an operation example of
_____
INT0 input filter.
Port P45
direction
register
Preliminary specification
Specifications in this manual are tentative and subject to change.
_______
_______
_____
INT0F1 to INT0F0
=01
=10
=11
2
2
2
Sampling clock
Digital filter
INT0
f
1
f
8
f
32
(input level
matches 3x)
INT0EN
Other than
INT0F1 to INT0F0
=00
2
=00
2
______
10.2 INT Interrupt
INT0 interrupt
P4_5 bit
INT0F0, INT0F1: Bits in INT0F register
INT0EN: Bit in INTEN register
Figure 10.11 INT0 Input Filter
______
P45 input
Sampling
timing
P4_5 in
P4 register
IR bit in
INT0IC register
This is an operation example when the INT0F1 to INT0F0 bits in the
INT0F register is set to “01
2
”, “012”, or “012” (passing digital filter).
Set to “0” in program
Figure 10.12 Operation Example of INT0 Input Filter
______
Rev.0.91 2003 Sep 08 page 61 of 184
Under development
g
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
______
10.2 INT Interrupt
10.2.3 INT1 Interrupt and INT2 Interrupt
______ ______
______ ______
INT1 interrupts are triggered by INT1 inputs. The edge polarity is selected with the R0EDG bit in the
______ ______
TXMR register. The INT1 pin can be used only when the Timer X is in timer mode because the INT1
pin shares the same pin with the CNTR0 pin.
______ ______
INT2 interrupts are triggered by INT2 inputs. The edge polarity is selected with the R1EDG bit in the
______ ______
TYZMR register. The INT2 pin can be used only when the Timer Y is in timer mode because the INT2
pin shares the same pin with the CNTR1 pin.
______ _____
Figure 10.13 shows the TXMR and TYZMR registers when using INT1 and INT2 interrupts.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
0
Symbol Address After reset
TXMR 008B
00
16
00
Bit name
polarity
1, 2
b1 b0
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
TXEDG
Operation mode
select bit 0, 1
INT1/CNTR
switching bit
Timer X count
start flag
Must set to "0" in timer mode
Operation mode
select bit 2
Must set to "0" in timer mode
0
16
FunctionBit symbol
0 0 : Timer mode or pulse period
measurement mode
0 : Rising edge
1 : Falling edge
0 : Stops counting
1 : Starts counting
0 : Other than pulse period measurement
3
mode
3
RW
RW
RW
RW
RW
RW
RW
RW
TXUND
Notes:
1. The IR bit in the INT1IC may be set to “1” (interrupt requested) when the R0EDG bit is rewritten. Refer to the
paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
2. This bit is used to select the polarity of INT1 interrupt in timer mode.
3. When usin
INT1 interrupts, should select timer mode.
Must set to "0" in timer mode
RW
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Notes:
1. When using INT2 interrupts, must set to timer mode.
2. The IR bit in the INT2IC may be set to “1” (interrupt requested) when the R1EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
Symbol Address After reset
TYZMR 0080
0
16
00
Bit name
TYMOD0
R1EDG
TYWC
TYS
TZMOD0
TZMOD1
TZWC
TZS
Timer Y operation
mode bit
INT2/CNTR1 polarity
switching bit
Timer Y write
control bit
Timer Y count
start flag
Timer Z-related bit
2
16
FunctionBit symbol
0 : Timer mode
0 : Rising edge
1 : Falling edge
0 : Write to reload register and counter
simultaneously
1 : Write to reload register
0 : Stops counting
1 : Starts counting
1
______ ______
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 10.13 TXMR Register and TYZMR Register when INT1 and INT2 Interrupt Used
Rev.0.91 2003 Sep 08 page 62 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
______
10.2 INT Interrupt
10.2.4 INT3 Interrupt
______
_____ ______
INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should be se to “0”
______ _______
(INT3). The INT3 input has a digital filter which can be sampled by one of three sampling clocks. The
sampling clock is selected using the TCC11 to TCC10 bits in the TCC1 register. The IR bit in the
INT3IC register is set to “1” (interrupt requested) when the sampled input level matches three times.
The P3_3 bit in the P3 register indicates the previous value before filtering regardless of values set in
the TCC11 to TCC10 bits.
When setting the TCC07 bit to “1” (fRING128), INT3 interrupts are triggered by fRING128 clock. The IR
_____
bit in the INT3IC register is set to “1” (interrupt requested) every fRING128 clock cycle or every half
fRING128 clock cycle.
Figure 10.14 shows the TCC0 and TCC1 registers.
Rev.0.91 2003 Sep 08 page 63 of 184
Under development
R8C/11 Group
Timer C control register 0
b7 b6 b5 b4 b3 b2 b1 b0
00
Preliminary specification
Specifications in this manual are tentative and subject to change.
Symbol Address After reset
TCC0 009A
16
00
______
10.2 INT Interrupt
16
1
8
32
RING
FunctionBit symbol
-fast
TCC00
TCC01
TCC02
TCC03
TCC04
Bit name
Timer C control bit
Timer C count source select
1
bit
INT3 interrupt and capture
polarity select bit
Reserved bit
1, 2
0 : Count stop
1 : Count start
b2 b1
0 0 : f
0 1 : f
1 0 : f
1 1 : f
b4 b3
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Avoid this setting
Must set to "0"
(b6-b5)
TCC07
INT3 interrupt/capture input
switching bit
1, 2
0 : INT3
1 : f
RING128
Notes:
1. Change this bit when TCC00 bit is set to “0” (count stop).
2. The IR bit in the INT3IC may be set to “1” (interrupt requested) when the TCC03, TCC04, or TCC07 bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
TCC1 009B
16
00
Bit name
b1 b0
TCC10
TCC11
TCC12
TCC13
TCC14
TCC15
INT3 input filter select bit
Timer C counter reload
2, 3
select bit
Compare 0/Capture select
bit
Compare 0 output mode
3
select bit
1
b5 b4
0 0: CMP0 output remains unchanged
0 1: CMP0 output is reversed when
1 0: CMP0 output is set to low when
1 1: CMP0 output is set to high when
16
FunctionBit symbol
0 0: No filter
0 1: Filter with f
1 0: Filter with f
1 1: Filter with f
0: No reload (free-run)
1: Set TC register to “0000
compare 1 match
0: Capture
(input capture mode)
1: Compare 0 output
(output compare mode)
even when compare 0 signal
matched
compare 0 signal is matched
compare 0 signal is matched
compare 0 signal is matched
1
sampling
8
sampling
32
sampling
2
16
” at
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
TCC16
Compare 1 output mode
select bit
TCC17
Notes:
1. Input is recognized only when the same value from INT3 pin is sampled three times in succession.
2. The TCC00 bit in the TCC0 register should be set to “0” (count stop) when rewriting the TCC13 bit.
3. The TCC12 and TCC14 to TCC17 should be set to “0” when the TCC13 bit is “0” (input capture mode).
Figure 10.14 TCC0 Register and TCC1 Register
Rev.0.91 2003 Sep 08 page 64 of 184
3
b7 b6
0 0: CMP1 output remains unchanged
even when compare 1 signal
matched
0 1: CMP1 output is reversed when
compare 1 signal is matched
1 0: CMP1 output is set to low when
compare 1 signal is matched
1 1: CMP1 output is set to high when
compare 1 signal is matched
RW
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.3 Key Input Interrupt
10.3 Key Input Interrupt
A key input interrupt is generated on an input edge of any of the K10 to K13 pins. Key input interrupts can
_____ _____
_____
be used as a key-on wakeup function to exit wait or stop mode. KIi input can be enabled or disabled
selecting with the KIiEN (i=0 to 3) bit in the KIEN register. The edge polarity can be rising edge or falling
_____
edge selecting with the KIiPL bit in the KIEN register. Note, however, that while input on any KIi pin which
has had the KIiPL bit set to “0” (falling edge) is pulled low, inputs on all other pins of the port are not
_____
detected as interrupts. Similarly, while input on any KIi pin which has had the KIiPL bit set to “1” (rising
edge) is pulled high, inputs on all other pins of the port are not detected as interrupts.
Figure 10.15 shows a block diagram of the key input interrupt.
PU02 bit in PUR0 register
Pull-up
transistor
KI
3
KI
2
KI
1
KI
0
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
KI3 input
polarity select
bit
KI2 input
polarity select
bit
KI1 input
polarity select
bit
KI0 input
polarity select
bit
PD1_3 bit in PD1 register
KI3PL=0
KI3PL=1
KI2PL=0
KI2PL=1
KI1PL=0
KI1PL=1
KI0PL=0
KI0PL=1
KI3EN bit
PD1_3 bit
KI2EN bit
PD1_2 bit
KI1EN bit
PD1_1 bit
KI0EN bit
PD1_0 bit
KUPIC register
Interrupt control circuit
KI0EN, KI1EN, KI2EN, KI3EN,
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
Key input interrupt
request
Figure 10.15 Key Input Interrupt
Key input enable register
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
KI0EN
KI0PL
KI1EN
KI1PL
KI2EN
KI2PL
KI3EN
KI3PL
Notes:
1. The IR bit in the KUPIC register may be set to “1” (interrupt requested) when the KIEN register is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
Figure 10.16 KIEN Register
Symbol Address After reset
KIEN 0098
KI0 input enable bit 0 : Disabled
KI0 input polarity select bit
KI1 input enable bit
KI1 input polarity select bit
KI2 input enable bit
KI2 input polarity select bit 0 : Falling edge
KI3 input enable bit 0 : Disabled
KI3 input polarity select bit 0 : Falling edge
16
00
Bit name Function
16
1 : Enabled
0 : Falling edge
1 : Rising edges
0 : Disabled
1 : Enabled
0 : Falling edge
1 : Rising edges
0 : Disabled
1 : Enabled
1 : Rising edges
1 : Enabled
1 : Rising edges
RW
RW
RW
RW
RW
RW
RW
RW
RW
Rev.0.91 2003 Sep 08 page 65 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.4 Address Match Interrupt
10.4 Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMADi register (i=0, 1). Set the start address of any instruction in the RMADi register.
Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt. Note that the
address match interrupt is unaffected by the I flag and IPL.
The value of the PC that is saved to the stack when an address match interrupt is acknowledged varies
depending on the instruction at the address indicated by the RMAD i register (see the paragraph “register
saving” for the value of the PC). Not appropriate return address is pushed on the stack. There are two
ways to return from the address match interrupt as follows:
• Change the content of the stack and use a REIT instruction.
• Use an instruction such as POP to restore the stack as it was before an interrupt request was acknowl-
edged. And then use a jump instruction.
Table 10.6 lists the value of the PC that is saved to the stack when an address match interrupt is acknowledged.
Figure 10.17 shows the AIER, and RMAD1 to RMAD0 registers.
Table 10.6 Value of PC Saved to Stack when Address Match Interrupt Acknowledged
Address indicated by RMADi register (i=0,1) PC value saved
Note
• 16-bit operation code instruction Address indicated by
• Instruction shown below among 8-bit operation code instructions RMADi register + 2
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest
STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (However, dest = A0 or A1)
• Instructions other than the above Address indicated by
RMADi register + 1
Note: See the paragraph “saving registers” for the PC value saved.
Table 10.7 Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit Address match interrupt register
Address match interrupt 0 AIER0 RMAD0
Address match interrupt 1 AIER1 RMAD1
Rev.0.91 2003 Sep 08 page 66 of 184
Under development
R8C/11 Group
Address match interrupt enable register
Preliminary specification
Specifications in this manual are tentative and subject to change.
10.4 Address Match Interrupt
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
AIER 0009
AIER0
AIER1
Address match interrupt 0
enable bit
Address match interrupt 1
enable bit
Nothing is assigned.
(b7-b2)
When write, set to “0”.
When read, their contents are indeterminate.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19) (b16)
(b15) (b8)
b0 b7 b0b3
Address setting register for address match interrupt
(b7-b4)
b7 b0
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
16 XXXXXX002
Bit nameBit symbol
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Symbol Address After reset
RMAD0 0012
16 to 001016 X0000016
RMAD1 001616 to 001416 X0000016
Function Setting range
0000016 to FFFFF16
RW
RW
RW
RW
RW
Figure 10.17 AIER Register and RMAD0 to RMAD1 Registers
Rev.0.91 2003 Sep 08 page 67 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
11. Watchdog Timer
11. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit in the PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it
cannot be set to “0” (watchdog timer interrupt) in a program. Refer to Section 5.1.5, “Watchdog Timer
Reset” for details.
The divide-by-N value for the prescaler can be chosen to be 16 or 128 with the WDC7 bit in the WDC
register. The period of watchdog timer can be calculated as given below. The period of watchdog timer is,
however, subject to an error due to the prescaler.
Watchdog timer period =
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register. After that, the watchdog timer is initialized by
writing to the WDTR register and the counting continues.
In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from
the held value when the modes or state are released.
Figure 11.1 shows the block diagram of the watchdog timer. Figure 11.2 shows the watchdog timerrelated registers.
CPU clock
Prescaler
1/16
1/128
WDC7 = 0
WDC7 = 1
Watchdog timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog
timer Reset
Write to WDTS register
RESET
Figure 11.1 Watchdog Timer Block Diagram
Rev.0.91 2003 Sep 08 page 68 of 184
Set to
“7FFF
16”
Under development
R8C/11 Group
Watchdog timer control register
Preliminary specification
Specifications in this manual are tentative and subject to change.
11. Watchdog Timer
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol Address After reset
WDC 000F
(b4-b0)
(b5)
(b6)
WDC7
Watchdog timer reset register
b7 b0
The watchdog is initialized after a write instruction to this register.
The watchdog timer value is always initialized to “7FFF
whatever value is written.
16
000XXXXX
Bit name
High-order bit of watchdog timer
Reserved bit Must set to “0”
Reserved bit Must set to “0”
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Symbol Address After reset
WDTR 000D
16 Indeterminate
Function
2
FunctionBit symbol RW
16” regardless of
RO
RW
RW
RW
RW
WO
Watchdog timer start register
b7 b0
Symbol Address After reset
WDTS 000E
16 Indeterminate
Function
The watchdog timer starts counting after a write instruction to this register.
Figure 11.2 WDC Register, WDTR Register, and WDTS Register
RW
WO
Rev.0.91 2003 Sep 08 page 69 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
12. Timers
The microcomputer has three 8-bit timers and one 16-bit timer. The three 8-bit timers are Timer X, Timer Y,
and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has input capture and
output compare. All these timers function independently. The count source for each timer is the operating
clock that regulates the timing of timer operations such as counting and reloading.
Table 12.1 lists functional comparison.
Table 12.1 Functional Comparison
Item Timer X Timer Y Timer Z Timer C
Configuration 8-bit timer 8-bit timer 8-bit timer 16-bit
with 8-bit with 8-bit with 8-bit free-run
prescaler prescaler prescaler timer
Count Down Down Down Up
Count source •f1 •f1 •f1 •f1
•f2 •f8 •f2 •f8
•f8 •fRING •f8 •f32
•f32 •Input from •Timer Y •fRING-fast
CNTR1 pin underflow
Function Timer mode provided provided provided not provided
Pulse output mode provided not provided not provided not provided
Event counter mode provided provided
Pulse width
measurement mode provided not provided not provided not provided
Pulse period
measurement mode provided not provided not provided not provided
Programmable waveform
generation mode not provided provided provided not provided
Programmable one-shot
generation mode not provided not provided provided not provided
Programmable wait
one-shot generation mode not provided not provided provided not provided
Input capture mode not provided not provided not provided provided
Output compare mode not provided not provided not provided provided
Input pin CNTR0 CNTR1
Output pin CNTR0
__________
CNTR0 CNTR1 TZOUT
Related interrupt Timer X int Timer Y int Timer Z int Timer C int
_____
INT1 int
_____
INT2 int
Timer stop provided provided provided provided
Note: Select the input from the CNTR1 pin as a count source of timer mode.
1
not provided not provided
_____
INT0 TCIN
CMP00 to CMP02
CMP10 to CMP12
_____
INT0 int
_____
INT3 int
compare 0 int
compare 1 int
12. Timers
Rev.0.91 2003 Sep 08 page 70 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.1 Timer (Timer X)
12.1 Timer X
The Timer X is an 8-bit timer with an 8-bit prescaler. Figure 12.1 shows the block diagram of Timer X.
Figures 12.2 and 12.3 show the Timer X-related registers.
The Timer X has five operation modes listed as follows:
• Timer mode: The timer counts an internal count source (clock source).
• Pulse output mode: The timer counts an internal count source and outputs the pulses
whose polarity is inverted at the timer the timer underflows.
• Event counter mode: The timer counts external pulses.
• Pulse width measurement mode: The timer measures an external pulse's pulse width.
• Pulse period measurement mode:The timer measures an external pulse's period.
Peripheral data bus
TXCK1 to TXCK0
INT1/CNTR
CNTR
=00
2
f
1
=01
2
f
8
=10
2
f
32
=11
2
f
2
Polarity
0
switching
TXMOD1 to TXMOD0 bits=01
TXOCNT bit
0
TXMOD1 to TXMOD0
=00
2
or 01
=11
2
2
=10
2
2
R0EDG =1
R0EDG=0
TXS bit
Q
Q
Reload register
PREX register
Toggle flip-flop
CLR
Counter
CK
Reload register
Counter
TX register
Write to TX register
TXMOD1 to TXMOD0 bits=01
2
Timer X interrupt
INT1 interrupt
Figure 12.1 Timer X Block Diagram
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Notes:
1. The IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
Symbol Address After reset
TXMR 008B
16 0016
Bit name
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
TXEDG
TXUND
Operation mode
select bit 0, 1
INT1/CNTR0
polarity switching
1
bit
Timer X count
start flag
P3
0
/CNTR0
select bit
Operation mode
select bit 2
Active edge
reception flag
Timer X under
flow flag
b1 b0
0 0 : Timer mode or
pulse period measurement mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
Function varies with each operation mode
0 : Stops counting
1 : Starts counting
Function varies with each operation mode
0 : Except in pulse period measurement mode
1 : Pulse period measurement mode
Function varies with each operation mode.
Function varies with each operation mode.
FunctionBit symbol
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.2 TXMR Register
Rev.0.91 2003 Sep 08 page 71 of 184
Under development
R8C/11 Group
Prescaler X Register
b7
Preliminary specification
Specifications in this manual are tentative and subject to change.
Symbol Address After reset
b0
PREX 008C
12.1 Timer (Timer X)
16
FF16
Timer X Register
b7
Mode
Timer mode
Pulse output mode
Event counter mode
Pulse width
measurement mode
Internal count source is counted
Internal count source is counted
Externally input pulses are counted
Pulse width of externally input
pulses is measured
(Internal count source is counted)
Pulse period
measurement mode
Pulse period of externally input
pulses is measured
(Internal count source is counted)
b0
Symbol Address After reset
TX 008D
Function
Underflow of Prescaler X is counted
Function
Setting range
0016 to FF
16
to FF
00
16
to FF
00
00
16
to FF
00
16
to FF
16
FF16
Setting range
0016 to FF
RW
16
RW
16
RW
16
RW
16
RW
RW
16
RW
RW
16
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
00
Notes:
1. Avoid switching a count source, while a counter is in progress. Timer counter must be stopped before switching a count
source.
Symbol Address After reset
TCSS 008E
Bit symbol
TXCK0
TXCK1
TYCK0
TYCK1
TZCK0
TZCK1
(b7-b6)
Bit name
Timer X count source
1
select bit
Timer Y count source
1
select bit
Timer Z count source
1
select bit
Reserved bit
16
b1 b0
0 0 : f
0 1 : f
1 0 : f
1 1 : f
b3 b2
0 0 : f
0 1 : f
1 0 : f
1 1 : Selects input from CNTR1 pin
b5 b4
0 0 : f
0 1 : f
1 0 : Selects Timer Y underflow
1 1 : f
Must be set to “0”
0016
1
8
32
2
1
8
RING
1
8
2
Figure 12.3 PREX Register, TX Register, and TCSS Register
Function
RW
RW
RW
RW
RW
RW
RW
RW
Rev.0.91 2003 Sep 08 page 72 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1.1 Timer Mode
In this mode, the timer counts an internally generated count source (See “Table 12.2 Timer Mode
Specifications”). Figure 12.4 shows the TXMR register in timer mode.
Table 12.2 Timer Mode Specifications
Item Specification
Count source f1, f2, f8, f32
Count operation • Down-count
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request generation timing
INT1/CNTR0 pin function Programmable I/O port, or INT1 interrupt input
CNTR0 pin function Programmable I/O port
Read from timer Count value can be read by reading TX register
Write to timer
When Timer X underflows [Timer X interruption]
Same applies to
PREX
register.
Value written to TX register is written to both reload register and counter.
Same applies to
PREX
register.
12.1 Timer (Timer X)
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
0
Notes:
1. The IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
2. This bit is used to select the polarity of INT1 interrupt in timer mode.
Symbol Address After reset
TXMR 008B
00
16 0016
Bit name
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
TXEDG
TXUND
Operation mode
select bit 0, 1
INT1/CNTR
switching bit
Timer X count
start flag
Must set to "0" in timer mode
Operation mode
select bit 2
Must set to "0" in timer mode
Must set to "0" in timer mode
0 polarity
1, 2
b1 b0
0 0 : Timer mode or pulse period
0 : Rising edge
1 : Falling edge
0 : Stops counting
1 : Starts counting
0 : Other than pulse period measurement mode
FunctionBit symbol
measurement mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.4 TXMR Register in Timer Mode
Rev.0.91 2003 Sep 08 page 73 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1.2 Pulse Output Mode
In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin
a pulse whose polarity is inverted each time the timer underflows (See “Table 12.3 Pulse Output mode
Specifications”). Figure 12.5 shows TXMR register in pulse output mode.
Table 12.3 Pulse Output Mode Specifications
Item Specification
Count source f1, f2, f8, f32
Count operation • Down-count
• When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request • When Timer X underflows [Timer X interruption]
generation timing • Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 output [INT1 interrupt]
INT1/CNTR0 pin function Pulse output
CNTR0 pin function Programmable I/O port or inverted output of CNTR0
Read from timer Count value can be read by reading TX register.
Same applies to
Write to timer
Value written to TX register is written to both reload register and counter.
Same applies to
Select function • Inverted pulse output function
The polarity of CNTR0 output pulse can be reversed with TXOCNT bit
_____
• INT1/CNTR0 polarity switching function
Polarity level at starting of pulse output can be selected with R0EDG bit
PREX
PREX
register.
register.
12.1 Timer (Timer X)
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Notes:
1. The IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
01
Symbol Address After reset
TXMR 008B
16
00
Bit name
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
TXEDG
TXUND
Operation mode
select bit 0, 1
0
INT1/CNTR
switching bit
Timer X count
start flag
0
/CNTR0
P3
select bit
Must set to "0" in pulse output mode
Must set to "0" in pulse output mode
Must set to "0" in pulse output mode
polarity
1
b1 b0
0 1 : Pulse output mode
0: CNTR0 output starts at "H"
1: CNTR
0 : Stops counting
1 : Starts counting
0 : Port P3
1 : CNTR0 output
0
output starts at "L"
16
FunctionBit symbol
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.5 TXMR Register in Pulse Output Mode
Rev.0.91 2003 Sep 08 page 74 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1.3 Event Counter Mode
In this mode, the timer counts an external signal fed to INT1/CNTR0 pin (See “Table 12.4 Event
Counter Mode Specifications”). Figure 12.6 shows TXMR register in event counter mode.
Table 12.4 Event Counter Mode Specifications
Item Specification
Count source External signals fed to CNTR0 pin (Active edge is selected by program)
Count operation • Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request • When Timer X underflows [Timer X interrupt]
generation timing • CNTR0 input count edges [INT1 interrupt]
INT1/CNTR0 pin function Count source input
CNTR0 pin function Programmable I/O port
Read from timer Count value can be read by reading TX register
Same applies to
Write to timer
Value written to TX register is written to both reload register and counter.
Same applies to
Select function • INT1/CNTR
Active edge of count source can be selected with R0EDG.
PREX
register.
PREX
register.
0 polarity switching function
12.1 Timer (Timer X)
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
0
00
Notes:
1. The IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
0
0
Symbol Address After reset
TXMR 008B
16
00
Bit name
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
TXEDG
TXUND
Operation mode
select bit 0, 1
0
INT1/CNTR
switching bit
Timer X count
start flag
Must set to "0" in event counter mode
Must set to "0" in event counter mode
Must set to "0" in event counter mode
Must set to "0" in event counter mode
polarity
1
b1 b0
1 0 : Event counter mode
0 : Rising edge
1 : Falling edge
0 : Stops counting
1 : Starts counting
16
FunctionBit symbol
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.6 TXMR Register in Event Counter Mode
Rev.0.91 2003 Sep 08 page 75 of 184
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1.4 Pulse Width Measurement Mode
In this mode, the timer measures the pulse width of an external signal fed to INT1/CNTR0 pin (See
“Table 12.5 Pulse Width Measurement Mode Specifications”). Figure 12.7 shows the TXMR register
in pulse width measurement mode. Figure 12.8 shows an operation example in pulse width measurement mode.
Table 12.5 Pulse Width Measurement Mode Specifications
Item Specification
Count source f1, f2, f8, f32
Count operation • Down-count
• Continuously counts the selected signal only when the measurement pulse is "H" level,
or conversely only "L" level.
• When the timer underflows, it reloads the reload register contents before continuing
counting
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request • When Timer X underflows [Timer X interruption]
generation timing • Rising or falling of CNTR0 input (end of measurement period) [INT1 interrupt]
INT1/CNTR0 pin function Measurement pulse input
CNTR0 pin function Programmable I/O port
Read from timer Count value can be read by reading TX register
Write to timer
Select function
Same applies to
Value written to TX register is written to both reload register and counter.
Same applies to
_____
• INT1/CNTR0 polarity switching function
Active edge of count source can be selected with R0EDG.
PREX
PREX
register.
register.
12.1 Timer (Timer X)
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00 1
Notes:
1. IThe IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
0
1
Symbol Address After reset
TXMR 008B
16
00
Bit name
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
TXEDG
TXUND
Operation mode
select bit 0, 1
0
INT1/CNTR
switching bit
Timer X count
start flag
Must set to "0" in pulse width measurement mode
Must set to "0" in pulse width measurement mode
Must set to "0" in pulse width measurement mode
Must set to "0" in pulse width measurement mode
polarity
1
b1 b0
1 1 : Pulse width measurement mode
0 : Measures “H” level width
1 : Measures “L” level width
0 : Stops counting
1 : Starts counting
16
FunctionBit symbol
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.7 TXMR Register in Pulse Width Measurement Mode
Rev.0.91 2003 Sep 08 page 76 of 184
Under development
R8C/11 Group
n = high-level: the contents of TX register, low-level: the contents of PREX register
Preliminary specification
Specifications in this manual are tentative and subject to change.
FFFF
16
n
Counter contents (hex)
Count start Underflow
Count stop
12.1 Timer (Timer X)
Count stop
16
0000
Set to "1" by program
TXS bit in TXMR
register
Measurement pulse
(CNTR0 pin input)
IR bit in INT1IC
register
IR bit in TXIC
register
Conditions: "H" level width of measurement pulse is measured. (R0EDG=1)
“1”
“0”
“H”
“L”
Cleared to “0” when interrupt request is accepted, or cleared by program
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by program
“1”
“0”
Figure 12.8 Operation Example in Pulse Width Measurement Mode
Count restart
Time
Rev.0.91 2003 Sep 08 page 77 of 184
Under development
G and
set to "0" by
ect.)
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.1 Timer (Timer X)
12.1.5 Pulse Period Measurement Mode
In this mode, the timer measures the pulse period of an external signal fed to INT1/CNTR0 pin (See
“Table 12.6 Pulse Period Measurement Mode Specifications”). Figure 12.9 shows the TXMR register
in pulse period measurement mode. Figure 12.10 shows an operation example in pulse period measurement mode.
Table 12.6 Pulse Period Measurement Mode Specifications
Item Specification
Count source f1, f2, f8, f32
Count operation • Down-count
• After an active edge of measurement pulse is input, contents in the read-out buffer is
retained in the first underflow of prescaler X. Then the timer X reloads contents in the
reload register in the second underflow of prescaler X and continues counting.
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request • When Timer X underflows or reloads [Timer X interrupt]
generation timing
INT1/CNTR0 pin function Measurement pulse input
• Rising or falling of CNTR0 input (end of measurement period) [INT1 interrupt]
1
CNTR0 pin function Programmable I/O port
Read from timer Contents in the read-out buffer can be read by reading TX register. The value retained in
the read-out buffer is released by reading TX register.
Write to timer
Select function
Value written to TX register is written to both reload register and counter.
Same applies to
_____
PREX
register.
• INT1/CNTR0 polarity switching function
Measurement period of input pulse can be selected with R0EDG bit.
Note: The period of input pulse must be longer than twice the period of prescaler X. Longer pulse for H width and L width
than the prescaler X period must be input. If shorter pulse than the period is input to the CNTR0 pin, the input may
be disabled.
_____
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Notes:
1. The IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
2. TXED
00
TXUND bits are
Symbol Address After reset
TXMR 008B
16
00
Bit name
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
TXEDG
TXUND
Operation mode
select bit 0, 1
INT1/CNTR0
polarity
switching bit
Timer X count
start flag
Must set to “0” in pulse period measurement mode
Operation mode
select bit 2
Active edge
2
reception flag
Timer X
2
underflow flag
writing a "0" in a program. (Writing a "1" has no eff
b1 b0
0 0 : Pulse period measurement mode
0: Measures a measurement pulse from one
rising edge to the next rising edge
1: Measures a measurement pulse from one
1
falling edge to the next falling edge
0 : Stops counting
1 : Starts counting
1 : Pulse period measurement mode
0 : No active edge
1 : Active edge found
0 : No under flow
1 : Under flow found
16
FunctionBit symbol
Figure 12.9 TXMR Register in Pulse Period Measurement Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
Rev.0.91 2003 Sep 08 page 78 of 184
Under development
R8C/11 Group
Underflow signal
of prescaler X
Preliminary specification
Specifications in this manual are tentative and subject to change.
Set to "1" by program
12.1 Timer (Timer X)
TXS bit in TXMR
register
CNTR0 pin
input
Timer X
contents
Contents of
read-out buffer
1
TXEDG bit in
TXMR register
TXUND bit in
TXMR register
IR bit in TXIC
register
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
Starts counting
0E
16
0F
16
0E
16
0F
16
Timer X
reloads
0F160E160D160C160B160A
0D
16
Retained
0D
16
(Note 2)
Cleared to "0" by program
16
0B
16
0A
16
Timer X read
(Note 3)
09
16
Retained
(Note 2)
Timer X
reloads
0F160E160D
09
16
(Note 4)
16
0D
16
Timer X read
(Note 3)
Cleared to "0" by program
01
16
01
16
Timer X
reloads
00160F160E
0F160E
00
16
(Note 6)
(Note 5)
16
16
Cleared to “0” when interrupt request is accepted, or cleared by program
IR bit in INT1IC
register
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by program
Conditions: A period from one rising edge to the next rising edge of measurement pulse is measured (R0EDG=0)
with TX register initial value=0F
Notes:
1. The contents of the read-out buffer can be read when the TX register is read in pulse period measurement mode.
2. After an active edge of measurement pulse is input, the TXEDG bit in the TXMR register is set to "1" (active edge found)
when the prescaler X underflows for the second time.
3. The TX register should be read before the next active edge is input after the TXEDG bit is set to "1" (active edge found).
The contents in the read-out buffer is retained until the TX register is read. If the TX register is not read before the next
active edge is input, the measured result of the previous period is retained.
4. When set to "0" by program, use a MOV instruction to write "0" to the TXEDG in the TXMR register. At the same time,
write "1" to the TXUND bit.
5. When set to "0" by program, use a MOV instruction to write "0" to the TXUND in the TXMR register. At the same time,
write "1" to the TXEDG bit.
6. The TXUND and TXEDG bits are both set to "1" if the timer underflows and reloads on an active edge simultaneously. In
this case, the validity of the TXUND bit should be determined by the contents of the read-out buffer.
16.
Figure 12.10 Operation Example in Pulse Period Measurement Mode
Rev.0.91 2003 Sep 08 page 79 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer (Timer Y)
12.2 Timer Y
Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Y Primary and Timer
Y Secondary. Figure 12.11 shows a block diagram of Timer Y. Figures 12.12 to 12.14 show the TYZMR,
PREY, TYSC, TYPR, TYZOC, PUM, and YCSS registers.
The Timer Y has two operation modes as follows:
• Timer mode: The timer counts an internal count source (clock source).
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
Peripheral data bus
TYCK1 to TYCK0
INT2/CNTR
f
1
f
8
f
RING
Polarity
switching
1
=00
=01
=10
=11
2
2
2
2
TYS=1
TYOCNT=0TYMOD0=1
TYOCNT=1
Reload register
Counter
PREY register
P3_2 bit in P3 register
TYSC register
Reload register
TYOPL=1
TYOPL=0
Q
Q
TYPR register
Reload register
Counter
Toggle
flip-flop
CK
CLR
Timer Y interrupt
INT2 interrupt
Write to TYZMR register
TYMOD0 bit=1
Figure 12.11 Timer Y Block Diagram
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
TYZMR 0080
TYMOD0
R1EDG
TYWC
TYS
TZMOD0
TZMOD1
TZWC
Bit name
Timer Y operation
mode bit
1
INT2/CNTR
switching bit
Timer Y write
control bit
Timer Y count
start flag
Timer Z operation
mode bit
Timer Z write
control bit
polarity
1
16
00
16
FunctionBit symbol
0 : Timer mode
1 : Programmable waveform generation mode
0 : Rising edge
1 : Falling edge
Function varies depending on the operation
mode
0 : Stops counting
1 : Starts counting
b5 b4
0 0 : Timer mode
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable wait one-shot generation
mode
Function varies depending on the operation
mode
RW
RW
RW
RW
RW
RW
RW
RW
TZS
Notes:
1. The IR bit in the INT2IC register may be set to “1” (interrupt requested) when the R1EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
Figure 12.12 TYZMR Register
Rev.0.91 2003 Sep 08 page 80 of 184
Timer Z count
start flag
0 : Stops counting
1 : Starts counting
RW
Under development
R8C/11 Group
Prescaler Y register
b7
Preliminary specification
Specifications in this manual are tentative and subject to change.
b0
Symbol Address After reset
PREY 0081
12.2 Timer (Timer Y)
16
FF16
Setting range
0016 to FF
00
16
to FF
FF16
Setting range
0016 to FF
16
16
16
Timer mode
Programmable
waveform generation
mode
Timer Y secondary register
b7
b0
Timer mode
Programmable
waveform generation
mode
Mode
Mode
Function
Internal count source or CNTR1
input is counted
Internal count source is counted
Symbol Address After reset
TYSC 0082
16
Function
Disabled
Underflow of Prescaler Y is
1
counted
Notes:
1. The values of TYPR register and TYSC register are reloaded to the counter alternately for counting.
2. The count value can be read out by reading the TYPR register even when the secondary period is being
counted.
Timer Y primary register
b7
b0
Symbol Address After reset
TYPR 0083
16
FF16
RW
RW
RW
RW
WO
2
Mode
Timer mode
Programmable
waveform generation
mode
Function
Underflow of Prescaler Y is
counted
Underflow of Prescaler Y is
1
counted
Setting range
00
16
to FF
16
0016 to FF
16
Notes:
1. The values of TYPR register and PYSC register are reloaded to the counter alternately for counting.
Timer Y, Z output control register
b7 b6 b5 b4 b3 b2 b1 b0
Notes:
1. This bit is set to "0" when the output of one-shot waveform is completed. The TZOS bit should be set to "0" if the
one-shot waveform output is terminated by setting the TYS bit in the TYZMR to "0" during the waveform output.
2. This bit is enabled only when operating in programmable waveform generation mode.
Symbol Address After reset
TYZOC 008A
16
Bit
name
TZOS
TYOCNT
TZOCNT
(b7-b3)
Timer Z one-shot
1
start bit
Timer Y programmable
waveform generation
output switching bit
Timer Z programmable
waveform generation
output switching bit
Nothing is assigned.
When write, set to "0". When read, its content is "0".
2
2
0 : Stops one-shot
1 : Starts one-shot
0 : Outputs programmable waveform
1 : Outputs the value of P3
0 : Outputs programmable waveform
1 : Outputs the value of P3
00
16
FunctionBit symbol
2
port register
1
port register
RW
RW
RW
RW
RW
RW
RW
Figure 12.13 PREY Register, TYSC Register, TYPR Register, and TYZOC Register
Rev.0.91 2003 Sep 08 page 81 of 184
Under development
R8C/11 Group
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Preliminary specification
Specifications in this manual are tentative and subject to change.
Symbol Address After reset
PUM 0084
0000
16
12.2 Timer (Timer Y)
0016
Bit symbol
(b3-b0)
TYOPL
TZOPL
INOSTG
INOSEG
Bit name
Reserved bit
Timer Y output level
latch
Timer Z output level
latch
INT0 pin one-shot
trigger control bit
2
(Timer Z)
INT0 pin one-shot trigger
polarity select bit
1
(Timer Z)
Function
Must set to “0”
Function varies depending on the operation mode
Function varies depending on the operation mode
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid
0 : Edge trigger at falling edge
1 : Edge trigger at rising edge
Notes:
1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is "0" (one-edge).
2. The INOSGT bit must be set to "1" after the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register
are set.
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
00
Notes:
1. Avoid switching a count source, while a counter is in progress. Timer counter must be stopped before switching a count
source.
Symbol Address After reset
TCSS 008E
Bit symbol
TXCK0
Bit name
Timer X count source
select bit
1
TXCK1
16
b1 b0
0 0 : f
0 1 : f
1 0 : f
1 1 : f
TYCK0
TYCK1
TZCK0
TZCK1
Timer Y count source
select bit
Timer Z count source
select bit
1
1
b3 b2
0 0 : f
0 1 : f
1 0 : f
1 1 : Selects input from CNTR1 pin
b5 b4
0 0 : f
0 1 : f
1 0 : Selects Timer Y underflow
1 1 : f
(b7-b6)
Reserved bit
Must be set to “0”
0016
Function
1
8
32
2
1
8
RING
1
8
2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.14 PUM Register and TCSS Register
Rev.0.91 2003 Sep 08 page 82 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer (Timer Y)
12.2.1 Timer Mode
In this mode, the timer counts an internally generated count source (see “Table 12.7 Timer Mode
Specifications”). An external signal input to the CNTR1 pin can be counted. The TYSC register is
unused in timer mode. Figure 12.15 shows the TYZMR and PUM registers in timer mode.
Table 12.7 Timer Mode Specifications
Item Specification
Count source f1, f8, fRING, external signal fed to CNTR1 pin
Count operation • Down-count
• When the timer underflows, it reloads the reload register contents before continuing
counting (When the Timer Y underflows, the contents of the Timer Y primary reload
register is reloaded.)
Divide ratio fi/(n+1)(m+1) n: set value in PREY register, m: set value in TYPR register
Count start condition Write “1” (count start) to TYS bit in TYZMR register
Count stop condition Write “0” (count stop) to TYS bit in TYZMR register
Interrupt request • When Timer Y underflows [Timer Y interrupt]
generation timing • Rising or falling of INT2/CNTR1 input [INT2 interrupt]
INT2/CNTR1 pin function Programmable I/O port, count source input or INT2 interrupt input
Read from timer Count value can be read out by reading TYPR register.
Same applies to PREY register.
Write to timer
Select function • Event counter function
Notes:
1. The IR bit in the TYIC register is set to "1" (interrupt requested) if you write to the TYPR or PREY register while both
of the following conditions are met.
Conditions:
• TYWC bit in TYZMR register is "0" (write to reload register and counter simultaneously)
• TYS bit is "1" (count start)
To write to the TYPR or PREY register in the above state, disable interrupts before writing.
1
Value written to TYPR register is written to both reload register and counter or written to
only reload register. Selected by program.
Same applies to PREY register.
When setting TYCK1 to TYCK0 bits to “112”, an external signal fed to CNTR1 pin is
counted.
• INT2/CNTR1 switching bit
Active edge of count source is selected by R1EDG bit.
Rev.0.91 2003 Sep 08 page 83 of 184
Under development
R8C/11 Group
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Preliminary specification
Specifications in this manual are tentative and subject to change.
Symbol Address After reset
TYZMR 0080
0
16
00
12.2 Timer (Timer Y)
16
FunctionBit symbol
TYMOD0
R1EDG
TYWC
TYS
TZMOD0
Bit name
Timer Y operation
mode bit
INT2/CNTR1 polarity
switching bit
Timer Y write
control bit
Timer Y count
start flag
Timer Z-related bit
1
2
0 : Timer mode
0 : Rising edge
1 : Falling edge
0 : Write to reload register and counter
simultaneously
1 : Write to reload register
0 : Stops counting
1 : Starts counting
TZMOD1
TZWC
TZS
Notes:
1. The IR bit in the INT2IC register may be set to “1” (interrupt requested) when the R1EDG bit is rewritten.
Refer to the paragraph 1.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
2. When TYS bit= 1 (starts counting), the value set in the TYWC bit is valid. If TYWC bit=0, the timer Y count value is
written to both reload register and counter. If TYWC bit=1, the timer Y count value is written to the reload register
only. When TYS bit=0 (stops counting), the timer Y count value is written to both reload register and counter
regardless of how the TYWC bit is set.
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
PUM 0084
0000
Bit symbol
(b3-b0)
TYOPL
TZOPL
INOSTG
INOSEG
Reserved bit
Timer Y output level
latch
Timer Z-related bits
Bit name
16
0016
Must set to “0”
Invalid in timer mode
Figure 12.15 TYZMR Register and PUM Register in Timer Mode
Function
RW
RW
RW
RW
RW
RW
Rev.0.91 2003 Sep 08 page 84 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer (Timer Y)
12.2.2 Programmable Waveform Generation Mode
In this mode, an signal output from the TYOUT pin is inverted each time the counter underflows, while
the values in the TYPR register and TYSC register are counted alternately (see “Table 12.8 Programmable Waveform Generation Mode Specifications”). A counting starts by counting the set value in the
TYPR register. Figure 12.16 shows the TYZMR register in programmable waveform generation mode.
Figure 12.17 shows the operation example.
Table 12.8 Programmable Waveform Generation Mode Specifications
Item Specification
Count source f1, f8, fRING
Count operation • Down count
• When the timer underflows, it reloads the contents of primary reload register and secondary reload register alternately before continuing counting.
Period fi/(n+1)((m+1)+(p+1))
n: set value in PREY register, m: set value in TYPR register, p: set value in TYSC register
Count start condition Write “1” (count start) to TYS bit in TYZMR register
Count stop condition Write “0” (count stop) to TYS bit in TYZMR register
Interrupt request generation timing
INT2/CNTR1 pin functions Pulse output
Read from timer Count value can be read out by reading TYPR register.
Write to timer
Select function • Output level latch select function
In half of count source, after Timer Y underflows during secondary period (at the same
time as the CNTR1 output change) [Timer Y interrupt].
1
Same applies to PREY register2.
Value written to TYPR register is written to only reload register.
Same applies to TYSC register and PREY register3.
The output level during primary and secondary periods is selected by the TYOPL bit.
• Programmable waveform generation output switching function
When the TYOCNT bit in the TYZOC register is set to “0”, the output from TYOUT is
inverted synchronously when Timer Y underflows during the secondary period. And
when set to “1”, a value in the P3_2 bit is output from TYOUT synchronously when Timer
Y underflows during the secondary period4.
Notes:
1. When the counting stopped, the output level is that in the secondary period.
2. Even when counting the secondary period, read out the TYPR register.
3. The set value in the TYPR register and TYSC register are made effective by writing a value to the TYPR register. The
written values are reflected to the waveform output from the next primary period after writing to the TYPR register.
4. The output is switched in sync with timer Y underflow in the secondary period.
Rev.0.91 2003 Sep 08 page 85 of 184
Under development
R8C/11 Group
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Preliminary specification
Specifications in this manual are tentative and subject to change.
Symbol Address After reset
TYZMR 0080
1
12.2 Timer (Timer Y)
16 0016
FunctionBit symbol
2
TYMOD0
R1EDG
TYWC
TYS
TZMOD0
Bit name
Timer Y operation
mode bit
INT2/CNTR
switching bit
Timer Y write
control bit
Timer Y count
start flag
Timer Z-related bit
1 polarity
1
1 : Programmable waveform generation mode
0 : Rising edge
1 : Falling edge
Must set to "1" in programmable
waveform generation mode.
0 : Stops counting
1 : Starts counting
TZMOD1
TZWC
TZS
Notes:
1. The IR bit in the INT2IC register may be set to “1” (interrupt requested) when the R1EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
2. When TYS bit= 1 (starts counting), the timer Y count value is written to the reload register only.
When TYS bit=0 (stops counting), the timer Y count value is written to both reload register and counter .
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
PUM 0084
0000
16
0016
RW
RW
RW
RW
RW
RW
RW
RW
RW
Bit symbol
(b3-b0)
TYOPL
TZOPL
INOSTG
INOSEG
Bit name
Reserved bit
Timer Y output level
latch
Timer Z-related bits
Function
Must set to “0”
0 : Outputs "H" for primary period
Outputs "L" for secondary period
Outputs "L" when the timer is stopped
1 : Outputs "L" for primary period
Outputs "H" for secondary period
Outputs "H" when the timer is stopped
RW
RW
RW
RW
RW
RW
Figure 12.16 TYZMR Register and PUM Register in Programmable Waveform Generation Mode
Rev.0.91 2003 Sep 08 page 86 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
Set to "1" by program
12.2 Timer (Timer Y)
TYS bit in TYZMR
register
Count source
Prescaler Y
underflow signal
Contents of Timer Y
IR bit in TYIC
register
TYOPL bit in PUM
register
"1"
"0"
"1"
"0"
"1"
"0"
Count starts
Set to "0" by program
Timer Y
secondary
reloads
0116 0016 0216
Timer Y
primary
reloads
0116 0016 0116
Set to "0" when interrupt request is
accepted, or set by program
0016 0216
CNTR1 pin output
"H"
Waveform output
started
Waveform output
inverted
Waveform output
inverted
"L"
Primary period
Conditions: PREY=0116, TYPR=01
16,
TYSC=02
Secondary period
16
Primary period
=
Figure 12.17 Timer Y Operation Example in Programmable Waveform Generation Mode
Rev.0.91 2003 Sep 08 page 87 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.3 Timer (Timer Z)
12.3 Timer Z
Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer
Z Secondary. Figure 12.18 shows a block diagram of Timer Z. Figures 12.19 to 12.21 show the TYZMR,
PREZ, TZSC, TZPR, TYZOC, PUM, and TCSS registers.
Timer Z has the following four operation modes.
• Timer mode: The timer counts an internal count source (clock source) or Timer Y underflow.
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse.
Peripheral data bus
TZCK1 to TZCK0
Timer Y underflow
INT0
TZMOD1 to TZMOD0=01
TZOUT
2
=00
f1
=012
f8
=102
=112
f2
Digital
filter
2, 102, 112
TZOCNT=0
TZOCNT=1
Reload register
Counter
PREZ register
Input polarity selected to be
one edge or both edges
INT0PL
INT0EN
PD3_1 bit in PD3 register
TZS
TZMOD1 to TZMOD0=10
TZSC register
Reload register
Polarity
select
INOSEG
TZOPL=1
TZOPL=0
2
,
112
Q
Q
Reload register
TZOS
Toggle
flip-flop
CLR
TZPR register
Counter
CK
Timer Z interrupt
INT0 interrupt
Write to TYZMR register
TZMOD1 to TZMOD0 bits=01
2, 102, 112
Figure 12.18 Timer Z Block Diagram
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Notes:
1. The IR bit in the INT2IC register may be set to “1” (interrupt requested) when the R1EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Source” in the Usage Notes Reference Book.
Symbol Address After reset
TYZMR 0080
TYMOD0
R1EDG
TYWC
TYS
TZMOD0
TZMOD1
TZWC
TZS
Bit name
Timer Y operation
mode bit
INT2/CNTR
switching bit
Timer Y write
control bit
Timer Y count
start flag
Timer Z operation
mode bit
Timer Z write
control bit
Timer Z count
start flag
1
polarity
1
16
00
16
FunctionBit symbol
0 : Timer mode
1 : Programmable waveform generation mode
0 : Rising edge
1 : Falling edge
Function varies depending on the operation
mode
0 : Stops counting
1 : Starts counting
b5 b4
0 0 : Timer mode
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable wait one-shot generation
mode
Function varies depending on the operation
mode
0 : Stops counting
1 : Starts counting
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.19 TYZMR Register
Rev.0.91 2003 Sep 08 page 88 of 184
Under development
R8C/11 Group
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.3 Timer (Timer Z)
Prescaler Z register
b7
Mode
Timer mode
Programmable
waveform
generation mode
Programmable
one-shot
generation mode
Programmable wait
one-shot generation
mode
Symbol Address After reset
b0
PREZ 0085
16
Function
Internal count source or Timer Y
underflow is counted
Internal count source or Timer Y
underflow is counted
Internal count source or Timer Y
underflow is counted
Internal count source or Timer Y
underflow is counted
FF16
Setting range
0016 to FF
00
16
to FF
16
to FF
00
16
to FF
00
16
16
16
Timer Z Secondary register
b7
Mode
Timer mode
Programmable
waveform
generation mode
Programmable
one-shot
generation mode
Programmable wait
one-shot generation
Notes:
1. Each value in the TZPR register and TZSC register is reloaded to the counter alternately for counting.
2. The count value can be read out by reading the TZSC register even when the secondary period is being
counted.
mode
Symbol Address After reset
b0
TZSC 0086
16
Function
Invalid
Underflow of Prescaler Z is
1
counted
Invalid
Underflow of Prescaler Z is
counted
(One-shot width is counted)
FF16
Setting range
0016 to FF
00
16
to FF
16
Timer Z Primary register
b7
Symbol Address After reset
b0
TZPR 0087
16
FF16
RW
RW
RW
RW
RW
16
RW
2
WO
WO
16
Mode
Timer mode
Programmable
waveform
generation mode
Programmable
one-shot
generation mode
Programmable wait
one-shot generation
Notes:
1. Each value in the TZPR register and TZSC register is reloaded to the counter alternately for counting.
mode
Underflow of Prescaler Z is
counted
Underflow of Prescaler Z is
counted
Underflow of Prescaler Z is
counted
(One-shot width is counted)
Underflow of Prescaler Z is
counted
(Wait period is counted)
Function
1
Setting range
0016 to FF
0016 to FF
16
to FF
00
00
16
to FF
16
16
16
16
Timer Y, Z output control register
b7 b6 b5 b4 b3 b2 b1 b0
Notes:
1. This bit is set to "0" when the output of one-shot waveform is completed. The TZOS bit should be set to "0" if the
one-shot waveform output is terminated by setting the TYS bit in the TYZMR to "0" during the waveform output.
2. This bit is enabled only when operating in programmable waveform generation mode.
Symbol Address After reset
TYZOC 008A
name
TZOS
TYOCNT
TZOCNT
(b7-b3)
Timer Z one-shot
start bit
Timer Y programmable
waveform generation
output switching bit
Timer Z programmable
waveform generation
output switching bit
Nothing is assigned.
When write, set to "0". When read, its content is "0".
16
Bit
1
0 : Stops one-shot
1 : Starts one-shot
0 : Outputs programmable waveform
1 : Outputs the value of P3
2
0 : Outputs programmable waveform
1 : Outputs the value of P3
2
00
16
FunctionBit symbol
2
port register
1
port register
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.20 PREZ Register, TZSC Register, TZPR Register, and TYZOC Register
Rev.0.91 2003 Sep 08 page 89 of 184
Under development
R8C/11 Group
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Preliminary specification
Specifications in this manual are tentative and subject to change.
Symbol Address After reset
PUM 0084
0000
16
12.3 Timer (Timer Z)
0016
Bit symbol
(b3-b0)
TYOPL
TZOPL
INOSTG
INOSEG
Bit name
Reserved bit
Timer Y output level
latch
Timer Z output level
latch
INT0 pin one-shot
trigger control bit
2
(Timer Z)
INT0 pin one-shot trigger
polarity select bit
1
(Timer Z)
Function
Must set to “0”
Function varies depending on the operation mode
Function varies depending on the operation mode
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid
0 : Edge trigger at falling edge
1 : Edge trigger at rising edge
Notes:
1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is "0" (one-edge).
2. The INOSGT bit must be set to "1" after the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register
are set.
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
00
Notes:
1. Avoid switching a count source, while a counter is in progress. Timer counter must be stopped before switching a count
source.
Symbol Address After reset
TCSS 008E
Bit symbol
TXCK0
Bit name
Timer X count source
select bit
1
TXCK1
16
b1 b0
0 0 : f
0 1 : f
1 0 : f
1 1 : f
TYCK0
TYCK1
TZCK0
TZCK1
Timer Y count source
select bit
Timer Z count source
select bit
1
1
b3 b2
0 0 : f
0 1 : f
1 0 : f
1 1 : Selects input from CNTR1 pin
b5 b4
0 0 : f
0 1 : f
1 0 : Selects Timer Y underflow
1 1 : f
(b7-b6)
Reserved bit
Must be set to “0”
0016
Function
1
8
32
2
1
8
RING
1
8
2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.21 PUM Register and TCSS Register
Rev.0.91 2003 Sep 08 page 90 of 184
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