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R8C-10
User Manual
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RENESAS R8C-10 User Manual

R8C/10 Group
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / R8C /Tiny SERIES
All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).
Rev. 1.20 Revision date: Jan 27, 2006
www.renesas.com

Keep safety first in your circuit designs!

1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap­propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non­flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2.
Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro­grams, algorithms, or circuit application examples contained in these materials.
3.
All information contained in these materials, including product data, diagrams, charts, pro­grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con­tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis­tributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by vari­ous means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com).
4.
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5.
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6.
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7.
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8.
Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

How to Use This Manual

0
1. Introduction
This hardware manual provides detailed information on the R8C/10 Group of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
X X X r e g i s t e r
b 7b 6b 5b 4b 3b2b 1b 0
0
d d r e s
f t e r r e s e
X S y m b o lA
X X XX
X X X
XXX1
(b2)
( b 3 )
XXX4
XXX5
X X X 6
X X X 7
Bit NameBit symbol
X X X B i t
N o t h i n g i s a s s i g n e d . W h e n w r i t e , s h o u l d s e t t o " 0 " . W h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e .
R e s e r v e d B i t
X X X B i t
XXX Bit
sA
X0
b 1 b 0
1 0 : X X X 0 1 : X X X 1 0 : A v o i d t h i s s e t t i n g 1 1 : X X X
Must set to “0”
Function varies depending on each operation mode
0: XXX 1: XXX
0
h
t
Function
*5
*1
Blank:Set to “0” or “1” according to the application 0: Set to “0” 1: Set to “1” X: Nothing is assigned
*2
RW: Read and write RO: Read only WO: Write only
−: Nothing is assigned
*3
•Reserved bit Reserved bit. Set to specified value.
*4
•Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to “0” when writing to this bit.
•Do not set to this value The operation is not guaranteed when a value is set.
•Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode.
*5
Follow the text in each manual for binary and hexadecimal notations.
*1
RW
RW
RW
RW
R W
W O
R W
RO
*2
*3
*4
3. M16C Family Documents
The following documents were prepared for the M16C family.
(1)
Document
Short Sheet Data Sheet Hardware Manual
Software Manual
Application Note
RENESAS TECHNICAL UPDATE
NOTES:
1. Before using this material, please visit the our website to verify that this is the most updated document available.
Hardware overview Hardware overview and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts). *Refer to the application note for how to use peripheral functions.
Detailed description of assembly instructions and microcomputer performance of each instruction
• Usage and application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
Preliminary report about the specification of a product, a document, etc.
Contents

Table of Contents

SFR Page Reference
Chapter 1. Overview............................................................. 1
1.1 Applications ...................................................................................................................1
1.2 Performance Overview..................................................................................................2
1.3 Block Diagram ............................................................................................................... 3
1.4 Product Information ...................................................................................................... 4
1.5 Pin Assignments............................................................................................................5
1.6 Pin Description ..............................................................................................................6
Chapter 2. Central Processing Unit (CPU)......................... 7
2.1 Data Registers (R0, R1, R2 and R3 ) .............................................................................7
2.2 AddressRegisters (A0 and A1) ......................................................................................8
2.3 Frame Base Register( FB ).............................................................................................8
2.4 Interrupt Table Register (INTB ).....................................................................................8
2.5 Program Counter (PC )...................................................................................................8
2.6 User Stack Pointer (USP ) and Interrupt Stack Pointer (ISP )..................................... 8
2.7 Static Base Register (SB ) ............................................................................................. 8
2.8 Flag Register (FLG ) ....................................................................................................... 8
2.8.1 Carry Flag ( C Flag )................................................................................................................................8
2.8.2 Debug Flag ( D Flag ) ..............................................................................................................................8
2.8.3 Zero Flag ( Z Flag )..................................................................................................................................8
2.8.4 Sign Flag ( S Flag ).................................................................................................................................. 8
2.8.5 Register Bank Select Flag ( B Flag ) .....................................................................................................8
2.8.6 Overflow Flag ( O Flag)........................................................................................................................... 8
2.8.7 Interrupt Enable Flag ( I Flag ) ...............................................................................................................8
2.8.8 Stack Pointer Select Flag ( U Flag )....................................................................................................... 8
2.8.9 Processor Interrupt Priority Level ( IPL ) ..............................................................................................8
2.8.10 Reserved Area.......................................................................................................................................8
Chapter 3. Memory............................................................... 9
Chapter 4. Special Function Registers (SFR).................. 10
Chapter 5. Reset.................................................................. 14
5.1 Hardware Reset ............................................................................................................14
5.2 Software Reset..............................................................................................................14
5.3 Watchdog Timer Reset................................................................................................. 14
Chapter 6. Clock Generation Circuit.................................. 17
6.1 Main Clock.....................................................................................................................21
6.2 On-Chip Oscillator Clock .............................................................................................22
A-1
6.3 CPU Clock and Peripheral Function Clock ................................................................ 23
6.3.1 CPU Clock.............................................................................................................................................. 23
6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO) .......................................................23
6.3.3 fRING and fRING128 ...................................................................................................................................................................23
6.4 Power Control ...............................................................................................................24
6.4.1 Normal Operation Mode .......................................................................................................................24
6.4.2 Wait Mode ..............................................................................................................................................25
6.4.3 Stop Mode..............................................................................................................................................26
6.5 Oscillation Stop Detection Function...........................................................................28
6.5.1 How to Use Oscillation Stop Detection Function ..............................................................................28
Chapter 7. Protection.......................................................... 30
Chapter 8. Processor Mode................................................ 31
8.1 Types of Processor Mode ............................................................................................31
Chapter 9. Bus..................................................................... 32
Chapter 10. Interrupt........................................................... 33
10.1 Interrupt Overview......................................................................................................33
10.1.1 Type of Interrupts................................................................................................................................33
10.1.2 Software Interrupts .............................................................................................................................34
10.1.3 Hardware Interrupts............................................................................................................................35
10.1.4 Interrupts and Interrupt Vector..........................................................................................................36
10.1.5 Interrupt Control .................................................................................................................................38
______
10.2 INT Interrupt ................................................................................................................46
10.2.1 INT0 Interrupt ......................................................................................................................................46
10.2.2 INT0 Input Filter...................................................................................................................................47
10.2.3 INT1 Interrupt and INT2 Interrupt ......................................................................................................48
10.2.4 INT3 Interrupt ......................................................................................................................................49
________
_______
______ ______
______
10.3 Key Input Interrupt .....................................................................................................50
10.4 Address Match Interrupt ............................................................................................51
Chapter 11. Watchdog Timer.............................................. 53
Chapter 12. Timers.............................................................. 55
12.1 Timer X ...........................................................................................................................56
12.1.1 Timer Mode ..........................................................................................................................................58
12.1.2 Pulse Output Mode .............................................................................................................................59
12.1.3 Event Counter Mode ........................................................................................................................... 60
12.1.4 Pulse Width Measurement Mode.......................................................................................................61
12.1.5 Pulse Period Measurement Mode..................................................................................................... 63
12.2 Timer Y ...........................................................................................................................65
12.2.1 Timer Mode ..........................................................................................................................................68
12.2.2 Programmable Waveform Generation Mode ....................................................................................70
12.3 Timer Z ...........................................................................................................................73
12.3.1 Timer Mode ..........................................................................................................................................76
12.3.2 Programmable Waveform Generation Mode ....................................................................................78
A-2
12.3.3 Programmable One-shot Generation Mode...................................................................................... 80
12.3.4 Programmable Wait One-shot Generation Mode ............................................................................. 83
12.4 Timer C ........................................................................................................................86
Chapter 13. Serial Interface................................................ 89
13.1 Clock Synchronous Serial I/O Mode.........................................................................94
13.1.1 Polarity Select Function .....................................................................................................................97
13.1.2 LSB First/MSB First Select Function ................................................................................................97
13.1.3 Continuous Receive Mode ................................................................................................................. 98
13.2 Clock Asynchronous Serial I/O (UART) Mode ......................................................... 99
13.2.1 TxD10/RxD1 Select Function (UART1)............................................................................................102
13.2.2 TxD11 Select Function (UART1) ......................................................................................................102
13.2.3 Bit Rate ..............................................................................................................................................103
Chapter 14. A/D Converter................................................ 104
14.1 One-shot Mode ......................................................................................................... 108
14.2 Repeat Mode .............................................................................................................109
14.3 Sample & Hold ..........................................................................................................110
14.4 A/D conversion cycles ...........................................................................................110
14.5 Internal Equivalent Circuit of Analog Input........................................................... 111
14.6 Inflow Current Bypass Circuit ................................................................................ 112
14.7 Output Impedance of Sensor under A/D Conversion........................................... 113
Chapter 15. Programmable I/O Ports .............................. 115
15. 1 Description...............................................................................................................115
15.1.1 Port Pi Direction Register (PDi Register, i = 0, 1, 3, 4)................................................................... 115
15.1.2 Port Pi Register (Pi Register, i = 0 to 4)........................................................................................... 115
15.1.3 Pull-up Control Register 0, Pull-up Control Register 1 (PUR0 and PUR1 Registers) ................. 115
15.1.4 Port P1 Drive Capacity Control Register (DRR Register)..............................................................115
15.2 Port setting................................................................................................................122
15.3 Unassigned Pin Handling ........................................................................................ 128
Chapter 16. Electrical Characteristics............................. 129
Chapter 17. Flash Memory Version ................................. 140
17.1 Overview....................................................................................................................140
17.2 Memory Map..............................................................................................................141
17.3 Functions To Prevent Flash Memory from Rewriting............................................ 142
17.3.1 ID Code Check Function ..................................................................................................................142
17.4 CPU Rewrite Mode....................................................................................................143
17.4.1 EW0 Mode..........................................................................................................................................144
17.4.2 EW1 Mode..........................................................................................................................................144
17.4.3 Software Commands ........................................................................................................................150
17.4.4 Status Register..................................................................................................................................154
17.4.5 Full Status Check..............................................................................................................................155
17.5 Standard Serial I/O Mode .........................................................................................157
17.5.1 ID Code Check Function ..................................................................................................................157
A-3
Chapter 18. On-chip Debugger ........................................ 161
18.1 Address Match Interrupt ..........................................................................................161
18.2 Single Step Interrupt ................................................................................................161
18.3 UART1........................................................................................................................161
18.4 BRK Instrucstion ...................................................................................................... 161
Chapter 19. Usage Notes.................................................. 162
19.1 Stop Mode and Wait Mode.......................................................................................162
19.1.1 Stop Mode..........................................................................................................................................162
19.1.2 Wait Mode ..........................................................................................................................................162
19.2 Interrupts...................................................................................................................163
19.2.1 Reading Address 0000016 ............................................................................................................................................ 163
19.2.2 SP Setting ..........................................................................................................................................163
19.2.3 External Interrupt and Key Input Interrupt .....................................................................................163
19.2.4 Watchdog Timer Interrupt ................................................................................................................163
19.2.5 Changing Interrupt Factor................................................................................................................ 164
19.2.6 Changing Interrupt Control Register ..............................................................................................165
19.3 Clock Generation Circuit ......................................................................................... 166
19.3.1 Oscillation Stop Detection Function ...............................................................................................166
19.3.2 Oscillation Circuit Constants...........................................................................................................166
19.4 Timers........................................................................................................................167
19.3.1 Timers X, Y and Z..............................................................................................................................167
19.3.2 Timer X...............................................................................................................................................167
19.3.3 Timer Y ...............................................................................................................................................167
19.3.4 Timer Z ...............................................................................................................................................167
19.3.5 Timer C...............................................................................................................................................167
19.5 Serial Interface..........................................................................................................168
19.6 A/D Converter............................................................................................................169
19.7 Flash Memory Version ............................................................................................. 170
19.7.1 CPU Rewrite Mode ............................................................................................................................170
19.8 Noise..........................................................................................................................173
Chapter 20. Usage Notes for On-chip Debugger............ 174
Appendix 1 Package Dimensions.................................... 175
Appendix 2 Connecting Examples for Serial Writer and
On-chip Debugging Emulator .......................................... 176
Appendix 3 Example of Oscillation Evaluation Circuit.. 178
Register Index ................................................................... 179
A-4

SFR Page Reference

A d d r e s s R
0 0 0 0
1 6
0 0 0 1
1 6
0 0 0 2
1 6
0 0 0 3
1 6
M
0 0 0 4
1 6
P r o c e s s o r m o d e r e g i s t e r 0P
M
0 0 0 5
1 6
P r o c e s s o r m o d e r e g i s t e r 1P
0 0 0 6
1 6
System clock control register 0 CM0 19
M
0 0 0 7
1 6
S y s t e m c l o c k c o n t r o l r e g i s t e r 1C
0 0 0 8
1 6
0 0 0 9
1 6
Address match interrupt enable register AIER 52
R C
0 0 0 A
1 6
P r o t e c t r e g i s t e rP
0 0 0 B
1 6
C
0 0 0 C
1 6
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO
D T
0 0 0 D
1 6
W a t c h d o g t i m e r r e s e t r e g i s t e rW
D T
0 0 0 E
1 6
W a t c h d o g t i m e r s t a r t r e g i s t e rW
D
0 0 0 F
1 6
W a t c h d o g t i m e r c o n t r o l r e g i s t e rW
M A D
0 0 1 0
1 6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0R
0 0 1 1
1 6
0 0 1 2
1 6
0 0 1 3
1 6
M A D
0 0 1 4
1 6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R
0 0 1 5
1 6
0 0 1 6
1 6
0 0 1 7
1 6
0 0 1 8
1 6
0 0 1 9
1 6
0 0 1 A
1 6
0 0 1 B
1 6
0 0 1 C
1 6
0 0 1 D
1 6
N T 0
0 0 1 E
1 6
I N T 0 i n p u t f i l t e r s e l e c t r e g i s t e rI
0 0 1 F
1 6
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
e g i s t e
rS
y m b o l
P a g e
03 1 13 1
11 9
R3 0
D2 0
R5 4
S5 4
C5 4
05 2
15 2
F4 6
Blank columns are all reserved space. No use is allowed.
A d d r e s s R 0 0 4 01
6
0 0 4 11
6
0 0 4 21
6
0 0 4 31
6
0 0 4 41
6
0 0 4 51
6
0 0 4 61
6
0 0 4 71
6
0 0 4 81
6
0 0 4 91
6
0 0 4 A1
6
0 0 4 B1
6
0 0 4 C1
6
U P I
0 0 4 D1
6
K e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e rK
0 0 4 E1
6
A D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e rA D I C3 9
0 0 4 F1
6
0 0 5 01
6
0 T I
0 0 5 11
6
U A R T 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S
0 R I
0 0 5 21
6
U A R T 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S
1 T I
0 0 5 31
6
U A R T 1 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S
1 R I
0 0 5 41
6
U A R T 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S
N T 2 I
0 0 5 51
6
I N T 2 i n t e r r u p t c o n t r o l r e g i s t e rI
X I
0 0 5 61
6
T i m e r X i n t e r r u p t c o n t r o l r e g i s t e rT
Y I
0 0 5 71
6
T i m e r Y i n t e r r u p t c o n t r o l r e g i s t e rT
Z I
0 0 5 81
6
T i m e r Z i n t e r r u p t c o n t r o l r e g i s t e rT
N T 1 I
0 0 5 91
6
I N T 1 i n t e r r u p t c o n t r o l r e g i s t e rI
N T 3 I
0 0 5 A1
6
I N T 3 i n t e r r u p t c o n t r o l r e g i s t e rI
C I
0 0 5 B1
6
T i m e r C i n t e r r u p t c o n t r o l r e g i s t e rT
0 0 5 C1
6
N T 0 I
0 0 5 D1
6
I N T 0 i n t e r r u p t c o n t r o l r e g i s t e rI
0 0 5 E1
6
0 0 5 F1
6
0 0 6 01
6
0 0 6 11
6
0 0 6 21
6
0 0 6 31
6
0 0 6 41
6
0 0 6 51
6
0 0 6 61
6
0 0 6 71
6
0 0 6 81
6
0 0 6 91
6
0 0 6 A1
6
0 0 6 B1
6
0 0 6 C1
6
0 0 6 D1
6
0 0 6 E1
6
0 0 6 F1
6
0 0 7 01
6
0 0 7 11
6
0 0 7 21
6
0 0 7 31
6
0 0 7 41
6
0 0 7 51
6
0 0 7 61
6
0 0 7 71
6
0 0 7 81
6
0 0 7 91
6
0 0 7 A1
6
0 0 7 B1
6
0 0 7 C1
6
0 0 7 D1
6
0 0 7 E1
6
0 0 7 F1
6
e g i s t e
rS
y m b o l
P a g e
C3 9
C3 9
C3 9
C3 9
C3 9
C3 9
C3 9
C3 9
C3 9
C3 9 C3 9
C3 9
C3 9
B-1
SFR Page Reference
A d d r e s s R
Y Z M
0 0 8 01
6
T i m e r Y , Z m o d e r e g i s t e rT
R E Pr e s c a l e r Y r e g i s t e rP
0 0 8 11
6
Y S T i m e r Y s e c o n d a r y r e g i s t e rT
0 0 8 21
6
Y P T i m e r Y p r i m a r y r e g i s t e rT
0 0 8 31
6
U
T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r P
0 0 8 41
6
R E Pr e s c a l e r Z r e g i s t e rP
0 0 8 51
6
Z S T i m e r Z s e c o n d a r y r e g i s t e rT
0 0 8 61
6
Z P T i m e r Z p r i m a r y r e g i s t e rT
0 0 8 71
6
0 0 8 81
6
0 0 8 91
6
Y Z O T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e rT
0 0 8 A1
6
X M T i m e r X m o d e r e g i s t e rT
0 0 8 B1
6
R E Pr e s c a l e r X r e g i s t e rP
0 0 8 C1
6
T i m e r X r e g i s t e r r e g i s t e rT
0 0 8 D1
6
C S T i m e r c o u n t s o u r c e s e t t i n g r e g i s t e rT
0 0 8 E1
6
0 0 8 F1
6
0 0 9 01
6
T i m e r C r e g i s t e rT
0 0 9 11
6
0 0 9 21
6
0 0 9 31
6
0 0 9 41
6
0 0 9 51
6
N T E E x t e r n a l i n p u t e n a b l e r e g i s t e rI
0 0 9 61
6
0 0 9 71
6
I E K e y i n p u t e n a b l e r e g i s t e rK
0 0 9 81
6
0 0 9 91
6
C C T i m e r C c o n t r o l r e g i s t e r 0T
0 0 9 A1
6
C C T i m e r C c o n t r o l r e g i s t e r 1T
0 0 9 B1
6
M C a p t u r e r e g i s t e rT
0 0 9 C1
6
0 0 9 D1
6
0 0 9 E1
6
0 0 9 F1
6
0 M
0 0 A 01
6
U A R T 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r U
0 B R
0 0 A 11
6
U A R T 0 b i t r a t e g e n e r a t o r U
0 T
0 0 A 21
6
U A R T 0 t r a n s m i t b u f f e r r e g i s t e rU
0 0 A 31
6
0 C
0 0 A 41
6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 U
0 C
0 0 A 51
6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 U
0 R
0 0 A 61
6
U A R T 0 r e c e i v e b u f f e r r e g i s t e r U
0 0 A 71
6
1 M
0 0 A 81
6
U A R T 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r U
1 B R
0 0 A 91
6
U A R T 1 b i t r a t e r e g i s t e rU
1 T
0 0 A A1
6
U A R T 1 t r a n s m i t b u f f e r r e g i s t e rU
0 0 A B1
6
1 C
0 0 A C1
6
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 U
1 C
0 0 A D1
6
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 U
1 R
0 0 A E1
6
U A R T 1 r e c e i v e b u f f e r r e g i s t e r U
0 0 A F1
6
C O
0 0 B 01
6
t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 2 U
U A R T
0 0 B 11
6
0 0 B 21
6
0 0 B 31
6
0 0 B 41
6
0 0 B 51
6
0 0 B 61
6
0 0 B 71
6
0 0 B 81
6
0 0 B 91
6
0 0 B A1
6
0 0 B B1
6
0 0 B C1
6
0 0 B D1
6
0 0 B E1
6
0 0 B F1
6
e g i s t e
rS
y m b o l
P a g e
R6 5 / 7 3
Y6 6 C6 6 R6 6
M6 7 / 7 5
Z7 4
C7 4 R7 4
C6 6 / 7 4
R5 6
X5 7
X5 7
S5 7
C8
N4 6
N5 0
08 7
18 7
08 7
R9 2
G9 1
B9 1
09 2 19 3 B9 1
R9 2
G9 1
B9 1
09 2 19 3
B9 1
N9 3
7
Blank columns are all reserved space. No use is allowed.
A d d r e s s R
0 0 C 01 0 0 C 11 0 0 C 21 0 0 C 31 0 0 C 41 0 0 C 51 0 0 C 61 0 0 C 71 0 0 C 81 0 0 C 91 0 0 C A1 0 0 C B1 0 0 C C1 0 0 C D1 0 0 C E1 0 0 C F1 0 0 D 01 0 0 D 11 0 0 D 21 0 0 D 31 0 0 D 41 0 0 D 51 0 0 D 61 0 0 D 71 0 0 D 81 0 0 D 91 0 0 D A1 0 0 D B1 0 0 D C1 0 0 D D1 0 0 D E1 0 0 D F1 0 0 E 01 0 0 E 11 0 0 E 21 0 0 E 31 0 0 E 41 0 0 E 51 0 0 E 61 0 0 E 71 0 0 E 81 0 0 E 91 0 0 E A1 0 0 E B1 0 0 E C1 0 0 E D1 0 0 E E1 0 0 E F1 0 0 F 01 0 0 F 11 0 0 F 21 0 0 F 31 0 0 F 41 0 0 F 51 0 0 F 61 0 0 F 71 0 0 F 81 0 0 F 91 0 3 F A1 0 0 F B1 0 0 F C1 0 0 F D1 0 0 F E1 0 0 F F1
0 1 B 31 0 1 B 41 0 1 B 51 0 1 B 61 0 1 B 71
6
A D r e g i s t e rA
6 6 6 6 6 6 6 6 6
6 6
6
6 6 6
6 6 6 6
D C O N 21 0 A D c o n t r o l r e g i s t e r 2A
6 6
D C O N 01 0 AD c o n t r o l r e g i s t e r 0A
6
D C O N 11 0 A D c o n t r o l r e g i s t e r 1 A
6 6 6
6 6
6
6 6 6
P o r t P 0 r e g i s t e rP
6 6
P o r t P 1 r e g i s t e rP
D
6
P o r t P 0 d i r e c t i o n r e g i s t e rP
D
6
P o r t P 1 d i r e c t i o n r e g i s t e rP
6 6
P o r t P 3 r e g i s t e rP
6
D P o r t P 3 d i r e c t i o n r e g i s t e rP
6
P o r t P 4 r e g i s t e rP
6 6
D
6
P o r t P 4 d i r e c t i o n r e g i s t e rP
6 6 6 6
6 6 6 6 6 6 6 6 6 6 6 6 6
U R
6
P u l l - u p c o n t r o l r e g i s t e r 0 P
U R
6
P u l l - u p c o n t r o l r e g i s t e r 1 P P o r t P 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r D R R1 2 1
6 6
M R
6
F l a s h m e m o r y c o n t r o l r e g i s t e r 4 F
6
M R
6
F l a s h m e m o r y c o n t r o l r e g i s t e r 1 F
6
M R
6
F l a s h m e m o r y c o n t r o l r e g i s t e r 0 F
e g i s t e
rS
y m b o l
P a g e
D1 0 7
01 2 0
11 2 0
01 2 0
11 2 0
31 2 0
31 2 0
41 2 0
41 2 0
01 2 1
11 2 1
41 4 7 11 4 7
01 4 6
7 6
6
B-2
R8C/10 Group
REJ09B0019-0120
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

1. Overview

This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing instructions at high speed.

1.1 Applications

Electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.
Rev.1.20
Jan 27, 2006
Rev.1.20 Jan 27, 2006 page 1 of 180 REJ09B0019-0120
R8C/10 Group
1.2 Performance Overview
Table 1.1. lists the performance outline of this MCU.
Table 1.1 Performance outline
Item Performance
CPU Number of basic instructions 89 instructions
Minimum instruction execution time
Operating mode Single-chip Address space 1M bytes
Memory capacity See Table 1.2 “Product List” Peripheral Port Input/Output: 22 (including LED drive port), Input: 2 function LED drive port I/O port: 8
Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Serial interface •1 channel
A/D converter 10-bit A/D converter: 1 circuit, 8 channels
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt Internal: 9 factors, External: 5 factors,
Clock generation circuit 2 circuits
Oscillation stop detection function Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 16 MHZ) characteristics
Power consumption Typ. 8mA (VCC = 5.0 V, (f(XIN) = 16MHZ)
Flash memory Program/erase supply voltage
Program/erase endurance 100 times Operating ambient temperature -20 to 85 °C
Package 32-pin plastic mold LQFP
62.5 ns (f(XIN) = 16 MHZ, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)
Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Input capture circuit)
Clock synchronous, UART
•1 channel UART
Software: 4 factors, Priority level: 7 levels
•Main clock generation circuit (Equipped with a built-in
feedback resistor)
•On-chip oscillator
Main clock oscillation stop detection function
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ)
Typ. 5mA (VCC = 3.0 V, (f(XIN) = 10MHZ) Typ. 35µA (VCC = 3.0 V, Wait mode, Peripheral clock off) Typ. 0.7µA (VCC = 3.0 V, Stop mode) VCC = 2.7 to 5.5 V
-40 to 85 °C (D-version)
1. Overview
Rev.1.20 Jan 27, 2006 page 2 of 180 REJ09B0019-0120
R8C/10 Group

1.3 Block Diagram

Figure 1.1 shows this MCU block diagram.
1. Overview
I / O p o r t
P o r t P 0
Pe r i p h e r a l f u n c t i o n s
T i m e r
T i m e r X ( 8 b i t s ) T i m e r Y ( 8 b i t s ) T i m e r Z ( 8 b i t s )
T i m e r C ( 1 6 b i t s )
W a t c h d o g t i m e r
( 1 5 b i t s )
R O M
RAM
1 2
Port P4
( 1 )
(2)
8
8
Port P1
A / D c o n v e r t e r
( 1 0 b i t s ✕ 8 c h a n n e l s )
U A R T o r C l o c k s y n c h r o n o u s
s e r i a l I / O
( 8 b i t s ✕ 1 c h a n n e l )
U A R T
( 8 b i t s ✕ 1 c h a n n e l )
R 8 C / T i n y S e r i e s C P U c o r e
R 0 LR 0 H
R1H R1L
R 2 R 3
A 0 A1 FB
P o r t P 3
SB
USP
I S P
INTB
P C
FLG
5
System clock generator
X
I N
- X
O n - c h i p o s c i l l a t o r
O U T
M e m o r y
M u l t i p l i e r
Figure 1.1 Block Diagram
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Rev.1.20 Jan 27, 2006 page 3 of 180 REJ09B0019-0120
R8C/10 Group

1.4 Product Information

Table 1.2 lists the product inforamation.
1. Overview
Table 1.2 Product Information
Type No. R5F21102FP R5F21103FP
R5F21104FP R5F21102DFP
R5F21103DFP R5F21104DFP
ROM capacity
8K bytes 12K bytes 16K bytes
8K bytes 12K bytes 16K bytes
T y p e N o .R 5 F 2 11 04DF P
As of January 2006
RAM capacity
512 bytes 768 bytes
1K bytes
512 bytes 768 bytes
1K bytes
Package type:
FP : PLQP0032GB-A
Classification: D: Operating am bient temperature –40 °C to 85 °C No symbol: Operating ambient temperature –20 °C to 85 °C
Package type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A
PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A
Flash memory version
D version
Remarks
ROM capacity:
2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes.
R8C/10 group
R8C/Tiny series
Memory type:
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.1.20 Jan 27, 2006 page 4 of 180 REJ09B0019-0120
R8C/10 Group

1.5 Pin Assignment

Figure 1.3 shows the pin Assignments (top view).
PIN CONFIGURATION (top view)
A
2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7
P 06/ A N1 P05/AN2
P 04/ A N3
P03/AN4 P 02/ A N5 P 01/ A N6
P 00/ A N7/T x D1
M O D E
2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
1
1 2 3 4 5 6 7 8
R0
N0
C
30/
07/
VC
P
C N T
I
P
R 8 C / 1 0 G r o u p
1. Overview
R1
N
CI
F
T
T3/
T2/
VR
ZO
C/
S
VS
31/
U
P
A
T
E
33/
32/
VC
P
P
I N
I N
T
C N T
A
P45/INT0
1 6 1 5
P 10/ K I0 P 11/ K I1
1 4 1 3
P 12/ K I2
1 2
P 13/ K I3 P 14/ T x D0
1 1 1 0
P15/RxD0
9
P 16/ C L K0
D1
0/
D1 37/
P
T x
R x
NOTES:
1. P4
7 functions only as an input port.
2. When using On-chip debugger, do not use pins P00/AN7/TxD11 and P37/TxD10/RxD1.
3. Do not connect IVcc to Vcc.
Figure 1.3 Pin Assignments (Top View)
)
S
S
T
(
1
VS
47
C
T/
R
E S E
N
XO
P
U
C
46
VS
R0
VC
N/
XI
P
T1/ 17/
P
I N
C N T
Package: PLQP0032GB-A (32P6U-A)
Rev.1.20 Jan 27, 2006 page 5 of 180 REJ09B0019-0120
R8C/10 Group

1.6 Pin Description

Table 1.3 shows the pin description
Table 1.3 Pin description
Signal name Pin name I/O type Power supply Vcc, I input Vss IVcc IVcc O
Analog power AVcc, I supply input AVss
Reset input
___________
RESET I CNVss CNVss I MODE MODE I Main clock input XIN I
Main clock output XOUT O
_____
INT interrupt input Key input interrupt Timer X CNTR0 I/O
_______ _______
INT0 to INT3 I
_____ _____
KI0 to KI3 I
____________
CNTR0 O Timer Y CNTR1 I/O Timer Z TZOUT O Timer C TCIN I Serial interface CLK0 I/O
RxD0, RxD1 I
TxD0, TxD10,O
TxD11 Reference voltage VREF I input A/D converter AN0 to AN7 I I/O port P00 to P07, I/O
P10 to P17,
P30 to P33, P37,
P45
Input port P46, P47 I
NOTES :
1. Refer to "19.8 Noise" for the connecting reference resistor value.
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the Vss pin. This pin is to stabilize internal power supply. Connect this pin to Vss via a capacitor (0.1 µF). Do not connect to Vcc.
Power supply input pins for A/D converter. Connect the AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a capacitor between pins AVcc and AVss.
Input “L” on this pin resets the MCU. Connect this pin to Vss via a resistor. Connect this pin to Vcc via a resistor. These pins are provided for the main clock generat­ing circuit I/O. Connect a ceramic resonator or a crys­tal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open.
______
INT interrupt input pins. Key input interrupt pins. Timer X I/O pin Timer X output pin Timer Y I/O pin Timer Z output pin Timer C input pin Transfer clock I/O pin. Serial data input pins. Serial data output pins.
Reference voltage input pin for A/D converter. Con­nect the VREF pin to Vcc. Analog input pins for A/D converter These are 8-bit CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pull­up resistor or not by program. P10 to P17 also function as LED drive ports. Port for input-only.
1. Overview
Function
(1)
Rev.1.20 Jan 27, 2006 page 6 of 180 REJ09B0019-0120
R8C/10 Group 2. Central Processing Unit (CPU)
e g
d

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.
b 3 1
R 2 R 3
b 1 9
I N T B H
The 4-high order bits of INTB are INTBH and the 16-low bits of INTB ar e INTBL.
b19
b 1 5 b 0 b7 b8
I P L
i s t e r b a n k c o m p r i s e s t h e s e r e g i s t e r s . T w o s e t s o f r e g i s t e r b a n k s a r e p r o v i d e
N O T E S : 1 .
A r
b 1 5 b
R 0 H ( h i g h - o r d e r o f R 0 )
R1H (high-order of R1)
8
b7 b 0
R 0 L ( h i g h - o r d e r o f R 0 ) R1L (high-order of R1)
R 2
Data registers
(1)
R 3 A0 A 1 FB
b 1 5 b
I N T B L
P C
b 1 5 b
U S P
ISP
SB
b 1 5 b
FLG
Address registers Frame base registers
0
Interrupt table re gis ter
b0
Program counter
0
User stack pointer Interrupt stack pointer Static base register
0
Flag register
(1)
(1)
CDZSBOIU
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit
Figure 2.1 CPU Register

2.1 Data Registers (R0, R1, R2 and R3)

R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.
Rev.1.20 Jan 27, 2006 page 7 of 180 REJ09B0019-0120
R8C/10 Group 2. Central Processing Unit (CPU)

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative address­ing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register indicates the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC, 20 bits wide, indicates the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is a 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.

2.8.2 Debug Flag (D)

The D flag is for debug only. Set to “0”.

2.8.3 Zero Flag (Z)

The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.

2.8.4 Sign Flag (S)

The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.

2.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is set to “1”.

2.8.6 Overflow Flag (O)

The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The I flag is set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”. The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

When write to this bit, set to “0”. When read, its content is indeterminate.
Rev.1.20 Jan 27, 2006 page 8 of 180 REJ09B0019-0120
R8C/10 Group 3. Memory

3. Memory

Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses 0000016 to FFFFF16. The internal ROM is allocated lower addresses beginning with address 0FFFF16. For example, a 16­Kbyte internal ROM is allocated addresses from 0C00016 to 0FFFF16. The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing data, but for calling subroutines and stacks when interrupt request is acknowledged. Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function control registers are located them. All addresses, which have nothing allocated within the SFR, are re­served area and cannot be accessed by users.
00000
16
(See Chapter 4 for details.)
002FF
16
00400
16
Internal RAM
0XXXX
16
0YYYY
16
Internal ROM
0FFFF
16
Expansion area
FFFFF
16
NOTES :
1. Blank spaces are reserved. No access is allowed.
Type name
R5F21104FP, R5F21104DFP R5F21103FP, R5F21103DFP R5F21102FP, R5F21102DFP
SFR
Internal ROM
Size
16K bytes 12K bytes
8K bytes
0FFDC
16
0FFFF
16
Address 0YYYY
0C000
16
0D000
16
0E000
16
Undefined instruction
Overflow BRK instruction Address match
Watchdog timer•Oscillation stop detection
Single step
(Reserved) (Reserved)
Reset
Internal RAM
16
Size
1K bytes 768 bytes 512 bytes
Address 0XXXX
007FF 006FF 005FF
16 16 16 16
Figure 3.1 Memory Map
Rev.1.20 Jan 27, 2006 page 9 of 180 REJ09B0019-0120
R8C/10 Group 4. Special Function Register (SFR)

4. Special Function Register (SFR)

SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information
Table 4.1 SFR Information(1)
A d d r e s s
0 0 0 01
6
0 0 0 11
6
0 0 0 21
6
0 0 0 31
6
M
X X
0 0 0 41
6
P r o c e s s o r m o d e r e g i s t e r 0P
M
0 X X X 0 X
0 0 0 51
6
P r o c e s s o r m o d e r e g i s t e r 1P
0 0 0 61
6
System clock control register 0 CM0 01101000
0 0 0 71
6
System clock control register 1 CM1 00100000
0 0 0 81
6
I E
X X X X X 0
0 0 0 91
6
A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e rA
R C
0 X X X 0 0
0 0 0 A1
6
P r o t e c t r e g i s t e rP
0 0 0 B1
6
C
0 0 0 0 1 0
0 0 0 C1
6
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO
D T
0 0 0 D1
6
W a t c h d o g t i m e r r e s e t r e g i s t e rW
0 0 0 E1
6
Watchdog timer start register WDTS XX
D
0 0 1 1 1 1
0 0 0 F1
6
W a t c h d o g t i m e r c o n t r o l r e g i s t e rW
M A D
0 0 1 01
6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0R
0 0 1 11
6
0 0 1 21
6
0 0 1 31
6
M A D
0 0 1 41
6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R
0 0 1 51
6
0 0 1 61
6
0 0 1 71
6
0 0 1 81
6
0 0 1 91
6
0 0 1 A1
6
0 0 1 B1
6
0 0 1 C1
6
0 0 1 D1
6
0 0 1 E1
6
INT0 input filter select register INT0F XXXXX000
0 0 1 F1
6
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
N O T E S : 1 . B l a n k s p a c e s a r e r e s e r v e d . N o a c c e s s i s a l l o w e d . X : U n d e f i n e d
(1)
R e g i s t e rS
y m b o l
A
0X 10
RX
R0
D0
RX
C0
00
10
0 0 X 0
0 0 X 0
f t e r r e s e
X
0
1 6 1 6
1 6
0
1 6 1 6
1 6
X0X 0 0
1 6 16
t
2
0
2 2 2
0
2
0
2
0
2
1
2
2
Rev.1.20 Jan 27, 2006 page 10 of 180 REJ09B0019-0120
R8C/10 Group 4. Special Function Register (SFR)
Table 4.2 SFR Information(2)
A d d r e s s
0 0 4 0
1 6
0 0 4 1
1 6
0 0 4 2
1 6
0 0 4 3
1 6
0 0 4 4
1 6
0 0 4 5
1 6
0 0 4 6
1 6
0 0 4 7
1 6
0 0 4 8
1 6
0 0 4 9
1 6
0 0 4 A
1 6
0 0 4 B
1 6
0 0 4 C
1 6
0 0 4 D
1 6
Key input interrupt control register KUPIC XXXXX000
D I
X X X X 0 0
0 0 4 E
1 6
A D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e rA
0 0 4 F
1 6
0 0 5 0
1 6
0 0 5 1
1 6
UART0 transmit interrupt control register
0 0 5 2
1 6
UART0 receive interrupt control register
0 0 5 3
1 6
UART1 transmit interrupt control register
0 0 5 4
1 6
UART1 receive interrupt control register
0 0 5 5
1 6
INT2 interrupt control register INT2IC XXXXX000
0 0 5 6
1 6
Timer X interrupt control register TXIC XXXXX000
0 0 5 7
1 6
Timer Y interrupt control register TYIC XXXXX000
0 0 5 8
1 6
Timer Z interrupt control register TZIC XXXXX000
0 0 5 9
1 6
INT1 interrupt contro l register INT1IC XXXXX000
0 0 5 A
1 6
INT3 interrupt contro l register INT3IC XXXXX000
0 0 5 B
1 6
Timer C interrupt control register TCIC XXXXX000
0 0 5 C
1 6
0 0 5 D
1 6
INT0 interrupt control register INT0IC XX00X000
0 0 5 E
1 6
0 0 5 F
1 6
0060
16
0061
16
0062
16
0063
16
0064
16
0065
16
0066
16
0067
16
0068
16
0069
16
006A
16
006B
16
006C
16
006D
16
006E
16
006F
16
0070
16
0071
16
0072
16
0073
16
0074
16
0075
16
0076
16
0077
16
0078
16
0079
16
007A
16
007B
16
007C
16
007D
16
007E
16
007F
16
NOTES :
1. Blank spaces are reserved. No access is allowed.
(1)
R e g i s t e r Symbol A f t e r r e s e t
X : Undefined
CX
S0TIC XXXXX000 S0RIC XXXXX000
S1TIC XXXXX000 S1RIC XXXXX000
2
0
2
2
2 2 2
2 2 2 2
2 2 2
2
Rev.1.20 Jan 27, 2006 page 11 of 180 REJ09B0019-0120
R8C/10 Group 4. Special Function Register (SFR)
Table 4.3 SFR Information(3)
A d d r e s s
N O T E S : 1 . B l a n k s p a c e s a r e r e s e r v e d . N o a c c e s s i s a l l o w e d .
Y Z M
0 0 8 0
1 6
T i m e r Y , Z m o d e r e g i s t e rT
R E
0 0 8 1
1 6
P r e s c a l e r Y r e g i s t e rP
Y S T i m e r Y s e c o n d a r y r e g i s t e rT
0 0 8 2
1 6
Timer Y primary register TYPR FF
0 0 8 3
1 6
U T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e rP
0 0 8 4
1 6
R E P r e s c a l e r Z r e g i s t e rP
0 0 8 5
1 6
Z S T i m e r Z s e c o n d a r y r e g i s t e rT
0 0 8 6
1 6
Z P T i m e r Z p r i m a r y r e g i s t e rT
0 0 8 7
1 6
0 0 8 8
1 6
0 0 8 9
1 6
Y Z O T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e rT
0 0 8 A
1 6
X M T i m e r X m o d e r e g i s t e rT
0 0 8 B
1 6
R E P r e s c a l e r X r e g i s t e rP
0 0 8 C
1 6
T i m e r X r e g i s t e rT
0 0 8 D
1 6
C S C o u n t s o u r c e s e t r e g i s t e rT
0 0 8 E
1 6
0 0 8 F
1 6
0 0 9 0
1 6
T i m e r C r e g i s t e rT
0 0 9 1
1 6
0 0 9 2
1 6
0 0 9 3
1 6
0 0 9 4
1 6
0 0 9 5
1 6
N T E
0 0 9 6
1 6
E x t e r n a l i n p u t e n a b l e r e g i s t e rI
0 0 9 7
1 6
I E K e y i n p u t e n a b l e r e g i s t e rK
0 0 9 8
1 6
0 0 9 9
1 6
C C T i m e r C c o n t r o l r e g i s t e r 0T
0 0 9 A
1 6
Timer C contro l register 1 TCC1 00
0 0 9 B
1 6
0 0 9 C
1 6
Capture regist er TM0 00
0 0 9 D
1 6
0 0 9 E
1 6
0 0 9 F
1 6
0 0 A 0
1 6
UART0 transmit/receive mode register
0 0 A 1
1 6
UART0 bit rate generator U0BRG XX
0 T
0 0 A 2
1 6
U A R T 0 t r a n s m i t b u f f e r r e g i s t e rU
0 0 A 3
1 6
0 0 0 1 0 0
0 0 A 4
1 6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0
0 0 0 0 0 1
0 0 A 5
1 6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1
0 R
0 0 A 6
1 6
U A R T 0 r e c e i v e b u f f e r r e g i s t e r U
0 0 A 7
1 6
0 0 A 8
1 6
UART1 transmit/receive mode register
0 0 A 9
1 6
UART1 bit rate generator U1BRG XX
0 0 A A
1 6
UART1 transmit buffer register U1TB XX
0 0 A B
1 6
0 0 A C
1 6
UART1 transmit/receive control register 0
0 0 0 0 0 1
0 0 A D
1 6
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1
0 0 A E
1 6
UART1 receive buffer register U1RB XX
0 0 A F
1 6
0 0 B 0
1 6
UART transmit/receive control register 2
0 0 B 1
1 6
0 0 B 2
1 6
0 0 B 3
1 6
0 0 B 4
1 6
0 0 B 5
1 6
0 0 B 6
1 6
0 0 B 7
1 6
0 0 B 8
1 6
0 0 B 9
1 6
0 0 B A
1 6
0 0 B B
1 6
0 0 B C
1 6
0 0 B D
1 6
0 0 B E
1 6
0 0 B F
1 6
(1)
R e g i s t e rS
X : U n d e f i n e d
y m b o l
A
R0
YF
CF
f t e r r e s e
1 6
0
F
1 6
F
1 6 16
M0
ZF CF RF
C0
R0
XF
XF
S0
C0
N0
N0
00
0 0
0
1 6
F
1 6
F
1 6
F
1 6
0
1 6
0
1 6
F
1 6
F
1 6
0
1 6
0
1 6 1 6
0
1 6
0
1 6
0
1 6 16 16
00
16
U0MR 00
16
16
BX
U 0 C 00 U 0 C 10
BX
U1MR 00
X X
X X
X
1 6 1 6
0 0
X
1 6 1 6
16
16 16
XX
16
U1C0 00001000 U 1 C 10
XX
UCON 00
0
16
16
16
t
2 2
2 2
Rev.1.20 Jan 27, 2006 page 12 of 180 REJ09B0019-0120
R8C/10 Group 4. Special Function Register (SFR)
Table 4.4 SFR Information(4)
A d d r e s s
X X X X X X
0 0 C 0
1 6
A D r e g i s t e rA
0 0 C 1
1 6
0 0 C 2
1 6
0 0 C 3
1 6
0 0 C 4
1 6
0 0 C 5
1 6
0 0 C 6
1 6
0 0 C 7
1 6
0 0 C 8
1 6
0 0 C 9
1 6
0 0 C A
1 6
0 0 C B
1 6
0 0 C C
1 6
0 0 C D
1 6
0 0 C E
1 6
0 0 C F
1 6
0 0 D 0
1 6
0 0 D 1
1 6
0 0 D 2
1 6
0 0 D 3
1 6
D C O N
0 0 D 4
1 6
A D c o n t r o l r e g i s t e r 2A
0 0 D 5
1 6
D C O N
0 0 0 0 X X
0 0 D 6
1 6
A D c o n t r o l r e g i s t e r 0A
D C O N
0 0 D 7
1 6
A D c o n t r o l r e g i s t e r 1 A
0 0 D 8
1 6
0 0 D 9
1 6
0 0 D A
1 6
0 0 D B
1 6
0 0 D C
1 6
0 0 D D
1 6
0 0 D E
1 6
0 0 D F
1 6
00E0
16
P o r t P 0 r e g i s t e rP
00E1
16
P o r t P 1 r e g i s t e rP
D
00E2
16
P o r t P 0 d i r e c t i o n r e g i s t e rP
00E3
16
Port P1 direction register PD1 00
00E4
16
00E5
16
P o r t P 3 r e g i s t e rP
00E6
16
00E7
16
Port P3 direction register PD3 00
00E8
16
Port P4 register P4 XX
00E9
16
D
00EA
16
P o r t P 4 d i r e c t i o n r e g i s t e rP
00EB
16
00EC
16
00ED
16
00EE
16
00EF
16
00F0
16
00F1
16
00F2
16
00F3
16
00F4
16
00F5
16
00F6
16
00F7
16
00F8
16
00F9
16
03FA
16
00FB
16
U R
0 X X 0 0 0
00FC
16
P u l l - u p c o n t r o l r e g i s t e r 0 P
00FD
16
Pull-up control register 1 PUR1 XXXXXX0X
00FE
16
Port P1 drive capacity control register DRR 00
00FF
16
(1)
R e g i s t e r
Symbol After reset
DX
X X X X X X X X
20
0
00 10
0
0X 1X
00
3X
40
X X
0
X
0
00
X
2 2
1 6
X
2
1 6
1 6
1 6 1 6 16
1 6
16
16
1 6
0
2
2
16
01B3
16
Flash memory control register 4 FMR4 01000000
01B4
16
M R
1 0 0 X X 0
01B5
16
F l a s h m e m o r y c o n t r o l r e g i s t e r 1 F
01B6
16
M R
0 0 0 0 0 0
01B7
16
F l a s h m e m o r y c o n t r o l r e g i s t e r 0 F
NOTES:
1. Blank columns, 0100
16
to 01B216 and 01B816 to 02FF16 are all reserved. No access is allowed.
X : Undefined
Rev.1.20 Jan 27, 2006 page 13 of 180 REJ09B0019-0120
10
00
1
2
X
2
2
R8C/10 Group 5. Reset

5. Reset

There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset.

5.1 Hardware Reset

A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply voltage is within the recommended operating condition, the pins are initial­ized (see Table 5.1 “Pin Status When RESET Pin Level is 'L'”). When the input level at the
____________
RESET pin is released from “L” to “H”, the CPU and SFR are initialized, and the program is executed starting from the address indicated by the reset vector. Figure 5.1 shows the CPU register status after reset and figure 5.2 shows the reset sequence. After reset, the on-chip oscillator clock divided by 8 is automatically selected for the CPU. The internal RAM is not initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM becomes indeterminate. Figures 5.3 to 5.4 show the reset circuit example. Refer to Chapter 4, “Special Function Register (SFR)” for the status of SFR after reset.
____________
____________ ____________
____________
• When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin. (2) Wait for 500 µs (1/fRING ✕ 20).
____________
(3) Apply an “H” signal to the RESET pin.
• Power on
____________
(1) Apply an “L” signal to the RESET pin. (2) Let the power supply voltage increase until it meets the recommended operating condition. (3) Wait td(P-R) or more until the internal power supply stabilizes. (4) Wait for 500 µs (1/fRING ✕ 20).
____________
(5) Apply an “H” signal to the RESET pin.
Table 5.1 Pin Status When RESET Pin Level is “L”
____________
Status
Pin name
P0 P1
0
to P33, P3
P3 P45
to P47
7
Input port Input port
Input port Input port
CNVSS = V
SS

5.2 Software Reset When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its

pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector. After reset, the on-chip oscillator clock divided by 8 is automatically selected for the CPU.

5.3 Watchdog Timer Reset

Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcom­puter initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is ex­ecuted starting from the address indicated by the reset vector. After reset, the on-chip oscillator clock divided by 8 is automatically selected for the CPU.
Rev.1.20 Jan 27, 2006 page 14 of 180 REJ09B0019-0120
R8C/10 Group 5. Reset
b15
000016
000016 000016 000016 000016 000016 000016
b19
0000016
Content of addresses 0FFFE16 to 0FFFC16
b15
16
0000 000016
000016
b15
0000
16
b0
Data register(R0)
Data register(R1)
Data register(R2) Data register(R3)
Address register(A0) Address register(A1)
Frame base register(FB)
b0
Interrupt table register(INTB)
Program counter(PC)
b0
User stack pointer(USP) Interrupt stack pointer(ISP)
Static base register(SB)
b0
Flag register(FLG)
b15
b7 b8
IPL
Figure 5.1 CPU Register Status After Reset
f
R I N G
Internal on-chip oscillation
CPU clock
A d d r e s s ( I n t e r n a l a d d r e s s s i g n a l )
N O T E S : 1 . T h i s s h o w s h a r d w a r e r e s e t
More than 20 cycles are needed
Flash memory activated time
(CPU clock ✕ 64 cycles)
(1)
CPU clock ✕ 28cycles
b0
CDZSBOIU
0 F F F C
0 F F F E
1 6
16
0FFFD
1 6
Content of reset vector
Figure 5.2 Reset Sequence
Rev.1.20 Jan 27, 2006 page 15 of 180 REJ09B0019-0120
R8C/10 Group 5. Reset
RESET
V
CC
RESET
V
CC
0V
0V
More than td(P-R) + 500 µs are needed.
Equal to or less than 0.2V
CC
2.7V
Figure 5.3 Example Reset Circuit
5V
VCC
VCCRESET
Supply voltage detection circuit
0V 5V
RESET
0V
Example when VCC = 5V.
Figure 5.4 Example Reset Circuit (Voltage Check Circuit)
2.7V
More than td(P-R) + 500 µs are needed.
Rev.1.20 Jan 27, 2006 page 16 of 180 REJ09B0019-0120
R8C/10 Group
p
k
q
y
y
p p
p
p
g
g
(N
)
p

6. Clock Generation Circuit

6. Clock Generation Circuit
The clock generation circuit contains two oscillator circuits as follows:
• Main clock oscillation circuit
• On-chip oscillator (with oscillation stop detection function)
Table 6.1 lists the clock generation circuit specifications. Figure 6.1 shows the clock generation circuit. Figures 6.2 and 6.3 show the clock-related registers.
Table 6.1 Clock Generation Circuit Specifications
I t e m
U s e o f c l o c
u e n c C l o c k f r e
U s a b l e o s c i l l a t o r
P i n s t o c o n n e c t
h e r a l f u n c t i o n c l o c k s o u r c
• C P U c l o c k s o u r c e
• P e r i
• C P U a n d p e r i p h e r a l f u n c t i o n
c l o c k s o u r c e s w h e n t h e m a i n c l o c k s t o p s o s c i l l a t i n g
0 to 16 MHz
s t a l o s c i l l a t o
• C e r a m i c r e s o n a t o r
• C r
X
M a i n c l o c k
o s c i l l a t i o n c i r c u i t
, X
O U T
( 1 )
I N
On-chip oscillator
• CPU clock source
e
• Peripheral function clock source
• CPU and peripheral function
clock sources when the main clock sto
s oscillatin
About 125 kHz
r
ote 1
o s c i l l a t o r
O s c i l l a t i o n s t a r t s a n d s t o
s
O s c i l l a t o r s t a t u s
P r e s e n t e
S t o
d
P r e s e n t
Oscillatin
a f t e r r e s e t Other
Externally derived
clock can be in
ut
NOTES:
1. Can be used as P46 and P47 when the on-chip oscillator clock is used for CPU clock while the main clock oscillation circuit is not used.
Rev.1.20 Jan 27, 2006 page 17 of 180 REJ09B0019-0120
R8C/10 Group
j
k
RQScR
S
R
T
8
0
O
8
8
O
2
k
C M 1 0 = 1 ( S t o p m o d e )
6. Clock Generation Circuit
I N
fR
G
I N G 1 2
fR
f1
S I
f1
fA
D
f
S I
f8
2 S I
f3
P e r i p h e r a l f u n c t i o n c l o c k
O
f
f3
2
c
d
C P U c l o c k
a
e
1 / 1 2
b
D i v i d e r
O n - c h i p o s c i l l a t o r c l o c k
O n - c h i p
C M 1 4
M a i n c l o c
Q
XI
N
o s c i l l a t o r
O s c i l l a t i o n s t o p d e t e c t i o n
O C D 2 = 1
U
XO
O C D 2 =
R E S E T
u d g m e n t o u t p u I n t e r r u p t r e q u e s t l e v e l
t
W A I T i n s t r u c t i o n
C M 0 2 , C M 0 5 , C M 0 6 : B i t s i n C M 0 r e g i s t e r C M 1 0 , C M 1 3 , C M 1 4 , C M 1 6 , C M 1 7 : B i t s i n C M 1 r e g i s t e r O C D 0 , O C D 1 , O C D 2 : B i t s i n O C D r e g i s t e r
O s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t
P u l s e g e n e r a t i o n
M a i n c l o c
c i r c u i t f o r c l o c k e d g e d e t e c t i o n a n d c h a r g e , d i s c h a r g e c o n t r o l c i r c u i t
N O T E S : 1 . S e t t h e s a m e v a l u e t o t h e O C D 1 b i t a n d O C D 0 b i t .
C M 1 3
C M 0 5
C M 0 2
a
F o r c i b l e d i s c h a r g e w h e n O C D 0
C h a r g e , d i s c h a r g e c i r c u i t
(1 )
O C D 1
e
1 / 2 1 / 2 1 / 2 1 / 2
C M 0 6 = 0 C M 1 7 t o C M 1 6 = 1 0
C M 0 6 = 0
C M 0 6 = 0 C M 1 7 t o C M 1 6 = 0 0
(1 )
O s c i l l a t i o n s t o p d e t e c t i o n i n t e r r u p t g e n e r a t i o n c i r c u i t
W a t c h d o g t i m e r i n t e r r u p t
C M 1 7 t o C M 1 6 = 0 1
2
O C D 2 b i t s w i t c h s i g n a l C M 1 4 b i t s w i t c h s i g n a l
2
b
C M 0 6 = 1
2
O s c i l l a t i o n s t o p d e t e c t i o n , W a t c h d o g t i m e r i n t e r r u p t
1 / 2
C M 0 6 = 0 C M 1 7 t o C M 1 6 = 1 12
d
D e t a i l s o f d i v i d e r
Figure 6.1 Clock Generation Circuit
Rev.1.20 Jan 27, 2006 page 18 of 180 REJ09B0019-0120
R8C/10 Group
6
g
0
W
0
0
W
W
W
4
W
3
W
W
W
W
6. Clock Generation Circuit
S y s t e m c l o c k c o n t r o l r e g i s t e r 0
b 7b 6b 5b 4b 3b 2b 1b 0
00001
( b 1 - b 0 )
C M 0 2
s t o p m o d e f r o m h i g h o r m i d d l e s p e e d m o d e , t h e C M 0 6 b i t i s s e t t o “ 1 ” ( d i v i d e - b y - 8 m o d e ) . N O T E S :
1 . S e t t h e P R C 0 b i t o f P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r . 2 . T h e C M 0 5 b i t i s p r o v i d e d t o s t o p t h e m a i n c l o c k w h e n t h e o n - c h i p o s c i l l a t o r m o d e i s s e l e c t e d . T h i s b i t c a n n o t b e u s e d f o r d e t e c t i o n a s t o
w h e t h e r t h e m a i n c l o c k s t o p p e d o r n o t . T o s t o p t h e m a i n c l o c k , t h e f o l l o w i n g s e t t i n g i s r e q u i r e d : ( 1 ) S e t t h e O C D 0 a n d O C D 1 b i t s i n t h e O C D r e g i s t e r t o “ 0 0
( 2 ) S e t t h e O C D 2 b i t t o “ 1 ” ( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) . 3 . S e t t h e C M 0 5 b i t t o “ 1 ” ( m a i n c l o c k s t o p s ) a n d t h e C M 1 3 b i t i n t h e C M 1 r e g i s t e r t o “ 1 ” ( X 4 . W h e n t h e C M 0 5 b i t i s s e t t o “ 1 ” ( m a i n c l o c k s t o p ) , P 4 5 . W h e n e n t e r i n
(1 )
d d r e s
0 0 S y m b o lA
C M 00
sA f t e r r e s e t
6
1 6
B i t n a m eF
Set to “0”
0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode
Set to “0”
) s t o p
0 : On 1 : Off
0 : CM16 and CM17 valid 1 : Divide-by-8 mode
2
” ( d i s a b l i n g o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n ) .
7
c a n b e u s e d a s i n p u t p o r t s .
( b 3 )
( b 4 )
C M 0 5
CM0
( b 7 )
R e s e r v e d b i t
W A I T p e r i p h e r a l f u n c t i o n c l o c k s t o p b i t
R e s e r v e d b i t Set to “1”
R e s e r v e d b i t
M a i n c l o c k ( X
( 2 , 4 )
b i t C P U c l o c k d i v i s i o n s e l e c t
b i t 0 R e s e r v e d b i t Set to “0”
I N
- X
O U T
( 5 )
6
a n d P 4
6 8
1 6
u n c t i o
nB i t s y m b o l
R W R W
R W R W R W
(3)
R W
R W
R W
I N
- X
O U T
p i n ) w h e n t h e e x t e r n a l c l o c k i s i n p u t .
System clock control register 1
b7b6 b5 b4 b3b2 b1 b
C M 1 5
C M 1 6 C M 1 7
(1)
d d r e s
0 0 S y m b o lA
C M 10
sA f t e r r e s e t
7
1 6
B i t n a m eF
( 4 )
C M 1 0
( b 1 )
( b 2 )
C M 1
C M 1
A l l c l o c k s t o p c o n t r o l b i t
R e s e r v e d b i t
R e s e r v e d b i t
P o r t X
I N
- X
O U T
s w i t c h b i t O n - c h i p o s c i l l a t i o n s t o p b i t
X
I N
- X
O U T
d r i v e c a p a c i t y
( 2 )
s e l e c t b i t M a i n c l o c k d i v i s i o n
s e l e c t b i t 1
( 3 )
0 : C l o c k o n 1 : A l l c l o c k s o f f ( s t o p m o d e )
S e t t o
S e t t o 0 : I n p u t p o r t P 46, P 47
1 : X 0 : O n - c h i p o s c i l l a t o r o n
1 : O n - c h i p o s c i l l a t o r o f f 0 : L O W
1 : H I G H
b 7 b 6
0 0 : N o d i v i s i o n m o d e 0 1 : D i v i s i o n b y 2 m o d e 1 0 : D i v i s i o n b y 4 m o d e 1 1 : D i v i s i o n b y 1 6 m o d e
2 0
1 6
u n c t i o
nBit symbol
“ 0 ”
“ 0 ”
I N
- X
O U T
p i n
( 5 )
R R
R
R
R
R R
R
R
N O T E S :
1 . W r i t e t o t h i s r e g i s t e r a f t e r s e t t i n g t h e P R C 0 b i t o f P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) . 2 . W h e n e n t e r i n g s t o p m o d e f r o m h i g h o r m i d d l e s p e e d m o d e , t h e C M 1 5 b i t i s s e t t o “ 1 ” ( d r i v e c a p a c i t y h i g h ) . 3 . E f f e c t i v e w h e n t h e C M 0 6 b i t i s “ 0 ” ( C M 1 6 a n d C M 1 7 b i t s e n a b l e ) . 4 . I f t h e C M 1 0 b i t i s “ 1 ” ( s t o p m o d e ) , t h e i n t e r n a l f e e d b a c k r e s i s t o r b e c o m e s i n e f f e c t i v e . 5 . T h e C M 1 4 b i t c a n b e s e t t o “ 1 ” ( o n - c h i p o s c i l l a t o r o f f ) i f t h e O C D 2 b i t = 0 ( s e l e c t i n g m a i n c l o c k ) . W h e n t h e O C D 2 b i t i s s e t t o “ 1 ”
( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) , t h e C M 1 4 b i t i s s e t t o “ 0 ” ( o n - c h i p o s c i l l a t o r o n ) . T h i s b i t r e m a i n s u n c h a n g e d w h e n “ 1 ” i s w r i t t e n .
6 . W h e n t h e C M 1 0 b i t i s s e t t o “ 1 ” ( s t o p m o d e ) o r t h e C M 0 5 b i t i n t h e C M 0 r e g i s t e r t o “ 1 ” ( m a i n c l o c k s t o p s ) a n d t h e C M 1 3 b i t i s s e t
t o “ 1 ” ( X
I N
- X
O U T
W h e n t h e C M 1 3 b i t i s s e t t o “ 0 ” ( i n p u t p o r t P 4
p i n ) , t h e X
O U T
( P 47) p i n i s h e l d “ H ” .
6
, P 47) , t h e P 47 i s i n i n p u t s t a t e .
Figure 6.2 CM0 Register and CM1 Register
Rev.1.20 Jan 27, 2006 page 19 of 180 REJ09B0019-0120
R8C/10 Group
W
W
W
b
W
6. Clock Generation Circuit
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e r
b 7b 6b 5b 4b 3b 2b 1b 0
0000
( o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n d i s a b l e d ) b e f o r e e n t e r i n g
( o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n d i s a b l e d ) . I f
( o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n N O T E S :
S y m b o lA O C D
B i t s y m b o l
O C D 0
O C D 1
O C D 2
O C D 3
( b 7 - b 4 )
( 1 )
d d r e s
0 0 0 C1
B i t n a m e
O s c i l l a t i o n s t o p d e t e c t i o n e n a b l e b i t
S y s t e m c l o c k s e l e c t b i t
C l o c k m o n i t o r b i t
R e s e r v e d b i t
( 3 , 5 )
sA f t e r r e s e t
6
0 41
6
1 b
0
F u n c t i o n
0 0 : T h e f u n c t i o n i s d i s a b l e d 0 1 : A v o i d t h i s s e t t i n g 1 0 : A v o i d t h i s s e t t i n g 1 1 : T h e f u n c t i o n i s e n a b l e d
0 : S e l e c t m a i n c l o c k
( 6 )
1 : S e l e c t o n - c h i p o s c i l l a t o r c l o c k 0 : M a i n c l o c k o n
1 : M a i n c l o c k o f f
S e t t o " 0 "
( 4 )
( 7 )
( 7 )
1 . S e t t h e P R C 0 b i t i n t h e P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) b e f o r e r e w r i t i n g t h i s r e g i s t e r . 2 . T h e O C D 2 b i t i s s e t t o “ 1 ” ( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) a u t o m a t i c a l l y i f a m a i n c l o c k o s c i l l a t i o n s t o p
i s d e t e c t e d w h i l e t h e O C D 1 t o O C D 0 b i t s a r e s e t t o “ 1 1
2”
t h e O C D 3 b i t i s s e t t o “ 1 ” ( m a i n c l o c k s t o p ) , t h e O C D 2 b i t r e m a i n s u n c h a n g e d w h e n t r y i n g t o w r i t e “ 0 ” ( s e l e c t i n g m a i n c l o c k ) .
3 . T h e O C D 3 b i t i s e n a b l e d w h e n t h e O C D 1 t o O C D 0 b i t s a r e s e t t o “ 1 1
2”
e n a b l e d ) .
4 . T h e O C D 1 t o O C D 0 b i t s m u s t b e s e t t o “ 0 0
2”
s t o p m o d e o r o n - c h i p o s c i l l a t o r m o d e ( m a i n c l o c k s t o p s ) .
5 . T h e O C D 3 b i t r e m a i n s s e t t o “ 0 ” ( m a i n c l o c k o n ) i f t h e O C D 1 t o O C D 0 b i t s a r e s e t t o “ 0 0
2”
.
6 . T h e C M 1 4 b i t g o e s t o “ 0 ” ( o n - c h i p o s c i l l a t o r o n ) i f t h e O C D 2 b i t i s s e t t o “ 1 ” ( s e l e c t i n g o n - c h i p o s c i l l a t o r
c l o c k ) .
7 . R e f e r t o F i g u r e 6 . 6 “ s w i t c h i n g c l o c k s o u r c e f r o m o n - c h i p o s c i l l a t o r t o m a i n c l o c k ” f o r t h e s w i t c h i n g
p r o c e d u r e w h e n t h e m a i n c l o c k r e - o s c i l l a t e s a f t e r d e t e c t i n g a n o s c i l l a t i o n s t o p .
R
R
R
( 2 )
R O
R
Figure 6.3 OCD Register
Rev.1.20 Jan 27, 2006 page 20 of 180 REJ09B0019-0120
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