Renesas R7F0C011B, R7F0C012B, R7F0C013B User Manual

User’s Manual

R7F0C011B, R7F0C012B,

8

R7F0C013B

User’s Manual: Hardware

8-Bit Single-Chip Microcontrollers

-Preliminary-

All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).

www.renesas.com

Rev.0.01 Sep 2012

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of
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modification, copy or otherwise misappropriation of Renesas Electronics product.

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6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
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Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(2012.4)

NOTES FOR CMOS DEVICES

(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a

reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the tra nsition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).

(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If

an input pin is unconnected, it is possible that an internal input level may be generate d due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-do wn circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.

(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause

destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should b e used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be gr oun ded usin g a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.

(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS

device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.

(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal

operation and external interface, as a rule, switch on the e xternal power suppl y after switching on th e internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse po wer on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degr adation of internal elements
due to the passage of an abnormal current. The correct po wer on/off sequence must be judged separately
for each device and according to related specifications governing the device.

(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply

while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the devic e.

How to Use This Manual

Readers This manual is intended for user engineers who wish to understand the functions of the

R7F0C011B, R7F0C012B, R7F0C013B and design and develop application systems and

programs for these devices.

The target products are as follows.

• R7F0C011B2DFP

• R7F0C012B2DFP

• R7F0C013B2DFP

Purpose This manual is intended to give users an understanding of the functions described in the

Organization below.

Organization The R7F0C011B, R7F0C012B, R7F0C013B manual is separated into two parts: this

manual and the instructions edition (common to the 78K0R Microcontroller).

R7F0C011B, R7F0C012B, R7F0C013B

User’s Manual

(This Manual)

• Pin functions

• Internal block functions

• Interrupts

• Other on-chip peripheral functions

• Electrical specifications (target)

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS.

• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved

word in the assembler, and is defined as an sfr variable using the #pragma sfr

directive in the compiler.

• To know details of the R7F0C011B, R7F0C012B, R7F0C013B Microcontroller instructions:
→ Refer to the separate document 78K0 Series Instructions User’s Manual (U12326E).

• CPU functions

• Instruction set

• Explanation of each instruction

78K/0 Series

User’s Manual

Instructions

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representations: ××× (overscore over pin and signal name)

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numerical representations: Binary

Decimal

Hexadecimal

...

×××× or ××××B

...

××××

...

××××H

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No.

R7F0C011B, R7F0C012B, R7F0C013B User’s Manual This manual

78K/0 Series Instructions User’s Manual U12326E

78K0/Kx2 Flash Memory Programming (Programmer) Application Note U17739E

Documents Related to Flash Memory Programming

Document Name Document No.

PG-FP5 Flash Memory Programmer User’s Manual R20UT0008E

QB-MINI2 On-Chip Debug Emulator with Programming Function User’s Manual R20UT0449E

QB-Programmer Programming GUI U18257E

Documents Related to Development Tools (Hardware)

Document Name Document No.

QB-MINI2 On-Chip Debug Emulator with Programming Function User’s Manual R20UT0449E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

Documents Related to Development Tools (Software)

Document Name Document No.

RA78K0 Ver.3.80 Assembler Package

User’s Manual

78K0 Assembler Package RA78K0 Ver.4.01 Operating Precautions (Notification Document)

User’s Manual

78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions (Notification Document)

User’s Manual

ID78K0-QB Ver.2.94 Integrated Debugger User’s Manual Operation U18330E

ID78K0-QB Ver.3.00 Integrated Debugger User’s Manual Operation U18492E

PM plus Ver.5.20

PM+ Ver.6.30

Note 1

Note 2

Note 3

Note 4

User’s Manual

User’s Manual

Operation U17199E

Language U17198E

Structured Assembly Language U17197E

Note 1

Operation U17201E CC78K0 Ver.3.70 C Compiler

Language U17200E

Note 2

Operation U18601E SM+ System Simulator

User Open Interface U18212E

ZUD-CD-07-0181-E

ZUD-CD-07-0103-E

U16934E

U18416E

Notes 1. This document is installed into the PC together with the tool when installing RA78K0 Ver. 4.01. For

descriptions not included in “78K0 Assembler Package RA78K0 Ver. 4.01 Operating Precautions”, refer to the

user’s manual of RA78K0 Ver. 3.80.

2. This document is installed into the PC together with the tool when installing CC78K0 Ver. 4.00. For

descriptions not included in “78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions”, refer to the user’s

manual of CC78K0 Ver. 3.70.

3. PM plus Ver. 5.20 is the integrated development environment included with RA78K0 Ver. 3.80.

4. PM+ Ver. 6.30 is the integrated development environment included with RA78K0 Ver. 4.01. Software tool

(assembler, C compiler, debugger, and simulator) products of different versions can be managed.

Other Documents

Document Name Document No.

RENESAS MICROCOMPUTER GENERAL CATALOG R01CS0001E

Semiconductor Device Mount Manual Note

Quality Grades on NEC Semiconductor Devices C11531E

NEC Semiconductor Device Reliability/Quality Control System C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Note See the “Semiconductor Device Mount Manual” website (http://www.renesas.com/prod/package/manual/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

All trademarks and registered trademarks are the property of their respective owners.
Windows is a registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.

®

Caution: This product uses SuperFlash

technology licensed from Silicon Storage Technology, Inc.

CONTENTS

CHAPTER 1 OUTLINE............................................................................................................................... 1

1.1 Features ....................................................................................................................................... 1

1.2 Applications................................................................................................................................. 2

1.3 Ordering Information .................................................................................................................. 2

1.4 Pin Configuration (Top View)..................................................................................................... 3

1.5 Pin Identification ......................................................................................................................... 4

1.6 Block Diagram ............................................................................................................................. 5

1.7 Outline of Functions ................................................................................................................... 6

CHAPTER 2 PIN FUNCTIONS ................................................................................................................. 8

2.1 Pin Function List ......................................................................................................................... 8

2.2 Description of Pin Functions ................................................................................................... 11

2.2.1 P00, P01 (port 0) .......................................................................................................................... 11

2.2.2 P10 to P17 (port 1) ....................................................................................................................... 11

2.2.3 P20 to P23 (port 2) ....................................................................................................................... 13

2.2.4 P30 to P33 (port 3) ....................................................................................................................... 13

2.2.5 P40 and P41 (port 4) .................................................................................................................... 14

2.2.6 P60 and P61 (port 6) .................................................................................................................... 14

2.2.7 P70 and P71 (port 7) .................................................................................................................... 14

2.2.8 P120 to P122 (port 12) ................................................................................................................. 15

2.2.9 VDD, VSS ........................................................................................................................................ 15

2.2.10 RESET.......................................................................................................................................... 15

2.2.11 REGC ........................................................................................................................................... 16

2.2.12 FLMD0 .......................................................................................................................................... 16

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................ 17

CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 20

3.1 Memory Space ........................................................................................................................... 20

3.1.1 Internal program memory space ................................................................................................... 25

3.1.2 Internal data memory space ......................................................................................................... 27

3.1.3 Special function register (SFR) area ............................................................................................. 27

3.1.4 Data memory addressing.............................................................................................................. 27

3.2 Processor Registers ................................................................................................................. 31

3.2.1 Control registers ........................................................................................................................... 31

3.2.2 General-purpose registers ............................................................................................................ 34

3.2.3 Special function registers (SFRs) ................................................................................................. 36

3.3 Instruction Address Addressing ............................................................................................. 41

3.3.1 Relative addressing ...................................................................................................................... 41

3.3.2 Immediate addressing................................................................................................................... 42

3.3.3 Table indirect addressing.............................................................................................................. 43

3.3.4 Register addressing...................................................................................................................... 43

3.4 Operand Address Addressing ................................................................................................. 44

3.4.1 Implied addressing........................................................................................................................ 44

3.4.2 Register addressing...................................................................................................................... 45

3.4.3 Direct addressing.......................................................................................................................... 46

i

3.4.3 Direct addressing.......................................................................................................................... 46

3.4.4 Short direct addressing................................................................................................................. 47

3.4.5 Special function register (SFR) addressing................................................................................... 48

3.4.6 Register indirect addressing ......................................................................................................... 49

3.4.7 Based addressing ......................................................................................................................... 50

3.4.8 Based indexed addressing............................................................................................................ 51

3.4.9 Stack addressing .......................................................................................................................... 52

CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 53

4.1 Port Functions ........................................................................................................................... 53

4.2 Port Configuration..................................................................................................................... 55

4.2.1 Port 0 ............................................................................................................................................ 56

4.2.2 Port 1 ............................................................................................................................................ 58

4.2.3 Port 2 ............................................................................................................................................ 64

4.2.4 Port 3 ............................................................................................................................................ 66

4.2.5 Port 4 ............................................................................................................................................ 68

4.2.6 Port 6 ............................................................................................................................................ 69

4.2.7 Port 7 ............................................................................................................................................ 70

4.2.8 Port 12 .......................................................................................................................................... 71

4.3 Registers Controlling Port Function ....................................................................................... 73

4.4 Port Function Operations......................................................................................................... 77

4.4.1 Writing to I/O port.......................................................................................................................... 77

4.4.2 Reading from I/O port ................................................................................................................... 77

4.4.3 Operations on I/O port .................................................................................................................. 77

4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function.......... 78

4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)................................... 80

CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 81

5.1 Functions of Clock Generator.................................................................................................. 81

5.2 Configuration of Clock Generator ........................................................................................... 82

5.3 Registers Controlling Clock Generator................................................................................... 84

5.4 System Clock Oscillator ........................................................................................................... 91

5.4.1 X1 oscillator .................................................................................................................................. 91

5.4.2 Internal high-speed oscillator ........................................................................................................ 93

5.4.3 Internal low-speed oscillator ......................................................................................................... 93

5.4.4 Prescaler....................................................................................................................................... 93

5.5 Clock Generator Operation ...................................................................................................... 94

5.6 Controlling Clock ...................................................................................................................... 97

5.6.1 Example of controlling high-speed system clock .......................................................................... 97

5.6.2 Example of controlling internal high-speed oscillation clock ....................................................... 100

5.6.3 Example of controlling internal low-speed oscillation clock......................................................... 103

5.6.4 Clocks supplied to CPU and peripheral hardware ...................................................................... 103

5.6.5 CPU clock status transition diagram ........................................................................................... 104

5.6.6 Condition before changing CPU clock and processing after changing CPU clock...................... 107

5.6.7 Time required for switchover of CPU clock and main system clock............................................ 108

5.6.8 Conditions before clock oscillation is stopped............................................................................. 109

5.6.9 Peripheral hardware and source clocks...................................................................................... 109

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ........................................................................... 110

ii

6.1 Functions of 16-Bit Timer/Event Counter 00 ........................................................................ 110

6.2 Configuration of 16-Bit Timer/Event Counter 00.................................................................. 111

6.3 Registers Controlling 16-Bit Timer/Event Counter 00 ......................................................... 117

6.4 Operation of 16-Bit Timer/Event Counter 00 ........................................................................ 125

6.4.1 Interval timer operation ............................................................................................................... 125

6.4.2 Square-wave output operation.................................................................................................... 128

6.4.3 External event counter operation ................................................................................................ 132

6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input ...................................... 136

6.4.5 Free-running timer operation ...................................................................................................... 152

6.4.6 PPG output operation ................................................................................................................. 162

6.4.7 One-shot pulse output operation................................................................................................. 166

6.4.8 Pulse width measurement operation........................................................................................... 171

6.5 Special Use of TM00................................................................................................................ 180

6.5.1 Rewriting CR010 during TM00 operation.................................................................................... 180

6.5.2 Setting LVS00 and LVR00 .......................................................................................................... 180

6.6 Cautions for 16-Bit Timer/Event Counter 00 ........................................................................ 182

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 187

7.1 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................ 187

7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 ..................................................... 187

7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................ 190

7.4 Operations of 8-Bit Timer/Event Counters 50 and 51.......................................................... 195

7.4.1 Operation as interval timer.......................................................................................................... 195

7.4.2 Operation as external event counter........................................................................................... 197

7.4.3 Square-wave output operation.................................................................................................... 198

7.4.4 PWM output operation ................................................................................................................ 199

7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................ 203

CHAPTER 8 8-BIT TIMERS H0 AND H1........................................................................................... 204

8.1 Functions of 8-Bit Timers H0 and H1 .................................................................................... 204

8.2 Configuration of 8-Bit Timers H0 and H1.............................................................................. 204

8.3 Registers Controlling 8-Bit Timers H0 and H1 ..................................................................... 208

8.4 Operation of 8-Bit Timers H0 and H1 .................................................................................... 213

8.4.1 Operation as interval timer/square-wave output ......................................................................... 213

8.4.2 Operation as PWM output........................................................................................................... 216

8.4.3 Carrier generator operation (8-bit timer H1 only) ........................................................................ 222

CHAPTER 9 WATCH TIMER................................................................................................................ 229

9.1 Functions of Watch Timer ......................................................................................................229

9.2 Configuration of Watch Timer................................................................................................ 230

9.3 Register Controlling Watch Timer ......................................................................................... 231

9.4 Watch Timer Operations......................................................................................................... 232

9.4.1 Watch timer operation................................................................................................................. 232

9.4.2 Interval timer operation ............................................................................................................... 233

9.5 Cautions for Watch Timer ...................................................................................................... 233

CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 234

10.1 Functions of Watchdog Timer ............................................................................................... 234

iii

10.2 Configuration of Watchdog Timer ......................................................................................... 235

10.3 Register Controlling Watchdog Timer .................................................................................. 236

10.4 Operation of Watchdog Timer................................................................................................ 237

10.4.1 Controlling operation of watchdog timer...................................................................................... 237

10.4.2 Setting overflow time of watchdog timer ..................................................................................... 238

10.4.3 Setting window open period of watchdog timer........................................................................... 239

CHAPTER 11 A/D CONVERTER ......................................................................................................... 241

11.1 Function of A/D Converter ..................................................................................................... 241

11.2 Configuration of A/D Converter ............................................................................................. 242

11.3 Registers Used in A/D Converter........................................................................................... 244

11.4 A/D Converter Operations ...................................................................................................... 250

11.4.1 Basic operations of A/D converter .............................................................................................. 250

11.4.2 Input voltage and conversion results .......................................................................................... 251

11.4.3 A/D converter operation mode.................................................................................................... 253

11.5 How to Read A/D Converter Characteristics Table.............................................................. 255

11.6 Cautions for A/D Converter .................................................................................................... 258

CHAPTER 12 SERIAL INTERFACE UART0 ...................................................................................... 262

12.1 Functions of Serial Interface UART0..................................................................................... 262

12.2 Configuration of Serial Interface UART0 .............................................................................. 263

12.3 Registers Controlling Serial Interface UART0...................................................................... 266

12.4 Operation of Serial Interface UART0..................................................................................... 271

12.4.1 Operation stop mode .................................................................................................................. 271

12.4.2 Asynchronous serial interface (UART) mode.............................................................................. 272

12.4.3 Dedicated baud rate generator ................................................................................................... 278

12.4.4 Calculation of baud rate.............................................................................................................. 280

CHAPTER 13 SERIAL INTERFACE UART6 ...................................................................................... 284

13.1 Functions of Serial Interface UART6..................................................................................... 284

13.2 Configuration of Serial Interface UART6 .............................................................................. 289

13.3 Registers Controlling Serial Interface UART6...................................................................... 292

13.4 Operation of Serial Interface UART6..................................................................................... 302

13.4.1 Operation stop mode .................................................................................................................. 302

13.4.2 Asynchronous serial interface (UART) mode.............................................................................. 303

13.4.3 Dedicated baud rate generator ................................................................................................... 317

13.4.4 Calculation of baud rate.............................................................................................................. 318

CHAPTER 14 SERIAL INTERFACE CSI10 ........................................................................................ 324

14.1 Functions of Serial Interface CSI10....................................................................................... 324

14.2 Configuration of Serial Interface CSI10 ................................................................................ 324

14.3 Registers Controlling Serial Interface CSI10........................................................................ 326

14.4 Operation of Serial Interface CSI10 ....................................................................................... 330

14.4.1 Operation stop mode .................................................................................................................. 330

14.4.2 3-wire serial I/O mode................................................................................................................. 331

CHAPTER 15 SERIAL INTERFACE IIC0............................................................................................ 341

15.1 Functions of Serial Interface IIC0 .......................................................................................... 341

iv

15.2 Configuration of Serial Interface IIC0.................................................................................... 344

15.3 Registers to Control Serial Interface IIC0 ............................................................................. 347

15.4 I

15.5 I

2

C Bus Mode Functions .........................................................................................................360

15.4.1 Pin configuration ......................................................................................................................... 360

2

C Bus Definitions and Control Methods ............................................................................. 361

15.5.1 Start conditions ........................................................................................................................... 361

15.5.2 Addresses................................................................................................................................... 362

15.5.3 Transfer direction specification ................................................................................................... 362

15.5.4 Acknowledge (ACK).................................................................................................................... 363

15.5.5 Stop condition ............................................................................................................................. 364

15.5.6 Wait ............................................................................................................................................ 365

15.5.7 Canceling wait ............................................................................................................................ 367

15.5.8 Interrupt request (INTIIC0) generation timing and wait control ................................................... 368

15.5.9 Address match detection method ............................................................................................... 369

15.5.10 Error detection ............................................................................................................................ 369

15.5.11 Extension code ........................................................................................................................... 370

15.5.12 Arbitration ................................................................................................................................... 371

15.5.13 Wakeup function ......................................................................................................................... 373

15.5.14 Communication reservation ........................................................................................................ 373

15.5.15 Cautions...................................................................................................................................... 377

15.5.16 Communication operations ......................................................................................................... 378

15.5.17 Timing of I

2

C interrupt request (INTIIC0) occurrence .................................................................. 386

15.6 Timing Charts .......................................................................................................................... 407

CHAPTER 16 INTERRUPT FUNCTIONS............................................................................................. 414

16.1 Interrupt Function Types ........................................................................................................ 414

16.2 Interrupt Sources and Configuration .................................................................................... 414

16.3 Registers Controlling Interrupt Functions............................................................................ 419

16.4 Interrupt Servicing Operations .............................................................................................. 427

16.4.1 Maskable interrupt acknowledgment .......................................................................................... 427

16.4.2 Software interrupt request acknowledgment............................................................................... 429

16.4.3 Multiple interrupt servicing .......................................................................................................... 430

16.4.4 Interrupt request hold.................................................................................................................. 433

CHAPTER 17 STANDBY FUNCTION .................................................................................................. 434

17.1 Standby Function and Configuration.................................................................................... 434

17.1.1 Standby function ......................................................................................................................... 434

17.1.2 Registers controlling standby function ........................................................................................ 435

17.2 Standby Function Operation .................................................................................................. 437

17.2.1 HALT mode................................................................................................................................. 437

17.2.2 STOP mode................................................................................................................................ 440

CHAPTER 18 RESET FUNCTION........................................................................................................ 446

18.1 Register for Confirming Reset Source.................................................................................. 455

CHAPTER 19 POWER-ON-CLEAR CIRCUIT...................................................................................... 456

19.1 Functions of Power-on-Clear Circuit..................................................................................... 456

19.2 Configuration of Power-on-Clear Circuit .............................................................................. 457

v

19.3 Operation of Power-on-Clear Circuit..................................................................................... 457

19.4 Cautions for Power-on-Clear Circuit ..................................................................................... 460

CHAPTER 20 LOW-VOLTAGE DETECTOR ....................................................................................... 462

20.1 Functions of Low-Voltage Detector....................................................................................... 462

20.2 Configuration of Low-Voltage Detector ................................................................................ 462

20.3 Registers Controlling Low-Voltage Detector ....................................................................... 463

20.4 Operation of Low-Voltage Detector....................................................................................... 466

20.4.1 When used as reset .................................................................................................................... 467

20.4.2 When used as interrupt............................................................................................................... 472

20.5 Cautions for Low-Voltage Detector ....................................................................................... 477

CHAPTER 21 OPTION BYTE............................................................................................................... 480

21.1 Functions of Option Bytes ..................................................................................................... 480

21.2 Format of Option Byte ............................................................................................................481

CHAPTER 22 FLASH MEMORY .......................................................................................................... 483

22.1 Internal Memory Size Switching Register............................................................................. 483

22.2 Writing with Flash Memory Programmer.............................................................................. 484

22.3 Programming Environment.................................................................................................... 484

22.4 Communication Mode............................................................................................................. 485

22.5 Connection of Pins on Board................................................................................................. 487

22.5.1 FLMD0 pin .................................................................................................................................. 488

22.5.2 Serial interface pins .................................................................................................................... 488

22.5.3 RESET pin.................................................................................................................................. 489

22.5.4 Port pins...................................................................................................................................... 490

22.5.5 REGC pin.................................................................................................................................... 490

22.5.6 Other signal pins......................................................................................................................... 490

22.5.7 Power supply .............................................................................................................................. 490

22.6 Programming Method ............................................................................................................. 491

22.6.1 Controlling flash memory ............................................................................................................ 491

22.6.2 Flash memory programming mode ............................................................................................. 492

22.6.3 Selecting communication mode .................................................................................................. 493

22.6.4 Communication commands ........................................................................................................ 493

22.7 Security Settings..................................................................................................................... 495

CHAPTER 23 INSTRUCTION SET....................................................................................................... 497

23.1 Conventions Used in Operation List ..................................................................................... 498

23.1.1 Operand identifiers and specification methods ........................................................................... 498

23.1.2 Description of operation column ................................................................................................. 499

23.1.3 Description of flag operation column........................................................................................... 499

23.2 Operation List.......................................................................................................................... 500

23.3 Instructions Listed by Addressing Type............................................................................... 508

CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET).............................................................. 512

CHAPTER 25 PACKAGE DRAWINGS ................................................................................................ 530

vi

CHAPTER 26 CAUTIONS FOR WAIT................................................................................................. 531

26.1 Cautions for Wait..................................................................................................................... 531

26.2 Peripheral Hardware That Generates Wait ........................................................................... 532

vii

R7F0C011B, R7F0C012B, R7F0C013B
RENESAS MCU

CHAPTER 1 OUTLINE

1.1 Features

 Minimum instruction execution time: 0.2
 General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
 I/O ports, ROM, RAM capacities

μ

s (@ 10 MHz operation with high-speed system clock)

R01UH0408EJ0001

Rev.0.01

Sep 25, 2012

Item

Products
R7F0C011B2DFP 16 KB 768 bytes
R7F0C012B2DFP 24 KB 1 KB
R7F0C013B2DFP

27 (CMOS I/O: 25, N-ch open drain I/O: 2)

I/O ports

Program Memory

(Flash Memory)

32 KB 1 KB

Data Memory

(Internal High-Speed RAM)

 On-chip single-power-supply flash memory
 On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
 On-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock)
 Timer

• 16-bit timer/event counter … PPG output, capture input, external event counter input

• 8-bit timers H0, H1 … PWM output, operable with internal low-speed oscillation clock

• 8-bit timer/event counters 50, 51 … External event counter input

• Watch timer

• Watchdog timer … Operable with internal low-speed oscillation clock

Item

16-Bit Timer/Event Counter 8-Bit Timer Watch Timer Watchdog Timer

Products
R7F0C011B2DFP
R7F0C012B2DFP
R7F0C013B2DFP

1 channel

Timer H: 2 channels
Timer 5: 2 channels

1 channel 1 channel

 Serial interface

• UART … 2-wire serial interface supporting asynchronous communication

• CSI … 3-wire serial interface supporting clocked communication

• IICA … 2-wire serial interface supporting clocked communication. Supporting multi-master and, in slave mode,

capable of releasing standby by address match

Products
R7F0C011B2DFP
R7F0C012B2DFP
R7F0C013B2DFP

Item

1 channel 1 channel 1 channel

UART6 CSI10/UART0 IIC

 On-chip 10-bit resolution A/D converter (AVREF = 4.0 to 5.5 V): 4 channels
 Power supply voltage: V
 Operating ambient temperature: T

DD = 4.0 to 5.5 V

A = –40 to +85°C

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE

1.2 Applications

 Household electrical appliances

• Air conditioners

1.3 Ordering Information

Pin Count Package ROM RAM Semiconductor Material Part Number

32-pin 32-pin plastic LQF (7 × 7)

16 KB 768 B R7F0C011B2DFP
24 KB 1 KB R7F0C012B2DFP
32 KB 1 KB

(External pin finish is Ni/Pd/Au plating)

Lead free product

R7F0C013B2DFP

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE

1.4 Pin Configuration (Top View)

• 32-pin plastic LQFP (fine pitch) (7 × 7)

P10/SCK00/TXD0

P11/SI10

P12/SO00

P13/TxD6

P14/RxD6

P15

P16/TOH1

P17/TI50/TO50

Exposed die pad

24 23 22 21 20 19 18 17

P23/ANI3

P22/ANI2
P21/ANI1
P20/ANI0

P01/TI010/TO00

P00/TI000

P120/INTP0/EXLVI

P41

25
26
27
28
29
30
31
32

1 2 3 4 5 6 7 8

16
15
14
13
12
11
10

9

P30
P31/INTP2
P32/INTP3
P70
P71
P33/TI51/TO51/INTP4
P61/SDA0
P60/SCL0

SS

DD

V

P40

FLMD0

RESET

P122/X2/EXCLK

P121/X1

V

REGC

Cautions 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).

2. ANI0/P20 to ANI3/P23 are set in the analog input mode after release of reset.

Remark For pin identification, see 1.6 Pin Identification.

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE

1.5 Pin Identification

ANI0 to ANI3: Analog input RxD0, RxD6: Receive data
EXCLK: External clock input SCK10: Serial clock Input/output
EXLVI: External potential input SCL0: Serial clock Input/output
for Low-voltage detector SDA0: Serial data Input/output
FLMD0: Flash programming mode SI10: Serial data Input
INTP0 to INTP5: External interrupt input SO10: Serial data output
P00, P01: Port 0 TI000, TI010,
P10 to P17: Port 1 TI50, TI51: Timer input
P20 to P23: Port 2 TO00 : Timer output
P30 to P33: Port 3 TO50, TO51:
P40, P41: Port 4 TOH1:
P60, P61: Port 6 TxD0, TxD6: Transmit data

P70, P71: Port 7
P120 to P122: Port 12 V

DD: Power supply

V

SS: Ground

REGC: Regulator capacitance X1, X2: Crystal oscillator (main system clock)
RESET: Reset

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE

1.6 Block Diagram

TO00/TI010/P01

TI000/P00

RxD6/P14 (LINSEL)

16-bit timer/
event counter 00

8-bit timer

H0

Port 0

Port 1

Port 2

2

8

4

P00, P01

P10 to P17

P20 to P23

TOH1/P16

TI50/TO50/P17

TI51/TO51/P33

RxD0/P11

TxD0/P10

RxD6/P14

TxD6/P13

SI10/P11

SO10/P12

SCK10/P10

SDA0/P61
SCL0/P60

ANI0/P20 to

ANI3/P23

8-bit timer

Watchdog timer

8-bit timer/
event counter 50

8-bit timer/
event counter 51

Serial
interface UART0

Serial
interface UART6

Serial
interface

Serial
interface

4

H1

Internal

low-speed

oscillator

LINSEL

CSI10

IIC0

A/D converter

78K0

CPU
core

Internal

high-speed

RAM

Flash

memory

Port 3

Port 4

Port 6

Port 7

Port 12

Power-on clear/

low-voltage

indicator

Reset control

System

control

Internal

high-speed

oscillator

Voltage regulator

4

P30 to P33

2

P40, P41

2

P60, P61

2

P70, P71

3

P120 to P122

POC/LVI

control

RESET
X1/P121

X2/EXCLK/P122

REGC

EXLVI/P120

RxD6/P14 (LINSEL)

INTP0/P120

INTP2/P31 to

INTP4/P33

3

Interrupt

control

VSSFLMD0 V

DD

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE

1.7 Outline of Functions

Products

Item
Flash memory (KB) 16 24 32
High-speed RAM (KB) 0.75 1 1
Power supply voltage VDD = 4.0 to 5.5 V
Regulator Provided
Minimum instruction execution

time

High-speed system 10 MHz: VDD = 4.0 to 5.5 V
Internal high-speed

oscillation

Clock

Internal low-speed
oscillation

Total 27

Port

N-ch O.D. (6 V tolerance) 2
16 bits (TM0) 1 ch
8 bits (TM5) 2 ch
8 bits (TMH) 2 ch

Timer

Watch 1 ch
Watchdog (WDT)
3-wire CSI
Automatic transmit/receive

3-wire CSI
UART/3-wire CSI
UART supporting LIN-bus 1 ch

Serial interface

I2C bus 1 ch

10-bit A/D 4 ch

External 6
Internal 14

Interrupt

RESET pin Provided
POC 1.59 V ±0.15 V

Reset

LVI The detection level of the supply voltage is selectable.

WDT Provided
On-chip debug function Supported by other product (R7F0C999B2DFP)
Operating ambient temperature TA = −40 to +85 °C

Note

Note Select either of the functions of these alternate-function pins.

R7F0C011B2DFP R7F0C012B2DFP R7F0C013B2DFP

0.2

μ

s (10 MHz: VDD = 4.0 to 5.5 V)

8 MHz (TYP.): V

240 kHz (TYP.): V

DD = 4.0 to 5.5 V

DD = 4.0 to 5.5 V

1 ch

−

−

1 ch

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE

An outline of the timer is shown below.

16-Bit Timer/

Event Counter 00

TM00 TM50 TM51 TMH0 TMH1

Function

Interrupt source 2 1 1 1 1 1

Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel
External event

counter
PPG output 1 output
PWM output
Pulse width

measurement
Square-wave

output
Carrier generator
Timer output
Watchdog timer

1 channel 1 channel 1 channel

−

2 inputs

1 output 1 output 1 output

− − − −

− − − − −

− − − − − −

8-Bit Timer/

Event Counters

50 and 51

− − − − − −

1 output 1 output

− − − − − −

8-Bit Timers H0 and H1

− − − −

−

−

1 output

1 output

1 output

Notes 1. In the watch timer, the watch timer function and i nterval timer function can be used simultaneously.

2. TM51 and TMH1 can be used in combination as a carrier generator mode.

Watch Timer Watchdog

Note 1

− −

− −

Nore 2

− −

1 channel

Nore 1

Timer

−

−

1 channel

−

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CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

Pin I/O buffer power supplies include one V

shown below.

Table 2-1. Pin I/O Buffer Power Supplies (AVREF, VDD)

Power Supply Corresponding Pins

VDD All pins

DD system. The relationship between these power supplies and the pins is

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS

(1) Port functions

Function Name I/O Function After Reset Alternate Function

P00 TI000

P01

P10 SCK10/TxD0

P11 SI10/RxD0

P12 SO10

P13 TxD6

P14 RxD6

P15

P16 TOH1

P17

P20 to P23 I/O

P30

P31 INTP2

P32 INTP3

P33

P40, P41 I/O

P60 SCL0

P61

P70, P71 I/O

P120 INTP0/EXLVI

P121 X1

P122

I/O

I/O

I/O

I/O

I/O

Port 0.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 2.
4-bit I/O port.
Input/output can be specified in 1-bit units.

Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 4.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 6.
2-bit I/O port.
Output is N-ch open-drain output (6 V tolerance).
Input/output can be specified in 1-bit units.

Port 7.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 12.
3-bit I/O port.
Input/output can be specified in 1-bit units.
Only for P120, use of an on-chip pull-up resistor can be
specified by a software setting.

Input port

TI010/TO00

Input port

−

TI50/TO50

Analog input ANI0 to ANI3

Input port

INTP4/TI51/TO51

Input port

Input port

SDA0

Input port

Input port

X2/EXCLK

−

−

−

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS

(2) Non-port functions

Function Name I/O Function After Reset Alternate Function

ANI0 to ANI3 Input A/D converter analog input

EXLVI Input Potential input for external low-voltage detection Input port P120/INTP0

FLMD0

INTP0 P120/EXLVI

INTP2 P31

INTP3 P32

INTP4

REGC

RESET Input System reset input

RxD0 Serial data input to UART0 P11/SI10

RxD6

TxD0 Serial data output from UART0 P10/SCK10

TxD6

SCK10 I/O Clock input/output for CSI10 P10/TxD0

SI10 Input Serial data input to CSI10 P11/RxD0

SO10 Output Serial data output from CSI10

SCL0 Clock input/output for I2C P60

SDA0

TI000 Input

TI010 Input

TI50 External count clock input to 8-bit timer/event counter 50 P17/TO50

TI51

TO00 Output 16-bit timer/event counter 00 output Input port P01/TI010

TO50 8-bit timer/event counter 50 output P17/TI50

TO51

TOH0 8-bit timer H0 output P15

TOH1

X1

X2

EXCLK Input External clock input for main system clock Input port P122/X2

VDD

VSS

Input

Input

Output

I/O

Input

Output

Output

Flash memory programming mode setting

−

External interrupt request input for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be
specified

Connecting regulator output (2.5 V) stabilization capacitance

−
for internal operation.
Connect to V

Serial data input to UART6

Serial data output from UART6

Serial data I/O for I2C

External count clock input to 16-bit timer/event counter 00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00

Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00

External count clock input to 8-bit timer/event counter 51

8-bit timer/event counter 51 output

8-bit timer H1 output

Connecting resonator for main system clock

−

−

Positive power supply and A/D converter reference voltage

−
input

Ground potential

−

SS via a capacitor (0.47 to 1

μ

F).

Analog
input

Input port

Input port

Input port

Input port

Input port

Input port P00

Input port P01/TO00

Input port

Input port

Input port

Input port P121

Input port P122/EXCLK

P20 to P23

− −

P33/TI51/TO51

− −

− −

P14

P13

P12

P61

P33/TO51/INTP4

P33/TI51/INTP4

P16

− −

− −

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions

2.2.1 P00, P01 (port 0)

P00 and P01 function as an I/O port. These pins also function as timer I/O.
The following operation modes can be specified in 1-bit units.

(1) Port mode

P00 and P01 function as an I/O port. P00 and P01 can be set to input or output port in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).

(2) Control mode

P00 and P01 function as timer I/O.

(a) TI000

This is a pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a
capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.

(b) TI010

This is a pin for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit timer/event
counters 00 and 01.

(c) TO00

This is a timer output pin of 16-bit timer/event counter 00.

2.2.2 P10 to P17 (port 1)

P10 to P17 function as an I/O port. These pins also function as pins for serial interface data I/O, clock I/O, and timer

I/O.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P10 to P17 function as an I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS

(2) Control mode

P10 to P17 function as serial interface data I/O, clock I/O, and timer I/O.

(a) SI10

This is a serial data input pin of serial interface CSI10.

(b) SO10

This is a serial data output pin of serial interface CSI10.

(c) SCK10

This is a serial clock I/O pin of serial interface CSI10.

(d) RxD0

This is a serial data input pin of serial interface UART0.

(e) RxD6

This is a serial data input pin of serial interface UART6.

(f) TxD0

This is a serial data output pin of serial interface UART0.

(g) TxD6

This is a serial data output pin of serial interface UART6.

(h) TI50

This is the pin for inputting an external count clock to 8-bit timer/event counter 50.

(i) TO50

This is a timer output pin of 8-it timer/event counter 50.

(j) TOH1

This is a timer output pin of 8-bit timer H1.

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2.2.3 P20 to P23 (port 2)

P20 to P23 function as an I/O port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.

(1) Port mode

P20 to P23 function as an I/O port. P20 to P23 can be set to input or output port in 1-bit units using port mode
register 2 (PM2).

(2) Control mode

P20 to P23 function as A/D converter analog input pins (ANI0 to ANI3). When using these pins as analog input pins,
see (5) ANI0/P20 to ANI3/P23 in 11.6 Cautions for A/D Converter.

Caution ANI0/P20 to ANI3/P23 are set in the analog input mode after release of reset.

2.2.4 P30 to P33 (port 3)

P30 to P33 function as an I/O port. These pins also function as pins for external interrupt request input and timer I/O.
The following operation modes can be specified in 1-bit units.

(1) Port mode

P30 to P33 function as an I/O port. P30 to P33 can be set to input or output port in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).

(2) Control mode

P30 to P33 function as external interrupt request input and timer I/O.

(a) INTP2 to INTP4

These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.

(b) TI51

This is an external count clock input pin to 8-bit timer/event counter 51.

(c) TO51

This is a timer output pin from 8-bit timer/event counter 51.

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2.2.5 P40 and P41 (port 4)

P40 and P41 function as an I/O port. P40 and P41 can be set to input or output port in 1-bit units using port mode

register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).

2.2.6 P60 and P61 (port 6)

P60 and P61 function as an I/O port. These pins also function as pins for serial interface data I/O and clock I/O.
The following operation modes can be specified in 1-bit units.

(1) Port mode

P60 and P61 function as an I/O port. P60 and P61 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
Output of P60 and P61 is N-ch open-drain output (6 V tolerance).

(2) Control mode

P60 and P61 function as serial interface data I/O and clock I/O.

(a) SDA0

This is a serial data I/O pin for serial interface IIC0.

(b) SCL0

This is a serial clock I/O pin for serial interface IIC0.

2.2.7 P70 and P71 (port 7)

P70 and P71 function as an I/O port. P70 and P71 can be set to input or output port in 1-bit units using port mode

register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).

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2.2.8 P120 to P122 (port 12)

P120 to P122 function as an I/O port. These pins also function as pins for external interrupt request input, potential
input for external low-voltage detection, connecting resonator for main system clock, and external clock input for main
system clock.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P120 to P122 function as an I/O port. P120 to P122 can be set to input or output port using port mode register 12
(PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12
(PU12).

(2) Control mode

P120 to P122 function as pins for external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, and external clock input for main system clock.

(a) INTP0

This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling edge, or
both rising and falling edges) can be specified.

(b) EXLVI

This is a potential input pin for external low-voltage detection.

(c) X1, X2

These are the pins for connecting a resonator for main system clock.

(d) EXCLK

This is an external clock input pin for main system clock.

2.2.9 V

2.2.10 RESET

DD, VSS

These are the power supply/ground pins.

(a) V

DD

V

DD is a positive power supply pin.

(b) V

SS

V

SS is a ground potential pin.

This is the active-low system reset input pin.

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS

2.2.11 REGC

This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this pin
to V

SS via a capacitor (0.47 to 1

Caution Keep the wiring length as short as possible for the broken-line part in the above figure.

2.2.12 FLMD0

This is a pin for setting flash memory programming mode.

Connect FLMD0 to V

SS in the normal operation mode.

In flash memory programming mode, connect this pin to the flash memory programmer.

μ

F).

REGC

SS

V

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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins.

See Figure 2-1 for the configuration of the I/O circuit of each type.

Table 2-3. Pin I/O Circuit Types (1/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins

P00/TI000
P01/TI010/TO00
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6 5-AQ
P15 5-AG
P16/TOH1
P17/TI50/TO50
ANI0/P20 to ANI3/P23

Note

5-AQ

5-AQ

5-AG

5-AQ

11-G

I/O

Note ANI0/P20 to ANI3/P23 are set in the analog input mode after release of reset.

Input: Independently connect to EV
Output: Leave open.

< Digital input setting and analog input setting>
Independently connect to AV
<Digital output setting>
Leave open.

REF or AVSS via a resistor.

DD or EVSS via a resistor.

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Table 2-3. Pin I/O Circuit Types (2/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins

P30

5-AQ

I/O
P31/INTP2
P32/INTP3
P33/TI51/TO51/INTP4
P40, P41 5-AG
P60/SCL0

13-AI Input: Independently connect to EV

P61/SDA0

P70, P71

5-AQ

P120/INTP0/EXLVI

P121/X1

P122/X2/EXCLK

Note 1

37

Note 1

FLMD0 38-A

RESET 2 Input Connect directly to EVDD or via a resistor.

REGC

− −

Notes 1. Use recommended connection above in I/O port mode (see Figure 5-2 Format of Clock Operation Mode

Select Register (OSCCTL)) when these pins are not used.

2. FLMD0 is a pin that is used to write data to the flash memory. To rewrite the data of the flash memory on­board, connect this pin to V

SS via a resistor (10 kΩ: recommended).

Figure 2-1. Pin I/O Circuit List (1/2)

Type 2 Type 5-AG

Input: Independently connect to EV

DD or EVSS via a resistor.

Output: Leave open.

DD or EVSS via a resistor, or

connect directly to EV

SS.

Output: Leave this pin open at low-level output after clearing
the output latch of the port to 0.

Input: Independently connect to EV

DD or EVSS via a resistor.

Output: Leave open.

Input: Independently connect to V

DD or VSS via a resistor.

Output: Leave open.

Connect to EVSS or VSS

−

Note 2

.

Connect to VSS via capacitor (0.47 to 1 μF).

IN

Schmitt-triggered input with hysteresis characteristics

DD

EV

Pull-up
enable

EV

Data

Output
disable

EV

Input
enable

DD

P-ch

N

-ch

SS

P-ch

IN/OUT

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Figure 2-1. Pin I/O Circuit List (2/2)

Type 5-AQ Type 37

DD

V

EV

Pull-up
enable

Data

Output
disable

Input
enable

EV

EV

DD

P-ch

N

SS

DD

P-ch

IN/OUT

-ch

Data

Output
disable

RESET

Data

Output
disable

RESET

Input
enable

Input
enable

P-ch

X2

N

-ch

V

SS

P-ch

N-ch

DD

V

P-ch

X1

N

-ch

V

SS

Type 11-G Type 38-A

REF

AV

Data

Output
disable

Comparator

Series resistor string voltage

+

_

Input enable

P-ch

N-ch

AVSS

AVSS

P-ch

N-ch

IN/OUT

IN

Input
enable

Type 13-AI

Data

Output
disable

N-ch

EVSS

IN/OUT

Input
enable

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CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

Products in the R7F0C011B, R7F0C012B, and R7F0C013B can access a 64 KB memory space. Figures 3-1 to 3-3

show the memory maps.

Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size

switching register (IMS) of all products in the R7F0C011B, R7F0C012B, and R7F0C013B are fixed
(IMS = CFH). Therefore, set the value corresponding to each product as indicated below.

Table 3-1. Set Values of Internal Memory Size Switching Register (IMS)

Product IMS ROM Capacity
R7F0C011B 04H 16 KB
R7F0C012B C6H 24 KB
R7F0C013B C8H 32 KB

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Figure 3-1. Memory Map (R7F0C011B)

FFFFH

Special function registers

(SFR)

FF00H
FEFFH

FEE0H

FEDFH

FC00H
FBFFH

256 × 8 bits

General-purpose

registers

32 × 8 bits

Internal high-speed RAM

768 × 8 bits

3FFFH

Program area

Data memory
space

Program
memory space

Reserved

4000H

3FFFH

Flash memory
16384 × 8 bits

0000H

1000H

0FFFH

0800H

07FFH

0085H
0084H

0080H
007FH

0040H
003FH

0000H

CALLF entry area

2048 × 8 bits

Program area

1915 × 8 bits

Option byte area

5 × 8 bits

CALLT table area

64 × 8 bits

Vector table area

64 × 8 bits

Boot cluster 0

Note Writing boot cluster 0 can be prohibited depending on the setting of security (see 22.7 Security Settings).

Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see

Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.

3FFFH
3C00H

3BFFH

Block 0FH

Note

07FFH

0400H

03FFH

0000H

Block 01H

Block 00H

1 KB

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Figure 3-2. Memory Map (R7F0C012B)

FFFFH

Special function registers

FF00H

FEFFH

FEE0H

FEDFH

Internal high-speed RAM

FB00H
FAFFH

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

1024 × 8 bits

5FFFH

Program area

Data memory
space

Program
memory space

Reserved

6000H

5FFFH

Flash memory

24576 × 8 bits

0000H

1000H

0FFFH

0800H

07FFH

0085H
0084H

0080H

007FH

0040H
003FH

0000H

CALLF entry area

2048 × 8 bits

Program area

1915 × 8 bits

Option byte area

5 × 8 bits

CALLT table area

64 × 8 bits

Vector table area

64 × 8 bits

Boot cluster 0

Note Writing boot cluster 0 can be prohibited depending on the setting of security (see 22.7 Security Settings).

Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see

Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.

5FFFH
5C00H

5BFFH

Block 17H

Note

07FFH

0400H

03FFH

0000H

Block 01H

Block 00H

1 KB

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Figure 3-3. Memory Map (R7F0C013B)

FFFFH

Special function registers

FF00H

FEFFH

FEE0H

FEDFH

Internal high-speed RAM

FB00H
FAFFH

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

1024 × 8 bits

7FFFH

Program area

Data mempory
space

Program
memory space

Reserved

8000H

7FFFH

Flash memory
32768 × 8 bits

0000H

1000H
0FFFH

0800H
07FFH

0085H
0084H

0080H
007FH

0040H

003FH

0000H

CALLF entry area

2048 × 8 bits

Program area

1915 × 8 bits

Option byte area

5 × 8 bits

CALLT table area

64 × 8 bits

Vector table area

64

×

8 bits

Boot cluster 0

Note Writing boot cluster 0 can be prohibited depending on the setting of security (see 22.7 Security Settings).

Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see

Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.

7FFFH
7C00H

7BFFH

Block 1FH

Note

07FFH

0400H

03FFH

0000H

Block 01H

Block 00H

1 KB

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Correspondence between the address values and block numbers in the flash memory are shown below.

Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory

Address Value

0000H to 03FFH 00H 4000H to 43FFH 10H
0400H to 07FFH 01H 4400H to 47FFH 11H
0800H to 0BFFH 02H 4800H to 4BFFH 12H
0C00H to 0FFFH 03H 4C00H to 4FFFH 13H
1000H to 13FFH 04H 5000H to 53FFH 14H
1400H to 17FFH 05H 5400H to 57FFH 15H
1800H to 1BFFH 06H 5800H to 5BFFH 16H
1C00H to 1FFFH 07H 5C00H to 5FFFH 17H
2000H to 23FFH 08H 6000H to 63FFH 18H
2400H to 27FFH 09H 6400H to 67FFH 19H
2800H to 2BFFH 0AH 6800H to 6BFFH 1AH
2C00H to 2FFFH 0BH 6C00H to 6FFFH 1BH
3000H to 33FFH 0CH 7000H to 73FFH 1CH
3400H to 37FFH 0DH 7400H to 77FFH 1DH
3800H to 3BFFH 0EH 7800H to 7BFFH 1EH
3C00H to 3FFFH 0FH 7C00H to 7FFFH 1FH

Remark R7F0C011B: Block numbers 00H to 07H
R7F0C012B: Block numbers 00H to 17H
R7F0C013B: Block numbers 00H to 1FH

Block

Number

Address Value

Block

Number

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3.1.1 Internal program memory space

The internal program memory space stores the program and table data . Normally, it is addressed with the program

counter (PC).

R7F0C011B, R7F0C012B, and R7F0C013B incorporate internal ROM (flash memory), as shown below.

Table 3-3. Internal ROM Capacity

Product Internal ROM (Flash Memory)
R7F0C011B
R7F0C012B 24576 × 8 bits (0000H to 5FFFH)
R7F0C013B 32768 × 8 bits (0000H to 7FFFH)

The internal program memory space is divided into the following areas.

(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upo n
reset or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.

16384 × 8 bits (0000H to 3FFFH)

Table 3-4. Vector Table

Vector Table Area Interrupt Factors

0000H RESET input, POC, LVI, WDT
0004H INTLVI

0006H INTP0
000AH INTP2
000CH INTP3
000EH INTP4
0012H INTSRE6
0014H INTSR6
0016H INTST6
0018H INTCSI10/INTST0
001AH INTTMH1
001CH INTTMH0
001EH INTTM50
0020H INTTM000
0022H INTTM010
0024H INTAD
0026H INTSR0
0028H INTWTI
002AH INTTM51
002EH INTWT
0034H INTIIC0
003EH BRK

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(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) Option byte area

A 5-byte area of 0080H to 0084H can be used as an option byte area. Set the option byte at 0080H to 0084H. For
details, see CHAPTER 21 OPTION BYTE.

(4) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

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3.1.2 Internal data memory space

R7F0C011B, R7F0C012B, and R7F0C013B incorporate the following RAMs.

(1) Internal high-speed RAM

The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.

Table 3-5. Internal High-Speed RAM Capacity

Product Internal High-Speed RAM
R7F0C011B 768 × 8 bits (FC00H to FEFFH)
R7F0C012B
R7F0C013B

3.1.3 Special function register (SFR) area

On-chip peripheral hardware special function registers (SFRs) are allocated in t he area FF00H to FFFFH (see Table 3-

6 Special Function Register List in 3.2.3 Special function registers (SFRs)).

Caution Do not access addresses to which SFRs are not assigned.

3.1.4 Data memory addressing

Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the

register or memory relevant to the execution of instructions.

Several addressing modes are provided for addressing the memory re levant to the execution of instructions for the
R7F0C011B, R7F0C012B, and R7F0C013B, based on operability and other co nsiderations. For areas containing data
memory in particular, special addressing methods designed for the functions of special function registers (SFR) and
general-purpose registers are available for use. Figures 3-4 to 3-6 show correspondence between data memory and
addressing. For details of each addressing mode, see 3.4 Operand Address Addressing.

1024 × 8 bits (FB00H to FEFFH)

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Figure 3-4. Correspondence Between Data Memory and Addressing (R7F0C011B)

FFFFH

FF20H

FF1FH

FF00H

FEFFH

FEE0H
FEDFH

FE20H

FE1FH
FC00H

FBFFH

Special function registers

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

Internal high-speed RAM

768 × 8 bits

SFR addressing

Register addressing

Short direct
addressing

Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing

Reserved

4000H

3FFFH

Flash memory

16384 × 8 bits

0000H

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Figure 3-5. Correspondence Between Data Memory and Addressing (R7F0C012B)

FFFFH

FF20H
FF1FH

FF00H

FEFFH

FEE0H

FEDFH

FE20H

FE1FH
FB00H

FAFFH

Special function registers

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

Internal high-speed RAM

1024 × 8 bits

SFR addressing

Register addressing

Short direct
addressing

Direct addressing

Register indirect addressing

6000H
5FFFH

0000H

Reserved

Flash memory

24576 × 8 bits

Based addressing

Based indexed addressing

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Figure 3-6. Correspondence Between Data Memory and Addressing (R7F0C013B)

FFFFH

FF20H
FF1FH

FF00H

FEFFH

FEE0H

FEDFH

FE20H

FE1FH

FB00H
FAFFH

Special function registers

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

Internal high-speed RAM

1024 × 8 bits

Reserved

SFR addressing

Register addressing

Short direct
addressing

Direct addressing

Register indirect addressing

Based addressing

Based indexed addressing

8000H

7FFFH

Flash memory
32768 × 8 bits

0000H

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3.2 Processor Registers

The R7F0C011B, R7F0C012B, and R7F0C013B incorporate the following processor registers.

3.2.1 Control registers

The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).

(1) Program counter (PC)

The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched.
When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-7. Format of Program Counter

15

PC15 PC14PC13PC12 PC11PC10

PC

PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vectored interrupt request acknowledgement or
PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
Reset signal generation sets PSW to 02H.

Figure 3-8. Format of Program Status Word

70

IE Z RBS1 AC RBS0 ISP CY

0PSW

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled
with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.

0

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(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

(c) Register bank select flags (RBS0 and RBS1)

These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction ex ecution is
stored.

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.

(e) In-service priority flag (ISP)

This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-level
vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (see

16.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual
request acknowledgment is controlled by the interrupt enable flag (IE).

(f) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out val ue up on
rotate instruction execution and functions as a bit accumulator during bit operation instruction exec ution.

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area
can be set as the stack area.

Figure 3-9. Format of Stack Pointer

15

SP15 SP14 SP13 SP12 SP11 SP10

SP

SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the
stack memory.
Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.

Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before

using the stack.

0

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Figure 3-10. Data to Be Saved to Stack Memory

(a) PUSH rp instruction (when SP = FEE0H)

SP

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

Register pair higher

Register pair lower

(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)

SP

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

PC15 to PC8

PC7 to PC0

(c) Interrupt, BRK instructions (when SP = FEE0H)

SP

FEE0H

FEE0H

SP

FEDDH

FEDFH

FEDEH

FEDDH

PSW

PC15 to PC8

PC7 to PC0

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Figure 3-11. Data to Be Restored from Stack Memory

(a) POP rp instruction (when SP = FEDEH)

SP

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

Register pair higher

Register pair lower

(b) RET instruction (when SP = FEDEH)

SP

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

PC15 to PC8

PC7 to PC0

(c) RETI, RETB instructions (when SP = FEDDH)

SP

FEE0H

FEE0H

SP

FEDDH

FEDFH

FEDEH

FEDDH

PSW

PC15 to PC8

PC7 to PC0

3.2.2 General-purpose registers

General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the dat a memory. The general­purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16- bit register (AX ,
BC, DE, and HL).

These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).

Register banks to be used for instruction execution are set by the CPU c ontrol instructi on ( SEL RBn). B ecaus e of the 4­register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.

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Figure 3-12. Configuration of General-Purpose Registers

(a) Function name

16-bit processing 8-bit processing

FEFFH

Register bank 0

FEF8H

Register bank 1

FEF0H

Register bank 2

FEE8H

Register bank 3

FEE0H

15 0 7 0

HL

DE

BC

AX

(b) Absolute name

16-bit processing 8-bit processing

FEFFH

Register bank 0

FEF8H

Register bank 1

FEF0H

Register bank 2

FEE8H

Register bank 3

FEE0H

15 0 7 0

RP3

RP2

RP1

RP0

H

L

D

E

B

C

A

X

R7

R6

R5

R4

R3

R2

R1

R0

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3.2.3 Special function registers (SFRs)

Unlike a general-purpose register, each special function reg ister has a special function.

SFRs are allocated to the FF00H to FFFFH area.

Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation

Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).

This manipulation can a lso be specified with an address.

• 8-bit manipulation

Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).

This manipulation can a lso be specified with an address.

• 16-bit manipulation

Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).

When specifyin g an address, describe an even address.

Table 3-6 gives a list of the special function registers. The meanings of items in the table are as follows.

• Symbol

Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined as

an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-QB, SM+ for 78K0,
and SM+ for 78K0/KX2, symbols can be written as an instruction operand.

• R/W

Indicates whether the corresponding special function register can be read or written.

R/W: Read/write enable

R: Read only

W: Write only

• Manipulatable bit units

Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.

• After reset

Indicates each register status upon reset signal generation.

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Table 3-6. Special Function Register List (1/4)

FF00H Port register 0 P0 R/W
FF01H Port register 1 P1 R/W
FF02H Port register 2 P2 R/W
FF03H Port register 3 P3 R/W
FF04H Port register 4 P4 R/W
FF06H Port register 6 P6 R/W
FF07H Port register 7 P7 R/W
FF08H 10-bit A/D conversion result register ADCR R
FF09H 8-bit A/D conversion result register ADCRH R
FF0AH Receive buffer register 6 RXB6 R
FF0BH Transmit buffer register 6 TXB6 R/W
FF0CH Port register 12 P12 R/W
FF0FH Serial I/O shift register 10 SIO10 R
FF10H
FF11H
FF12H
FF13H
FF14H
FF15H
FF16H 8-bit timer counter 50 TM50 R
FF17H 8-bit timer compare register 50 CR50 R/W
FF18H 8-bit timer H compare register 00 CMP00 R/W
FF19H 8-bit timer H compare register 10 CMP10 R/W
FF1AH 8-bit timer H compare register 01 CMP01 R/W
FF1BH 8-bit timer H compare register 11 CMP11 R/W
FF1FH 8-bit timer counter 51 TM51 R
FF20H Port mode register 0 PM0 R/W
FF21H Port mode register 1 PM1 R/W
FF22H Port mode register 2 PM2 R/W
FF23H Port mode register 3 PM3 R/W
FF24H Port mode register 4 PM4 R/W
FF26H Port mode register 6 PM6 R/W
FF27H Port mode register 7 PM7 R/W
FF28H A/D converter mode register ADM R/W
FF29H Analog input channel specification register ADS R/W
FF2CH Port mode register 12 PM12 R/W
FF2EH Port mode register 14 PM14 R/W
FF2FH A/D port configuration register ADPC R/W
FF30H Pull-up resistor option register 0 PU0 R/W

16-bit timer counter 00 TM00 R

16-bit timer capture/compare register 000 CR000 R/W

16-bit timer capture/compare register 010 CR010 R/W

Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −

− − √

− √ −

− √ −

− √ −
√ √ −

− √ −

− − √

− − √

− − √

− √ −

− √ −

− √ −

− √ −

− √ −

− √ −

− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −

After

Reset

00H
00H
00H
00H
00H
00H
00H

0000H

00H
FFH
FFH

00H

00H

0000H

0000H

0000H

00H

00H

00H

00H

00H

00H

00H
FFH
FFH
FFH
FFH
FFH
FFH
FFH

00H

00H
FFH
FFH

00H

00H

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Table 3-6. Special Function Register List (2/4)

FF31H Pull-up resistor option register 1 PU1 R/W
FF33H Pull-up resistor option register 3 PU3 R/W
FF34H Pull-up resistor option register 4 PU4 R/W
FF37H Pull-up resistor option register 7 PU7 R/W
FF3CH Pull-up resistor option register 12 PU12 R/W
FF41H 8-bit timer compare register 51 CR51 R/W
FF43H 8-bit timer mode control register 51 TMC51 R/W
FF48H External interrupt rising edge enable register EGP R/W
FF49H External interrupt falling edge enable register EGN R/W
FF4FH Input switch control register ISC R/W
FF50H

FF53H

FF55H

FF56H Clock selection register 6 CKSR6 R/W
FF57H Baud rate generator control register 6 BRGC6 R/W
FF58H Asynchronous serial interface control register 6 ASICL6 R/W
FF69H 8-bit timer H mode register 0 TMHMD0 R/W
FF6AH Timer clock selection register 50 TCL50 R/W
FF6BH 8-bit timer mode control register 50 TMC50 R/W
FF6CH 8-bit timer H mode register 1 TMHMD1 R/W
FF6DH 8-bit timer H carrier control register 1 TMCYC1 R/W
FF6FH Watch timer operation mode register WTM R/W

Asynchronous serial interface operation mode
register 6

Asynchronous serial interface reception error
status register 6

Asynchronous serial interface transmission
status register 6

ASIM6 R/W

ASIS6 R

ASIF6 R

Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

√ √ −
√ √ −
√ √ −
√ √ −
√ √ −

− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −

− √ −

− √ −

− √ −

− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −

After

Reset

00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
01H

00H

00H

00H
FFH
16H
00H
00H
00H
00H
00H
00H

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Table 3-6. Special Function Register List (3/4)

After

Reset

01H

1FH
FFH
00H

FFH
00H
00H
00H
00H

1AH/

9AH

00H

80H

00H
80H
00H

05H
00H
00H
00H
00H
00H
00H
00H

00H

Note 1

Note 2

Note 3

FF70H

FF71H Baud rate generator control register 0 BRGC0 R/W
FF72H Receive buffer register 0 RXB0 R
FF73H

FF74H Transmit shift register 0 TXS0 W
FF80H Serial operation mode register 10 CSIM10 R/W
FF81H Serial clock selection register 10 CSIC10 R/W
FF84H Transmit buffer register 10 SOTB10 R/W
FF8CH Timer clock selection register 51 TCL51 R/W
FF99H Watchdog timer enable register WDTE R/W

FF9FH Clock operation mode select register OSCCTL R/W
FFA0H Internal oscillation mode register RCM R/W
FFA1H Main clock mode register MCM R/W
FFA2H Main OSC control register MOC R/W
FFA3H

FFA4H Oscillation stabilization time select register OSTS R/W
FFA5H IIC shift register 0 IIC0 R/W
FFA6H IIC control register 0 IICC0 R/W
FFA7H Slave address register 0 SVA0 R/W
FFA8H IIC clock selection register 0 IICCL0 R/W
FFA9H IIC function expansion register 0 IICX0 R/W
FFAAH IIC status register 0 IICS0 R
FFABH IIC flag register 0 IICF0 R/W
FFACH Reset control flag register RESF R

Asynchronous serial interface operation mode
register 0

Asynchronous serial interface reception error
status register 0

Oscillation stabilization time counter status
register

ASIM0 R/W

ASIS0 R

OSTC R

Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

√ √ −

− √ −

− √ −

− √ −

− √ −
√ √ −
√ √ −

− √ −
√ √ −

− √ −

√ √ −
√ √ −
√ √ −
√ √ −
√ √ −

− √ −

− √ −
√ √ −

− √ −
√ √ −
√ √ −
√ √ −
√ √ −

− √ −

Notes 1. The reset value of WDTE is determined by setting of option byte.

2. The value of this register is 00H immediately after a reset release but automatically changes to 80H after
oscillation accuracy stabilization of high-speed internal oscillator has been waited.

3. The reset value of RESF varies depending on the reset source.

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Table 3-6. Special Function Register List (4/4)

After

Reset

00H
00H
00H
00H

Note 1

00H

Note 1

00H

00H

√

00H
00H

√

00H
FFH

√

FFH
FFH

√

FFH
FFH

√

FFH
FFH

√

FFH
CFH
0CH
01H

FFBAH 16-bit timer mode control register 00 TMC00 R/W
FFBBH Prescaler mode register 00 PRM00 R/W
FFBCH Capture/compare control register 00 CRC00 R/W
FFBDH 16-bit timer output control register 00 TOC00 R/W
FFBEH Low-voltage detection register LVIM R/W
FFBFH Low-voltage detection level selection register LVIS R/W
FFE0H Interrupt request flag register 0L IF0 IF0L R/W
FFE1H Interrupt request flag register 0H IF0H R/W
FFE2H Interrupt request flag register 1L IF1 IF1L R/W
FFE3H Interrupt request flag register 1H IF1H R/W
FFE4H Interrupt mask flag register 0L MK0 MK0L R/W
FFE5H Interrupt mask flag register 0H MK0H R/W
FFE6H Interrupt mask flag register 1L MK1 MK1L R/W
FFE7H Interrupt mask flag register 1H MK1H R/W
FFE8H Priority specification flag register 0L PR0 PR0L R/W
FFE9H Priority specification flag register 0H PR0H R/W
FFEAH Priority specification flag register 1L PR1 PR1L R/W
FFEBH Priority specification flag register 1H PR1H R/W
FFF0H Internal memory size switching register
FFF4H Internal expansion RAM size switching register

Note 2

IMS R/W

Note 2

IXS R/W

FFFBH Processor clock control register PCC R/W

Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √

− √ −

− √ −
√ √ −

Notes 1. The reset values of LVIM and LVIS vary depending on the reset source.

2. Regardless of the internal memory capacity, the initial values of the internal memory size switching register

(IMS) and internal expansion RAM size switching register (IXS) of all products in the R7F0C011B,
R7F0C012B, and R7F0C013B are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to
each product as indicated in Tables 3-1.

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3.3 Instruction Address Addressing

An instruction address is determined by contents of the program counter (PC) and memory bank select register (BANK),
and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be
fetched each time another instruction is executed. When a branch instruction is executed, the branch destination
information is set to PC and branched by the following a ddressing (for details of instructions, refer to the 78K/0 Series

Instructions User’s Manual (U12326E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement val ue: jdisp8) of an instruction code to the start
address of the following instruction is transferred to the program counter (PC) and branched. The displacement
value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address o f the foll owi ng instruction t o
the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15 0

PC

+

15 0

876

PC indicates the start address

...

of the instruction after the BR instruction.

α

15 0

PC

When S = 0, all bits of are 0.
When S = 1, all bits of are 1.

α
α

S

jdisp8

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3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. However, before
branching to a memory bank that is not set by the memory bank select register (BANK), change the setting of the
memory bank by using BANK.
The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area.

[Illustration]

In the case of CALL !addr16 and BR !addr16 instructions

70

CALL or BR

Low Addr.

High Addr.

15 0

PC

In the case of CALLF !addr11 instruction

PC

87

70

643

10–8

fa

15 0

00001

CALLF

fa

7–0

11 10

87

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3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate
data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address that is indicated by addr5 and is stored in the memory table from 0040H to
007FH, and allows branching to the entire memory space.

[Illustration]

addr5

Operation code

15 1

01

00000000

765 10

ta

4–0

65 0

111

ta

4–0

0

Effective address

Effective address+1

15 1

01

00000000

Memory (Table)

70

Low Addr.

High Addr.

15 0

PC

87

65 0

87

... The value of the effective address is

0

the same as that of addr5.

3.3.4 Register addressing

[Function]

Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and
branched.
This function is carried out when the BR AX instruction is executed.

[Illustration]

70

07

rp

15 0

PC

AX

87

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3.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) to undergo manipulati on during
instruction execution.

3.4.1 Implied addressing

[Function]

The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the R7F0C011B, R7F0C012B, and R7F0C013B instruction words, the following instructions employ implied
addressing.

Instruction Register to Be Specified by Implied Addressing
MULU A register for multiplicand and AX register for product storage
DIVUW AX register for dividend and quotient storage
ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets
ROR4/ROL4 A register for storage of digit data that undergoes digit rotation

[Operand format]

Because implied addressing can be automatically determined with an instruction, no p articular operand format is
necessary.

[Description example]

In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.

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3.4.2 Register addressing

[Function]

The general-purpose register to be specified is accessed as an operand with the register b ank select flags (RBS0 to
RBS1) and the register specify codes of an operation code.
Register addressing is carried out when an instruction with the following o perand format is executed. W hen an 8-bit
register is specified, one of the eight registers is specified with 3 bits in the operation code.

[Operand format]

Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL

‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E,
D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; when selecting C register as r

Operation code 01100010

Register specify code

INCW DE; when selecting DE register pair as rp

Operation code 10000100

Register specify code

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3.4.3 Direct addressing

[Function]

The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that
is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK.

[Operand format]

Identifier Description
addr16 Label or 16-bit immediate data

[Description example]

MOV A, !0FE00H; when setting !addr16 to FE00H

Operation code 10001110 OP code

00000000 00H

11111110 FEH

[Illustration]

07

OP code

addr16 (lower)

addr16 (upper)

Memory

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3.4.4 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-spe ed RAM and special function
registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports
that are frequently accessed in a program and compare and capture reg isters of the timer/event counter are mapped
in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8
is set to 1. See the [Illustration] shown below.

[Operand format]

Identifier Description
saddr Immediate data that indicate label or FE20H to FF1FH
saddrp Immediate data that indicate label or FE20H to FF1FH (even address only)

[Description example]

LB1 EQU 0FE30H ; Defines FE30H by LB1.

:

MOV LB1, A ; When LB1 indicates FE30H of the saddr area and the value of register A is transferred to that

address

Operation code 1 1110010 OP code

0 0110000 30H (saddr-offset)

[Illustration]

07

OP code

saddr-offset

Short direct memory

Effective address

15

1

111111

87

α

0

When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH,

α

= 1

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3.4.5 Special function register (SFR) addressing

[Function]

A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier Description
sfr Special function register name
sfrp 16-bit manipulatable special function register name (even address only)

[Description example]

MOV PM0, A; when selecting PM0 (FF20H) as sfr

Operation code 1 1110110 OP code

0 0100000 20H (sfr-offset)

[Illustration]

07

Effective address

OP code
sfr-offset

15

1

111111

87

1

SFR

0

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3.4.6 Register indirect addressing

[Function]

Register pair contents specified by a register pair specify code in an instruction word and by a register bank select
flag (RBS0 and RBS1) serve as an operand address for addressing the memory.
This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that
is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK.

[Operand format]

Identifier Description

−

[Description example]

MOV A, [DE]; when selecting [DE] as register pair

[Illustration]

16 08D7

[DE], [HL]

Operation code 10000101

DE

The contents of the memory
addressed are transferred.

7 0

A

E

Memory

The memory address

07

specified with the
register pair DE

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3.4.7 Based addressing

[Function]

8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the
register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the
memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16t h
bit is ignored.
This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that
is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK.

[Operand format]

Identifier Description

−

[Description example]

MOV A, [HL + 10H]; when setting byte to 10H

[Illustration]

16 08H7

[HL + byte]

Operation code 10101110

00010000

HL

The contents of the memory
addressed are transferred.

7 0

A

L

Memory

07

+10H

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3.4.8 Based indexed addressing

[Function]

The B or C register contents specified in an instruction word are added to the contents of the base register, that is,
the HL register pair in the register bank specified by the register bank select flag (RBS0 a nd RBS1), and the sum is
used to address the memory. Addition is performed by expanding the B or C register contents as a positive number
to 16 bits. A carry from the 16th bit is ignored.
This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that
is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK.

[Operand format]

Identifier Description

−

[Description example]

MOV A, [HL +B]; when selecting B register

[Illustration]

[HL + B], [HL + C]

Operation code 10101011

16 0

78

HL

The contents of the memory
addressed are transferred.

7 0

A

H

+

L

B

Memory

07

07

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3.4.9 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are
executed or the register is saved/reset upon generation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.

[Description example]

PUSH DE; when saving DE register

Operation code 10110101

[Illustration]

Memory 07

SP

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

D

E

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CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

Pin I/O buffer power supplies include one V

shown below.

Power Supply Corresponding Pins

VDD All pins

The R7F0C011B, R7F0C012B, and R7F0C013B, microcontrollers are provided with digital I/O ports, which enable

variety of control operations. The functions of each port are shown in Table 4-2.

In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate

functions, see CHAPTER 2 PIN FUNCTIONS.

DD system. The relationship between these power supplies and the pins is

Table 4-1. Pin I/O Buffer Power Supplies

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Table 4-2. Port Functions

Function

Name

P00 TI000

P01

P10 SCK10/TxD0

P11 SI10/RxD0

P12 SO10

P13 TxD6

P14 RxD6

P15

P16 TOH1

P17

P20 to P23 I/O

P30

P31 INTP2

P32 INTP3

P33

P40, P41 I/O

P60 SCL0

P61

P70, P71 I/O

P120 INTP0/EXLVI

P121 X1

P122

I/O Function After Reset Alternate Function

I/O

I/O

I/O

I/O

I/O

Port 0.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 2.
4-bit I/O port.
Input/output can be specified in 1-bit units.

Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 4.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 6
2-bit I/O port.
Output is N-ch open-drain output (6 V tolerance).
Input/output can be specified in 1-bit units.

Port 7
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.

Port 12.
3-bit I/O port.
Input/output can be specified in 1-bit units.
Only for P120, use of an on-chip pull-up resistor can be
specified by a software setting.

Input port

Input port

Analog
input

Input port

Input port

Input port

Input port

Input port

TI010/TO00

−

TI50/TO50

ANI0 to ANI3

−

INTP4/TI51/TO51

−

SDA0

−

X2/EXCLK

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4.2 Port Configuration

Ports include the following hardware.

Table 4-3. Port Configuration

Item Configuration

Control registers

Port Total: 27 (CMOS I/O: 25, N-ch open drain I/O: 2)

Pull-up resistor Total: 17

Port mode register (PMxx): PM0 to PM4, PM6, PM7, PM12
Port register (Pxx): P0 to P4, P6, P7, P12
Pull-up resistor option register (PUxx): PU0, PU1, PU3, PU4, PU7, PU12
A/D port configuration register (ADPC)

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4.2.1 Port 0

Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 0 (PU0).

This port can also be used for timer I/O.

Reset signal generation sets port 0 to input mode.

Figures 4-1 and 4-2 show block diagrams of port 0.

Figure 4-1. Block Diagram of P00

V

DD

WR

PU

PU0

PU00

Alternate

function

RD

P-ch

Selector

WR

Internal bus

WR

PORT

PM

P0

Output latch

(P00)

PM0

PM00

P00/TI000

P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal

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Figure 4-2. Block Diagram of P01

V

DD

WR

PU

PU0

Internal bus

WR

WR

PU01

Alternate

function

RD

Selector

PORT

P0

Output latch

(P01)

PM

PM0

P-ch

P01/TI010/TO00

PM01

Alternate

function

P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal

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4.2.2 Port 1

Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port
mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 1 (PU1).

This port can also be used for, serial interface data I/O, clock I/O, and timer I/O.

Reset signal generation sets port 1 to input mode.

Figures 4-3 to 4-7 show block diagrams of port 1.

Cautions 1. To use P10/SCK10/TxD0 and P12/SO10 as general-purpose ports, set serial operation mode

register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the default status (00H).

2. To use P13/TxD6 as general-purpose port, clear bit 0 (TXDLV6) of asynchronous serial interface

control register 6 (ASICL6) to 0 (normal output of TxD6).

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Figure 4-3. Block Diagram of P10

V

DD

WR

PU

PU1

Internal bus

WR

WR

PU10

Alternate

function

RD

Selector

PORT

P1

Output latch

(P10)

PM

PM1

P-ch

P10/SCK10/TxD0

PM10

Alternate

function

P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal

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Figure 4-4. Block Diagram of P11 and P14

V

DD

WR

PU

PU1

Internal bus

WR

WR

PU11, PU14

Alternate

function

RD

Selector

PORT

P1

Output latch

(P11, P14)

PM

PM1

P-ch

P11/SI10/RxD0,
P14/RxD6

PM11, PM14

P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal

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Figure 4-5. Block Diagram of P12 and P15

V

DD

PU

WR

PU1

Internal bus

WR

WR

PU12, PU15

RD

Selector

PORT

P1

Output latch

(P12, P15)

PM

PM1

P-ch

P12/SO10,
P15

PM12, PM15

Alternate

function

P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal

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Figure 4-6. Block Diagram of P13

VDD

WR

PU

PU1

Internal bus

RD

WR

WRPM

PU13

Selector

PORT

P1

Output latch

(P13)

PM1

P-ch

P13/TxD6

PM13

Alternate

function

P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal

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Figure 4-7. Block Diagram of P16 and P17

V

DD

PU

WR

PU1

Internal bus

WR

WR

PU16, PU17

Alternate

function

RD

Selector

PORT

P1

Output latch

(P16, P17)

PM

PM1

P-ch

P16/TOH1,
P17/TI50/TO50

PM16, PM17

Alternate

function

P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal

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4.2.3 Port 2

Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port
mode register 2 (PM2).

This port can also be used for A/D converter analog input.

To use P20/ANI0 to P23/ANI3 as digital input pins, set them in the digital I/O mode by using the A/D port configuration
register (ADPC) and in the input mode by using PM2. Use these pins starting from the lower bit.

To use P20/ANI0 to P23/ANI3 as digital output pins, set them in the digital I/O mode by using ADPC and in the output
mode by using PM2.

Table 4-4. Setting Functions of P20/ANI0 to P23/ANI3 Pins

ADPC PM2 ADS P20/ANI0 to P23/ANI3 Pin

Analog input selection

Input mode

Output mode

Output mode

Selects ANI. Analog input (to be converted) Input mode

Does not select ANI. Analog input (not to be converted)

Selects ANI.

Does not select ANI.

−

−

All P20/ANI0 to P23/ANI3 are set in the analog input mode when the reset signal is generated.

Figure 4-8 shows a block diagram of port 2.

Digital input Digital I/O selection

Digital output

Setting prohibited

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Figure 4-8. Block Diagram of P20 to P23

RD

Selector

PORT

WR

Int ernal bus

WR

PM

P2: Port register 2

PM2: Port mode register 2

RD: Read signal
WR××: Write signal

P2

Output latch

(P20 to P23)

PM2

PM20 to PM23

P20/ANI0 to
P23/ANI3

A/D converter

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4.2.4 Port 3

Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port
mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 3 (PU3).

This port can also be used for external interrupt request input and timer I/O.

Reset signal generation sets port 3 to input mode.

Figures 4-9 and 4-10 show block diagrams of port 3.

Figure 4-9. Block Diagram of P30 to P32

V

DD

WR

PU

PU3

PU30 to PU32

Alternate

function

RD

P-ch

Internal bus

WR

WR

PORT

P3

Output latch
(P30 to P32)

PM

PM3

PM30 to PM32

Selector

P30,
P31/INTP2,
P32/INTP3

P3: Port register 3
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal

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Figure 4-10. Block Diagram of P33

V

DD

WR

PU

PU3

Internal bus

WR

WR

PU33

Alternate

function

RD

Selector

PORT

P3

Output latch

(P33)

PM

PM3

P-ch

P33/INTP4/TI51/TO51

PM33

Alternate

function

P3: Port register 3
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal

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4.2.5 Port 4

Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port
mode register 4 (PM4). When the P40 and P41 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 4 (PU4).

Reset signal generation sets port 4 to input mode.

Figure 4-11 shows a block diagram of port 4.

Figure 4-11. Block Diagram of P40 and P41

V

DD

WR

PU

RD

PU4

PU40, PU41

P-ch

Selector

WR

Internal bus

WR

PORT

PM

P4

Output latch

(P40, P41)

PM4

PM40, PM41

P40, P41

P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal

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4.2.6 Port 6

Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port
mode register 6 (PM6).

The output of the P60 and P61 pins is N-ch open-drain output (6 V tolerance).

This port can also be used for serial interface data I/O, clock I/O.

Reset signal generation sets port 6 to input mode.

Figure 4-12 shows block diagram of port 6.

Figure 4-12. Block Diagram of P60 and P61

Alternate

function

RD

Selector

PORT

WR

Internal bus

WR

PM

P6

Output latch

(P60, P61)

PM6

P60/SCL0,
P61/SDA0

PM60, PM61

Alternate

function

P6: Port register 6
PM6: Port mode register 6
RD: Read signal
WR××: Write signal

Caution A through current flows through P60 and P61 if an intermediate potential is input to these pins,

because the input buffer is also turned on when P60 and P61 are in output mode. Consequently, do

not input an intermediate potential when P60 and P61 are in output mode.

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4.2.7 Port 7

Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port
mode register 7 (PM7). When the P70 and P71 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 7 (PU7).

Reset signal generation sets port 7 to input mode.

Figure 4-13 shows a block diagram of port 7.

Figure 4-13. Block Diagram of P70 and P71

V

DD

WR

PU

PU7

PU70, PU71

Alternate

function

RD

P-ch

Internal bus

WR

WR

PORT

P7

Output latch

(P70, P71)

PM

PM7

PM70, PM71

Selector

P70, P71

P7: Port register 7
PU7: Pull-up resistor option register 7
PM7: Port mode register 7
RD: Read signal
WR××: Write signal

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4.2.8 Port 12

Port 12 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port
mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified
by pull-up resistor option register 12 (PU12).

This port can also be used as pins for external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, and external clock input for main system clock.

Reset signal generation sets port 12 to input mode.

Figures 4-14 and 4-15 show block diagrams of port 12.

Caution When using the P121 and P122 pins to connect a resonator for the main system clock (X1, X2), or to

input an external clock for the main system clock (EXCLK), the X1 oscillation mode, or external clock

input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see

5.3 (1) Clock operation mode select register (OSCCTL)). The reset value of OSCCTL is 00H (all of the

P121 and P122 pins are I/O port pins). At this time, setting of the PM121, PM122, P121, and P122 pins

is not necessary.

Figure 4-14. Block Diagram of P120

WR

PU

PU12

V

DD

Internal bus

WR

WR

PU120

Alternate

function

RD

Selector

PORT

P12

Output latch

(P120)

PM

PM12

PM120

P-ch

P120/INTP0/EXLVI

P12: Port register 12
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
RD: Read signal
WR××: Write signal

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Figure 4-15. Block Diagram of P121 and P122

OSCCTL

OSCSEL

Selector

P122/X2/EXCLK

OSCCTL

WR

WR

RD

PORT

P12

Output latch

(P122)

PM

PM12

PM122

OSCCTL

OSCSEL

EXCLK, OSCSEL

Internal bus

RD

Selector

WR

WR

PORT

PM

P12

Output latch

(P121)

PM12

PM121

OSCCTL

OSCSEL

P121/X1

P12: Port register 12
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
OSCCTL: Clock operation mode select register
RD: Read signal
WR××: Write signal

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4.3 Registers Controlling Port Function

Port functions are controlled by the following four types of registers.

• Port mode registers (PMxx)

• Port registers (Pxx)

• Pull-up resistor option registers (PUxx)

• A/D port configuration register (ADPC)

(1) Port mode registers (PMxx)

These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Settings of Port

Mode Register and Output Latch When Using Alternate Function.

Figure 4-16. Format of Port Mode Register

Symbol

PM0

7

1

6

1

5

1

4

1

3

1

2

1

1

PM010PM00

Address

FF20H

After reset

FFH

R/W

R/W

PM1

PM2

PM3

PM4

PM6

PM7

PM12

PM17

1

1

1

1

1

1

PM16 PM15 PM14 PM13 PM12 PM11 PM10

1 1 1 PM23 PM22 PM21 PM20 FF22H FFH R/W

1 1 1 PM33 PM32 PM31 PM30

1 1 1 1 1 PM41 PM40

1 1 1 1 1 PM61 PM60

1 1 1 1 1 PM71 PM70

1 1 1 1 PM122 PM121 PM120

FF21H FFH R/W

FF23H FFH R/W

FF24H FFH R/W

FF26H FFH R/W

FF27H FFH R/W

FF2CH FFH R/W

PMmn

0 Output mode (output buffer on)

1 Input mode (output buffer off)

Pmn pin I/O mode selection

(m = 0 to 4, 6, 7, 12; n = 0 to 7)

Caution Be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM2, bits 4 to 7 of PM3, bits 2 to 7 of PM4,

bits 2 to 7 of PM6, bits 2 to 7 of PM7, and bits 3 to 7 of PM12 to “1”.

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(2) Port registers (Pxx)

These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.

Figure 4-17. Format of Port Mode Register

Symbol

P0

P1

P2

P3

7

0

P17

0

0

6

0

P16 P15 P14 P13 P12 P11 P10

0 0 0 P23 P22 P21 P20

0 0 0 P33 P32 P31 P30

5

0

4

0

3

0

2

0

1

P01

0

P00

Address

FF00H

FF01H 00H (output latch) R/W

FF02H 00H (output latch)

FF03H 00H (output latch) R/W

After reset

00H (output latch)

R/W

R/W

R/W

P4

P6

P7

P12

0

0

0

0

0 0 0 0 0 P41 P40

0 0 0 P63 P62 P61 P60

0 0 0 0 0 P71 P70

0 0 0 0 P122

Output data control (in output mode) Input data reading (in input mode)

0 Output mode (output buffer on)

1 Input mode (output buffer off)

Note “0” is always read from the output latch of P121 and P122 if the pin is in the external clock input mode.

Caution Be sure to set bits 2 to 7 of P0, bits 4 to 7 of P2, bits 4 to 7 of P3, bits 2 to 7 of P4, bits 2 to 7

of P6, bits 2 to 7 of P7, and bits 3 to 7 of P12 to “0”.

FF04H 00H (output latch) R/W

FF06H 00H (output latch) R/W

FF07H 00H (output latch) R/W

Note

m = 0 to 4, 6, 7, 12; n = 0 to 7 PMmn

P121

Note

P120 FF0CH 00H (output latch) R/W

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(3) Pull-up resistor option registers (PUxx)

These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be
used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has
been specified in these registers. On-chip pull-up resistors cannot be connected to bits set to output mode and bits
used as alternate-function output pins, regardless of the settings of these registers.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.

Figure 4-18. Format of Pull-up Resistor Option Register

Symbol

PU0

PU1

PU3

PU4

7

0

PU17

0

0

6

0

PU16 PU15 PU14 PU13 PU12 PU11 PU10

0 0 0 PU33 PU32 PU31 PU30

0 0 0 0 0 PU41 PU40

5

0

4

0

3

0

2

0

1

PU010PU00

Address

FF30H

FF31H 00H R/W

FF33H 00H R/W

FF34H 00H R/W

After reset

00H

R/W

R/W

PU7

PU12

0

0

0 0 0 0 0 PU71 PU70

0 0 0 0 0 0 PU120

FF37H 00H R/W

FF3CH 00H R/W

PUmn

0 On-chip pull-up resistor not connected

1 On-chip pull-up resistor connected

Pmn pin on-chip pull-up resistor selection

(m = 0, 1, 3, 4, 7, 12; n = 0 to 7)

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(4) A/D port configuration register (ADPC)

This register switches the P20/ANI0 to P23/ANI3 pins to digital I/O of port or analog input of A/D converter.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.

Figure 4-19. Format of A/D Port Configuration Register (ADPC)

Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register 2 (PM2).

2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the

Address: FF2FH After reset: 00H R/W

Symbol

ADPC

ADPC3

0

0

0

0

0

1

ADPC2

0

0

0

0

1

0

Other than above

ADPC1

ADPC0

0

0

1

1

0

0

0

1

0

1

0

0

Digital I/O (D)/analog input (A) switching

P23/ANI3

A

A

A

A

D

D

Setting prohibited

P22/ANI2

A

A

A

D

D

D

P21/ANI1

A

A

D

D

D

D

01234567

ADPC0ADPC1ADPC2ADPC30000

P20/ANI0

A

D

D

D

D

D

peripheral hardware clock is stopped. For details, see CHAPTER 26 CAUTIONS FOR WAIT.

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4.4 Port Function Operations

Port operations differ depending on whether the input or output mode is set, as shown below.

4.4.1 Writing to I/O port

(1) Output mode

A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.

(2) Input mode

A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not
change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.

4.4.2 Reading from I/O port

(1) Output mode

The output latch contents are read by a transfer instruction. The output latch contents do not change.

(2) Input mode

The pin status is read by a transfer instruction. The output latch contents do not change.

4.4.3 Operations on I/O port

(1) Output mode

An operation is performed on the output latch contents, and the result is written to the output latch. The output latch
contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.

(2) Input mode

The pin level is read and an operation is performed on its contents. The result of the operation is written to the output
latch, but since the output buffer is off, the pin status does not change.
The data of the output latch is cleared when a reset signal is generated.

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4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function

To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-5.

Remark The port pins mounted depend on the product. See Table 4-2 Port Functions.

Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2)

Alternate Function Pin Name

Function Name I/O

P00 TI000 Input 1
P01

P10

P11

P12 SO10 Output 0 0
P13 TxD6 Output 0 1
P14 RxD6 Input 1

P17

P20 to P23

TI010 Input 1
TO00 Output 0 0
SCK10

TxD0 Output 0 1
SI10 Input 1
RxD0 Input 1

TOH1 Output 0 0 P16
INTP5 Input 1
TI50 Input 1
TO50 Output 0 0

Note

ANI0 to ANI3

Note

Input 1
Output 0 1

Input 1

Note The function of the ANI0/P20 to ANI3/P23 pins can be selected by using the A/D port configuration register

(ADPC), the analog input channel specification register (ADS), and PM2.

ADPC PM2 ADS ANI0/P20 to ANI3/P23 Pins

Analog input selection

Output mode

Input mode

Output mode

Selects ANI. Analog input (to be converted) Input mode

Does not select ANI. Analog input (not to be converted)

Selects ANI.

Does not select ANI.

−

−

Setting prohibited

Digital input Digital I/O selection

Digital output

Remark ×: Don’t care

PM××: Port mode register

P××: Port output latch

PM×× P××

×
×

×

×
×

×

×
×

×

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Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2)

Alternate Function Pin Name

Function Name I/O

P31 and P32 INTP2 and INTP3 Input 1
P33

P60 SCL0 I/O 0 0
P61 SDA0 I/O 0 0
P120

P121 X1
P122

INTP4 Input 1
TI51 Input 1
TO51 Output 0 0

INTP0 Input 1
EXLVI Input 1

Note

Note

X2
EXCLK

Note

− × ×

− × ×

Input

Note When using the P121 and P122 pins to connect a resonator for the main system clock (X1, X2), or to input an

external clock for the main system clock (EXCLK), the X1 oscillation mode or external clock input mode must be
set by using the clock operation mode select register (OSCCTL) (for details, see 5.3 (1) Clock operation
mode select register (OSCCTL)). The reset value of OSCCTL is 00H (all of the P121 and P122 are I/O port
pins). At this time, setting of PM121, PM122, P121, and P122 is not necessary.

Remarks ×: Don’t care

PM××: Port mode register

P××: Port output latch

PM×× P××

×
×
×

×
×

× ×

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4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)

When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output
latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.

Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.

<Example> When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port

latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a
1-bit manipulation instruction, the output latch value of port 1 is FFH.

Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output

latch and pin status, respectively.

A 1-bit manipulation instruction is executed in the following order in the RF0C011B, RF0C012B,

RF0C013B microcontrollers.

<1> The Pn register is read in 8-bit units.

<2> The targeted one bit is manipulated.

<3> The Pn register is written in 8-bit units.

In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses of

P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time,

the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.

Figure 4-20. Bit Manipulation Instruction (P10)

P10

Low-level output

P11 to P17

Pin status: High level

1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.

P10

High-level output

P11 to P17

Pin status: High level

Port 1 output latch

00000000

1-bit manipulation instruction for P10 bit

<1> Port register 1 (P1) is read in 8-bit units.

• In the case of P10, an output port, the value of the port output latch (0) is read.

• In the case of P11 to P17, input ports, the pin status (1) is read.

<2> Set the P10 bit to 1.
<3> Write the results of <2> to the output latch of port register 1 (P1)

in 8-bit units.

Port 1 output latch

11111111

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CHAPTER 5 CLOCK GENERATOR

5.1 Functions of Clock Generator

The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.

(1) Main system clock

<1> X1 oscillator

This circuit oscillates a clock of f
Oscillation can be stopped by executing the STOP instruction or using the main OSC control register (MOC).

<2> Internal high-speed oscillator

This circuit oscillates a clock of f
with this internal high-speed oscillation clock. Oscillation can be stopped by executing the STOP instruction
or using the internal oscillation mode register (RCM).

An external main system clock (f
external main system clock input can be disabled by executing the STOP instruction or using RCM.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal high­speed oscillation clock can be selected by using the main clock mode register (MCM).

(2) Internal low-speed oscillation clock (clock for watchdog timer)

• Internal low-speed oscillator

This circuit oscillates a clock of f
clock always starts operating.
Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed
oscillator can be stopped by software” is set by option byte.
The internal low-speed oscillation clock cannot be used as the CPU clock. The following hardware operates with
the internal low-speed oscillation clock.

• Watchdog timer

• TMH1 (when f

RL, fRL/2

7

, or fRL/29 is selected)

Remark f
f
f
f

X: X1 clock oscillation frequency
RH: Internal high-speed oscillation clock frequency
EXCLK: External main system clock frequency
RL: Internal low-speed oscillation clock frequency

X = 1 to 10 MHz by connecting a resonator to X1 and X2.

RH = 8 MHz (TYP.). After a reset release, the CPU always starts operating

EXCLK = 1 to 10 MHz) can also be supplied from the EXCLK/X2/P122 pin. An

RL = 240 kHz (TYP.). After a reset release, the internal low-speed oscillation

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5.2 Configuration of Clock Generator

The clock generator includes the following hardware.

Table 5-1. Configuration of Clock Generator

Item Configuration

Control registers Clock operation mode select register (OSCCTL)

Processor clock control register (PCC)
Internal oscillation mode register (RCM)
Main OSC control register (MOC)
Main clock mode register (MCM)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)

Oscillators X1 oscillator

Internal high-speed oscillator
Internal low-speed oscillator

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)

Processor clock

control register

(PCC)

Main clock

mode register

(MCM)

Oscillation stabilization

time select register (OSTS)

Internal bus

PCC2 PCC1 PCC0

MCM0

XSEL

OSTS1 OSTS0OSTS2

3

Oscillation

stabilization

3

X1 oscillation

stabilization time counter

Peripheral

time counter

status register

(OSTC)

16

MOST

15

MOST

14

MOST

13

MOST

11

MOST

PRS

Peripheral

hardware

clock (f

hardware

clock switch

Controller

Prescaler

XP

f

System

clock switch

XP

f

XP

f

XP

f

XP

f

4

2

3

2

2

2

2

)

CPU

CPU clock

(f

Selector

Watchdog timer,

8-bit timer H1

RL

f

Internal low-

speed oscillator

(240 kHz (TYP.))

Cannot be stopped

Can be stopped

Option byte

1:

0:

LSRSTOP

RSTS RSTOP

Internal oscillation

(RCM)

mode register

Internal bus

MCS

Figure 5-1. Block Diagram of Clock Generator

Main clock

mode register

(MCM)

MSTOP

(MOC)

Main OSC

control register

OSCSEL

EXCLK

(OSCCTL)

select register

Clock operation mode

STOP

XH

f

X

f

clock oscillator

oscillation

High-speed system

Crystal/ceramic

X1/P121

X2/EXCLK

RH

f

Internal high-

(8 MHz (TYP.))

speed oscillator

EXCLK

f

clock

External input

/P122

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Remark fX: X1 clock oscillation frequency
fRH: Internal high-speed oscillation clock frequency
f
f

EXCLK: External main system clock frequency
XH: High-speed system clock frequency

fXP: Main system clock frequency
f
f

PRS: Peripheral hardware clock frequency
CPU: CPU clock frequency

fRL: Internal low-speed oscillation clock frequency

5.3 Registers Controlling Clock Generator

The following seven registers are used to control the clock generator.

• Clock operation mode select register (OSCCTL)

• Processor clock control register (PCC)

• Internal oscillation mode register (RCM)

• Main OSC control register (MOC)

• Main clock mode register (MCM)

• Oscillation stabilization time counter status register (OSTC)

• Oscillation stabilization time select register (OSTS)

(1) Clock operation mode select register (OSCCTL)

This register selects the operation modes of the high-speed system clock.
OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.

Figure 5-2. Format of Clock Operation Mode Select Register (OSCCTL)

Address: FF9FH After reset: 00H R/W

Symbol <7> <6> 5 4 3 2 1 0

OSCCTL EXCLK OSCSEL 0 0 0 0 0 0

EXCLK OSCSEL High-speed system clock

pin operation mode

0 0 I/O port mode I/O port

0 1 X1 oscillation mode Crystal/ceramic resonator connection

1 0 I/O port mode I/O port

1 1 External clock input

mode

Cautions 1. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of

the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external

clock from the EXCLK pin is disabled).

2. Be sure to clear bits 0 to 5 to 0.

Remark f

XH: High-speed system clock oscillation frequency

P121/X1 pin P122/X2/EXCLK pin

I/O port External clock input

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(2) Processor clock control register (PCC)

This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock.
PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PCC to 01H.

Figure 5-3. Format of Processor Clock Control Register (PCC)

Address: FFFBH After reset: 01H R/W

Symbol 7 6 5 4 3 2 1 0

PCC 0 0 0 0 0 PCC2 PCC1 PCC0

PCC2 PCC1 PCC0 CPU clock (fCPU) selection
0 0 0 fXP
0 0 1 fXP/2 (default)
0 1 0 fXP/2
0 1 1 fXP/2
1 0 0 fXP/2

2

3

4

Other than above Setting prohibited

Cautions 1. Be sure to clear bits 3 to 7 to 0.

2. The peripheral hardware clock (fPRS) is not divided when the division ratio of the PCC is set.

Remark f

XP: Main system clock oscillation frequency

The fastest instruction can be executed in 2 clocks of the CPU clock in the R7F0C011B, R7F0C012B, and
R7F0C013B. Therefore, the relationship between the CPU clock (f

CPU) and the minimum instruction execution time is

as shown in Table 5-2.

Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time

CPU Clock (fCPU)

High-Speed System Clock

At 10 MHz Operation At 8 MHz (TYP.) Operation
fXP 0.2
fXP/2 0.4

2

fXP/2

3

fXP/2

4

fXP/2

Minimum Instruction Execution Time: 2/fCPU

Main System Clock

Note

μ

s 0.25

μ

s 0.5

0.8 μs 1.0

1.6 μs 2.0

3.2 μs 4.0

Internal High-Speed Oscillation Clock

μ

s (TYP.)

μ

s (TYP.)

μ

s (TYP.)

μ

s (TYP.)

μ

s (TYP.)

Note

Note The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock (high-speed

system clock/internal high-speed oscillation clock) (see Figure 5-6).

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(3) Internal oscillation mode register (RCM)

This register sets the operation mode of internal oscillator.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80H

Figure 5-4. Format of Internal Oscillation Mode Register (RCM)

Address: FFA0H After reset: 80H

Symbol <7> 6 5 4 3 2 <1> <0>

RCM RSTS 0 0 0 0 0 LSRSTOP RSTOP

Note 1

R/W

RSTS Status of internal high-speed oscillator

0 Waiting for accuracy stabilization of internal high-speed oscillator

1 Stability operating of internal high-speed oscillator

LSRSTOP Internal low-speed oscillator oscillating/stopped

0 Internal low-speed oscillator oscillating

1 Internal low-speed oscillator stopped

RSTOP Internal high-speed oscillator oscillating/stopped

0 Internal high-speed oscillator oscillating

1 Internal high-speed oscillator stopped

Notes 1. The value of this register is 00H immediately after a reset release but automatically changes to

80H after internal high-speed oscillator has been stabilized.

2. Bit 7 is read-only.

Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock other

than the internal high-speed oscillation clock. Specifically, set under either of the

following conditions.

• When MCS = 1 (when CPU operates with the high-speed system clock)

In addition, stop peripheral hardware that is operating on the internal high-speed

oscillation clock before setting RSTOP to 1.

Note 2

Note 1

.

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(4) Main OSC control register (MOC)

This register selects the operation mode of the high-speed system clock.
This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU
operates with a clock other than the high-speed system clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80H.

Figure 5-5. Format of Main OSC Control Register (MOC)

Address: FFA2H After reset: 80H R/W

Symbol <7> 6 5 4 3 2 1 0

MOC MSTOP 0 0 0 0 0 0 0

Control of high-speed system clock operation

0 X1 oscillator operating External clock from EXCLK pin is enabled

1 X1 oscillator stopped External clock from EXCLK pin is disabled

MSTOP

X1 oscillation mode External clock input mode

Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock

other than the high-speed system clock. Specifically, set under either of the

following conditions.

• When MCS = 0 (when CPU operates with the internal high-speed oscillation

clock)

In addition, stop peripheral hardware that is operating on the high-speed system

clock before setting MSTOP to 1.

2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select

register (OSCCTL) is 0 (I/O port mode).

3. The peripheral hardware cannot operate when the peripheral hardware clock is

stopped. To resume the operation of the peripheral hardware after the peripheral

hardware clock has been stopped, initialize the peripheral hardware.

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