Renesas R7F0C011B, R7F0C012B, R7F0C013B User Manual
User’s Manual
R7F0C011B, R7F0C012B,
8
R7F0C013B
User’s Manual: Hardware
8-Bit Single-Chip Microcontrollers
-Preliminary-
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.0.01 Sep 2012
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
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and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
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(2012.4)
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the tra nsition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generate d due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-do wn circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should b e used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be gr oun ded usin g a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the e xternal power suppl y after switching on th e internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse po wer on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degr adation of internal elements
due to the passage of an abnormal current. The correct po wer on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the devic e.
How to Use This Manual
Readers This manual is intended for user engineers who wish to understand the functions of the
R7F0C011B, R7F0C012B, R7F0C013B and design and develop application systems and
programs for these devices.
The target products are as follows.
• R7F0C011B2DFP
• R7F0C012B2DFP
• R7F0C013B2DFP
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The R7F0C011B, R7F0C012B, R7F0C013B manual is separated into two parts: this
manual and the instructions edition (common to the 78K0R Microcontroller).
R7F0C011B, R7F0C012B, R7F0C013B
User’s Manual
(This Manual)
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• Electrical specifications (target)
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved
word in the assembler, and is defined as an sfr variable using the #pragma sfr
directive in the compiler.
• To know details of the R7F0C011B, R7F0C012B, R7F0C013B Microcontroller instructions:
→ Refer to the separate document 78K0 Series Instructions User’s Manual (U12326E).
• CPU functions
• Instruction set
• Explanation of each instruction
78K/0 Series
User’s Manual
Instructions
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
Decimal
Hexadecimal
...
×××× or ××××B
...
××××
...
××××H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
R7F0C011B, R7F0C012B, R7F0C013B User’s Manual This manual
78K/0 Series Instructions User’s Manual U12326E
78K0/Kx2 Flash Memory Programming (Programmer) Application Note U17739E
Documents Related to Flash Memory Programming
Document Name Document No.
PG-FP5 Flash Memory Programmer User’s Manual R20UT0008E
QB-MINI2 On-Chip Debug Emulator with Programming Function User’s Manual R20UT0449E
QB-Programmer Programming GUI U18257E
Documents Related to Development Tools (Hardware)
Document Name Document No.
QB-MINI2 On-Chip Debug Emulator with Programming Function User’s Manual R20UT0449E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Documents Related to Development Tools (Software)
Document Name Document No.
RA78K0 Ver.3.80 Assembler Package
User’s Manual
78K0 Assembler Package RA78K0 Ver.4.01 Operating Precautions (Notification Document)
User’s Manual
78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions (Notification Document)
User’s Manual
ID78K0-QB Ver.2.94 Integrated Debugger User’s Manual Operation U18330E
ID78K0-QB Ver.3.00 Integrated Debugger User’s Manual Operation U18492E
PM plus Ver.5.20
PM+ Ver.6.30
Note 1
Note 2
Note 3
Note 4
User’s Manual
User’s Manual
Operation U17199E
Language U17198E
Structured Assembly Language U17197E
Note 1
Operation U17201E CC78K0 Ver.3.70 C Compiler
Language U17200E
Note 2
Operation U18601E SM+ System Simulator
User Open Interface U18212E
ZUD-CD-07-0181-E
ZUD-CD-07-0103-E
U16934E
U18416E
Notes 1. This document is installed into the PC together with the tool when installing RA78K0 Ver. 4.01. For
descriptions not included in “78K0 Assembler Package RA78K0 Ver. 4.01 Operating Precautions”, refer to the
user’s manual of RA78K0 Ver. 3.80.
2. This document is installed into the PC together with the tool when installing CC78K0 Ver. 4.00. For
descriptions not included in “78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions”, refer to the user’s
manual of CC78K0 Ver. 3.70.
3. PM plus Ver. 5.20 is the integrated development environment included with RA78K0 Ver. 3.80.
4. PM+ Ver. 6.30 is the integrated development environment included with RA78K0 Ver. 4.01. Software tool
(assembler, C compiler, debugger, and simulator) products of different versions can be managed.
Other Documents
Document Name Document No.
RENESAS MICROCOMPUTER GENERAL CATALOG R01CS0001E
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.renesas.com/prod/package/manual/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners.
Windows is a registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
®
Caution: This product uses SuperFlash
technology licensed from Silicon Storage Technology, Inc.
CONTENTS
CHAPTER 1 OUTLINE............................................................................................................................... 1
1.1 Features ....................................................................................................................................... 1
1.2 Applications................................................................................................................................. 2
1.3 Ordering Information .................................................................................................................. 2
1.4 Pin Configuration (Top View)..................................................................................................... 3
1.5 Pin Identification ......................................................................................................................... 4
1.6 Block Diagram ............................................................................................................................. 5
1.7 Outline of Functions ................................................................................................................... 6
CHAPTER 2 PIN FUNCTIONS ................................................................................................................. 8
2.1 Pin Function List ......................................................................................................................... 8
2.2 Description of Pin Functions ................................................................................................... 11
2.2.1 P00, P01 (port 0) .......................................................................................................................... 11
2.2.2 P10 to P17 (port 1) ....................................................................................................................... 11
2.2.3 P20 to P23 (port 2) ....................................................................................................................... 13
2.2.4 P30 to P33 (port 3) ....................................................................................................................... 13
2.2.5 P40 and P41 (port 4) .................................................................................................................... 14
2.2.6 P60 and P61 (port 6) .................................................................................................................... 14
2.2.7 P70 and P71 (port 7) .................................................................................................................... 14
2.2.8 P120 to P122 (port 12) ................................................................................................................. 15
2.2.9 VDD, VSS ........................................................................................................................................ 15
2.2.10 RESET.......................................................................................................................................... 15
2.2.11 REGC ........................................................................................................................................... 16
2.2.12 FLMD0 .......................................................................................................................................... 16
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................ 17
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 20
3.1 Memory Space ........................................................................................................................... 20
3.1.1 Internal program memory space ................................................................................................... 25
3.1.2 Internal data memory space ......................................................................................................... 27
3.1.3 Special function register (SFR) area ............................................................................................. 27
3.1.4 Data memory addressing.............................................................................................................. 27
3.2 Processor Registers ................................................................................................................. 31
3.2.1 Control registers ........................................................................................................................... 31
3.2.2 General-purpose registers ............................................................................................................ 34
3.2.3 Special function registers (SFRs) ................................................................................................. 36
3.3 Instruction Address Addressing ............................................................................................. 41
3.3.1 Relative addressing ...................................................................................................................... 41
3.3.2 Immediate addressing................................................................................................................... 42
3.3.3 Table indirect addressing.............................................................................................................. 43
3.3.4 Register addressing...................................................................................................................... 43
3.4 Operand Address Addressing ................................................................................................. 44
3.4.1 Implied addressing........................................................................................................................ 44
3.4.2 Register addressing...................................................................................................................... 45
3.4.3 Direct addressing.......................................................................................................................... 46
i
3.4.3 Direct addressing.......................................................................................................................... 46
3.4.4 Short direct addressing................................................................................................................. 47
3.4.5 Special function register (SFR) addressing................................................................................... 48
3.4.6 Register indirect addressing ......................................................................................................... 49
3.4.7 Based addressing ......................................................................................................................... 50
3.4.8 Based indexed addressing............................................................................................................ 51
3.4.9 Stack addressing .......................................................................................................................... 52
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 53
4.1 Port Functions ........................................................................................................................... 53
4.2 Port Configuration..................................................................................................................... 55
4.2.1 Port 0 ............................................................................................................................................ 56
4.2.2 Port 1 ............................................................................................................................................ 58
4.2.3 Port 2 ............................................................................................................................................ 64
4.2.4 Port 3 ............................................................................................................................................ 66
4.2.5 Port 4 ............................................................................................................................................ 68
4.2.6 Port 6 ............................................................................................................................................ 69
4.2.7 Port 7 ............................................................................................................................................ 70
4.2.8 Port 12 .......................................................................................................................................... 71
4.3 Registers Controlling Port Function ....................................................................................... 73
4.4 Port Function Operations......................................................................................................... 77
4.4.1 Writing to I/O port.......................................................................................................................... 77
4.4.2 Reading from I/O port ................................................................................................................... 77
4.4.3 Operations on I/O port .................................................................................................................. 77
4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function.......... 78
4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)................................... 80
CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 81
5.1 Functions of Clock Generator.................................................................................................. 81
5.2 Configuration of Clock Generator ........................................................................................... 82
5.3 Registers Controlling Clock Generator................................................................................... 84
5.4 System Clock Oscillator ........................................................................................................... 91
5.4.1 X1 oscillator .................................................................................................................................. 91
5.4.2 Internal high-speed oscillator ........................................................................................................ 93
5.4.3 Internal low-speed oscillator ......................................................................................................... 93
5.4.4 Prescaler....................................................................................................................................... 93
5.5 Clock Generator Operation ...................................................................................................... 94
5.6 Controlling Clock ...................................................................................................................... 97
5.6.1 Example of controlling high-speed system clock .......................................................................... 97
5.6.2 Example of controlling internal high-speed oscillation clock ....................................................... 100
5.6.3 Example of controlling internal low-speed oscillation clock......................................................... 103
5.6.4 Clocks supplied to CPU and peripheral hardware ...................................................................... 103
5.6.5 CPU clock status transition diagram ........................................................................................... 104
5.6.6 Condition before changing CPU clock and processing after changing CPU clock...................... 107
5.6.7 Time required for switchover of CPU clock and main system clock............................................ 108
5.6.8 Conditions before clock oscillation is stopped............................................................................. 109
5.6.9 Peripheral hardware and source clocks...................................................................................... 109
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ........................................................................... 110
ii
6.1 Functions of 16-Bit Timer/Event Counter 00 ........................................................................ 110
6.2 Configuration of 16-Bit Timer/Event Counter 00.................................................................. 111
6.3 Registers Controlling 16-Bit Timer/Event Counter 00 ......................................................... 117
6.4 Operation of 16-Bit Timer/Event Counter 00 ........................................................................ 125
6.4.1 Interval timer operation ............................................................................................................... 125
6.4.2 Square-wave output operation.................................................................................................... 128
6.4.3 External event counter operation ................................................................................................ 132
6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input ...................................... 136
6.4.5 Free-running timer operation ...................................................................................................... 152
6.4.6 PPG output operation ................................................................................................................. 162
6.4.7 One-shot pulse output operation................................................................................................. 166
6.4.8 Pulse width measurement operation........................................................................................... 171
6.5 Special Use of TM00................................................................................................................ 180
6.5.1 Rewriting CR010 during TM00 operation.................................................................................... 180
6.5.2 Setting LVS00 and LVR00 .......................................................................................................... 180
6.6 Cautions for 16-Bit Timer/Event Counter 00 ........................................................................ 182
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 187
7.1 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................ 187
7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 ..................................................... 187
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................ 190
7.4 Operations of 8-Bit Timer/Event Counters 50 and 51.......................................................... 195
7.4.1 Operation as interval timer.......................................................................................................... 195
7.4.2 Operation as external event counter........................................................................................... 197
7.4.3 Square-wave output operation.................................................................................................... 198
7.4.4 PWM output operation ................................................................................................................ 199
7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................ 203
CHAPTER 8 8-BIT TIMERS H0 AND H1........................................................................................... 204
8.1 Functions of 8-Bit Timers H0 and H1 .................................................................................... 204
8.2 Configuration of 8-Bit Timers H0 and H1.............................................................................. 204
8.3 Registers Controlling 8-Bit Timers H0 and H1 ..................................................................... 208
8.4 Operation of 8-Bit Timers H0 and H1 .................................................................................... 213
8.4.1 Operation as interval timer/square-wave output ......................................................................... 213
8.4.2 Operation as PWM output........................................................................................................... 216
8.4.3 Carrier generator operation (8-bit timer H1 only) ........................................................................ 222
CHAPTER 9 WATCH TIMER................................................................................................................ 229
9.1 Functions of Watch Timer ......................................................................................................229
9.2 Configuration of Watch Timer................................................................................................ 230
9.3 Register Controlling Watch Timer ......................................................................................... 231
9.4 Watch Timer Operations......................................................................................................... 232
9.4.1 Watch timer operation................................................................................................................. 232
9.4.2 Interval timer operation ............................................................................................................... 233
9.5 Cautions for Watch Timer ...................................................................................................... 233
CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 234
10.1 Functions of Watchdog Timer ............................................................................................... 234
iii
10.2 Configuration of Watchdog Timer ......................................................................................... 235
10.3 Register Controlling Watchdog Timer .................................................................................. 236
10.4 Operation of Watchdog Timer................................................................................................ 237
10.4.1 Controlling operation of watchdog timer...................................................................................... 237
10.4.2 Setting overflow time of watchdog timer ..................................................................................... 238
10.4.3 Setting window open period of watchdog timer........................................................................... 239
CHAPTER 11 A/D CONVERTER ......................................................................................................... 241
11.1 Function of A/D Converter ..................................................................................................... 241
11.2 Configuration of A/D Converter ............................................................................................. 242
11.3 Registers Used in A/D Converter........................................................................................... 244
11.4 A/D Converter Operations ...................................................................................................... 250
11.4.1 Basic operations of A/D converter .............................................................................................. 250
11.4.2 Input voltage and conversion results .......................................................................................... 251
11.4.3 A/D converter operation mode.................................................................................................... 253
11.5 How to Read A/D Converter Characteristics Table.............................................................. 255
11.6 Cautions for A/D Converter .................................................................................................... 258
CHAPTER 12 SERIAL INTERFACE UART0 ...................................................................................... 262
12.1 Functions of Serial Interface UART0..................................................................................... 262
12.2 Configuration of Serial Interface UART0 .............................................................................. 263
12.3 Registers Controlling Serial Interface UART0...................................................................... 266
12.4 Operation of Serial Interface UART0..................................................................................... 271
12.4.1 Operation stop mode .................................................................................................................. 271
12.4.2 Asynchronous serial interface (UART) mode.............................................................................. 272
12.4.3 Dedicated baud rate generator ................................................................................................... 278
12.4.4 Calculation of baud rate.............................................................................................................. 280
CHAPTER 13 SERIAL INTERFACE UART6 ...................................................................................... 284
13.1 Functions of Serial Interface UART6..................................................................................... 284
13.2 Configuration of Serial Interface UART6 .............................................................................. 289
13.3 Registers Controlling Serial Interface UART6...................................................................... 292
13.4 Operation of Serial Interface UART6..................................................................................... 302
13.4.1 Operation stop mode .................................................................................................................. 302
13.4.2 Asynchronous serial interface (UART) mode.............................................................................. 303
13.4.3 Dedicated baud rate generator ................................................................................................... 317
13.4.4 Calculation of baud rate.............................................................................................................. 318
CHAPTER 14 SERIAL INTERFACE CSI10 ........................................................................................ 324
14.1 Functions of Serial Interface CSI10....................................................................................... 324
14.2 Configuration of Serial Interface CSI10 ................................................................................ 324
14.3 Registers Controlling Serial Interface CSI10........................................................................ 326
14.4 Operation of Serial Interface CSI10 ....................................................................................... 330
14.4.1 Operation stop mode .................................................................................................................. 330
14.4.2 3-wire serial I/O mode................................................................................................................. 331
CHAPTER 15 SERIAL INTERFACE IIC0............................................................................................ 341
15.1 Functions of Serial Interface IIC0 .......................................................................................... 341
iv
15.2 Configuration of Serial Interface IIC0.................................................................................... 344
15.3 Registers to Control Serial Interface IIC0 ............................................................................. 347
15.4 I
15.5 I
2
C Bus Mode Functions .........................................................................................................360
15.4.1 Pin configuration ......................................................................................................................... 360
2
C Bus Definitions and Control Methods ............................................................................. 361
15.5.1 Start conditions ........................................................................................................................... 361
15.5.2 Addresses................................................................................................................................... 362
15.5.3 Transfer direction specification ................................................................................................... 362
15.5.4 Acknowledge (ACK).................................................................................................................... 363
15.5.5 Stop condition ............................................................................................................................. 364
15.5.6 Wait ............................................................................................................................................ 365
15.5.7 Canceling wait ............................................................................................................................ 367
15.5.8 Interrupt request (INTIIC0) generation timing and wait control ................................................... 368
15.5.9 Address match detection method ............................................................................................... 369
15.5.10 Error detection ............................................................................................................................ 369
15.5.11 Extension code ........................................................................................................................... 370
15.5.12 Arbitration ................................................................................................................................... 371
15.5.13 Wakeup function ......................................................................................................................... 373
15.5.14 Communication reservation ........................................................................................................ 373
15.5.15 Cautions...................................................................................................................................... 377
15.5.16 Communication operations ......................................................................................................... 378
15.5.17 Timing of I
2
C interrupt request (INTIIC0) occurrence .................................................................. 386
15.6 Timing Charts .......................................................................................................................... 407
CHAPTER 16 INTERRUPT FUNCTIONS............................................................................................. 414
16.1 Interrupt Function Types ........................................................................................................ 414
16.2 Interrupt Sources and Configuration .................................................................................... 414
16.3 Registers Controlling Interrupt Functions............................................................................ 419
16.4 Interrupt Servicing Operations .............................................................................................. 427
16.4.1 Maskable interrupt acknowledgment .......................................................................................... 427
16.4.2 Software interrupt request acknowledgment............................................................................... 429
16.4.3 Multiple interrupt servicing .......................................................................................................... 430
16.4.4 Interrupt request hold.................................................................................................................. 433
CHAPTER 17 STANDBY FUNCTION .................................................................................................. 434
17.1 Standby Function and Configuration.................................................................................... 434
17.1.1 Standby function ......................................................................................................................... 434
17.1.2 Registers controlling standby function ........................................................................................ 435
17.2 Standby Function Operation .................................................................................................. 437
17.2.1 HALT mode................................................................................................................................. 437
17.2.2 STOP mode................................................................................................................................ 440
CHAPTER 18 RESET FUNCTION........................................................................................................ 446
18.1 Register for Confirming Reset Source.................................................................................. 455
CHAPTER 19 POWER-ON-CLEAR CIRCUIT...................................................................................... 456
19.1 Functions of Power-on-Clear Circuit..................................................................................... 456
19.2 Configuration of Power-on-Clear Circuit .............................................................................. 457
v
19.3 Operation of Power-on-Clear Circuit..................................................................................... 457
19.4 Cautions for Power-on-Clear Circuit ..................................................................................... 460
CHAPTER 20 LOW-VOLTAGE DETECTOR ....................................................................................... 462
20.1 Functions of Low-Voltage Detector....................................................................................... 462
20.2 Configuration of Low-Voltage Detector ................................................................................ 462
20.3 Registers Controlling Low-Voltage Detector ....................................................................... 463
20.4 Operation of Low-Voltage Detector....................................................................................... 466
20.4.1 When used as reset .................................................................................................................... 467
20.4.2 When used as interrupt............................................................................................................... 472
20.5 Cautions for Low-Voltage Detector ....................................................................................... 477
CHAPTER 21 OPTION BYTE............................................................................................................... 480
21.1 Functions of Option Bytes ..................................................................................................... 480
21.2 Format of Option Byte ............................................................................................................481
CHAPTER 22 FLASH MEMORY .......................................................................................................... 483
22.1 Internal Memory Size Switching Register............................................................................. 483
22.2 Writing with Flash Memory Programmer.............................................................................. 484
22.3 Programming Environment.................................................................................................... 484
22.4 Communication Mode............................................................................................................. 485
22.5 Connection of Pins on Board................................................................................................. 487
22.5.1 FLMD0 pin .................................................................................................................................. 488
22.5.2 Serial interface pins .................................................................................................................... 488
22.5.3 RESET pin.................................................................................................................................. 489
22.5.4 Port pins...................................................................................................................................... 490
22.5.5 REGC pin.................................................................................................................................... 490
22.5.6 Other signal pins......................................................................................................................... 490
22.5.7 Power supply .............................................................................................................................. 490
22.6 Programming Method ............................................................................................................. 491
22.6.1 Controlling flash memory ............................................................................................................ 491
22.6.2 Flash memory programming mode ............................................................................................. 492
22.6.3 Selecting communication mode .................................................................................................. 493
22.6.4 Communication commands ........................................................................................................ 493
22.7 Security Settings..................................................................................................................... 495
CHAPTER 23 INSTRUCTION SET....................................................................................................... 497
23.1 Conventions Used in Operation List ..................................................................................... 498
23.1.1 Operand identifiers and specification methods ........................................................................... 498
23.1.2 Description of operation column ................................................................................................. 499
23.1.3 Description of flag operation column........................................................................................... 499
23.2 Operation List.......................................................................................................................... 500
23.3 Instructions Listed by Addressing Type............................................................................... 508
CHAPTER 24 ELECTRICAL SPECIFICATIONS (TARGET).............................................................. 512
CHAPTER 25 PACKAGE DRAWINGS ................................................................................................ 530
vi
CHAPTER 26 CAUTIONS FOR WAIT................................................................................................. 531
26.1 Cautions for Wait..................................................................................................................... 531
26.2 Peripheral Hardware That Generates Wait ........................................................................... 532
vii
R7F0C011B, R7F0C012B, R7F0C013B
RENESAS MCU
CHAPTER 1 OUTLINE
1.1 Features
Minimum instruction execution time: 0.2
General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
I/O ports, ROM, RAM capacities
μ
s (@ 10 MHz operation with high-speed system clock)
R01UH0408EJ0001
Rev.0.01
Sep 25, 2012
Item
Products
R7F0C011B2DFP 16 KB 768 bytes
R7F0C012B2DFP 24 KB 1 KB
R7F0C013B2DFP
27 (CMOS I/O: 25, N-ch open drain I/O: 2)
I/O ports
Program Memory
(Flash Memory)
32 KB 1 KB
Data Memory
(Internal High-Speed RAM)
On-chip single-power-supply flash memory
On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
On-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock)
Timer
• 16-bit timer/event counter … PPG output, capture input, external event counter input
• 8-bit timers H0, H1 … PWM output, operable with internal low-speed oscillation clock
• 8-bit timer/event counters 50, 51 … External event counter input
• Watch timer
• Watchdog timer … Operable with internal low-speed oscillation clock
Item
16-Bit Timer/Event Counter 8-Bit Timer Watch Timer Watchdog Timer
Products
R7F0C011B2DFP
R7F0C012B2DFP
R7F0C013B2DFP
1 channel
Timer H: 2 channels
Timer 5: 2 channels
1 channel 1 channel
Serial interface
• UART … 2-wire serial interface supporting asynchronous communication
• CSI … 3-wire serial interface supporting clocked communication
• IICA … 2-wire serial interface supporting clocked communication. Supporting multi-master and, in slave mode,
capable of releasing standby by address match
Products
R7F0C011B2DFP
R7F0C012B2DFP
R7F0C013B2DFP
Item
1 channel 1 channel 1 channel
UART6 CSI10/UART0 IIC
On-chip 10-bit resolution A/D converter (AVREF = 4.0 to 5.5 V): 4 channels
Power supply voltage: V
Operating ambient temperature: T
DD = 4.0 to 5.5 V
A = –40 to +85°C
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE
1.2 Applications
Household electrical appliances
• Air conditioners
1.3 Ordering Information
Pin Count Package ROM RAM Semiconductor Material Part Number
32-pin 32-pin plastic LQF (7 × 7)
16 KB 768 B R7F0C011B2DFP
24 KB 1 KB R7F0C012B2DFP
32 KB 1 KB
(External pin finish is Ni/Pd/Au plating)
Lead free product
R7F0C013B2DFP
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE
1.4 Pin Configuration (Top View)
• 32-pin plastic LQFP (fine pitch) (7 × 7)
P10/SCK00/TXD0
P11/SI10
P12/SO00
P13/TxD6
P14/RxD6
P15
P16/TOH1
P17/TI50/TO50
Exposed die pad
24 23 22 21 20 19 18 17
P23/ANI3
P22/ANI2
P21/ANI1
P20/ANI0
P01/TI010/TO00
P00/TI000
P120/INTP0/EXLVI
P41
25
26
27
28
29
30
31
32
1 2 3 4 5 6 7 8
16
15
14
13
12
11
10
9
P30
P31/INTP2
P32/INTP3
P70
P71
P33/TI51/TO51/INTP4
P61/SDA0
P60/SCL0
SS
DD
V
P40
FLMD0
RESET
P122/X2/EXCLK
P121/X1
V
REGC
Cautions 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
2. ANI0/P20 to ANI3/P23 are set in the analog input mode after release of reset.
Remark For pin identification, see 1.6 Pin Identification.
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE
1.5 Pin Identification
ANI0 to ANI3: Analog input RxD0, RxD6: Receive data
EXCLK: External clock input SCK10: Serial clock Input/output
EXLVI: External potential input SCL0: Serial clock Input/output
for Low-voltage detector SDA0: Serial data Input/output
FLMD0: Flash programming mode SI10: Serial data Input
INTP0 to INTP5: External interrupt input SO10: Serial data output
P00, P01: Port 0 TI000, TI010,
P10 to P17: Port 1 TI50, TI51: Timer input
P20 to P23: Port 2 TO00 : Timer output
P30 to P33: Port 3 TO50, TO51:
P40, P41: Port 4 TOH1:
P60, P61: Port 6 TxD0, TxD6: Transmit data
P70, P71: Port 7
P120 to P122: Port 12 V
DD: Power supply
V
SS: Ground
REGC: Regulator capacitance X1, X2: Crystal oscillator (main system clock)
RESET: Reset
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1.6 Block Diagram
TO00/TI010/P01
TI000/P00
RxD6/P14 (LINSEL)
16-bit timer/
event counter 00
8-bit timer
H0
Port 0
Port 1
Port 2
2
8
4
P00, P01
P10 to P17
P20 to P23
TOH1/P16
TI50/TO50/P17
TI51/TO51/P33
RxD0/P11
TxD0/P10
RxD6/P14
TxD6/P13
SI10/P11
SO10/P12
SCK10/P10
SDA0/P61
SCL0/P60
ANI0/P20 to
ANI3/P23
8-bit timer
Watchdog timer
8-bit timer/
event counter 50
8-bit timer/
event counter 51
Serial
interface UART0
Serial
interface UART6
Serial
interface
Serial
interface
4
H1
Internal
low-speed
oscillator
LINSEL
CSI10
IIC0
A/D converter
78K0
CPU
core
Internal
high-speed
RAM
Flash
memory
Port 3
Port 4
Port 6
Port 7
Port 12
Power-on clear/
low-voltage
indicator
Reset control
System
control
Internal
high-speed
oscillator
Voltage regulator
4
P30 to P33
2
P40, P41
2
P60, P61
2
P70, P71
3
P120 to P122
POC/LVI
control
RESET
X1/P121
X2/EXCLK/P122
REGC
EXLVI/P120
RxD6/P14 (LINSEL)
INTP0/P120
INTP2/P31 to
INTP4/P33
3
Interrupt
control
VSSFLMD0 V
DD
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1.7 Outline of Functions
Products
Item
Flash memory (KB) 16 24 32
High-speed RAM (KB) 0.75 1 1
Power supply voltage VDD = 4.0 to 5.5 V
Regulator Provided
Minimum instruction execution
time
High-speed system 10 MHz: VDD = 4.0 to 5.5 V
Internal high-speed
oscillation
Clock
Internal low-speed
oscillation
Total 27
Port
N-ch O.D. (6 V tolerance) 2
16 bits (TM0) 1 ch
8 bits (TM5) 2 ch
8 bits (TMH) 2 ch
Timer
Watch 1 ch
Watchdog (WDT)
3-wire CSI
Automatic transmit/receive
3-wire CSI
UART/3-wire CSI
UART supporting LIN-bus 1 ch
Serial interface
I2C bus 1 ch
10-bit A/D 4 ch
External 6
Internal 14
Interrupt
RESET pin Provided
POC 1.59 V ±0.15 V
Reset
LVI The detection level of the supply voltage is selectable.
WDT Provided
On-chip debug function Supported by other product (R7F0C999B2DFP)
Operating ambient temperature TA = −40 to +85 °C
Note
Note Select either of the functions of these alternate-function pins.
R7F0C011B2DFP R7F0C012B2DFP R7F0C013B2DFP
0.2
μ
s (10 MHz: VDD = 4.0 to 5.5 V)
8 MHz (TYP.): V
240 kHz (TYP.): V
DD = 4.0 to 5.5 V
DD = 4.0 to 5.5 V
1 ch
−
−
1 ch
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 1 OUTLINE
An outline of the timer is shown below.
16-Bit Timer/
Event Counter 00
TM00 TM50 TM51 TMH0 TMH1
Function
Interrupt source 2 1 1 1 1 1
Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel
External event
counter
PPG output 1 output
PWM output
Pulse width
measurement
Square-wave
output
Carrier generator
Timer output
Watchdog timer
1 channel 1 channel 1 channel
−
2 inputs
1 output 1 output 1 output
− − − −
− − − − −
− − − − − −
8-Bit Timer/
Event Counters
50 and 51
− − − − − −
1 output 1 output
− − − − − −
8-Bit Timers H0 and H1
− − − −
−
−
1 output
1 output
1 output
Notes 1. In the watch timer, the watch timer function and i nterval timer function can be used simultaneously.
2. TM51 and TMH1 can be used in combination as a carrier generator mode.
Watch Timer Watchdog
Note 1
− −
− −
Nore 2
− −
1 channel
Nore 1
Timer
−
−
1 channel
−
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
Pin I/O buffer power supplies include one V
shown below.
Table 2-1. Pin I/O Buffer Power Supplies (AVREF, VDD)
Power Supply Corresponding Pins
VDD All pins
DD system. The relationship between these power supplies and the pins is
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS
(1) Port functions
Function Name I/O Function After Reset Alternate Function
P00 TI000
P01
P10 SCK10/TxD0
P11 SI10/RxD0
P12 SO10
P13 TxD6
P14 RxD6
P15
P16 TOH1
P17
P20 to P23 I/O
P30
P31 INTP2
P32 INTP3
P33
P40, P41 I/O
P60 SCL0
P61
P70, P71 I/O
P120 INTP0/EXLVI
P121 X1
P122
I/O
I/O
I/O
I/O
I/O
Port 0.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
Port 2.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
Port 4.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
Port 6.
2-bit I/O port.
Output is N-ch open-drain output (6 V tolerance).
Input/output can be specified in 1-bit units.
Port 7.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
Port 12.
3-bit I/O port.
Input/output can be specified in 1-bit units.
Only for P120, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port
TI010/TO00
Input port
−
TI50/TO50
Analog input ANI0 to ANI3
Input port
INTP4/TI51/TO51
Input port
Input port
SDA0
Input port
Input port
X2/EXCLK
−
−
−
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS
(2) Non-port functions
Function Name I/O Function After Reset Alternate Function
ANI0 to ANI3 Input A/D converter analog input
EXLVI Input Potential input for external low-voltage detection Input port P120/INTP0
FLMD0
INTP0 P120/EXLVI
INTP2 P31
INTP3 P32
INTP4
REGC
RESET Input System reset input
RxD0 Serial data input to UART0 P11/SI10
RxD6
TxD0 Serial data output from UART0 P10/SCK10
TxD6
SCK10 I/O Clock input/output for CSI10 P10/TxD0
SI10 Input Serial data input to CSI10 P11/RxD0
SO10 Output Serial data output from CSI10
SCL0 Clock input/output for I2C P60
SDA0
TI000 Input
TI010 Input
TI50 External count clock input to 8-bit timer/event counter 50 P17/TO50
TI51
TO00 Output 16-bit timer/event counter 00 output Input port P01/TI010
TO50 8-bit timer/event counter 50 output P17/TI50
TO51
TOH0 8-bit timer H0 output P15
TOH1
X1
X2
EXCLK Input External clock input for main system clock Input port P122/X2
VDD
VSS
Input
Input
Output
I/O
Input
Output
Output
Flash memory programming mode setting
−
External interrupt request input for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be
specified
Connecting regulator output (2.5 V) stabilization capacitance
−
for internal operation.
Connect to V
Serial data input to UART6
Serial data output from UART6
Serial data I/O for I2C
External count clock input to 16-bit timer/event counter 00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
External count clock input to 8-bit timer/event counter 51
8-bit timer/event counter 51 output
8-bit timer H1 output
Connecting resonator for main system clock
−
−
Positive power supply and A/D converter reference voltage
−
input
Ground potential
−
SS via a capacitor (0.47 to 1
μ
F).
Analog
input
Input port
Input port
Input port
Input port
Input port
Input port P00
Input port P01/TO00
Input port
Input port
Input port
Input port P121
Input port P122/EXCLK
P20 to P23
− −
P33/TI51/TO51
− −
− −
P14
P13
P12
P61
P33/TO51/INTP4
P33/TI51/INTP4
P16
− −
− −
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00, P01 (port 0)
P00 and P01 function as an I/O port. These pins also function as timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 and P01 function as an I/O port. P00 and P01 can be set to input or output port in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 and P01 function as timer I/O.
(a) TI000
This is a pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a
capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.
(b) TI010
This is a pin for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit timer/event
counters 00 and 01.
(c) TO00
This is a timer output pin of 16-bit timer/event counter 00.
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an I/O port. These pins also function as pins for serial interface data I/O, clock I/O, and timer
I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS
(2) Control mode
P10 to P17 function as serial interface data I/O, clock I/O, and timer I/O.
(a) SI10
This is a serial data input pin of serial interface CSI10.
(b) SO10
This is a serial data output pin of serial interface CSI10.
(c) SCK10
This is a serial clock I/O pin of serial interface CSI10.
(d) RxD0
This is a serial data input pin of serial interface UART0.
(e) RxD6
This is a serial data input pin of serial interface UART6.
(f) TxD0
This is a serial data output pin of serial interface UART0.
(g) TxD6
This is a serial data output pin of serial interface UART6.
(h) TI50
This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
(i) TO50
This is a timer output pin of 8-it timer/event counter 50.
(j) TOH1
This is a timer output pin of 8-bit timer H1.
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2.2.3 P20 to P23 (port 2)
P20 to P23 function as an I/O port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P23 function as an I/O port. P20 to P23 can be set to input or output port in 1-bit units using port mode
register 2 (PM2).
(2) Control mode
P20 to P23 function as A/D converter analog input pins (ANI0 to ANI3). When using these pins as analog input pins,
see (5) ANI0/P20 to ANI3/P23 in 11.6 Cautions for A/D Converter.
Caution ANI0/P20 to ANI3/P23 are set in the analog input mode after release of reset.
2.2.4 P30 to P33 (port 3)
P30 to P33 function as an I/O port. These pins also function as pins for external interrupt request input and timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as an I/O port. P30 to P33 can be set to input or output port in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as external interrupt request input and timer I/O.
(a) INTP2 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin from 8-bit timer/event counter 51.
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2.2.5 P40 and P41 (port 4)
P40 and P41 function as an I/O port. P40 and P41 can be set to input or output port in 1-bit units using port mode
register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
2.2.6 P60 and P61 (port 6)
P60 and P61 function as an I/O port. These pins also function as pins for serial interface data I/O and clock I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P60 and P61 function as an I/O port. P60 and P61 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
Output of P60 and P61 is N-ch open-drain output (6 V tolerance).
(2) Control mode
P60 and P61 function as serial interface data I/O and clock I/O.
(a) SDA0
This is a serial data I/O pin for serial interface IIC0.
(b) SCL0
This is a serial clock I/O pin for serial interface IIC0.
2.2.7 P70 and P71 (port 7)
P70 and P71 function as an I/O port. P70 and P71 can be set to input or output port in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
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2.2.8 P120 to P122 (port 12)
P120 to P122 function as an I/O port. These pins also function as pins for external interrupt request input, potential
input for external low-voltage detection, connecting resonator for main system clock, and external clock input for main
system clock.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 to P122 function as an I/O port. P120 to P122 can be set to input or output port using port mode register 12
(PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12
(PU12).
(2) Control mode
P120 to P122 function as pins for external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, and external clock input for main system clock.
(a) INTP0
This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling edge, or
both rising and falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are the pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
2.2.9 V
2.2.10 RESET
DD, VSS
These are the power supply/ground pins.
(a) V
DD
V
DD is a positive power supply pin.
(b) V
SS
V
SS is a ground potential pin.
This is the active-low system reset input pin.
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS
2.2.11 REGC
This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this pin
to V
SS via a capacitor (0.47 to 1
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
2.2.12 FLMD0
This is a pin for setting flash memory programming mode.
Connect FLMD0 to V
SS in the normal operation mode.
In flash memory programming mode, connect this pin to the flash memory programmer.
μ
F).
REGC
SS
V
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R7F0C011B, R7F0C012B, R7F0C013B CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins.
See Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-3. Pin I/O Circuit Types (1/2)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/TI000
P01/TI010/TO00
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6 5-AQ
P15 5-AG
P16/TOH1
P17/TI50/TO50
ANI0/P20 to ANI3/P23
Note
5-AQ
5-AQ
5-AG
5-AQ
11-G
I/O
Note ANI0/P20 to ANI3/P23 are set in the analog input mode after release of reset.
Input: Independently connect to EV
Output: Leave open.
< Digital input setting and analog input setting>
Independently connect to AV
<Digital output setting>
Leave open.
REF or AVSS via a resistor.
DD or EVSS via a resistor.
R01UH0408EJ0001 Rev.0.01 17
Sep 25, 2012
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