Renesas R2J20605ANP Schematics
Preliminary
R2J20605ANP
Integrated Driver – MOS FET (DrMOS)
REJ03G1821-0300
Rev.3.00
Feb 26, 2010
Description
The R2J20605ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver
in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating
the need for an external SBD for this purpose.
Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the
package standard "integrated Driver – MOS FET (DrMOS)" proposed by Intel Corporation.
Features
Built-in power MOS FET suitable for Notebook, Desktop, Server application
Built-in driver circuit which matches the power MOS FET
Low-side MOS FET with built-in SBD for lower loss and reduced ringing
Built-in tri-state input function which can support a number of PWM controllers
VIN operating-voltage range: 27 V max
High-frequency operation (above 1 MHz) possible
Large average output current (Max. 40 A)
Achieve low power dissipation
Controllable driver: Remote on/off
Low-side MOS FET disabled function for DCM operation
Built-in thermal warning
Built-in bootstrapping switch
Small package: QFN56 (8 mm 8 mm 0.95 mm)
Terminal Pb-free/Halogen-free
Outline
Reg5V
DISBL#
LSDBL#
PWM
VINGHBOOTVCIN
MOS FET Driver
THWN CGND GL PGND
VSWH
56
43
114
15
Driver
PAD
42 29
QFN56 package 8 mm × 8 mm
High-side MOS
PAD
Low-side MOS PAD
28
(Bottom view)
REJ03G1821-0300 Rev.3.00 Feb 26, 2010
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R2J20605ANP Preliminary
Block Diagram
Driver Chip
THWN
DISBL#
LSDBL#
PWM
THWN
20 μA
CGND
150 k
Reg5V
Input Logic
(TTL Level)
(3 state in)
Reg5V
VCIN BOOT GH
UVL
Reg5V
Boot
SW
Reg5V
Supervisor
Level Shifter
25 k
Overlap
Protection.
& Logic
Reg5V
VIN
High Side
MOS FET
VSWH
Low Side
MOS FET
20 μA
PGND
GLCGND
Notes: 1. Truth table for the DISBL# pin. 2. Truth table for the LSDBL# pin.
DISBL# Input Driver Chip Status
"L" Shutdown (GL, GH = "L")
"Open" Shutdown (GL, GH = "L")
"H" Enable (GL, GH = "Active")
LSDBL# Input GL Status
"L" "L"
"Open" "Active"
"H" "Active"
3. Output signal from the UVL block 4. Output signal from the THWN block
VHVL
For active
VCIN
Thermal Warning
Logic Level
"H"
"L"
Normal
operating
Thermal
Warning
T
(°C)
IC
TwarnHTwarnL
UVL output
Logic Level
"H"
For shutdown
"L"
REJ03G1821-0300 Rev.3.00 Feb 26, 2010
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R2J20605ANP Preliminary
Pin Arrangement
VIN
VIN
VSWH
PGND
PGND
VIN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
VIN
VSWH
GH
PGND
BOOT
CGND
VCIN
CGNDVIN
PGND
(Top view)
LSDBL#
NC
VSWH
CGND
114 13 12 11 10 9 8 7 6 5 4 3 2
4229 30 31 32 33 34 35 36 37 38 39 40 41
VSWH
56
PWM
55
DISBL#
54
Reg5V
53
THWN
52
GL
51
CGND
50
VSWH
49
48
47
46
45
44
43
VSWH
Note: All die-pads (three pads in total) should be soldered to PCB.
Pin Description
Pin Name Pin No. Description Remarks
CGND 1, 6, 51, Pad Control signal ground Should be connected to PGND externally
LSDBL# 2 Low-side gate disable When asserted "L" signal, Low-side gate disable
NC 3, 8 No connect
VCIN 4 Control input voltage Driver Vcc input
BOOT 5 Bootstrap voltage pin To be supplied +5 V through internal BOOT SW
GH 7 High-side gate signal Pin for Monitor
VIN 9 to 20, Pad Input voltage
VSWH 21, 40 to 50, Pad Phase output/Switch output
PGND 22 to 39 Power ground
GL 52 Low-side gate signal Pin for Monitor
THWN 53 Thermal warning
Reg5V 54 +5 V logic power supply output
DISBL# 55 Signal disable Disabled when DISBL# is "L"
PWM 56 PWM drive logic input 5 V logic input
REJ03G1821-0300 Rev.3.00 Feb 26, 2010
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R2J20605ANP Preliminary
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Rating Units Note
Pt(25) 25 Power dissipation
Pt(110) 8
Average output current Iout 40 A
VIN(DC) –0.3 to +27 2 Input voltage
VIN(AC) 30
VSWH(DC) 27 2 Switch node voltage
VSWH(AC) 30
VBOOT(DC) 32 2 BOOT voltage
VBOOT(AC) 36
Supply voltage VCIN –0.3 to +27 V 2
PWM voltage Vpwm
Other I/O voltage
Reg5V voltage Vreg5V –0.3 to +6 V 7
Reg5V current Ireg5V –20 to +0.1 mA 3
THWN current Ithwn 0 to 1.0 mA 3
Operating junction temperature Tj-opr –40 to +150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C.
2. Rated voltages are relative to voltages on the CGND and PGND pins.
3. For rated current, (+) indicates inflow to the chip and (–) indicates outflow.
4. This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode).
5. This rating is when UVL (Under Voltage Lock out) is effective (lock out mode).
6. The specification values indicated "AC" are limited within 100 ns.
7. This rating is when the external power-source is applied to Reg5V pin.
8. Reg5V + 0.3 V < 6 V
Vdisble, Vlsdbl,
Vthwn
–0.3 to +5.5 @UVL OFF
–0.3 to +0.3 @UVL ON
–0.3 to Reg5V + 0.3
–0.3 to VCIN + 0.3 V 2
W 1
V
2, 4, 6
V
2, 4, 6
V
2, 4, 6
V
2, 4
2, 5
2, 7, 8
Safe Operating Area
50
45
40
35
30
25
20
VOUT = 1.3 V
VIN = 12 V
15
VCIN = Reg5V = 5 V
10
L = 0.45 μH
5
Average Output Current (A)
fsw = 600 kHz
0
0 25 50 75 100 125 150 175
PCB Temperature (°C)
REJ03G1821-0300 Rev.3.00 Feb 26, 2010
Page 4 of 16
R2J20605ANP Preliminary
Recommended Operating Condition
Item Symbol Rating Units Note
Input voltage VIN 4.5 to 22 V
Supply voltage VCIN
4.5 to 5.5
V
or
When the usage of VCIN = 4.5 V to 5.5 V,
VCIN should be connected to Reg5V
(Refer to "Pin Connection")
8 to 22
Electrical Characteristics
(Ta = 25C, VCIN = 12 V, VSWH = 0 V, unless otherwise specified)
Item Symbol Min Typ Max Units Test Conditions
Supply
PWM
input
5 V
regulator
DISBL#
input
LSDBL#
input
Thermal
warning
Note: 1. Reference values for design. Not 100% tested in production.
VCIN start threshold VH 7.0 7.4 7.8 V
VCIN shutdown threshold VL 6.6 7.0 7.4 V
UVLO hysteresis dUVL — 0.4 — V VH – VL
VCIN operating current I
— 52 — mA
CIN
f
PWM
= 1 MHz,
Ton_pwm = 120 ns
VCIN disable current I
— — 2.5 mA
CIN-DISBL
DISBL# = 0 V, PWM = 0 V,
LSDBL# = Open
PWM rising threshold V
PWM falling threshold V
PWM input resistance R
Tri-state shutdown window V
Shutdown hold-off time t
3.0 3.4 3.8 V
H-PWM
0.9 1.2 1.5 V
L-PWM
10 20 40 k PWM = 1 V
IN-PWM
V
IN-SD
*1 — 100 — ns
HOLD-OFF
L-PWM
— V
H-PWM
V
Output voltage Vreg 4.95 5.2 5.45 V
Line regulation Vreg-line –10 0 10 mV VCIN = 12 V to 16 V
Load regulation Vreg-load –10 0 10 mV Ireg = 0 to 10 mA
Disable threshold V
Enable threshold V
Input current I
Low-side activation threshold V
Low-side disable threshold V
Input current I
Warning temperature T
Temperature hysteresis T
THWN on resistance R
THWN leakage current I
0.9 1.2 1.5 V
DISBL
1.9 2.4 2.9 V
ENBL
10 20 40 A DISBL# = 1 V
DISBL
1.9 2.4 2.9 V
LSDBLH
0.9 1.2 1.5 V
LSDBLL
–56 –28 –14 A LSDBL# = 1 V
LSDBL
*1 95 115 135 °C Driver IC temperature
THWN
*1 — 15 — °C
HYS
*1 0.2 0.5 1.0 k THWN = 0.2 V
THWN
— 0.001 1.0 A THWN = 5 V
LEAK
REJ03G1821-0300 Rev.3.00 Feb 26, 2010
Page 5 of 16
R2J20605ANP Preliminary
Typical Application
(1) Desktop/Server Application
+12 V
+5 V
PWM
Control
Circuit
PWM1
PWM2
PWM3
PWM4
VCIN THWN
DISBL#
Reg5V
R2J20605ANP
PWM
CGND GL
VCIN THWN
DISBL#
Reg5V
LSDBL#
GH
R2J20605ANP
PWM
CGND GL
LSDBL#
GH
BOOT
VIN
VSWH
PGND
BOOT
VIN
VSWH
PGND
+1.3 V
VCIN THWN
DISBL#
Reg5V
R2J20605ANP
PWM
LSDBL#
CGND GL
VCIN THWN
DISBL#
Reg5V
GH
R2J20605ANP
PWM
LSDBL#
CGND GL
GH
BOOT
VSWH
PGND
BOOT
VSWH
PGND
VIN
Power GND Signal GND
VIN
REJ03G1821-0300 Rev.3.00 Feb 26, 2010
Page 6 of 16
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