Renesas MIPI D-PHY for TSMC 40nm LP Datasheet

MIPI D-PHY Transmitter/Receiver
for TSMC 40nm LP

Renesas Electronics Corporation

www.renesas.com

MIPI D-PHY Datasheet

*Before purchasing or using any Renesas Electronics products listed herein, please refer to the latest product manual and/or data sheet in advance.

Overview

The Renesas MIPI D-PHY Transmitter/Receiver is useful 2 Data Channel transmitter/receiver hard

macro for DSI/CSI-2 of TSMC 40nm LP process.

Key Features

⚫ Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of

following interface .

- MIPI alliance Specification for D-PHY Version 2.1 15 December 2016.

- MIPI alliance Specification for Display Serial Interface (DSI) Version 1.3.1 Aug 2015.

- MIPI alliance Specification for Camera Serial Interface 2 (CSI-2) Version 2.0 7 Dec 2016.

⚫ Technology is TSMC 40nm LP 1p6M (4x1z) .
⚫ Supply voltage can be applied 1.1V for core voltage, 1.8V for IO voltage.
⚫ Maximum data rate of each channel is 0.72Gbps at High-speed mode.

Block Diagram

MIPI D-PHY Transmitter/Receiver

Lane Control

and

Interface Logic

DATA0_P

DATA0_N

CSI-2

Logic

PPI

LP-CD

DATA1_P

DATA1_N

CLK_P
CLK_N

DSI

Logic

PLL

R06PM0073EJ0100

Rev.1.00

2019.10.28

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*These IPs are contract design IP. Please contact for detail.