Renesas 16-bit single-chip microcomputer, M16C, M6NN, M6NL User Manual

REJ09B0126-0102

M16C/6N Group

(M16C/6NL, M16C/6NN)

Hardware Manual

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

M16C FAMILY / M16C/60 SERIES

Before using this material, please visit our website to verify that this is the most updated document available.

Rev. 1.02 Revision date: Jul. 01, 2005

www.renesas.com

Keep safety first in your circuit designs!

•

Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.

• Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com).

• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

• Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

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• Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

How to Use This Manual

1. Introduction

This hardware manual provides detailed information on the M16C/6N Group (M16C/6NL, M16C/6NN) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.

2. Register Diagram

The symbols, and descriptions, used for bit function in each register are shown below.

XXX Register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

XXX

(b2)

(b4-b3)

Symbol

XXX

Bit

Bit Name

XXX Bit

Nothing is assigned. When write, set to "0", When read, its content is indeterminate.

Reserved Bit Set to "0"

Address

XXX

Function

b1b0

0 0: XXX 0 1: XXX 1 0: Do not set a value 1 1: XXX

After Reset

00h

XXX5

XXX

XXX Bit

Function varies depending on mode of operation

0: XXX 1: XXX

Blank:Set to “0” or “1” according to the application 0 : Set to “0” 1 : Set to “1” X : Nothing is assigned

RW : Read and write RO : Read only WO: Write only – : Nothing is assigned

• Reserved bit Reserved bit. Set to specified value.

• Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to “0” when writing to this bit.

• Do not set to this value The operation is not guaranteed when a value is set.

• Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode.

Follow the text in each manual for binary and hexadecimal notations.

3. M16C Family Documents

The following documents were prepared for the M16C family

Document Contents

Short Sheet Hardware overview

Data Sheet Hardware overview and electrical characteristics

Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral

specifications, electrical characteristics, timing charts)

Software Manual Detailed description of assembly instructions and microcomputer

performance of each instruction

Application Note • Application examples of peripheral functions

• Sample programs

• Introduction to the basic functions in the M16C family

• Programming method with Assembly and C languages

RENESAS TECHNICAL UPDATE

Preliminary report about the specification of a product, a document, etc.

NOTE:

1. Before using this material , please visit our website to verify that this is the most updated document

available.

(1)

SFR Page Reference ............................................................................................................ B-1

1. Overview ............................................................................................................................... 1

1.1 Applications ..................................................................................................................................................1

1.2 Performance Outline ....................................................................................................................................2

1.3 Block Diagram .............................................................................................................................................. 4

1.4 Product List ..................................................................................................................................................5

1.5 Pin Configuration .........................................................................................................................................6

1.6 Pin Description ............................................................................................................................................. 8

2. Central Processing Unit (CPU) ........................................................................................... 10

2.1 Data Registers (R0, R1, R2, and R3) ........................................................................................................ 10

2.2 Address Registers (A0 and A1) .................................................................................................................. 10

2.3 Frame Base Register (FB) ......................................................................................................................... 11

2.4 Interrupt Table Register (INTB) .................................................................................................................. 11

2.5 Program Counter (PC) ............................................................................................................................... 11

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ........................................................................... 11

2.7 Static Base Register (SB) .......................................................................................................................... 11

2.8 Flag Register (FLG) ................................................................................................................................... 11

2.8.1 Carry Flag (C Flag) ............................................................................................................................ 11

2.8.2 Debug Flag (D Flag) .......................................................................................................................... 11

2.8.3 Zero Flag (Z Flag) .............................................................................................................................. 11

2.8.4 Sign Flag (S Flag) .............................................................................................................................. 11

2.8.5 Register Bank Select Flag (B Flag).................................................................................................... 11

2.8.6 Overflow Flag (O Flag)....................................................................................................................... 11

2.8.7 Interrupt Enable Flag (I Flag) ............................................................................................................. 11

2.8.8 Stack Pointer Select Flag (U Flag)..................................................................................................... 11

2.8.9 Processor Interrupt Priority Level (IPL) .............................................................................................. 11

2.8.10 Reserved Area ................................................................................................................................. 11

3. Memory ............................................................................................................................... 12

4. Special Function Register (SFR)......................................................................................... 13

5. Reset ................................................................................................................................... 25

5.1 Hardware Reset .........................................................................................................................................25

5.1.1 Reset on a Stable Supply Voltage ..................................................................................................... 25

5.1.2 Power-on Reset ................................................................................................................................. 25

5.2 Software Reset ..........................................................................................................................................25

5.3 Watchdog Timer Reset ............................................................................................................................... 25

5.4 Oscillation Stop Detection Reset ............................................................................................................... 25

6. Processor Mode ..................................................................................................................28

7. Clock Generating Circuit .....................................................................................................31

7.1 Types of Clock Generating Circuit ............................................................................................................. 31

7.1.1 Main Clock ......................................................................................................................................... 39

7.1.2 Sub Clock........................................................................................................................................... 40

7.1.3 On-chip Oscillator Clock .................................................................................................................... 41

7.1.4 PLL Clock ........................................................................................................................................... 41

A-1

7.2 CPU Clock and Peripheral Function Clock ................................................................................................ 43

7.2.1 CPU Clock and BCLK ........................................................................................................................43

7.2.2 Peripheral Function Clock .................................................................................................................. 43

7.3 Clock Output Function ............................................................................................................................... 43

7.4 Power Control ............................................................................................................................................ 44

7.4.1 Normal Operation Mode..................................................................................................................... 44

7.4.2 Wait Mode .......................................................................................................................................... 46

7.4.3 Stop Mode.......................................................................................................................................... 48

7.5 Oscillation Stop and Re-oscillation Detection Function ............................................................................. 53

7.5.1 Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset) .................................................... 53

7.5.2 Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt) ........................ 53

7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function .................................................. 54

8. Protection ............................................................................................................................55

9. Interrupt ............................................................................................................................... 56

9.1 Type of Interrupts ....................................................................................................................................... 56

9.2 Software Interrupts ..................................................................................................................................... 57

9.2.1 Undefined Instruction Interrupt........................................................................................................... 57

9.2.2 Overflow Interrupt .............................................................................................................................. 57

9.2.3 BRK Interrupt ..................................................................................................................................... 57

9.2.4 INT Instruction Interrupt ..................................................................................................................... 57

9.3 Hardware Interrupts ................................................................................................................................... 58

9.3.1 Special Interrupts ...............................................................................................................................58

9.3.2 Peripheral Function Interrupts............................................................................................................ 58

9.4 Interrupts and Interrupt Vector ...................................................................................................................59

9.4.1 Fixed Vector Tables ............................................................................................................................ 59

9.4.2 Relocatable Vector Tables .................................................................................................................59

9.5 Interrupt Control .........................................................................................................................................61

9.5.1 I Flag ..................................................................................................................................................63

9.5.2 IR Bit .................................................................................................................................................. 63

9.5.3 ILVL2 to ILVL0 Bits and IPL ............................................................................................................... 63

9.5.4 Interrupt Sequence ............................................................................................................................ 64

9.5.5 Interrupt Response Time.................................................................................................................... 65

9.5.6 Variation of IPL when Interrupt Request is Accepted ......................................................................... 65

9.5.7 Saving Registers ................................................................................................................................ 66

9.5.8 Returning from an Interrupt Routine .................................................................................................. 67

9.5.9 Interrupt Priority ................................................................................................................................. 67

9.5.10 Interrupt Priority Resolution Circuit .................................................................................................. 67

______

9.6 INT Interrupt ...............................................................................................................................................69

______

9.7 NMI Interrupt ..............................................................................................................................................73

9.8 Key Input Interrupt .....................................................................................................................................73

9.9 CAN0 Wake-up Interrupt ............................................................................................................................ 73

9.10 Address Match Interrupt ........................................................................................................................... 74

10. Watchdog Timer ................................................................................................................ 76

10.1 Count Source Protective Mode ................................................................................................................77

A-2

11. DMAC ................................................................................................................................ 78

11.1 Transfer Cycle .......................................................................................................................................... 83

11.1.1 Effect of Source and Destination Addresses .................................................................................... 83

11.1.2 Effect of Software Wait ..................................................................................................................... 83

11.2 DMA Transfer Cycles ................................................................................................................................ 85

11.3 DMA Enable ............................................................................................................................................. 86

11.4 DMA Request ...........................................................................................................................................86

11.5 Channel Priority and DMA Transfer Timing ..............................................................................................87

12. Timers ............................................................................................................................... 88

12.1 Timer A .....................................................................................................................................................90

12.1.1 Timer Mode ......................................................................................................................................94

12.1.2 Event Counter Mode ........................................................................................................................95

12.1.3 One-shot Timer Mode ....................................................................................................................100

12.1.4 Pulse Width Modulation (PWM) Mode ...........................................................................................102

12.2 Timer B................................................................................................................................................... 105

12.2.1 Timer Mode ....................................................................................................................................108

12.2.2 Event Counter Mode ......................................................................................................................109

12.2.3 Pulse Period and Pulse Width Measurement Mode ...................................................................... 110

13. Three-Phase Motor Control Timer Function .................................................................... 113

14. Serial I/O ......................................................................................................................... 124

14.1 UARTi.....................................................................................................................................................124

14.1.1 Clock Synchronous Serial I/O Mode ..............................................................................................134

14.1.2 Clock Asynchronous Serial I/O (UART) Mode ...............................................................................142

14.1.3 Special Mode 1 (I2C Mode) ............................................................................................................150

14.1.4 Special Mode 2 .............................................................................................................................. 159

14.1.5 Special Mode 3 (IE Mode) ............................................................................................................. 164

14.1.6 Special Mode 4 (SIM Mode) (UART2) ........................................................................................... 166

14.2 SI/Oi .......................................................................................................................................................171

14.2.1 SI/Oi Operation Timing................................................................................................................... 175

14.2.2 CLK Polarity Selection ................................................................................................................... 175

14.2.3 Functions for Setting an SOUTi Initial Value .................................................................................. 176

15. A/D Converter ..................................................................................................................177

15.1 Mode Description ...................................................................................................................................181

15.1.1 One-shot Mode .............................................................................................................................. 181

15.1.2 Repeat Mode ................................................................................................................................. 183

15.1.3 Single Sweep Mode .......................................................................................................................185

15.1.4 Repeat Sweep Mode 0 .................................................................................................................. 187

15.1.5 Repeat Sweep Mode 1 .................................................................................................................. 189

15.2 Function ................................................................................................................................................. 191

15.2.1 Resolution Select Function ............................................................................................................ 191

15.2.2 Sample and Hold ........................................................................................................................... 191

15.2.3 Extended Analog Input Pins........................................................................................................... 191

15.2.4 External Operation Amplifier (Op-Amp) Connection Mode ............................................................191

15.2.5 Current Consumption Reducing Function ...................................................................................... 192

15.2.6 Output Impedance of Sensor under A/D Conversion..................................................................... 192

16. D/A Converter.................................................................................................................. 194

17. CRC Calculation.............................................................................................................. 196

A-3

18. CAN Module .................................................................................................................... 198

18.1 CAN Module-Related Registers ............................................................................................................. 199

18.1.1 CAN Message Box......................................................................................................................... 199

18.1.2 Acceptance Mask Registers........................................................................................................... 199

18.1.3 CAN SFR Registers .......................................................................................................................199

18.2 CAN0 Message Box ............................................................................................................................... 200

18.3 Acceptance Mask Registers...................................................................................................................202

18.4 CAN SFR Registers ...............................................................................................................................203

18.5 Operational Modes ................................................................................................................................. 210

18.5.1 CAN Reset/Initialization Mode ....................................................................................................... 210

18.5.2 CAN Operation Mode..................................................................................................................... 211

18.5.3 CAN Sleep Mode ........................................................................................................................... 211

18.5.4 CAN Interface Sleep Mode ............................................................................................................ 211

18.5.5 Bus Off State.................................................................................................................................. 212

18.6 Configuration CAN Module System Clock ............................................................................................. 213

18.7 Bit Timing Configuration ......................................................................................................................... 213

18.8 Bit-rate ................................................................................................................................................... 214

18.9 Acceptance Filtering Function and Masking Function............................................................................215

18.10 Acceptance Filter Support Unit (ASU)..................................................................................................216

18.11 Basic CAN Mode ..................................................................................................................................217

18.12 Return from Bus off Function ...............................................................................................................218

18.13 Time Stamp Counter and Time Stamp Function ..................................................................................218

18.14 Listen-Only Mode ................................................................................................................................. 218

18.15 Reception and Transmission................................................................................................................219

18.15.1 Reception ..................................................................................................................................... 220

18.15.2 Transmission ................................................................................................................................ 221

18.16 CAN Interrupt .......................................................................................................................................222

19. Programmable I/O Ports ................................................................................................. 223

19.1 PDi Register ........................................................................................................................................... 224

19.2 Pi Register, PC14 Register ....................................................................................................................224

19.3 PURj Register ........................................................................................................................................ 224

19.4 PCR Register .........................................................................................................................................224

20. Flash Memory Version .................................................................................................... 235

20.1 Memory Map ..........................................................................................................................................236

20.1.1 Boot Mode...................................................................................................................................... 237

20.2 Functions to Prevent Flash Memory from Rewriting .............................................................................. 237

20.2.1 ROM Code Protect Function .......................................................................................................... 237

20.2.2 ID Code Check Function ................................................................................................................ 237

20.3 CPU Rewrite Mode ................................................................................................................................ 239

20.3.1 EW0 Mode ..................................................................................................................................... 240

20.3.2 EW1 Mode ..................................................................................................................................... 240

20.3.3 FMR0, FMR1 Registers ................................................................................................................. 241

20.3.4 Precautions on CPU Rewrite Mode ............................................................................................... 245

20.3.5 Software Commands ..................................................................................................................... 247

20.3.6 Data Protect Function .................................................................................................................... 252

20.3.7 Status Register (SRD Register) .....................................................................................................252

20.3.8 Full Status Check ........................................................................................................................... 254

A-4

20.4 Standard Serial I/O Mode ...................................................................................................................... 256

20.4.1 ID Code Check Function ................................................................................................................ 256

20.4.2 Example of Circuit Application in Standard Serial I/O Mode .......................................................... 260

20.5 Parallel I/O Mode ................................................................................................................................... 261

20.5.1 User ROM and Boot ROM Areas ................................................................................................... 261

20.5.2 ROM Code Protect Function .......................................................................................................... 261

20.6 CAN I/O Mode ........................................................................................................................................ 262

20.6.1 ID Code Check Function ................................................................................................................ 262

20.6.2 Example of Circuit Application in CAN I/O Mode ...........................................................................265

21. Electrical Characteristics ................................................................................................. 266

22. Usage Precaution............................................................................................................ 276

22.1 SFR ........................................................................................................................................................ 276

22.2 External Clock ........................................................................................................................................ 277

22.3 PLL Frequency Synthesizer ...................................................................................................................278

22.4 Power Control ........................................................................................................................................ 279

22.5 Oscillation Stop, Re-oscillation Detection Function ............................................................................... 281

22.6 Protection ............................................................................................................................................... 282

22.7 Interrupt .................................................................................................................................................. 283

22.7.1 Reading Address 00000h............................................................................................................... 283

22.7.2 Setting SP ......................................................................................................................................283

_______

22.7.3 NMI Interrupt ..................................................................................................................................283

22.7.4 Changing Interrupt Generate Factor ..............................................................................................284

22.7.5 INT Interrupt ................................................................................................................................... 284

22.7.6 Rewrite Interrupt Control Register ................................................................................................. 285

22.7.7 Watchdog Timer Interrupt .............................................................................................................. 285

22.8 DMAC .................................................................................................................................................... 286

22.8.1 Write to DMAE Bit in DMiCON Register ........................................................................................ 286

22.9 Timers .................................................................................................................................................... 287

22.9.1 Timer A........................................................................................................................................... 287

22.9.2 Timer B........................................................................................................................................... 291

22.10 Thee-Phase Motor Control Timer Function .......................................................................................... 293

22.11 Serial I/O ..............................................................................................................................................294

22.11.1 Clock Synchronous Serial I/O Mode ............................................................................................ 294

22.11.2 Special Modes .............................................................................................................................. 295

22.11.3 SI/Oi ............................................................................................................................................. 296

22.12 A/D Converter ...................................................................................................................................... 297

22.13 CAN Module ......................................................................................................................................... 299

22.13.1 Reading C0STR Register ............................................................................................................ 299

22.13.2 Performing CAN Configuration .................................................................................................... 301

22.13.3 Suggestions to Reduce Power Consumption .............................................................................. 302

22.13.4 CAN Transceiver in Boot Mode.................................................................................................... 303

22.14 Programmable I/O Ports ...................................................................................................................... 304

22.15 Dedicated Input Pin .............................................................................................................................. 305

22.16 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers ..... 306

22.17 Mask ROM Version ............................................................................................................................. 307

_____

A-5

22.18 Flash Memory Version .........................................................................................................................308

22.18.1 Functions to Prevent Flash Memory from Rewriting ....................................................................308

22.18.2 Stop Mode.................................................................................................................................... 308

22.18.3 Wait Mode .................................................................................................................................... 308

22.18.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode ................. 308

22.18.5 Writing Command and Data......................................................................................................... 308

22.18.6 Program Command...................................................................................................................... 308

22.18.7 Lock Bit Program Command ........................................................................................................ 308

22.18.8 Operation Speed .......................................................................................................................... 309

22.18.9 Prohibited Instructions ................................................................................................................. 309

22.18.10 Interrupt...................................................................................................................................... 309

22.18.11 How to Access............................................................................................................................ 309

22.18.12 Rewriting in User ROM Area...................................................................................................... 309

22.18.13 DMA Transfer .............................................................................................................................309

22.19 Flash Memory Programming Using Boot Program .............................................................................. 310

22.19.1 Programming Using Serial I/O Mode ........................................................................................... 310

22.19.2 Programming Using CAN I/O Mode ............................................................................................. 310

22.20 Noise .................................................................................................................................................... 311

Appendix 1. Package Dimensions ........................................................................................ 312

Register Index .......................................................................................................................313

Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free

of error. Specifications in this manual may be changed for functional or performance improvements.

Please make sure your manual is the latest edition.

A-6

SFR Page Reference

C01WKIC C0RECIC C0TRMIC INT3IC TB5IC S5IC TB4IC U1BCNIC TB3IC U0BCNIC S4IC INT5IC S3IC INT4IC U2BCNIC DM0IC DM1IC C01ERRIC ADIC KUPIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC INT7IC TA3IC INT6IC TA4IC TB0IC S6IC TB1IC INT8IC TB2IC INT0IC INT1IC INT2IC

Address Register Symbol Page

0040h 0041h 0042h 0043h 0044h

0045h

0046h

0047h

0048h

0049h

004Ah 004Bh 004Ch 004Dh

004Eh

004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh

61 61 61 62 61 61 61 61 61 61 62 62 62 62 61 61 61 61 61 61 61 61 61 61 61 61 61 61 62 62 62 62 61 61 61 62 62 61 62 62 62

200 201

CAN0 Wake-up Interrupt Control Register CAN0 Successful Reception Interrupt Control Register CAN0 Successful Transmission Interrupt Control Register INT3 Interrupt Control Register Timer B5 Interrupt Control Register SI/O5 Interrupt Control Register Timer B4 Interrupt Control Register UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register UART0 Bus Collision Detection Interrupt Control Register SI/O4 Interrupt Control Register INT5 Interrupt Control Register SI/O3 Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register CAN0 Error Interrupt Control Register A/D Conversion Interrupt Control Register Key Input Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register INT7 Interrupt Control Register Timer A3 Interrupt Control Register INT6 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register SI/O6 Interrupt Control Register Timer B1 Interrupt Control Register INT8 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register

CAN0 Message Box 0: Identifier / DLC

CAN0 Message Box 0: Data Field

CAN0 Message Box 0: Time Stamp

CAN0 Message Box 1: Identifier / DLC

CAN0 Message Box 1: Data Field

CAN0 Message Box 1: Time Stamp

Address Register Symbol Page

0000h 0001h 0002h 0003h

Processor Mode Register 0

0004h

Processor Mode Register 1

0005h

System Clock Control Register 0

0006h 0007h

The blank areas are reserved.

System Clock Control Register 1 0008h 0009h

Address Match Interrupt Enable Register 000Ah

Protect Register 000Bh 000Ch

Oscillation Stop Detection Register 000Dh 000Eh

Watchdog Timer Start Register 000Fh

Watchdog Timer Control Register 0010h 0011h

Address Match Interrupt Register 0 0012h 0013h 0014h 0015h

Address Match Interrupt Register 1 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch

PLL Control Register 0 001Dh 001Eh

Processor Mode Register 2 001Fh 0020h 0021h

DMA0 Source Pointer 0022h 0023h 0024h 0025h

DMA0 Destination Pointer 0026h 0027h 0028h

DMA0 Transfer Counter 0029h

002Ah 002Bh 002Ch

DMA0 Control Register 002Dh 002Eh 002Fh 0030h 0031h

DMA1 Source Pointer 0032h 0033h 0034h 0035h

DMA1 Destination Pointer 0036h 0037h 0038h

DMA1 Transfer Counter 0039h

003Ah 003Bh 003Ch

DMA1 Control Register 003Dh 003Eh 003Fh

PM0 PM1 CM0 CM1

AIER PRCR

CM2

WDTS WDC

RMAD0

RMAD1

PLC0

PM2

SAR0

DAR0

TCR0

DM0CON

SAR1

DAR1

TCR1

DM1CON

28 29 33 34

75 55

77 77

B-1

Address Register Symbol Page

00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh

200 201

CAN0 Message Box 6: Identifier / DLC

CAN0 Message Box 6: Data Field

CAN0 Message Box 6: Time Stamp

CAN0 Message Box 7: Identifier / DLC

CAN0 Message Box 7: Data Field

CAN0 Message Box 7: Time Stamp

CAN0 Message Box 8: Identifier / DLC

CAN0 Message Box 8: Data Field

CAN0 Message Box 8: Time Stamp

CAN0 Message Box 9: Identifier / DLC

CAN0 Message Box 9: Data Field

CAN0 Message Box 9: Time Stamp

0080h 0081h 0082h

CAN0 Message Box 2: Identifier / DLC 0083h

0084h 0085h 0086h 0087h 0088h 0089h

CAN0 Message Box 2: Data Field 008Ah

008Bh 008Ch 008Dh 008Eh

CAN0 Message Box 2: Time Stamp 008Fh

0090h 0091h 0092h

CAN0 Message Box 3: Identifier / DLC 0093h

0094h 0095h 0096h 0097h 0098h 0099h

CAN0 Message Box 3: Data Field 009Ah

009Bh 009Ch 009Dh 009Eh

CAN0 Message Box 3: Time Stamp 009Fh

00A0h 00A1h 00A2h

CAN0 Message Box 4: Identifier / DLC 00A3h

00A4h 00A5h 00A6h 00A7h 00A8h 00A9h

CAN0 Message Box 4: Data Field 00AAh

00ABh 00ACh 00ADh 00AEh

CAN0 Message Box 4: Time Stamp 00AFh

00B0h 00B1h 00B2h

CAN0 Message Box 5: Identifier / DLC 00B3h

00B4h 00B5h 00B6h 00B7h 00B8h 00B9h

CAN0 Message Box 5: Data Field 00BAh

00BBh 00BCh 00BDh 00BEh

CAN0 Message Box 5: Time Stamp 00BFh

200 201

B-2

Address Register Symbol Page

C0GMR

C0LMAR

C0LMBR

Address Register Symbol Page

0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh

200 201

202

CAN0 Message Box 14: Identifier /DLC

CAN0 Message Box 14: Data Field

CAN0 Message Box 14: Time Stamp

CAN0 Message Box 15: Identifier /DLC

CAN0 Message Box 15: Data Field

CAN0 Message Box 15: Time Stamp

CAN0 Global Mask Register

CAN0 Local Mask A Register

CAN0 Local Mask B Register

0100h 0101h 0102h

CAN0 Message Box 10: Identifier / DLC 0103h

0104h 0105h 0106h 0107h 0108h 0109h

CAN0 Message Box 10: Data Field 010Ah

010Bh 010Ch 010Dh 010Eh

CAN0 Message Box 10: Time Stamp 010Fh

0110h 0111 h 0112h

CAN0 Message Box 11: Identifier / DLC 0113h

0114h 0115h 0116h 0117h 0118h 0119h

CAN0 Message Box 11: Data Field 011Ah

011Bh 011Ch 011Dh 011Eh

CAN0 Message Box 11: Time Stamp 011Fh

0120h 0121h 0122h

CAN0 Message Box 12: Identifier / DLC 0123h

0124h 0125h 0126h 0127h 0128h 0129h

CAN0 Message Box 12: Data Field 012Ah

012Bh 012Ch 012Dh 012Eh

CAN0 Message Box 12: Time Stamp 012Fh

0130h 0131h 0132h

The blank areas are reserved.

CAN0 Message Box 13: Identifier / DLC 0133h

0134h 0135h 0136h 0137h 0138h 0139h

CAN0 Message Box 13: Data Field 013Ah

013Bh 013Ch 013Dh 013Eh

CAN0 Message Box 13: Time Stamp 013Fh

200 201

B-3

Address Register Symbol Page

TBSR

TA11

TA21

TA41

INVC0 INVC1 IDB0 IDB1 DTT ICTB2

IFSR2

TB3

TB4

TB5

S6TRR

S6C S6BRG S3456TRR TB3MR TB4MR TB5MR IFSR0 IFSR1 S3TRR

S3C S3BRG S4TRR

S4C S4BRG S5TRR

S5C S5BRG U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG

U2TB

U2C0 U2C1

U2RB

Address Register Symbol Page

01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh

107

118

115 116 117 117 117 119

116

106

172

172 172 173

106 108 109

111

70 71

172

172 172 172

172 172 133 132 132 131 133 132 132 131 133 132 132 131 129 128

128

129 130

128

Timer B3, B4, B5 Count Start Flag

Timer A1-1 Register

Timer A2-1 Register

Timer A4-1 Register

Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Occurrence Frequency Set Counter

Interrupt Cause Select Register 2

Timer B3 Register

Timer B4 Register

Timer B5 Register

SI/O6 Transmit/Receive Register

SI/O6 Control Register SI/O6 Bit Rate Generator SI/O3, 4, 5, 6 Transmit/Receive Register Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register Interrupt Cause Select Register 0 Interrupt Cause Select Register 1 SI/O3 Transmit/Receive Register

SI/O3 Control Register SI/O3 Bit Rate Generator SI/O4 Transmit/Receive Register

SI/O4 Control Register SI/O4 Bit Rate Generator SI/O5 Transmit/Receive Register

SI/O5 Control Register SI/O5 Bit Rate Generator UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Generator

UART2 Transmit Buffer Register

UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1

UART2 Receive Buffer Register

0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h

The blank areas are reserved.

Flash Memory Control Register 1 01B6h 01B7h

Flash Memory Control Register 0 01B8h 01B9h

Address Match Interrupt Register 2 01BAh 01BBh

Address Match Interrupt Enable Register 2 01BCh 01BDh

Address Match Interrupt Register 3 01BEh 01BFh

FMR1

FMR0

RMAD2

AIER2

RMAD3

241

B-4

Address Register Symbol Page

C0AFS

PCLKR CCLKR

0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h to 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh

209

36 37

CAN0 Acceptance Filter Support Register

Peripheral Clock Select Register CAN0 Clock Select Register

0200h

CAN0 Message Control Register 0 CAN0 Message Control Register 1

0201h

CAN0 Message Control Register 2

0202h 0203h

CAN0 Message Control Register 3

0204h

CAN0 Message Control Register 4

0205h

CAN0 Message Control Register 5

0206h

CAN0 Message Control Register 6

0207h

CAN0 Message Control Register 7

0208h

The blank areas are reserved.

CAN0 Message Control Register 8

0209h

CAN0 Message Control Register 9

020Ah

CAN0 Message Control Register 10

020Bh

CAN0 Message Control Register 11

020Ch

CAN0 Message Control Register 12

020Dh

CAN0 Message Control Register 13

020Eh

CAN0 Message Control Register 14

020Fh

CAN0 Message Control Register 15

0210h

CAN0 Control Register

0211h 0212h

CAN0 Status Register

0213h 0214h

CAN0 Slot Status Register

0215h 0216h

CAN0 Interrupt Control Register

0217h 0218h

CAN0 Extended ID Register

0219h 021Ah

CAN0 Configuration Register

021Bh 021Ch

CAN0 Receive Error Count Register

021Dh

CAN0 Transmit Error Count Register

021Eh

CAN0 Time Stamp Register

021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h

CAN1 Control Register

0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh

C0MCTL0 C0MCTL1

C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15

C0CTLR

C0STR

C0SSTR

C0ICR

C0IDR

C0CONR

C0RECR C0TECR

C0TSR

C1CTLR

203

204

206

207

208

209 209

209

205

B-5

Address Register Symbol Page

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

ADCON2

ADCON0 ADCON1 DA0

DA1

DACON

PC14 PUR3 P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 PUR0 PUR1 PUR2 PCR

Address Register Symbol Page

03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh

180

179,182,184 186,188,190

195

231 233 231 231 230 230 231 231 230 230 231 231 230 230 231 231 230 230 231 231 230 230 231 231 230 230 231 231 230 230 232 232 232 233

A/D Register 0

A/D Register 1

A/D Register 2

A/D Register 3

A/D Register 4

A/D Register 5

A/D Register 6

A/D Register 7

A/D Control Register 2

A/D Control Register 0 A/D Control Register 1 D/A Register 0

D/A Register 1

D/A Control Register

Port P14 Control Register Pull-Up Control Register 3 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register Port P12 Register Port P13 Register Port P12 Direction Register Port P13 Direction Register

Pull-up Control Register 0 Pull-up Control Register 1 Pull-up Control Register 2 Port Control Register

0380h

Count Start Flag

0381h

Clock Prescaler Reset Flag

0382h

One-Shot Start Flag

0383h

Trigger Select Register

0384h

Up/Down Flag 0385h 0386h

Timer A0 Register 0387h

0388h

The blank areas are reserved.

Timer A1 Register 0389h

038Ah

Timer A2 Register 038Bh

038Ch

Timer A3 Register 038Dh

038Eh

Timer A4 Register 038Fh

0390h

Timer B0 Register 0391h

0392h

Timer B1 Register 0393h

0394h

Timer B2 Register 0395h

Timer A0 Mode Register

0396h

Timer A1 Mode Register

0397h

Timer A2 Mode Register

0398h

Timer A3 Mode Register

0399h

Timer A4 Mode Register

039Ah

Timer B0 Mode Register

039Bh

Timer B1 Mode Register

039Ch

Timer B2 Mode Register

039Dh

Timer B2 Special Mode Register

039Eh 039Fh

UART0 Transmit/Receive Mode Register

03A0h

UART0 Bit Rate Generator

03A1h 03A2h

UART0 Transmit Buffer Register 03A3h

UART0 Transmit/Receive Control Register 0

03A4h

UART0 Transmit/Receive Control Register 1

03A5h 03A6h

UART0 Receive Buffer Register 03A7h

03A8h

UART1 Transmit/Receive Mode Register 03A9h

UART1 Bit Rate Generator 03AAh

UART1 Transmit Buffer Register 03ABh

03ACh

UART1 Transmit/Receive Control Register 0 03ADh

UART1 Transmit/Receive Control Register 1 03AEh

UART1 Receive Buffer Register 03AFh

03B0h

UART Transmit/Receive Control Register 2 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h

DMA0 Request Cause Select Register 03B9h 03BAh

DMA1 Request Cause Select Register 03BBh 03BCh

CRC Data Register 03BDh

03BEh

CRC Input Register 03BFh

TABSR CPSRF ONSF TRGSR UDF

TA0

TA1

TA2

TA3

TA4

TB0

TB1

TB2

TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC

U0MR U0BRG

U0TB

U0C0 U0C1

U0RB

U1MR U1BRG

U1TB

U1C0 U1C1

U1RB

UCON

DM0SL

DM1SL

CRCD

CRCIN

92,107,120

93,107

93,120

118

106

118 91 94

121

98,121

101

103

98,121 106,108 109,111

121

119

129 128

128

129 130

128

129 128

128

129 130

128

131

196

B-6

M16C/6N Group (M16C/6NL, M16C/6NN)

Under development

This document is under development and its contents are subject to change

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

1. Overview

The M16C/6N Group (M16C/6NL, M16C/6NN) of single-chip microcomputers are built using the

high-performance silicon gate CMOS process using an M16C/60 Series CPU core and are packaged in

100-pin and 128-pin plastic molded LQFP. These single-chip microcomputers operate using sophisticated

instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable

of executing instructions at high speed. Being equipped with one CAN (Controller Area Network) module in

M16C/6N Group (M16C/6NL, M16C/6NN), the microcomputer is suited to car audio and industrial control

systems. The CAN module complies with the 2.0B specification. In addition, this microcomputer contains a

multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control

of various OA and communication equipment which requires high-speed arithmetic/logic operations.

1.1 Applications

Car audio and industrial control systems, other

Rev.1.02

Jul 01, 2005

Rev.1.02 Jul 01, 2005 page 1 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview

1.2 Performance Outline

Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NL, M16C/6NN).

Table 1.1 Performance Outline of M16C/6N Group (100-pin Version: M16C/6NL)

Item Performance

CPU Number of Basic Instructions 91 instructions

Minimum Instruction Execution Time Operation Mode Single-chip mode Address Space 1 Mbyte

Memory Capacity See Table 1.3 Product List Peripheral Port Input/Output: 87 pins, Input: 1 pin Function Multifunction Timer Timer A: 16 bits ✕ 5 channels

Serial I/O 3 channels

A/D Converter 10-bit A/D converter: 1 circuit, 26 channels

D/A Converter 8 bits ✕ 2 channels

DMAC 2 channels

CRC Calculation Circuit CRC-CCITT

CAN Module 1 channel with 2.0B specification

Watchdog Timer 15 bits ✕ 1 channel (with prescaler)

Interrupt Internal: 30 sources, External: 9 sources

Clock Generating Circuit 4 circuits

Oscillation Stop Detection Main clock oscillation stop and re-oscillation detection function

Function Electrical Supply Voltage VCC = 3.0 to 5.5V Characteristics

Power Mask ROM 19mA (f(BCLK) = 24MHz, PLL operation, no division)

Consumption

Flash Memory Mask ROM 3µA

Flash Memory Flash Memory Version

Program/Erase Supply Voltage

Program and Erase Endurance I/O I/O Withstand Voltage 5.0V Characteristics

Output Current 5mA Operating Ambient Temperature -40 to 85°C Device Configuration CMOS high performance silicon gate Package 100-pin plastic mold LQFP

NOTES:

1. I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

41.7ns (f(BCLK) = 24MHz, 1/1 prescaler, without software wait)

Timer B: 16 bits ✕ 6 channels Three-phase motor control circuit

Clock synchronous, UART, I2C-bus

(1)

, IEBus

(2)

2 channels

Clock synchronous

Software: 4 sources, Priority level: 7 levels

• Main clock oscillation circuit (*)

• Sub clock oscillation circuit (*)

• On-chip oscillator

• PLL frequency synthesizer

(*) Equipped with a built-in feedback resistor

(f(BCLK) = 24MHz, 1/1 prescaler, without software wait)

21mA (f(BCLK) = 24MHz, PLL operation, no division)

(f(BCLK) = 32kHz, Wait mode, Oscillation capacity Low)

0.8µA (Stop mode, Topr = 25°C)

3.3 ± 0.3V or 5.0 ± 0.5V 100 times

Rev.1.02 Jul 01, 2005 page 2 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview

Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NN)

Item Performance

CPU Number of Basic Instructions 91 instructions

Minimum Instruction Execution Time

41.7ns (f(BCLK) = 24MHz, 1/1 prescaler, without software wait) Operation Mode Single-chip mode Address Space 1 Mbyte Memory Capacity See Table 1.3 Product List

Peripheral Port Input/Output: 113 pins, Input: 1 pin Function Multifunction Timer Timer A: 16 bits ✕ 5 channels

Timer B: 16 bits ✕ 6 channels Three-phase motor control circuit

Serial I/O 3 channels

Clock synchronous, UART, I2C-bus

(1)

, IEBus

(2)

4 channels

Clock synchronous A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits ✕ 2 channels DMAC 2 channels CRC Calculation Circuit CRC-CCITT CAN Module 1 channel with 2.0B specification Watchdog Timer 15 bits ✕ 1 channel (with prescaler) Interrupt Internal: 32 sources, External: 12 sources

Software: 4 sources, Priority level: 7 levels

Clock Generating Circuit 4 circuits

• Main clock oscillation circuit (*)

• Sub clock oscillation circuit (*)

• On-chip oscillator

• PLL frequency synthesizer

(*) Equipped with a built-in feedback resistor Oscillation Stop Detection Main clock oscillation stop and re-oscillation detection function Function

Electrical Supply Voltage VCC = 3.0 to 5.5V Characteristics

(f(BCLK) = 24MHz, 1/1 prescaler, without software wait) Power Mask ROM 19mA (f(BCLK) = 24MHz, PLL operation, no division)

Flash Memory Version

Consumption

Program/Erase Supply Voltage Program and Erase Endurance

Flash Memory

21mA (f(BCLK) = 24MHz, PLL operation, no division)

Mask ROM 3µA Flash Memory

0.8µA (Stop mode, Topr = 25°C)

3.3 ± 0.3V or 5.0 ± 0.5V

100 times

(f(BCLK) = 32kHz, Wait mode, Oscillation capacity Low)

I/O I/O Withstand Voltage 5.0V Characteristics

Output Current 5mA

Operating Ambient Temperature -40 to 85°C Device Configuration CMOS high performance silicon gate Package 128-pin plastic mold LQFP

NOTES:

1. I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

Rev.1.02 Jul 01, 2005 page 3 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview

1.3 Block Diagram

Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NL, M16C/6NN).

Port P0

Port P18Port P2

Internal peripheral functions

Expandable up to 26 channels)

Timer (16 bits)

Output (timer A): 5

Input (timer B): 6

Three-phase motor

control circuit

Watchdog timer

(15 bits)

DMAC

(2 channels)

D/A converter

(8 bits ✕ 2 channels)

NOTES:

1: ROM size depends on microcomputer type. 2: RAM size depends on microcomputer type. 3: Ports P11 to P14 are only in the 128-pin version. 4: 8 bits ✕ 2 channels in the 100-pin version.

Clock synchronous serial I/O

CRC arithmetic circuit (CCITT)

8 8 8 8

A/D converter

(10 bits ✕ 8 channels

UART or

(3 channels)

(Polynomial: X

R0H R0L R1H R1L

R2 R3

A0 A1

16+X12+X5

+1)

USP

ISP

INTB

FLG

Port P14

(3)

Port P5Port P4Port P3

System clock generating circuit

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

On-chip oscillator

Clock synchronous serial I/O

(8 bits ✕ 4 channels)

CAN module

(1 channel)

(4)

MemoryM16C/60 series CPU core

(1)

ROM

(2)

RAM

Multiplier

Port P13

Port P12

(3)

Port P6

Port P7

Port P8

Port P8_5

Port P9

Port P10

Port P11

(3)

Figure 1.1 Block Diagram

Rev.1.02 Jul 01, 2005 page 4 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview

1.4 Product List

Table 1.3 lists the M16C/6N Group (M16C/6NL, M16C/6NN) products and Figure 1.2 shows the type numbers,

memory sizes and packages.

Table 1.3 Product List

As of Jul. 2005

Type No. ROM Capacity RAM Capacity Package Type Remarks

M306NLFHGP 384 K + 4 Kbytes 31 Kbytes PLQP0100KB-A Flash memory

M306NNFHGP PLQP0128KB-A version

M306NLFJGP (D) 512 K + 4 Kbytes 31 Kbytes PLQP0100KB-A

M306NNFJGP PLQP0128KB-A

M306NLME-XXXGP 192 Kbytes 16 Kbytes PLQP0100KB-A Mask ROM version

M306NNME-XXXGP PLQP0128KB-A

M306NLMG-XXXGP 256 Kbytes 20 Kbytes PLQP0100KB-A

M306NNMG-XXXGP PLQP0128KB-A

(D): Under development

Type No.

M30 6N L M G - XXX GP

Package type:

GP: Package PLQP0100KB-A, PLQP0128KB-A

ROM No.

Omitted on flash memory version

ROM capacity: E : 192 Kbytes G: 256 Kbytes H : 384 Kbytes J : 512 Kbytes

Figure 1.2 Type No., Memory Size, and Package

Memory type:

M : Mask ROM version F : Flash memory version

Shows the number of CAN module, pin count, etc.

6N Group

M16C Family

Rev.1.02 Jul 01, 2005 page 5 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview

1.5 Pin Configuration

Figures 1.3 and 1.4 show the pin configuration (top view).

PIN CONFIGURATION (top view)

P2_3/AN2_3

P2_2/AN2_2

P2_1/AN2_1

P2_0/AN2_0

P1_5/INT3

P1_6/INT4

P1_7/INT5

M16C/6N Group

(M16C/6NL)

BYTE

CNVSS

P8_7/XCIN

P8_6/XCOUT

P9_1/TB1IN/SIN3

P9_0/TB0IN/CLK3

P9_2/TB2IN/SOUT3

(1)

P1_2 P1_1

P1_0 P0_7/AN0_7 P0_6/AN0_6 P0_5/AN0_5 P0_4/AN0_4 P0_3/AN0_3 P0_2/AN0_2 P0_1/AN0_1 P0_0/AN0_0

P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0

P10_3/AN3 P10_2/AN2 P10_1/AN1

AVSS

P10_0/AN0

VREF

P9_7/ADTRG/SIN4

P9_6/ANEX1/CTX0/SOUT4

P9_5/ANEX0/CRX0/CLK4

AVCC

P1_4

P1_3

81 82

100

1 2 3 4 5 6 7 8 9 10111213141516171819202122232425

P9_3/DA0/TB3IN

P9_4/DA1/TB4IN

NOTE:

1. P7_1 and P9_1 are N channel open-drain pins.

P2_7/AN2_7

P2_6/AN2_6

P2_5/AN2_5

P2_4/AN2_4

XIN

VSS

XOUT

RESET

VSS

P3_0

VCC1

P8_5/NMI

P3_3

P3_2

VCC2

P3_1

57585960616263646566676869707172737475

P8_2/INT0

P8_3/INT1

P8_4/INT2/ZP

P8_1/TA4IN/U

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

515253545556

27 26

P7_7/TA3IN

P7_6/TA3OUT

P8_0/TA4OUT/U/(SIN4)

P7_5/TA2IN/W/(SOUT4)

P7_4/TA2OUT/W/(CLK4)

P7_3/CTS2/RTS2/TA1IN/V

P4_2 P4_3 P4_4 P4_5 P4_6 P4_7 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT P7_1/RXD2/SCL2/TA0IN/TB5IN P7_2/CLK2/TA1OUT/V

(1)

Package: PLQP0100KB-A

Figure 1.3 Pin Configuration (Top View) (1)

Rev.1.02 Jul 01, 2005 page 6 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview

PIN CONFIGURATION (top view)

P1_0 P0_7/AN0_7 P0_6/AN0_6 P0_5/AN0_5 P0_4/AN0_4 P0_3/AN0_3 P0_2/AN0_2 P0_1/AN0_1 P0_0/AN0_0

P11_7/SIN6

P11_6/SOUT6

P11_5/CLK6

P11_4

P11_3

P11_2/SOUT5

P11_1/SIN5

P11_0/CLK5

P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0

P10_3/AN3 P10_2/AN2 P10_1/AN1

AVSS

P10_0/AN0

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127 128

P1_1

P1_2

P1_5/INT3

P1_4

P1_3

P1_6/INT4

100101102

VREF

AVCC

P9_4/DA1/TB4IN

P9_7/ADTRG/SIN4

P9_5/ANEX0/CRX0/CLK4

P9_6/ANEX1/CTX0/SOUT4

P2_3/AN2_3

P2_2/AN2_2

P2_1/AN2_1

P1_7/INT5

P2_0/AN2_0

P2_4/AN2_4

P14_1

P14_0

P9_3/DA0/TB3IN

P9_1/TB1IN/SIN3

P9_0/TB0IN/CLK3

P9_2/TB2IN/SOUT3

(1)

VSS

VCC2

P12_1

P12_0

P12_3

P3_0

P12_2

P2_7/AN2_7

P2_6/AN2_6

P2_5/AN2_5

M16C/6N Group

(M16C/6NN)

21 22 23 24 25 26 27 28 29 3011 12 13 14 15 16 17 18 19 2012345678910

XIN

RESET

P8_7/XCIN

P8_6/XCOUT

VSS

XOUT

VCC1

P8_5/NMI

P8_4/INT2/ZP

BYTE

CNVSS

P12_4

P3_1

P8_2/INT0

P8_3/INT1

P3_3

P3_2

P8_1/TA4IN/U

P4_3

P4_2

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

737475767778798081828384858687888990919293949596979899

31 32 33 34 35 36 37

P7_7/TA3IN

P7_6/TA3OUT

P8_0/TA4OUT/U/(SIN4)

P7_2/CLK2/TA1OUT/V

P7_5/TA2IN/W/(SOUT4)

P7_4/TA2OUT/W/(CLK4)

P7_3/CTS2/RTS2/TA1IN/V

P7_1/RXD2/SCL2/TA0IN/TB5IN

(1)

P4_7

P4_6

P4_5

P4_4

66676869707172

P12_5

P12_6

P12_7

P5_0

P5_1

P5_2

P5_3

P13_0

P13_1

P13_2

P13_3

P5_4

P5_5

P5_6

P5_7/CLKOUT

P13_4

P13_5/INT6

P13_6/INT7

P13_7/INT8

P6_0/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

VSS

VCC1

P6_7/TXD1/SDA1

P6_6/RXD1/SCL1

P7_0/TXD2/SDA2/TA0OUT

1. P7_1 and P9_1 are N channel open-drain pins.

Figure 1.4 Pin Configuration (Top View) (2)

Package: PLQP0128KB-ANOTE:

Rev.1.02 Jul 01, 2005 page 7 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview

1.6 Pin Description

Tables 1.4 and 1.5 list the pin descriptions.

Table 1.4 Pin Description (100-pin and 128-pin Versions) (1)

Signal Name Pin Name I/O Type Description

Power supply input Analog power supply input Reset input

CNVSS External data

VCC1, VCC2, VSS AVCC, AVSS

_____________

RESET

CNVSS

BYTE bus width select input Main clock

XIN input Main clock

XOUT output Sub clock

XCIN input Sub clock

XCOUT output Clock output

______

INT interrupt input

_______

NMI interrupt input Key input

CLKOUT

________ ________

INT0 to INT8

________

NMI

______ ______

KI0 to KI3

(3)

interrupt input Timer A

TA0OUT to TA4OUT

I/O TA0IN to TA4IN ZP

Timer B Three-phase motor control output Serial I/O

TB0IN to TB5IN

___ ___ ____

U, U, V, V, W, W

__________ __________

CTS0 to CTS2

__________ __________

RTS0 to RTS2 CLK0 to CLK6

(3)

I/O RXD0 to RXD2 SIN3 to SIN6

(3)

TXD0 to TXD2 SOUT3 to SOUT6

(3)

CLKS1

C mode

SDA0 to SDA2 SCL0 to SCL2

I/O

I: Input O: Output I/O: Input/Output

Apply 3.0 to 5.5V to the VCC1 and VCC2 pins and 0V to the

VSS pin. The VCC apply condition is that VCC2 = VCC1 Applies the power supply for the A/D converter. Connect the

AVCC pin to VCC1. Connect the AVSS pin to VSS. The microcomputer is in a reset state when applying “L” to the

this pin. Connect this pin to VSS.

Connect this pin to VSS.

I/O pins for the main clock oscillation circuit. Connect a ceramic

resonator or crystal oscillator between XIN and XOUT To use the external clock, input the clock from XIN and leave

XOUT open. I/O pins for a sub clock oscillation circuit. Connect a crystal

oscillator between XCIN and XCOUT To use the external clock, input the clock from XCIN and leave

(2)

XCOUT open. The clock of the same cycle as fC, f8, or f32 is output.

Input pins for the INT interrupt.

Input pin for the NMI interrupt.

Input pins for the key input interrupt.

______

_______

These are timer A0 to timer A4 I/O pins. These are timer A0 to timer A4 input pins.

Input pin for the Z-phase.

These are timer B0 to timer B5 input pins.

These are Three-phase motor control output pins.

These are send control input pins.

These are receive control output pins.

These are transfer clock I/O pins. These are serial data input pins.

These are serial data input pins.

These are serial data output pins.

This is output pin for transfer clock output from multiple pins function.

These are serial data I/O pins. These are transfer clock I/O pins. (except SCL2 for the N-channel open drain output.)

(1)

(2)

NOTES:

1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

2. Ask the oscillator maker the oscillation characteristic.

________ ________

3. INT6 to INT8, CLK5, CLK6, SIN5, SIN6, SOUT5, SOUT6 are only in the 128-pin version.

Rev.1.02 Jul 01, 2005 page 8 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview

Table 1.5 Pin Description (100-pin and 128-pin Versions) (2)

Signal Name Pin Name I/O Type Description Reference

voltage input

A/D converter

VREF

AN0 to AN7

Applies the reference voltage for the A/D converter and D/A

converter.

Analog input pins for the A/D converter.

AN0_0 to AN0_7

AN2_0 to AN2_7

_____________

ADTRG

ANEX0

I/O

This is an A/D trigger input pin.

This is the extended analog input pin for the A/D converter,

and is the output in external op-amp connection mode.

D/A converter

CAN module

I/O port

ANEX1

DA0, DA1

CRX0

CTX0

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7 P4_0

P4_7

P5_0 to P5_7

I/O

This is the extended analog input pin for the A/D converter.

These are the output pins for the D/A converter.

This is the input pin for the CAN module.

This is the output pin for the CAN module.

8-bit I/O ports in CMOS, having a direction register to select

an input or output.

Each pin is set as an input port or output port. An input port

can be set for a pull-up or for no pull-up in 4-bit unit by

program.

(except P7_1 and P9_1 for the N-channel open drain output.)

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_4

P8_6, P8_7

P9_0 to P9_7

P10_0 to P10_7

(1)

Input pin for the NMI interrupt.

_______

Input port

P11_0 to P11_7

P12_0 to P12_7

P13_0 to P13_7

P14_0, P14_1

P8_5

Pin states can be read by the P8_5 bit in the P8 register.

I: Input O: Output I/O: Input/Output

NOTE:

1. Ports P11 to P14 are only in the 128-pin version.

Rev.1.02 Jul 01, 2005 page 9 of 314 REJ09B0126-0102

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This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 2. Central Processing Unit (CPU)

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. There are two register banks.

b31 b15 b8 b7 b0

R0H (R0's high bits) R0L (R0's low bits)

R1H (R1's high bits) R1L (R1's low bits)

Data Registers

Address Registers

Frame Base Registers

(1)

b19 b15

INTBLINTBH

The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.

b19

b15 b0

USP

ISP

b15 b0

FLG

b15 b0

IPL U I O B S Z D C

NOTE:

1. These registers comprise a register bank. There are two register banks.

b7b8

Interrupt Table Register

Program Counter

User Stack Pointer

Interrupt Stack Pointer

Static Base Register

Flag Register

Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area

Figure 2.1 CPU Registers

2.1 Data Registers (R0, R1, R2, and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit

data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The A0 register consists of 16 bits, and is used for address register indirect addressing and address

same as A0.

In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).

Rev.1.02 Jul 01, 2005 page 10 of 314 REJ09B0126-0102

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This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 2. Central Processing Unit (CPU)

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3 Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4 Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5 Register Bank Select Flag (B Flag)

2.8.6 Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is set to “0” when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0” ; USP is selected when the U flag is “1”. The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt request is enabled.

2.8.10 Reserved Area

When white to this bit, write “0”. When read, its content is indeterminate.

Rev.1.02 Jul 01, 2005 page 11 of 314 REJ09B0126-0102

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M16C/6N Group (M16C/6NL, M16C/6NN) 3. Memory

3. Memory

Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NL, M16C/6NN). The address space

extends the 1 Mbyte from address 00000h to FFFFFh.

The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a

512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh.

As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is

mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.

The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the

start address of each interrupt routine here.

The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a

31-Kbyte internal RAM is allocated to the addresses from 00400h to 07FFFh. In addition to storing data, the

internal RAM also stores the stack used when calling subroutines and when interrupts are generated.

The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are

located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be

used by users.

The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by

the JMPS or JSRS instruction. For details, refer to M16C/60 and M16C/20 Series Software Manual.

00000h

00400h

(program area)

Internal RAM

Reserved area

Internal ROM (data area)

Reserved area

Internal ROM

Internal RAM

Capacity

16 Kbytes 043FF

20 Kbytes

31 Kbytes

Address XXXXX

053FF

07FFF

Capacity

192 Kbytes D0000

256 Kbytes C0000

384 Kbytes A0000

512 Kbytes 80000

Internal ROM

Address YYYYY

XXXXX

0F000h

0FFFFh

10000h

(1)

YYYYY

FFFFFh

NOTES:

1. As for the flash memory version, 4-Kbyte space (block A) exists.

2. Shown here is a memory map for the case where the PM13 bit in the PM1 register is "1". If the PM13 bit is set to "0", 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.

3. When using the masked ROM version, write nothing to internal ROM area.

Figure 3.1 Memory Map

SFR

FFE00h

Special page

(1)

FFFDCh

(3)

FFFFFh

vector table

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Oscillation stop and re-oscillation

detection / watchdog timer

DBC NMI

Reset

Rev.1.02 Jul 01, 2005 page 12 of 314 REJ09B0126-0102

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This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR)

4. Special Function Register (SFR)

SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.12 list the SFR information.

Table 4.1 SFR Information (1)

Address Register Symbol After Reset

0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

X: Undefined

Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1

Address Match Interrupt Enable Register Protect Register

Oscillation Stop Detection Register

Watchdog Timer Start Register Watchdog Timer Control Register

Address Match Interrupt Register 0

Address Match Interrupt Register 1

PLL Control Register 0

Processor Mode Register 2

DMA0 Source Pointer

DMA0 Destination Pointer

DMA0 Transfer Counter

DMA0 Control Register

DMA1 Source Pointer

DMA1 Destination Pointer

DMA1 Transfer Counter

DMA1 Control Register

(1)

PM0 PM1 CM0 CM1

AIER PRCR

CM2

WDTS WDC

RMAD0

RMAD1

PLC0

PM2

SAR0

DAR0

TCR0

DM0CON

SAR1

DAR1

TCR1

DM1CON

00h 00001000b 01001000b 00100000b

XXXXXX00b

XX000000b

0X000000b

XXh

00XXXXXXb

00h

X0h

00h

X0h

0001X010b

XXX00000b

XXh XXh XXh

XXh XXh

00000X00b

XXh XXh XXh

XXh XXh

00000X00b

NOTES:

1. The CM20, CM21, and CM27 bits in the CM2 register do not change at oscillation stop detection reset.

2. The blank areas are reserved and cannot be accessed by users.

Rev.1.02 Jul 01, 2005 page 13 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR)

Table 4.2 SFR Information (2)

Address Register

0040h 0041h 0042h 0043h 0044h

0045h

0046h

0047h

0048h

0049h

004Ah 004Bh 004Ch 004Dh

004Eh

004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch 005Dh 005Eh 005Fh 0060h

(1)

Timer B4 Interrupt Control Register UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register UART0 Bus Collision Detection Interrupt Control Register SI/O4 Interrupt Control Register INT5 Interrupt Control Register SI/O3 Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register CAN0 Error Interrupt Control Register A/D Conversion Interrupt Control Register Key Input Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register INT7 Interrupt Control Register Timer A3 Interrupt Control Register INT6 Interrupt Control Register

(1)

Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register SI/O6 Interrupt Control Register Timer B1 Interrupt Control Register INT8 Interrupt Control Register

(1)

Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register

0061h 0062h 0063h

CAN0 Message Box 0: Identifier / DLC

0064h 0065h 0066h 0067h 0068h 0069h 006Ah

CAN0 Message Box 0: Data Field

006Bh 006Ch 006Dh 006Eh 006Fh

CAN0 Message Box 0: Time Stamp

0070h 0071h 0072h 0073h

CAN0 Message Box 1: Identifier / DLC

0074h 0075h 0076h 0077h 0078h 0079h 007Ah

CAN0 Message Box 1: Data Field

007Bh 007Ch 007Dh 007Eh 007Fh

CAN0 Message Box 1: Time Stamp

X: Undefined

Symbol After Reset

XXXXX000b XXXXX000b XXXXX000b XX00X000b

XXXXX000b

XX00X000b

XXXXX000b XXXXX000b XXXXX000b XXXXX000b

XXXXX000b

XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b

XX00X000b

XXXXX000b

XX00X000b

XXXXX000b XX00X000b XX00X000b XX00X000b

XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh

NOTES:

1. These registers exist only in the 128-pin version.

2. The blank area is reserved and cannot be accessed by users.

Rev.1.02 Jul 01, 2005 page 14 of 314 REJ09B0126-0102

+ 304 hidden pages

Renesas 16-bit single-chip microcomputer, M16C, M6NN, M6NL User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Keep safety first in your circuit designs!

Notes regarding these materials

How to Use This Manual

1. Introduction

2. Register Diagram

3. M16C Family Documents

Table of Contents

SFR Page Reference

1. Overview

1.1 Applications

1.2 Performance Outline

1.3 Block Diagram

1.4 Product List

1.5 Pin Configuration

1.6 Pin Description

2. Central Processing Unit (CPU)

2.1 Data Registers (R0, R1, R2, and R3)

2.2 Address Registers (A0 and A1)

2.3 Frame Base Register (FB)

2.4 Interrupt Table Register (INTB)

2.5 Program Counter (PC)

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

2.7 Static Base Register (SB)

2.8 Flag Register (FLG)

2.8.1 Carry Flag (C Flag)

2.8.2 Debug Flag (D Flag)

2.8.3 Zero Flag (Z Flag)

2.8.4 Sign Flag (S Flag)

2.8.5 Register Bank Select Flag (B Flag)

2.8.6 Overflow Flag (O Flag)

2.8.7 Interrupt Enable Flag (I Flag)

2.8.8 Stack Pointer Select Flag (U Flag)

2.8.9 Processor Interrupt Priority Level (IPL)

2.8.10 Reserved Area

3. Memory

4. Special Function Register (SFR)