Renesas M65881AFP User Manual

M65881AFP

Digital Amplifier Processor of S-Master* Technology

DESCRIPTION

The M65881AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal to high precise switching-pulse digital output without analog processing. The M65881AFP has built-in 24bit sampling rate converter and digital-gain-controller. The M65881AFP enables to realize high precise ( X`tal oscillation accuracy.) full digital amplifier systems combining with power driver IC.

FEATURES

•Built-in 24bit Sampling Rate Converter. Input Signal Sampling Rate from 32KHz to 192KHz (24bit Maximum). 4 kinds of Digital Input Format.

•Built-in L/R Independent Digital Gain Control.

•Built-in Soft Mute Function with Exponential Approximate-Curve.

•Correspondence to Output for Headphone.

MAIN SPECIFICATION

•Master Clock Primary Clock: 256Fsi/512Fsi Secondary Clock: 1024Fso/512Fso

•Input Signal Format: MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit) LSB First Right Justified(24bit),I

•Input Signal Sampling Rate from 32kHz to 192kHz.

•Gain Control Function: +30dB~-∞dB (0.1dB Step until -96dB, -138dB Minimum)

•Third Order ∆Σ (16Fso:6bit/5bit,32Fso:5bit)

2

S(24bit)

OUTLINE : 42P2R

0.8mm pitch 42pin SSOP

REJ03F0004-0100Z

Rev.1.00

2003.05.08

APPLICATION

DVD Receiver, AV Amplifier

RECOMMENDED OPERATING CONDITIONS

Logic Block:1.8V±10%,PWM Buffer Block :3.3V±10%

SYSTEM BLOCK DIAGRAM)

CD DVD Audio etc.

LRCK BCK

DATA

256fsi/512fsi

24bit

32kHz

192kHz

Sampling

Rate

Converter

to

Clock

M65881AFP

Level

Control

+30dB

to

-∞

MCU I/F

Clock

∆Σ

PWM

Stream

Power Driver

Stream

Power Driver

Output for Headphone

LC

Filter

LC

Filter

1024fso/512fso

* "S-Master" is the digital amplifier technology developed by Sony Corporation. "S-Master" is a trademark of Sony Corporation.

Rev.1.00 2003.05.08

page 1 of 23

M65881AFP

PIN CONFIGURATION

3.3V

system

1.8V

system

VddL

OUTL1

OUTL2

XOVdd

XfsoOUT

XOVss

DVdd

DVss

MCKSEL

SCDT

1

2

3

4

5

6

7

8

9

10

11

PWM output

for Power Stage

42

41

40

39

38

37

36

35

34

33

32

VddR

OUTR1

VssRVssL

OUTR2

VssLR

XVdd

XfsoIN

XVss

HPVddL

HPOUTL1

HPVssL

3.3V system

3.3V

system

SCSHIFT

SCLATCH

NSPMUTE

INIT

LRCK

BCK

DATA

BFVdd SFLAG

BFVss

XfsiIN FsoCKO

12

13

14

15

16

17

18

19

20

21

PWM output for Headphone

31

30

29

28

27

26

25

24

23

22

HPOUTL2

HPVddR

HPOUTR1

HPVssR

HPOUTR2

TEST1

TEST2

FsoI

Rev.1.00 2003.05.08

page 2 of 23

M65881AFP

BLOCK DIAGRAM

OUTL2

4

OUTR1

OUTR2

41

39

HPOUTL1

HPOUTL2

33

31

HPOUTR1

HPOUTR2

29

27

25 26

2

T T

T

E

S

1

T

E

S

OUTL1

2

PWM

L

F

S

f

X

A

G

24

M T

T

E

U

S

P

N

14

I

s

o

N

36

∆Σ

15

N

INIT/MUTE

f

s

F

M

s

C

o

O

o

C s

F KSE

K o

X

6

T

U

O

2210

I

23

Generator

L

Clock

( Secondary )

Gain Control

Serial

Control

11 12 13

L

T

S S S

A

C

S

H

C

T

C

D

H

I

F

T

i

f

X

Rev.1.00 2003.05.08

I

s

N

21

Clock

page 3 of 23

Generator

( Primary )

Sampling

Rate Converter

S⇒P

17

BCK

16

LRCK

18

DATA

M65881AFP

ABSOLUTE MAXIMUM RATINGS

Parameter

Supply Voltage

Input Voltage Range

Power Dissipation

Storage Temperature

Symbol Condition Min. Typ. Max Unit

PWMVdd V

3.3V system (XVdd, XOVdd, PWM Output for Power Stage & Headphone)

BFVdd 3.3V system -0.3 – 3.8 V

DVdd 1.8V system -0.3 – 2.5 V

Vi -0.3 – Vdd+0.3 V

Pd Ta=75ºC 350 mW

Tstg -40 – 125

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage

Operating Temperature

Operating Frequency

Symbol Condition

PWMVdd

3.3V system (XVdd, XOVdd, PWM Output

for Power Stage & Headphone)

BFVdd 3.3V system

DVdd 1.8V system

Ta

XfsoIN

XfsiIN

-0.3 – 3.8

Min. Typ. Max

3.0 3.3

3.0 3.3 3.6

1.6 1.8 2.0

-20 16 52.5

8 25

– – –

3.6

75

ºC

Unit

V V

V

ºC

MHz MHz

ELECTRICAL CHARACTERISTICS

Parameter

"H" Level Input Voltage

"L" Level Input Voltage

Input Leek Current

"H" Level Output

Voltage

"L" Level Output

Voltage

Power Supply Current

XfsoOUT

SFLAG FsoCKO OUTL1,2

OUTR1,2

HPOUTL1,2

HPOUTR1,2

XfsoOUT

SFLAG FsoCKO OUTL1,2

OUTR1,2

HPOUTL1,2

HPOUTR1,2

Symbol Conditions

VIH3 BFVdd=3.0 to 3.6V VIH3 BFVdd=3.0 to 3.6V Ileak

VOH3 Vdd-0.5 – –

VOL3 – – 0.5

Idd2 1.8V system (DVdd) Idd3 – 2.5

(Ta=25ºC,PWMVdd=3.3V, DVdd=1.8V : Unless otherwise specified.)

Min. Typ. M

0.75Vdd – – – – 0.25Vdd – – 10

BFVdd=3.0 to 3.6V IOH3=-4.0mA (SFLAG,FsoCKO) IOH3=-2.0mA (XfsoOUT,OUTL1,2,OUTR1,2) IOH3=-1.0mA (HPOUTL1,2,HPOUTR1,2)

BFVdd=3.0 to 3.6V IOL3=4.0mA (SFLAG, FsoCKO) IOL3=2.0mA (XfsoOUT,OUTL1,2,OUTR1,2) IOL3=1.0mA (HPOUTL1,2,HPOUTR1,2)

–

3.3V system (PWMVdd, BFVdd) OUTxx, HPOUTxx="OPEN"

3.5

Unit

µA

V

– – mA

mA

V V

Rev.1.00 2003.05.08

page 4 of 23

M65881AFP

CHARACTERISTICS EVALUATION CIRCUIT

-

OUTL1

2

+

OUTL2

4

-

OUTR2

39

+

-

+

GND

+

-

+

-

LRCK

BCK

DATA

16 17 18

OUTR1

M65881AFP

HPOUTL1 HPOUTL2

HPOUTR2 HPOUTR1

41

33 31

27 29

+

GND

-

+

Power Supply

GND

+

-

Reference characteristic

Output for

Power Stage

Output for

Headphone

Rev.1.00 2003.05.08

THD+N

S/N

page 5 of 23

102dB(typ)

0.002%(typ) 100dB(typ)

0.006%(typ)

Conditions

• Input :1kHz 0dB Full scale sine wave

• FS :Primary clock 44.1kHz, Secondary clock 48kHz

• PWM Output format 1 • AC dithering E • DC dithering : 0.1%

• Gain data setting : (Index) 10000b/ (Mantissa) 10000000b

• THD+N: Filter 20kHz LPF S/N: Filter 22kHz LPF + JIS-A

M65881AFP

PIN DESCRIPTION

Pin No. Name I/O

1 VddL 2 OUTL1 O 3 VssL 4 OUTL2 O 5 XOVdd 6 XfsoOUT O 7 XOVss 8 DVdd

9 DVss 10 MCKSEL I 11 SCDT I 12 SCSHIFT I 13 SCLATCH I 14 NSPMUTE I 15 INIT I 16 LRCK I 17 BCK I 18 DATA I 19 BFVdd 20 BFVss 21 XfsiIN I 22 FsoCKO O 23 FsoI I 24 SFLAG O 25 TEST2 I 26 TEST1 I 27 HPOUTR2 O 28 HPVssR 29 HPOUTR1 O 30 HPVddR 31 HPOUTL2 O 32 HPVssL 33 HPOUTL1 O 34 HPVddL 35 XVss 36 XfsoIN I 37 XVdd 38 VssLR 39 OUTR2 O 40 VssR 41 OUTR1 O 42 VddR

Output

Current

Description

Power Supply for Lch PWM Power Stage (3.3V) Lch PWM1 Output for Power Stage 3.3V GND for Lch PWM Power Stage Lch PWM2 Output for Power Stage 3.3V Power Supply for Secondary Master Clock Buffer ( 3.3V ) Buffered Output of Secondary Master Clock (1024/512fso) 2mA 3.3V GND for Secondary Master Clock Buffer Power Supply for Digital Block (1.8V) GND for Digital Block Secondary Master Clock Selector "L":1024fso, "H":512fso 3.3V Serial Control • Data Input 3.3V Serial Control • Shift Clock Input 3.3V Serial Control • Latch Signal Input 3.3V PWM Duty 50% Mute ( "L": Active ) 3.3V Initialize Input ( Power Supply Reset ) ; "L" : Reset, "H" : Release 3.3V LRCK Input (PCM Signal ) 3.3V BCK Input ( PCM Signal ) 3.3V DATA Input ( PCM Signal ) 3.3V Power Supply for Input/Output 3.3V Buffer GND for Input/Output 3.3V Buffer Primary Master Clock Input (256fsi/512fsi ) 3.3V Secondary Fso Clock Output 4mA 3.3V Secondary Fso Clock Input 3.3V Asynchronous Flag ( H: Active ) 4mA 3.3V Test2 must be connected to GND 3.3V Test1 must be connected to GND 3.3V Rch PWM2 Output for Headphone 3.3V GND for Rch Headphone Rch PWM1 Output for Headphone 3.3V Power Supply for Rch Headphone ( 3.3V ) Lch PWM2 Output for Headphone 3.3V GND for Lch Headphone Lch PWM1 Output for Headphone 3.3V Power Supply for Lch Headphone ( 3.3V ) GND for Secondary Master Clock Input Buffer Secondary Master Clock Input (1024fso/512fso) 3.3V Power Supply for Secondary Master Clock Buffer ( 3.3V ) GND for PWM Power Stage Rch PWM 2 Output for Power Stage 3.3V GND for Rch PWM Power Stage Rch PWM 1 Output for Power Stage 3.3V Power Supply for Rch PWM Power Stage ( 3.3V)

on 3.3V

–

– – –

– – – – – – – – – – – –

–

– –

–

– –

– – –

–

Signal Level

–

– – –

– –

–

– –

–

Rev.1.00 2003.05.08

page 6 of 23

M65881AFP

EXPLANATION OF OPERATION

1. DATA,BCK,LRCK

DATA,BCK, and LRCK are input pins for Digital Audio Signal of CD, MD, DVD etc.. Input formats are supported by 4 ways, and are set by Serial Control, "System1 Mode, bit3 and bit4". Input data length are selectable in a case of "MSB First Right Justified" (Serial Control "System1 Mode,bit5 and bit6").

•Input formats are shown in following figures.

MSB first left justified

(24bit)

MSB first right justified

(16bit, 20bit, 24bit)

LRCK

BCK

DATA (24bit)

LRCK

BCK

DATA (16bit)

DATA (20bit)

DATA (24bit)

MSB

1/fsi, 1/2fsi, 1/4fsi

Left Right

LSB

24cycle

Left

MSB

16 cycle

MSB

20 cycle

24 cycle 24 cycle

MSB

1/fsi, 1/2fsi, 1/4fsi

LSB

MSB

24cycle

MSB

LSB

Right

LSB

16 cycle

LSB

20 cycle

LSB

LSB first right justified

(24bit)

I2S(24bit)

LRCK

BCK

DATA (24bit)

LRCK

BCK

DATA (24bit)

1 BCK

1/fsi, 1/2fsi, 1/4fsi

Left Right

MSB

24 cycle 24 cycle

1/fsi, 1/2fsi, 1/4fsi

Left

LSB LSB

24 cycle

LSBLSB

1 BCK

MSBMSB

MSB

Right

24 cycle

Rev.1.00 2003.05.08

page 7 of 23

Renesas M65881AFP User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual