On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Send any inquiries to http://www.renesas.com/inquiry
.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
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characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
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control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
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owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
User’s Manual
SH7619 CPU Board
M3A-HS19
User’s Manual
Renesas 32-Bit RISC Microcomputers
SuperH™ RISC engine Family/SH7619 Group
Rev.1.01 2008.10
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
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information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
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transmission. If you are considering the use of our products for such purposes, please contact a Renesas
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8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
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12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
1.8 Absolute Maximum Ratings...................................................................................................................................... 1-10
2.4 Serial Port Interface.................................................................................................................................................. 2-13
2.6 LAN Port Interface.................................................................................................................................................... 2-15
2.8 Power Supply Circuit................................................................................................................................................ 2-19
3.2 Switches and LEDs ..................................................................................................................................................3-15
3.2.2 Features of Switches and LEDs...................................................................................................................... 3-18
The M3A-HS19 is a CPU board designed to evaluate the feature and performance of the SH7619 Group of Renesas Technology
original MCU, as well as developing and evaluating the application software for the MCUs.
SH7619 data bus, address bus and on-chip peripheral pins are all connected to expansion connectors and appropriate connectors
to allow for the timing evaluation with peripherals using measurement instruments, and the development of the optional boards
according to its application. Furthermore, it can be connected with an RS-232C connector and a LAN connector, and a PC card
can be mounted on the board.
Renesas Technology E10A-USB on-chip emulator can also be connected to the M3A-HS19.
1.2 Configuration
Figure 1.2.1 shows an example of system configuration using the M3A-HS19.
The M3A-HS19 CPU board includes the SH7619, the 32-bit RISC MCU operates with a maximum frequency of 125 MHz.
The SH7619 is equipped with an Ethernet controller that includes an IEEE802.3u compliant Media Access Controller and
a Physical Layer Transceiver. Moreover, the SH7619 has both a 16-KB U memory (RAM) and a 16-KB instruction/data
unified cache memory. These on-chip modules enable the SH7619 to be used in a wide range of applications from data
processing to control equipments.
The M3A-HS19 can be operated at a maximum frequency of 125 MHz (external bus: 62.5 MHz, max) using a 15.625 MHz
input clock. The dedicated clock of 25.000 MHz input from CK_PHY pin is used as an on-chip PHY clock.
Figure 2.2.1 shows the SH7619 pin assignments.
The M3A-HS19 includes the SH7619 on-chip U memory, an external flash memory, external SDRAM and EEPROM.
Details are described below (Except the PC card).
2.3.1 SH7619 U Memory and Cache Memory
The SH7619 has a 16-KB (RAM) U memory module (address: H’E55FC000~H’E55FFFFF) and a 16-KB
instruction/data-unified cache memory.
The M3A-HS19 comes standard with a flash memory listed in Table 2.3.1 to store a user program.
The flash memory is an external bus 16-bit mode fixed and operates at 3.3 V single. The write-protection of flash memory
can be enabled or disabled by DIP switches (SW4-4).
Figure 2.3.1 shows the Flash Memory Block Diagram. Table 2.3.2 lists setting examples of the bus state
controller(write/read) when the SH7619 bus clock operates at 62.5 MHz (clock mode 1), and Figure 2.3.2 shows read and
write access timing example.
Table 2.3.1 Flash Memory Specifications
Part Number Bus Size Capacity Access Time
S29GL032A90TFIR4 16-bit mode 4 MB (16 bits x 2 Mwords x 1) 90 ns
SH7619 (U1)
D15-D0
A21-A1
RD#
WE0#
CS0#
3.3 V
21
16
3.3 V
3.3 V
3.3 V
Reset Signal
NC
3.3 V
DIP Switch
(SW4-4)
S29GL032A90TFIR4 (U2)
(2 Mwords x 16 bits)
A20-A0
DQ15-DQ0
BYTE#
OE#
WE#
CE#
RESET#
RY/BY#
WP#
Rev.1.01
REJ10J1351-0101
Oct 28, .2008 2-4
Figure 2.3.1 Flash Memory Block Diagram
Features and Specifications
A
2
Table 2.3.2 Setting Example of Bus State Controller (Flash Memory Write and Read)
User Area Applicable Device Settings for Bus State Controller
CS0 S29GL032A90TFIR4 CS0 Space Bus Control Register: CS0BCR
Figure 2.3.2 Flash Memory Read and Write Access Timing Example
tAD1tAD1
tCSD1
tRSDtRSD
tDF(CE)
tRDS1tDHtDStDH
tRDH1
tDF(OE)
Rev.1.01
REJ10J1351-0101
Oct 28, .2008 2-5
Features and Specifications
2
2.3.3 External Synchronous DRAM (SDRAM)
The M3A-HS19 is provided with a 16-MB synchronous DRAM (SDRAM) as an external main memory. T he SDRAM is
controlled by the SH7619 on-chip bus state controller. The SDRAM is accessed in 16-bit bus.
Table 2.3.3 lists SDRAM specifications used on the M3A-HS19, and Figure 2.3.3 shows its block diagram.
Table 2.3.3 SDRAM Specifications
Items Description
Part Number EDS1216AATA-75E
Configuration 16 MB (16-bit bus width) x 1
Capacity 16 MB
Access Time 5.4 ns
CAS Latency 2 (at 62.5 MHz bus clock)
Refresh Interval 4,096 refresh cycles in every 64 ms
Row Address A1 1- A0
Column Address A8 - A0
Number of Banks 4-banks controlled by BA0, BA1
2.3.3 External Synchronous DRAM
3.3V
EDS1216AATA-75(U3)
(
SH7619(U1)
A14-13BA1-0
A12-1
CS3#
CKIO
CKE
RD/WR#
RAS#
CAS#
DQMLU
DQMLL
D15-0
x 16
2
11
16
2 M x 16 bits x 4-bank)
A11-0
CS#
CLK
CKE
WE#
RAS#
CAS#
DQMU
DQML
DQ15-DQ0
Figure 2.3.3 External SDRAM Block Diagram
Rev.1.01
Oct 28, .2008 2-6
REJ10J1351-0101
Features and Specifications
2
A power-on sequence is required to use a SDRAM. Power-on sequence is to initialize the pin function controller (PFC),
set registers in the bus state controller and write data in the SDRAM mode register.
Table 2.3.4 lists the access address when writing in the SDRAM mode register on the CS3 space.
• CAS latency: 2 cycles
To write data in the SDRAM mode register as shown in Table 2.3.4, write the arbitrary data in words to the address of
H'F8FD 5440 (the data in this case is ignored). Following commands are sequentially issued to the SDRAM by the word
writing.
1.All banks precharge command (PALL)
Idle cycles (Tpw), of which number is specified by bits WTRP1 and WTRP0 in CS3WCR, are inserted between the PALL
and the first REF commands.
2. Auto-refreshing command (REF) for eight times
Idle cycles (Trc), of which number is specified by bits WTRP1 and WTRP0 in CS3WCR are inserted after issuing REF
command
Figure 2.3.4 shows a timing example of SDRAM mode register writing.
tRCtRP
CKIO
SDRAM
Command
A11-A1(A9-A0)
A12(A10/AP)
CS3#
RASL#
CASL#
RD/WR#
Tp
PALL
TpwTrr
DESL
TrcTrc
TrcTrc
DESLDESL
REF
DESL
REF command is issued 8 times
DESL
Trr
Trc
DESLREF
Features and Specifications
2.3.3 External Synchronous DRAM
Tmw
REF
TrcTrr
DESL
MRS
Tnop
DESL
DQMUU-LL
D15-0
[Symbols Descriptions]
PALL
:All bank precharge command
REF :Auto-refreshing command
:Mode register write commamd
MRS
DESL
:Deselect command
(High)
Hi-Z
Figure 2.3.4 Timing Example of SDRAM Mode Register Writing
Rev.1.01
Oct 28, .2008 2-8
REJ10J1351-0101
Features and Specifications
2
Table2.3.5 lists setting examples of the bus state controller with SH7619 bus clock at 62.5 MHz.
Figure 2.3.5 shows the SDRAM single read/write timing example.
Table2.3.5 Setting Example of Bus State Controller (SDRAM Read/Write)
User Area Applicable Device Settings for Bus State Controller
CS3 EDS1216AATA-75E CS3 Space Bus Control Register: CS3BCR
Initial value: H'36DB 0600
Recommended value: H'0000 4400 (in 16-bit bus width)
• Memory specification
TYPE[3:0] = B'0100; SDRAM
• Data bus specification
BSZ[1:0] = B'10; 16-bit bus width
The M3A-HS19 is provided with an EEPROM for storing MAC address.
Access to the EEPROM is enabled by using the SH7261 I/O ports (PC03, PC02, PC01 and PC00). A MAC address
consists of 48-bit numbers.
Table 2.3.6 lists instruction sets, and Figure 2.3.6 shows the block diagram of CPU and EEPROM connection.
Figure 2.3.7 shows the EEPROM-AC timing and Figure 2.3.8 shows EEPROM-read/write timing.
Settings for following instruction sets are not required;
- A7 to A0 for WRAL, ERAL, EWEN, and EWDS instructions
- Data for ERASE, ERAL, EWEN and EWDS instructions
The SH7619 MCU mounted on the M3A-HS19 is provided with a 3 channel’s of the Serial Communication Interface with
FIFO (SCIF).
SCIF channel 0 is connected to the 2-pin serial port connector, SCIF channel 2 is connected to the D-sub 9-pin serial port
connector, and SCIF channel 1 is connected to the 4-pin serial port connector.
Figure 2.4.1 shows the block diagram of the serial port interface.
Rev.1.01
REJ10J1351-0101
Oct 28, .2008 2-13
Figure 2.4.1 Serial Port Interface
Features and Specifications
2
2.5 PCMCIA Card Interface
2.5 PCMCIA Card Interface
The SH7619 MCU mounted on the M3A-HS19 is compliant with the JEIDA 4.2 (PCMCIA2.1 Rev.2.1). However, only
3.3 V interface PC card is supported. An on-chip bus state controller (BSC) and a PFC control the PC card.
High byte and low byte of the data is switched at the bus switch on the M3A-HS19. When the byte order of the SH7619 is
big-endian, the order of the PC card connector is little-endian (IOIS16#: ”L”).
The M3A-HS19 is provided with a PCMCIA card slot in area 5, allowing both IC memory card and I/O card to be mounted.
Figure 2.5.1 shows the block diagram of PCMCIA card interface.
PC card connector (J4)
20-bit bus switch
D15-D6
D5-D0
10
6
1B[9:0]
2B[9:0]
1A[9:0]
2A[9:0]
1OE#
2OE#
10
6
SH7619 (U1)
D7-D0, D15, D14
D13-D8
20-bit bus switch
A25-A16
A15-A6
A5-A0
RESET
CE1#
CE2#
REG#
OE#
WE#
IORD#
IOWR#
CD1#
CD2#
WAIT#
IOIS16#
IREQ#
VS1#
VS2#
INPACK#
SPKR#
STSCHG#
VCC
3.3 V
x3
PCVCC
10
10
6
1B[9:0]
2B[9:0]
20-bit bus switch
4
4
2
x5
1B[9:0]
2B[9:0]
PCMCIA
Power supply
circuit
PCVCC
1A[9:0]
2A[9:0]
1OE#
2OE#
10
10
A25-A16
A15-A6
A5-A0
6
PC09/RX_ER(GPIO)
CE2A#
1A[9:0]
2A[9:0]
10
8
4
4
CE1A#
PC14/COL
RD#
WE#
PB05/ICIORD#
1OE#
2OE#
4
PB06/ICIOWR#
PC15/CRS
PB0/WAIT#
PB1/IOIS16#
PD7/IRQ7
JP2
3.3 V5.0 V
PC20/WOL
PB13/BS#
JP1
Figure 2.5.1 PCMCIA Card Interface
Rev.1.01
Oct 28, .2008 2-14
REJ10J1351-0101
Features and Specifications
2
2.6 LAN Port Interface
2.6 LAN Port Interface
An IEEE 802.3 compliant (MAC layer) Ethernet controller and an IEEE802.3/802.3u compliant (10/100 Mbps Ethernet
PHY) physical layer transceiver are embedded in the SH7619 MCU.
Figure 2.6.1 shows the block diagram of LAN port interface.
SH7619 (U1)
SPEED100#
LINK#
CRS#
DUPLEX#
(MII)
TxP
TxM
ETC
PHY
RxP
RxM
EXRES1
TSTBUSA
LED1
Yellow
3.3 V
LED2
Yellow
LED3
Yellow
LED4
Yellow
3.3 VA
1
2
3
4
5
6
7
8
RJ-45 (J5)
TX +
TX −
TCT
RX +
RX −
RCT
CK_PHY
25.000 MHz-OSC
MII-compliant signal
12.4 K(1%)
3 VAGND
Figure 2.6.1 LAN Port Interface
Rev.1.01
Oct 28, .2008 2-15
REJ10J1351-0101
Features and Specifications
2
2.7 I/O Port
2.7 I/O Port
Following I/O ports on the M3A-HS19 can be configured by the SH7619 MCU. These ports are multiplexed pins with up to
four features. Some pins have several initial features for normal mode and HIF (Host Interface) boot mode. Features can
be controlled by PFC (pin function controller).
• PA16 - PA25
• PB00 - PB13
• PC00 - PC20
• PD0 - PD7
• PE00 - PE24
The M3A-HS19 is connected with a memory, expansion connectors, a PCMCIA connector, a LAN connector, an RS-232C
connector, an RS-422 connector and other control ICs. Some I/O ports are connected to DIP switches and LEDs, which
can be used in the port mode as intended use. LED shows status in the PHY mode.
Table 2.7.1 lists Mode DIP Switch (SW4) Features. The state will be loaded when the board is reset and started.
Table 2.7.1 Mode DIP Switch (SW4) Features
SW4-No.
1 ON: Big-endian OFF: Little-endian
2 ON: Host interface (HIF) is NOT operating OFF: Host interface (HIF) is operating
3 ON: Normal boot mode OFF: HIF boot mode
4 ON: Flash ROM is write-protected OFF: Write-enabled
Figure 2.7.1 shows the block diagram of I/O port connections to switches and LEDs.
Table 2.7.2 and Table 2.7.3 list I/O port features.
Description
Rev.1.01
REJ10J1351-0101
Oct 28, .2008 2-16
Figure 2.7.1 I/O Port Connection to Switches and LEDs
The main power supply input 5 V DC to the M3A-HS19 and it generates 3.3 V and 1.8 V using a regulator.
It is an adjustable output voltage regulator to generate a desired voltage by changing resistance values.
A through-hole is provided with the M3A-HS19 to input 1.8 V DC from an external power supply. The PC card power
supply is controlled by software.
Figure 2.8.1 shows the schematic diagram of the power supply circuit.
5 V
Expansion connector (J12)
1
2
5 V-IN
(J7)
.8 V-IN
(J8)
Flash
Regulator (U12)
SW1
1
5 V
3.3 V
memory
(U2)
SH7619
2
GND
Regulator (U16)
5 V
1.8 V
(U1)
JP3
SDRAM
(U3)
PB13/BS#
1
Other
logic IC
JP1
EN1
EN0
Expansion connector
(J10)
LTC1470
PCMCIA connector
(U5)
(J4)
2
GND
Figure 2.8.1 Power Supply Circuit
Rev.1.01
REJ10J1351-0101
Oct 28, .2008 2-19
Features and Specifications
2
2.9 Clock Module
2.9 Clock Module
The clock module on the M3A-HS19 consists of following three blocks;
• A block connecting X1 (oscillator) output to SH7619 EXTAL
• A block connecting X2 (ceramic resonator) to EXTAL and XTAL (Optional)
• A block connecting X3 (oscillator) to CK-PHY
An on-chip oscillator (15.625 MHz) is connected to the SH7619 MCU to provide an operating clock. Another on-chip
oscillator (25.000 MHz) is also connected to the MCU to provide clock to physical layer. Bus clock output is connected to
a SDRAM and expansion connectors via damping resisters respectively.
Figure 2.9.1 shows the block diagram of clock module.
* : To mount a ceramic resonator,remove the resistance R13 and mount the resistance R14.
:Optional
SH7619(U1)
CLK
Oscillator(X1)
15.625
MHz
R13
Optional
CSTCE-G15M7
(Murata)
R14
Ceramic
resonator*(X2)
EXTAL
XTAL
CKIO
R98
R117
EXCLK expansion
connector(J10-36)
CLK SDRAM(U3)
CLK
Oscillator(X3)
25.000
MHz
R18
CK-PHY
Figure 2.9.1 Clock Module
Rev.1.01
Oct 28, .2008 2-20
REJ10J1351-0101
Features and Specifications
R
R
H-UDI connector
2
2.10 Reset Module
2.10 Reset Module
Reset module controls reset signals connected to the SH7619 MCU, a flash memory and connectors. Software controls to
reset PCMCIA connector.
Figure 2.10.1 shows the schematic diagram of resets.
Reset IC output delay time: td = 0.34×Cd(pF)µsec = 34 ms
3.3 V
0.1 µF
Ra+Rb
)
Rb
100 Ω
)
LVC14(U14)
SW2
Reset switch
Reset IC output detect voltage: Vs = 1.25×= 2.5 V
3.3 V
Open collector output
*
Reset
a
10 KΩ
M51957BFP(U13)
Input
K
Ω
Delay capacitor
10
b
IC
Output
*
Cd
RESET_IN(J9-1)
JP2
S08(U15)
1OE#
2OE#
RESET#
Expansion connector
RESET#
Flash memory
RESET#
SH7619
RES#
PC09/RX_ER
PC20/WOL
RESET
PCMCIA(J4)
Bus switch
Figure 2.10.1 M3A-HS19 Reset System
Rev.1.01
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(U9)
2
3.3 V
0
E
2.11 Interrupt Switch
Push-button switches are connected to the SH7619 NMI pin and IRQ0 pin.
Interrupts are connected to IRQ7 from an expansion connector and a PCMCIA connector.
Figure 2.11.1 shows the schematic diagram of interrupts.
Features and Specifications
2.11 Interrupt Switch
SH7619 (U1)
SW 5
NMI switch
SW 6
IRQ0 switch
IREQ#
PCMCIA(J4)
xpansion connector (J11)
16
NMI
LVC14(U14)
3.3 V
PD0/IRQ0/-/TEND
LVC14(U14)
PC20/WOL
PD7/IRQ7/SCK2
JP2
1OE#
2OE#
R106
18
Figure 2.11.1 Interrupts
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Bus switch (U9)
Features and Specifications
2
2.12 E10A-USB Interface
The M3A-HS19 is provided with a 14-pin H-UDI connector to embed the E10A-USB emulator.
Figure 2.12.1 shows the block diagram of the E10A-USB interface.
3.3 V
3.3 V
2.12 E10A-USB Interface
H-UDI connector (J6)
8
NC
10
GND
12
GND
13
GND
14
GND
Reset
UVCC
TCK
TRST#
TDO
NC
TMS
TDI
(GND)
RES#
11
1
3
4
5
6
9
7
TCK
TRST#
TDO
TMS
TDI
ASEMD#
RES#
SH7619 (U1)
Figure 2.12.1 E10A-USB Interface
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Features and Specifications
2.12 E10A-USB Interface
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Chapter3Operational Specifications
Chapter3
Operational Specifications
3-1
3
3.1 M3A-HS19 Connectors
Figure 3.1.1 shows the connector assignments on the M3A-HS19.
Top view of the component side
Operational Specifications
3.1 M3A-HS19 Connector
J7
Power
supply
connector
J14
AC adapter
jack
J15
GND pin
for test
J8
1.8 V External
power supply
connector (optional)
J3
RS-422
serial
connector
(optional)
Top view of the solder side
J6
H-UDI
connector
J1
RS-232C (ch1)
serial connector
(optional)
J2
RS-232C (ch2)
serial connector
J5
RJ-45 LAN
connector
J4
PC card
connector
J10, J12
Expansion
connectors
J9, J11, J13
Expansion
connectors
Figure 3.1.1 M3A-HS19 Connector Assignments
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3.1.1 UART Connector Pin (J1)
The M3A-HS19 is provided with an UART connector pin (J1).
Figure 3.1.2 shows the pin assignment for the UART connector (J1).
Top view of the component side
Operational Specifications
3.1.1 UART Connector Pin (J1)
J1
1
2
UART
Board Edge
Figure 3.1.2 Pin assignment for UART Connector (J1)
Table 3.1.1 lists the pin assignment for the UART connector (J1).
Table 3.1.1 Pin assignment for UART Connector (J1)
9 OE# (RD#) 43 VS1# (Pulled up to the PCMCIA power supply)
10 A11 44 IORD# (PB05/WE2#/DQMUL/ICIORD#)
11 A9 45 IOWR# (PB06/WE3#/DQMUU/ICIOWR#)
12 A8 46 A17
13 A13 47 A18
14 A14 48 A19
15 WE# (WE1#/DQMLU/WE#) 49 A20
16 IREQ# (PD7/IRQ7/SCK2) 50 A21
17 VCC 51 VCC
18 VPP1 52 VPP2
19 A16 53 A22
20 A15 54 A23
21 A12 55 A24
22 A7 56 A25
23 A6 57 VS2# (Pulled up to the PCMCIA power supply)
24 A5 58 RESET (PC09/RX_ER)
25 A4 59 WAIT# (PB00/WAIT#)
26 A3 60 INPACK# (Pulled up to the PCMCIA power supply)
27 A2 61 REG# (PC14/COL)
28 A1 62 SPKR# (Pulled up to the PCMCIA power supply)
29 A0 63 STSCHG# (Pulled up to the PCMCIA power supply)
30 D0 64 D8
31 D1 65 D9
32 D2 66 D10
33 IOIS16#
34 GND 68 GND
(PB01/IOIS16#)
67 CD2# (PC15/CRS)
3.1.4 PCMCIA Connector (J4)
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3
2
4
6
8
3.1.5 LAN Connector (J5)
The M3A-HS19 is provided with a LAN connector (J5).
Figure 3.1.6 shows the pin assignment for the LAN connector (J5).
Operational Specifications
3.1.5 LAN Connector (J5)
Top view of the
component side
Top view of
the solder side
J5
8
6
4
2
7
5
3
1
Board Edge
Figure 3.1.6 Pin assignment for LAN Connector (J5)
Table 3.1.5 lists the pin assignment for the LAN connector (J5).
Table 3.1.5 Pin assignment for LAN Connector (J5)
Pin no. Signal Name Pin no.Signal Name
Board Edge
7
5
3
1
1 TD+ 5 RD2 TD- 6 RCT
3 TCT 7 NC
4 RD+ 8 NC
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3
Top view the
component side
J6
1
7
H-UDI
8
14
3.1.6 H-UDI Connector (J6)
The M3A-HS19 is provided with an H-UDI (J6) connector to connect the E10A-USB emulator.
Figure 3.1.7 shows the pin assignment for the H-UDI connector (J6).
Operational Specifications
3.1.6 H-UDI Connector (J6)
Figure 3.1.7 Pin assignment for H-UDI Connector (J6)
Table 3.1.6 lists the pin assignment for the H-UDI connector (J6).
Table 3.1.6 Pin assignment for H-UDI Connector (J6)
Pin no. Signal Name Pin no.Signal Name
1
TCK
2
TRST#
3
TDO
4
N.C.
5
TMS
6
TDI
7
RESET#
8
9
10
11
12
13
14
N.C.
(GND) ASEMD#
GND
UVCC
GND
GND
GND
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3
3.1.7 Power Supply Connector (J7)
The M3A-HS19 is provided with a connector for power supply.
Figure 3.1.8 shows the pin assignment for the power supply connector (J7).
Board Edge
J7
Operational Specifications
3.1.7 Power Supply Connector (J7)
Top view of the
component side
Board Edge
Figure 3.1.8 Pin assignment for Power Supply Connector (J7)
Table 3.1.7 lists the pin assignment for the power supply connector (J7).
Table 3.1.7 Pin assignment for Power Supply Connector (J7)
Pin no. Signal Name Pin no.Signal Name
1 +5 V 2 GND
Side view
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Operational Specifications
3
3.1.8 External Power Supply Connector (J8)
The M3A-HS19 is provided with a through-hole for the SH7619 external power supply connector (J8: Supplies 1.8 V).
Figure 3.1.9 shows the pin assignment for the external power supply connector (J8).
Top view of the
component side
Top view of
the solder side
3.1.8 External Power Supply Connector (J8)
1
2
1
2
J8
Board Edge
Figure 3.1.9 Pin assignment for External Power Supply Connector (J8)
Table 3.1.8 lists the pin assignment for the external power supply connector (J8).
Table 3.1.8 Pin assignment for External Power Supply Connector (J8)
Pin no. Signal Name Pin no.Signal Name
1 +1.8 V 2 GND
Board Edge
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Operational Specifications
3
3.1.9 Expansion Connectors (J9-J13)
The M3A-HS19 is provided with through-holes for expansion connectors. The Through-holes are connected to the
SH7619 I/O pins. Expansion connectors (J9 - J13) can be connected to the MIL STD connector to mount expansion
boards or to monitor the SH7619 bus signals.
Figure 3.1.10 shows the pin assignment for expansion connectors.
3.1.9 Expansion Connectors (J9-J13)
Figure 3.1.10 Pin assignment for Expansion Connectors
Table 3.1.9 lists the pin assignment for the expansion connector (J9).
Table 3.1.9 Pin assignment for Expansion Connector (J9)
The M3A-HS19 is provided with nine jumpers.
Figure 3.2.2 shows the jumper assignments (JP1 - JP9), and Table 3.2.1 through Table 3.2.6 list the jumper settings (JP1
"H" ON: PC16 = "L"
"H" ON: PC17 = "L"
"H" ON: PC18 = "L"
"H" ON: PC19 = "L"
SW4 Mode DIP switches (4/package) See
PC16, PC17, PC18, and PC19 are pulled up.
See section 2.7 for details.
Table 3.2.8
for features.
SW5 NMI interrupt switch See section 2.11 for details.
SW6 IRQ0 switch See section 2.11 for details.
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Table 3.2.8 lists the SW4 features. Indicates the default setting.
Table 3.2.8 SW 4 Features
No. Setting Description
OFF MD5 = "H" Little endian SW4-1
MD5
HIFEBL
HIFMD
FLASH_WP#
Table 3.2.9 lists the LEDs on the M3A-HS19.
No. Color
LED1 Yellow User LED (LED1 lights when PC04/SPEED100# outputs "L")
LED2 Yellow User LED (LED2 lights when PC05/LINK# outputs "L")
LED3 Yellow User LED (LED3 lights when PC06/MII_TXD2/-/CRS# outputs "L")
LED4 Yellow User LED (LED4 lights when PC07/DUPLEX# outputs "L")
LED5 Blue Power LED (LED5 lights when 3.3 V power is supplied)
ON MD5 = "L" Big endian
OFF HIFEBL = "H" HIF pin is activated SW4-2
ON HIFEBL = "L" HIF pin is released to activate
OFF HIFMD = "H" Starts up from the host interface (HIF) SW4-3
ON HIFMD = "L" Not start up from the host interface (
OFF FLASH_WP# = "H" Flash memory is write-enabled SW4-4
ON FLASH_WP# = "L" Flash memory is write-protected
Table 3.2.9 LEDs
Description
Operational Specifications
3.2.2 Features of Switches and LED
Data alignment setting
HIF)
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<Top view of the component side>
<
3.3 Dimensions
Figure 3.3.1 shows the M3A-HS19 dimensions. Connectors can be mounted on J9 through J13 to simplify to mount an
expansion board.
Operational Specifications
3.3 Dimensions
Transparent view of the component side>
Figure 3.3.1 M3A-HS19 Dimensions
Rev.1.01
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Appendix
M3A-HS19 SCHEMATICS
A-1
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A-2
1
2
3
4
5
SH-2 SH7619 CPU BOARD M3A-HS19 Rev.C SCHEMATICS
AA
TITLE
INDEX
BB
CPU SH7619
FLASH MEMORY/SDRAM/EEPROM
UART/ETHER/PCMCIA
H-UDI/RESET/POWER
BUS CONNECTORS/PUSH SW
OTHERS
PAGE
1
2
3
4
5
6
7
Note:
CC
VCC = 5V
3VCC = 3.3V
1.8VCC = 1.8V
R = Fixed Resistors
RA = Resistor Array
C = Ceramic Caps
CE = Tantalum Electrolytic Caps
CP = Decoupling Caps
1:ON BIG ENDIAN (MSB FIRST)
1:OFF LITTLE ENDIAN (LSB FIRST)
2:ON NOT HIF ACTIVE
2:OFF HIF ACTIVE
3:ON NORMAL BOOT
3:OFF HIF BOOT
4:ON FLASH WRITE PROTECT
4:OFF FLASH UNLOCK