Renesas M32R-FPU User Manual

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User’s Manual

M32R-FPU

Software Manual

RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

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Rev.1.01 2003.10

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REVISION HISTORY

M32R-FPU Software Manual

Rev. Date Description

Page Summary

1.00 Jan 08, 2003 First edition issued –

1.01 Oct 31, 2003 Hexadecimal Instruction Code Table corrected (BTST instruction)APPENDICES-3

APPENDICES-8

Appendix Figure 3.1.1 corrected Incorrect) *The E1 stage of the FDIV instruction requires 13 cycles. Correct) *The E1 stage of the FDIV instruction requires 14 cycles.

APPENDICES-10

Appendix Figure 3.2.1 corrected Incorrect) LD1 Correct) LDI

APPENDICES-13

Appendix Figure 3.2.4 corrected Incorrect) ADD R1,R6,R7 Correct) FMADD R1,R6,R7

CHAPTER 1 CPU PROGRAMMING MODEL

1.1 CPU register .......................................................................................................... 1-2

1.2 General-purpose registers ...................................................................................... 1-2

1.3 Control registers ..................................................................................................... 1-3

1.3.1 Processor status word register: PSW (CR0) ...................................... 1-4

1.3.2 Condition bit register: CBR (CR1) ......................................................1-5

1.3.3 Interrupt stack pointer: SPI (CR2)

User stack pointer: SPU (CR3) ..........................................................1-5

1.3.4 Backup PC: BPC (CR6) .....................................................................1-5

1.3.5 Floating-Point Status Register: FPSR (CR7) .....................................1-6

1.3.6 Floating-Point Exceptions (FPE) ........................................................1-8

1.4 Accumulator............................................................................................................ 1-11

1.5 Program counter ..................................................................................................... 1-11

1.6 Data format ............................................................................................................. 1-12

1.6.1 Data type ............................................................................................1-12

1.6.2 Data format......................................................................................... 1-13

1.7 Addressing mode.................................................................................................... 1-15

CHAPTER 2 INSTRUCTION SET

2.1 Instruction set overview ......................................................................................... 2-2

2.1.1 Load/store instructions .......................................................................2-2

2.1.2 Transfer instructions...........................................................................2-4

2.1.3 Operation instructions ........................................................................2-4

2.1.4 Branch instructions.............................................................................2-6

2.1.5 EIT-related instructions ......................................................................2-8

2.1.6 DSP function instructions ...................................................................2-8

2.1.7 Floating-point Instructions ..................................................................2-11

2.1.8 Bit Operation Instructions ................................................................... 2-11

2.2 Instruction format ................................................................................................... 2-12

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M32R-FPU Software Manual (Rev.1.01)

CHAPTER 3 INSTRUCTIONS

3.1 Conventions for instruction description................................................................... 3-2

3.2 Instruction description............................................................................................. 3-5

APPENDIX

Appendix 1 Hexadecimal Instraction Code..................................................................

Appendix 2 Instruction List...........................................................................................

Appendix 3 Pipeline Processing ..................................................................................

Appendix 3.1 Instructions and Pipeline Processing ....................................

Appendix 3.2 Pipeline Basic Operation .......................................................

Appendix 4 Instruction Execution Time .......................................................................

Appendix 5 IEEE754 Specification Overview ..............................................................

Appendix 5.1 Floating Point Formats ..........................................................

Appendix 5.2 Rounding ...............................................................................

Appendix 5.3 Exceptions.............................................................................

Appendix 6 M32R-FPU Specification Supplemental Explanation ......................................

Appendix 6.1 Operation Comparision: Using 1 instruction (FMADD or FMSBU)

vs. two instructions (FMUL and FADD) .................................

Appendix 6.1.1 Rounding Mode ............................................................

Appendix 6.1.2 Exception occurring in Step 1 .......................................

Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU ...........

Appendix 7 Precautions...............................................................................................

Appendix 7.1 Precautions to be taken when aligning data...........................

Appendix Appendix

Appendix Appendix Appendix

Appendix Appendix Appendix Appendix

Appendix

-2

Appendix

-4

Appendix

-8

-10

Appendix

-17

Appendix

-18

-20

Appendix

-23

-28

Appendix

-29

INDEX

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M32R-FPU Software Manual (Rev.1.01)

CHAPTER 1

CPU PROGRAMMIING MODEL

1.1 CPU Register

1.2 General-purpose Registers

1.3 Control Registers

1.4 Accumulator

1.5 Program Counter

1.6 Data Format

1.7 Addressing Mode

CPU PROGRAMMING MODEL

1.1 CPU Register

The M32R family CPU, with a built-in FPU (herein referred to as M32R-FPU) has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are a 32bit configuration.

1.2 General-purpose Registers

The 16 general-purpose registers (R0 – R15) are of 32-bit width and are used to retain data and base addresses, as well as for integer calculations, floating-point operations, etc. R14 is used as the link register and R15 as the stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depending on the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW). At reset release, the value of the general-purpose registers is undefined.

1.1 CPU Register

Note 1: The stack pointer functions as either the SPI or the SPU depending on the value of the SM bit in the PSW.

b31

R0 R1 R2 R3 R4 R5 R6 R7

b31

R8 R9 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer)

Figure 1.2.1 General-purpose Registers

(Note 1)

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M32R-FPU Software Manual (Rev.1.01)

CPU PROGRAMMING MODEL

1.3 Control Registers

There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floating-point Status Register (FPSR). The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW instruction or the CLRPSW instruction.

CRn

Notes: • CRn (n = 0 - 3, 6 and 7) denotes the control register number.

• The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.

• The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW instruction or the CLRPSW

instruction.

Figure 1.3.1 Control Registers

CR0 CR1 CR2 CR3

CR6 CR7

PSW CBR

SPI

SPU

BPC

FPSR

b31

Processor Status Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer

Backup PC Floating-point Status Register

1-3 M32R-FPU Software Manual (Rev.1.01)

1.3.1 Processor Status Word Register: PSW (CR0)

7654321 8 9 10 11 12 13 14 b15b0

CPU PROGRAMMING MODEL

1.3 Control Registers

0000 000 0000000

BIEBSM

?? 00000?00000000

b Bit Name Function R W

0-15 No function assigned. Fix to "0". 0 0

16 BSM Saves value of SM bit when EIT occurs R W

Backup SM Bit

17 BIE Saves value of IE bit when EIT occurs R W

Backup IE Bit

18-22 No function assigned. Fix to "0". 0 0

23 BC Saves value of C bit when EIT occurs R W

Backup C Bit

24 SM 0: Uses R15 as the interrupt stack pointer R W

Stack Mode Bit 1: Uses R15 as the user stack pointer

25 IE 0: Does not accept interrupt R W

Interrupt Enable Bit 1: Accepts interrupt

26-30 No function assigned. Fix to "0". 0 0

31 C Indicates carry, borrow and overflow resulting R W

Condition Bit from operations (instruction dependent)

BPSW field

23 24 25 26 27 28 29 30 b3117 18 19 20 21 22b16

BC SM IE C

PSW field

< At reset release: "B'0000 0000 0000 0000 ??00 000? 0000 0000 >

The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs. The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit. The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the Backup Condition (BC) bit. At reset release, BSM, BIE and BC are undefined. All other bits are "0".

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M32R-FPU Software Manual (Rev.1.01)

1.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register's C bit is reflected in this register. The register can only be read. (Writing to the register with the MVTC instruction is ignored.) At reset release, the value of CBR is "H'0000 0000".

0000000000000000000000000000000

CBR

1.3.3 Interrupt Stack Pointer: SPI (CR2) User Stack Pointer: SPU (CR3)

The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack pointer. These registers can be accessed as the general-purpose register R15. R15 switches between representing the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW. At reset release, the value of the SPI and SPU are undefined.

CPU PROGRAMMING MODEL

1.3 Control Registers

b31

SPI

SPU

SPI

SPU

1.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to "0". When an EIT occurs, the register sets either the PC value when the EIT occurred or the PC value for the next instruction depending on the type of EIT. The BPC value is loaded to the PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC are always "00" when returned (PC always returns to the word-aligned address). At reset release, the value of the BPC is undefined.

BPC

b31

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CPU PROGRAMMING MODEL

1.3.5 Floating-point Status Register: FPSR (CR7)

234567891011121314b151b0

FS FX FU FZ

0000 00 0 0000000

18 19 20 21 22 23 24 25 26 27 28 29 30 b3117b16

EZ EO

EUEX

00 00000100000000

b Bit Name Function R W 0 FS Reflects the logical sum of FU, FZ, FO and FV. R –

Floating-point Exception Summary Bit

1 FX Set to "1" when an inexact exception occurs R W

Inexact Exception Flag (if EIT processing is unexecuted (Note 1)).

2 FU Set to "1" when an underflow exception occurs R W

Underflow Exception Flag (if EIT processing is unexecuted (Note 1)).

3 FZ Set to "1" when a zero divide exception occurs R W

Zero Divide Exception Flag (if EIT processing is unexecuted (Note 1)).

4 FO Set to "1" when an overflow exception occurs R W

Overflow Exception Flag (if EIT processing is unexecuted (Note 1)).

5 FV Set to "1" when an invalid operation exception R W

Invalid Operation Exception occurs (if EIT processing is unexecuted (Note 1)). Flag Once set, the flag retains the value "1" until

6–16 No function assigned. Fix to "0". 0 0

17 EX 0: Mask EIT processing to be executed when an R W

Inexact Exception Enable inexact exception occurs Bit 1: Execute EIT processing when an inexact

18 EU 0: Mask EIT processing to be executed when an R W

Underflow Exception Enable underflow exception occurs Bit 1: Execute EIT processing when an underflow

19 EZ 0: Mask EIT processing to be executed when a R W

Zero Divide Exception zero divide exception occurs Enable Bit 1: Execute EIT processing when a zero divide

20 EO 0: Mask EIT processing to be executed when an R W

Overflow Exception overflow exception occurs Enable Bit 1: Execute EIT processing when an overflow

0FO0

DN CE CX CU CZ CO CV RM

Once set, the flag retains the value "1" until it is cleared to "0" in software.

it is cleared to "0" in software.

exception occurs

1.3 Control Registers

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M32R-FPU Software Manual (Rev.1.01)

CPU PROGRAMMING MODEL

21 EV 0: Mask EIT processing to be executed when an R W

Invalid Operation Exception invalid operation exception occurs Enable Bit 1: Execute EIT processing when an invalid

operation exception occurs 22 No function assigned. Fix to "0". 0 0 23 DN 0: Handle the denormalized number as a R W

Denormalized Number Zero denormalized number Flash Bit (Note 2) 1: Handle the denormalized number as zero

24 CE 0: No unimplemented operation exception occurred . R(Note 3)

Unimplemented Operation 1: An unimplemented operation exception occurred. Exception Cause Bit When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0". 25 CX 0: No inexact exception occurred. R (Note 3)

Inexact Exception Cause 1: An inexact exception occurred. Bit When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0". 26 CU 0: No underflow exception occurred. R (Note 3)

Underflow Exception Cause 1: An underflow exception occurred. Bit When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0". 27 CZ 0: No zero divide exception occurred. R (Note 3)

Zero Divide Exception 1: A zero divide exception occurred. Cause Bit When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0". 28 CO 0: No overflow exception occurred. R(Note 3)

Overflow Exception 1: An overflow exception occurred. Cause Bit When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0". 29 CV 0: No invalid operation exception occurred. R (Note 3)

Invalid Operation Exception 1: An invalid operation exception occurred. Cause Bit When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0".

30, 31 RM 00: Round to Nearest R W

Rounding Mode Selection Bit 01: Round toward Zero

10: Round toward +Infinity

11: Round toward -Infinity

Note 1: ‘If EIT processing is unexecuted’ means whenever one of the exceptions occurs, enable bits

17 to 21 are set to "0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is executed. In this case, these two flags do not change state regardless of the enable bit settings.

Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented

exception occurs.

Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had

before the write).

1.3 Control Registers

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CPU PROGRAMMING MODEL

1.3.6 Floating-point Exceptions (FPE)

Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in the IEEE754 standard (OVF/UDF/IXCT/ DIV0/IVLD) is detected. Each exception processing is outlined below.

(1) Overflow Exception (OVF)

The exception occurs when the absolute value of the operation result exceeds the largest describable precision in the floating-point format. The following table shows the operation results when an OVF occurs.

Operation Result (Content of the Destination Register)

Rounding Mode Sign of the Result When the OVF EIT processing When the OVF EIT processing

is masked (Note 1) is executed (Note 2)

–infinity + +MAX

––infinity

+infinity + +infinity

––MAX No change

0 + +MAX

––MAX

Nearest + +infinity

––infinity

Note 1: When the Overflow Exception Enable (EO) bit (FPSR register bit 20) = "0" Note 2: When the Overflow Exception Enable (EO) bit (FPSR register bit 20) = "1" Note: • If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time.

• +MAX = H'7F7F FFFF, –MAX = H'FF7F FFFF

1.3 Control Registers

(2) Underflow Exception (UDF)

The exception occurs when the absolute value of the operation result is less than the largest describable precision in the floating-point format. The following table shows the operation results when a UDF occurs.

Operation Result (Content of the Destination Register)

When UDF EIT processing is masked (Note 1) When UDF EIT processing is executed (Note 2)

DN = 0: An unimplemented exception occurs No change

DN = 1: 0 is returned

Note 1: When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "0" Note 2: When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "1"

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M32R-FPU Software Manual (Rev.1.01)

CPU PROGRAMMING MODEL

(3) Inexact Exception (IXCT)

The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs.

Operation Result (Content of the Destination Register)

Occurrence Condition When the IXCT EIT processing is When the IXCT EIT processing is

masked (Note 1) executed (Note 2)

Overflow occurs in OVF Reference OVF operation results No change masked condition

Rounding occurs Rounded value No change

Note 1: When the Inexact Exception Enable (EX) bit (FPSR register bit 17) = "0" Note 2: When the Inexact Exception Enable (EX) bit (FPSR register bit 17) = "1"

(4) Zero Division Exception (DIV0)

The exception occurs when a finite nonzero value is divided by zero. The following table shows the operation results when a DIV0 occurs.

1.3 Control Registers

Operation Result (Content of the Destination Register)

Dividend When the DIV0 EIT processing is When the DIV0 EIT processing is

masked (Note 1) executed (Note 2)

Nonzero finite value ±infinity (Sign is derived by exclusive- No change

ORing the signs of divisor and dividend)

Note 1: When the Zero Division Exception Enable (EZ) bit (FPSR register bit 19) = "0" Note 2: When the Zero Division Exception Enable (EZ) bit (FPSR register bit 19) = "1"

Please note that the DIV0 EIT processing does not occur in the following conditions.

Dividend Behavior 0 An invalid operation exception occurs infinity No exception occur (with the result "infinity")

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CPU PROGRAMMING MODEL

(5) Invalid Operation Exception (IVLD)

The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs.

Occurrence Condition Operation Result (Content of the Destination Register)

When the IVLD EIT processing When the IVLD EIT is masked (Note 1) processing is executed

Operation for SNaN operand +infinity -(+infinity), -infinity -(-infinity) QNaN 0 ✕ infinity 0 ÷ 0, infinity ÷ infinity

When FTOI Return value when

instruction pre-conversion signed bit is: When an integer conversion was executed "0" = H’7FFF FFFF No change overflowed "1" = H’8000 0000

When NaN or Infinity was When FTOS Return value when converted into an integer instruction pre-conversion signed bit is:

was executed "0" = H’0000 7FFF

"1" = H’FFF 8000

When < or > comparison was Comparison results performed on NaN (comparison invalid)

Note 1: When the Invalid Operation Exception Enable (EV) bit (FPSR register bit 21) = "0" Note 2: When the Invalid Operation Exception Enable (EV) bit (FPSR register bit 21) = "1" Notes: • NaN (Not a Number)

SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction is “0”. When SNaN is used as the source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used as the initial value in a variable. However, SNaNs cannot be generated by hardware. QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction is "1". Even when QNaN is used as the source operand in an operation, an IVLD will not occur (excluding comparison and format conversion). Because a result can be checked by the arithmetic operations, QNaN allows the user to debug without executing an EIT processing. QNaNs are created by hardware.

1.3 Control Registers

(Note 2)

(6) Unimplemented Exception (UIPL)

The exception occurs when the Denormalized Number Zero Flash (DN) bit (FPSR register bit 23) = "0" and a denormalized number is given as an operation operand (Note 1). Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination register remains unchanged.

Note: • A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if the DN bit (FPSR register bit 23) = "0", an UIPL occurs.

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M32R-FPU Software Manual (Rev.1.01)

CPU PROGRAMMING MODEL

1.4 Accumulator

The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used for the multiply instruction "MUL", in which case the accumulator value is destroyed by instruction execution.

Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the high-order 32 bits (bits 0-31) and the low-order 32 bits (bits 32-63), respectively.

Use the MVFACHI, MVFACLO, and MVFACMI instructions for reading data from the accumulator. The MVFACHI, MVFACLO and MVFACMI instructions read data from the high-order 32 bits (bits 0-31), the low-order 32 bits (bits 32-63) and the middle 32 bits (bits 16-47), respectively. At reset release, the value of accumulator is undefined.

1.4 Accumulator

(Note 1)

ACC

read/write range with

MVTACHI or MVFACHI instruction

Note 1: When read, bits 0 to 7 always show the sign-extended value of bit 8. Writing to this bit field is ignored.

read range with MVFACMI instruction

32 48 b63311615b0 4778

read/write range with

MVTACLO or MVFACLO instruction

1.5 Program Counter

The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R CPU instruction starts with evennumbered addresses, the LSB (bit 31) is always "0". At reset release, the value of the PC is "H’0000 0000."

b31

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1.6 Data Format

1.6.1 Data Type

The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16, and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2's complements.

CPU PROGRAMMING MODEL

1.6 Data Format

signed byte (8-bit) integer

unsigned byte (8-bit) integer

signed halfword (16-bit) integer

unsigned halfword (16-bit) integer

signed word (32-bit) integer

unsigned word (32-bit) integer

floating-point single precision values

Figure 1.6.1 Data Type

b0 8 9 b31

SE F

b7b0

b15

S: Sign bit E: Exponent field F: Fraction field

b31

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1.6.2 Data Format

(1) Data format in a register

The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded into the register. When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and the 8-bit data on the LSB side of the register are stored into memory by the ST, STH and STB instructions, respectively.

CPU PROGRAMMING MODEL

1.6 Data Format

< load >

b0 b31

sign-extention (LDH instruction) or zero-extention (LDUH instruction)

b0 b31

< store >

b0 b31

sign-extention (LDB instruction) or zero-extention (LDUB

instruction)

from memory (LD instruction

word

from memory (LDH, LDUH

(LDB, LDUB instruction)

halfword

)

to memory (STB instruction)

halfword

to memory (STH instruction)

from memory

byte

instruction)

byte

Figure 1.6.2 Data Format in a Register

to memory (ST

instruction)

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(2) Data format in memory

The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word boundary, an address exception occurs.

CPU PROGRAMMING MODEL

1.6 Data Format

Address

+0 address +1 address +2 address +3 address

b0 b31

byte

half word

word

Figure 1.6.3 Data Format in Memory

7 8 15 16 23 24

byte

halfword

word

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1.7 Addressing Mode

M32R-FPU supports the following addressing modes.

(1) Register direct [R or CR]

The general-purpose register or the control register to be processed is specified.

(2) Register indirect [@R]

The contents of the register specify the address of the memory. This mode can be used by all load/store instructions.

(3) Register relative indirect [@(disp, R)]

(The contents of the register) + (16-bit immediate value which is signextended to 32 bits) specify the address of the memory.

(4) Register indirect and register update

CPU PROGRAMMING MODEL

1.7 Addressing Mode

• Adds 4 to register contents [@R+] The contents of the register specify the memory address, then 4 is added to the register contents. (Can only be specified with LD instruction).

• Add 2 to register contents [@R+] [M32R-FPU extended addressing mode] The contents of the register specify the memory address, then 2 is added to the register contents. (Can only be specified with STH instruction).

• Add 4 to register contents [@+R] The contents of the register is added by 4, the register contents specify the memory address. (Can only be specified with ST instruction).

• Subtract 4 to register contents [@–R] The content of the register is decreased by 4, then the register contents specify the memory address. (Can only be specified with ST instruction).

(5) immediate [#imm]

The 4-, 5-, 8-, 16- or 24-bit immediate value.

(6) PC relative [pcdisp]

(The contents of PC) + (8, 16, or 24-bit displacement which is sign-extended to 32 bits and 2 bits left-shifted) specify the address of memory.

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CPU PROGRAMMING MODEL

1.7 Addressing Mode

This page left blank intentionally.

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CHAPTER 2

INSTRUCTION SET

2.1 Instruction set overview

2.2 Instruction format

INSTRUCTION SET

2.1 Instruction set overview

The M32R-FPU has a total of 100 instructions. The M32R-FPU has a RISC architecture. Memory is accessed by using the load/store instructions and other operations are executed by using register-to-register operation instructions. M32R CPU supports compound instructions such as " load & address update" and "store & address update" which are useful for high-speed data transfer.

2.1.1 Load/store instructions

The load/store instructions carry out data transfers between a register and a memory.

LD Load LDB Load byte LDUB Load unsigned byte LDH Load halfword LDUH Load unsigned halfword LOCK Load locked ST Store STB Store byte STH Store halfword UNLOCK Store unlocked

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INSTRUCTION SET

Three types of addressing modes can be specified for load/store instructions.

(1) Register indirect

The contents of the register specify the address. This mode can be used by all load/ store instructions.

(2) Register relative indirect

(The contents of the register) + (32-bit sign-extended 16-bit immediate value) specifies the address. This mode can be used by all except LOCK and UNLOCK instructions.

(3) Register indirect and register update

• Adds 4 to register contents [@R+] The contents of the register specify the memory address, then 4 is added to the register contents. (Can only be specified with LD instruction).

2.1 Instruction set overview

• Add 4 to register contents [@+R] The contents of the register is added by 4, the register contents specity the memory address. (Can only be specified with ST instruction).

• Subtract 4 to register contents [@–R] The content of the register is decreased by 4, then the register contents specify the memory address. (Can only be specified with ST instruction).

When accessing halfword and word size data, it is necessary to specify the address on the halfword boundary or the word boundary (Halfword size should be such that the loworder 2 bits of the address are "00" or "10", and word size should be such that the low order 2 bits of the address are "00"). If an unaligned address is specified, an address exception occurs. When accessing byte data or halfword data with load instructions, the high-order bits are sign-extended or zero-extended to 32 bits, and loaded to a register.

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INSTRUCTION SET

2.1.2 Transfer instructions

The transfer instructions carry out data transfers between registers or a register and an immediate value.

LD24 Load 24-bit immediate LDI Load immediate MV Move register MVFC Move from control register MVTC Move to control register SETH Set high-order 16-bit

2.1.3 Operation instructions

Compare, arithmetic/logic operation, multiply and divide, and shift are carried out between registers.

2.1 Instruction set overview

• compare instructions

CMP Compare CMPI Compare immediate CMPU Compare unsigned CMPUI Compare unsigned immediate

• arithmetic operation instructions

ADD Add ADD3 Add 3-operand ADDI Add immediate ADDV Add with overflow checking ADDV3 Add 3-operand with overflow checking ADDX Add with carry NEG Negate SUB Subtract SUBV Subtract with overflow checking SUBX Subtract with borrow

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• logic operation instructions

AND AND AND3 AND 3-operand NOT Logical NOT OR OR OR3 OR 3-operand XOR Exclusive OR XOR3 Exclusive OR 3-operand

• multiply/divide instructions

DIV Divide DIVU Divide unsigned MUL Multiply REM Remainder REMU Remainder unsigned

• shift instructions

SLL Shift left logical SLL3 Shift left logical 3-operand SLLI Shift left logical immediate SRA Shift right arithmetic SRA3 Shift right arithmetic 3-operand SRAI Shift right arithmetic immediate SRL Shift right logical SRL3 Shift right logical 3-operand SRLI Shift right logical immediate

INSTRUCTION SET

2.1 Instruction set overview

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2.1.4 Branch instructions

The branch instructions are used to change the program flow.

BC Branch on C-bit BEQ Branch on equal to BEQZ Branch on equal to zero BGEZ Branch on greater than or equal to zero BGTZ Branch on greater than zero BL Branch and link BLEZ Branch on less than or equal to zero BLTZ Branch on less than zero BNC Branch on not C-bit BNE Branch on not equal to BNEZ Branch on not equal to zero BRA Branch JL Jump and link JMP Jump NOP No operation

INSTRUCTION SET

2.1 Instruction set overview

Only a word-aligned (word boundary) address can be specified for the branch address.

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+ 164 hidden pages

Renesas M32R-FPU User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

REVISION HISTORY

Table of contents

1.1 CPU Register

1.2 General-purpose Registers

1.3 Control Registers

1.3.1 Processor Status Word Register: PSW (CR0)

1.3.2 Condition Bit Register: CBR (CR1)

1.3.3 Interrupt Stack Pointer: SPI (CR2) User Stack Pointer: SPU (CR3)

1.3.4 Backup PC: BPC (CR6)

1.3.5 Floating-point Status Register: FPSR (CR7)

1.3.6 Floating-point Exceptions (FPE)

1.4 Accumulator

1.5 Program Counter

1.6 Data Format

1.6.1 Data Type

1.6.2 Data Format

1.7 Addressing Mode

2.1 Instruction set overview

2.1.1 Load/store instructions

2.1.2 Transfer instructions

2.1.3 Operation instructions

2.1.4 Branch instructions