Renesas M32R/ECU Series User Manual

To all our customers

Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas

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Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been

made to the contents of the document, and these changes do not constitute any alteration to the

contents of the document itself.

Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices

and power devices.

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

Mitsubishi 32-Bit RISC Single-Chip Microcomputers

32180

M32R Family M32R/ECU Series

32180

Group

User's Manual

http://www.infomicom.maec.co.jp/

The latest version of this manual is published at the Mitsubishi microcomputer home
page shown above. Please make sure you are using the latest version of the manual.

Rev. 1.0

Jan. 24, 2003

Keep safety first in your circuit designs!

•

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor prod­ucts better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appro­priate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non­flammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

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Mitsubishi Electric Corporation or a third party .

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Revision History

32180 Group User’s Manual

Rev. Date of Issue

Page Changes Made

1.0 Jan. 24, 2 0 03 – First edition issued

Contents of Revision

(1/1)

0000000000000

Before Use

• Guide to Understanding the Register Table

(1) Bit number: Indicates a register’s bit number.
(2) Register border: The registers enclosed with thick border lines must be accessed in halfwords or words.
(3) Status after reset: The initial state of each register after reset is indicated in hexadecimal or binary.
(4) Status after reset: The initial state of each register after reset is indicated bitwise.

0: This bit is “0” after reset.
1: This bit is “1” after reset.

?: This bit is undefined after reset.
(5) The shaded bits mean that they have no functions assigned.
(6) Read conditions:

R: This bit can be accessed for read.

?: The value read from this bit is undefined. (Reading this bit has no effect.)

0: The value read from this bit is always “0”.

1: The value read from this bit is always “1”.
(7) Write conditions:

W: This bit can be accessed for write.

N: This bit is write protected.

0: To write to this bit, always write “0”.

1: To write to this bit, always write “1”.

–: Writing to this bit has no effect. (It does not matter whether this bit is set to “0” or “1” by writing in software.)

Note: Care must be taken when writing to this bit. See Note in each register table.

XXXRegister(XXX) <Address: H’XXXX XXXX>

b01234567891011121314b15

AAA BBB CCC

000

b Bit name Function R W
0 AAA 0 :

• • • • • • • • • bit 1 : • • • • • • • • • bit

1 BBB 0 :

• • • • • • • • • bit 1 : • • • • • • • • • bit

2 CCC 0 :

• • • • • • • • • bit 1 : • • • • • • • • • bit

3–15 No function assigned. Fix to “0”.00

Note 1: Only writing “0” is effective. Writing “1” has no effect, in which case the bit retains the value it had before the write.

• Notation of active-low pins (signals)

(1)

(5)

(3)

<After reset: H’0000>

• • • • • • • • • bit R W

• • • • • • • • • bit R W

• • • • • • • • • bit R (Note 1)

(2)

(4)

(6) (7)

The symbol “#” suffixed to the pin (or signal) names means that the pins (or signals) are active-low.

Table of contents

CHAPTER 1 OVERVIEW

1.1 Outline of the 32180 Group ---------------------------------------------------------------------------------------------1-2

1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU) ---------------------------------------------1-2

1.1.2 1.1.2 Built-in Multiplier/Accumulator ----------------------------------------------------------------------1-3

1.1.3 Built-in Single-precision FPU --------------------------------------------------------------------------------1-3

1.1.4 Built-in Flash Memory and RAM----------------------------------------------------------------------------1-3

1.1.5 Built-in Clock Frequency Multiplier-------------------------------------------------------------------------1-4

1.1.6 Powerful Peripheral Functions Built-in --------------------------------------------------------------------1-4

1.2 Block Diagram--------------------------------------------------------------------------------------------------------------1-5

1.3 Pin Functions ---------------------------------------------------------------------------------------------------------------1-8

1.4 Pin Assignments -----------------------------------------------------------------------------------------------------------1-14

CHAPTER 2 CPU

2.1 CPU Registers -------------------------------------------------------------------------------------------------------------2-2

2.2 General-purpose Registers ---------------------------------------------------------------------------------------------2-2

2.3 Control Registers ----------------------------------------------------------------------------------------------------------2-2

2.3.1 Processor Status Word Register: PSW (CR0) ---------------------------------------------------------- 2-3

2.3.2 Condition Bit Register: CBR (CR1) ------------------------------------------------------------------------2-4

2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)-------------------------2-4

2.3.4 Backup PC: BPC (CR6) --------------------------------------------------------------------------------------2-4

2.3.5 Floating-point Status Register: FPSR (CR7) ------------------------------------------------------------2-5

2.4 Accumulator-----------------------------------------------------------------------------------------------------------------2-7

2.5 Program Counter ----------------------------------------------------------------------------------------------------------2-7

2.6 Data Formats ---------------------------------------------------------------------------------------------------------------2-8

2.6.1 Data Types-------------------------------------------------------------------------------------------------------2-8

2.6.2 Data Formats ---------------------------------------------------------------------------------------------------- 2-9

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution -----------------2-14

2.8 Precautions on CPU -----------------------------------------------------------------------------------------------------2-14

CHAPTER 3 ADDRESS SPACE

3.1 Outline of the Address Space ------------------------------------------------------------------------------------------3-2

3.2 Operation Modes ----------------------------------------------------------------------------------------------------------3-4

3.3 Internal ROM and Extended External Areas------------------------------------------------------------------------3-5

3.3.1 Internal ROM Area ---------------------------------------------------------------------------------------------3-5

3.3.2 Extended External Area --------------------------------------------------------------------------------------3-5

3.4 Internal RAM and SFR Areas ------------------------------------------------------------------------------------------3-6

3.4.1 Internal RAM Area ---------------------------------------------------------------------------------------------3-6

3.4.2 SFR (Special Function Register) Area --------------------------------------------------------------------3-6

3.5 EIT Vector Entry -----------------------------------------------------------------------------------------------------------3-35

3.6 ICU Vector Table ----------------------------------------------------------------------------------------------------------3-36

3.7 Notes on Address Space ------------------------------------------------------------------------------------------------3-38

(1)

CHAPTER 4 EIT

4.1 Outline of EIT ---------------------------------------------------------------------------------------------------------------4-2

4.2 EIT Events ------------------------------------------------------------------------------------------------------------------4-3

4.2.1 Exception ---------------------------------------------------------------------------------------------------------4-3

4.2.2 Interrupt -----------------------------------------------------------------------------------------------------------4-5

4.2.3 Trap ----------------------------------------------------------------------------------------------------------------4-6

4.3 EIT Processing Procedure ----------------------------------------------------------------------------------------------4-6

4.4 EIT Processing Mechanism---------------------------------------------------------------------------------------------4-7

4.5 Acceptance of EIT Events-----------------------------------------------------------------------------------------------4-8

4.6 Saving and Restoring the PC and PSW -----------------------------------------------------------------------------4-8

4.7 EIT Vector Entry -----------------------------------------------------------------------------------------------------------4-10

4.8 Exception Processing ----------------------------------------------------------------------------------------------------4-11

4.8.1 Reserved Instruction Exception (RIE)---------------------------------------------------------------------4-11

4.8.2 Address Exception (AE) --------------------------------------------------------------------------------------4-12

4.8.3 Floating-Point Exception (FPE) -----------------------------------------------------------------------------4-13

4.9 Interrupt Processing ------------------------------------------------------------------------------------------------------4-15

4.9.1 Reset Interrupt (RI) --------------------------------------------------------------------------------------------4-15

4.9.2 System Break Interrupt (SBI)--------------------------------------------------------------------------------4-15

4.9.3 External Interrupt (EI) -----------------------------------------------------------------------------------------4-17

4.10 Trap Processing----------------------------------------------------------------------------------------------------------4-18

4.10.1 Trap ----------------------------------------------------------------------------------------------------------------4-18

4.11 EIT Priority Levels -------------------------------------------------------------------------------------------------------4-19

4.12 Example of EIT Processing -------------------------------------------------------------------------------------------4-20

4.13 Precautions on EIT ------------------------------------------------------------------------------------------------------4-22

CHAPTER 5 INTERRUPT CONTROLLER (ICU)

5.1 Outline of the Interrupt Controller--------------------------------------------------------------------------------------5-2

5.2 ICU Related Registers ---------------------------------------------------------------------------------------------------5-4

5.2.1 Interrupt Vector Register -------------------------------------------------------------------------------------5-5

5.2.2 Interrupt Request Mask Register --------------------------------------------------------------------------- 5-6

5.2.3 SBI (System Break Interrupt) Control Register ---------------------------------------------------------5-7

5.2.4 Interrupt Control Registers ----------------------------------------------------------------------------------- 5-8

5.3 Interrupt Request Sources in Internal Peripheral I/O -------------------------------------------------------------5-11

5.4 ICU Vector Table ----------------------------------------------------------------------------------------------------------5-12

5.5 Description of Interrupt Operation -------------------------------------------------------------------------------------5-13

5.5.1 Acceptance of Internal Peripheral I/O Interrupts -------------------------------------------------------5-13

5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers -------------------------------------------- 5-15

5.6 Description of System Break Interrupt (SBI) Operation---------------------------------------------------------- 5-18

5.6.1 Acceptance of SBI ---------------------------------------------------------------------------------------------5-18

5.6.2 SBI Processing by Handler ---------------------------------------------------------------------------------- 5-18

CHAPTER 6 INTERNAL MEMORY

6.1 Outline of the Internal Memory -----------------------------------------------------------------------------------------6-2

6.2 Internal RAM----------------------------------------------------------------------------------------------------------------6-2

6.3 Internal Flash Memory ---------------------------------------------------------------------------------------------------6-2

6.4 Registers Associated with the Internal Flash Memory -----------------------------------------------------------6-4

6.4.1 Flash Mode Register ------------------------------------------------------------------------------------------6-4

(2)

6.4.2 Flash Status Registers ---------------------------------------------------------------------------------------- 6-5

6.4.3 Flash Status Register 2 (FSTAT2) ------------------------------------------------------------------------- 6-5

6.4.4 Flash Control Registers---------------------------------------------------------------------------------------6-7

6.4.5 Virtual Flash S Bank Registers -----------------------------------------------------------------------------6-11

6.5 Programming the Internal Flash Memory----------------------------------------------------------------------------6-12

6.5.1 Outline of Internal Flash Memory Programming --------------------------------------------------------6-12

6.5.2 Controlling Operation Modes during Flash Programming --------------------------------------------6-17

6.5.3 P8 Data Register ----------------------------------------------------------------------------------------------- 6-18

6.5.4 Procedure for Programming/Erasing the Internal Flash Memory-----------------------------------6-20

6.5.5 Flash Programming Time (Reference)--------------------------------------------------------------------6-29

6.6 Virtual Flash Emulation Function --------------------------------------------------------------------------------------6-30

6.6.1 Virtual Flash Emulation Area --------------------------------------------------------------------------------6-31

6.6.2 Entering Virtual Flash Emulation Mode -------------------------------------------------------------------6-33

6.6.3 Application Example of Virtual Flash Emulation Mode------------------------------------------------6-34

6.7 Connecting to A Serial Programmer ----------------------------------------------------------------------------------6-36

6.8 Internal Flash Memory Protect Function-----------------------------------------------------------------------------6-38

6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory --------------------------------------6-39

CHAPTER 7 RESET

7.1 Outline of Reset------------------------------------------------------------------------------------------------------------7-2

7.2 Reset Operation -----------------------------------------------------------------------------------------------------------7-2

7.2.1 Reset at Power-on ---------------------------------------------------------------------------------------------7-3

7.2.2 Reset during Operation ---------------------------------------------------------------------------------------7-3

7.2.3 Reset at Entering RAM Backup Mode --------------------------------------------------------------------7-3

7.2.4 Reset Vector Relocation during Flash Programming--------------------------------------------------7-3

7.3 Internal State Immediately after Reset -------------------------------------------------------------------------------7-4

7.4 Things to Be Considered after Reset---------------------------------------------------------------------------------7-4

CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8.1 Outline of Input/Output Ports ------------------------------------------------------------------------------------------- 8-2

8.2 Selecting Pin Functions --------------------------------------------------------------------------------------------------8-3

8.3 Input/Output Port Related Registers----------------------------------------------------------------------------------8-5

8.3.1 Port Data Registers -------------------------------------------------------------------------------------------- 8-7

8.3.2 Port Direction Registers --------------------------------------------------------------------------------------8-8

8.3.3 Port Operation Mode Registers-----------------------------------------------------------------------------8-9

8.3.4 Port Peripheral Output Select Registers------------------------------------------------------------------8-20

8.3.5 Port Input Special Function Control Register------------------------------------------------------------ 8-21

8.4 Port Input Level Switching Function ---------------------------------------------------------------------------------- 8-24

8.5 Port Peripheral Circuits --------------------------------------------------------------------------------------------------8-27

8.6 Precautions on Input/Output Ports ------------------------------------------------------------------------------------8-31

CHAPTER 9 DMAC

9.1 Outline of the DMAC------------------------------------------------------------------------------------------------------9-2

9.2 DMAC Related Registers------------------------------------------------------------------------------------------------9-4

9.2.1 DMA Channel Control Registers ---------------------------------------------------------------------------9-6

9.2.2 DMA Software Request Generation Registers----------------------------------------------------------9-18

9.2.3 DMA Source Address Registers----------------------------------------------------------------------------9-19

(3)

9.2.4 DMA Destination Address Registers ---------------------------------------------------------------------- 9-20

9.2.5 DMA Transfer Count Registers -----------------------------------------------------------------------------9-21

9.2.6 DMA Interrupt Related Registers---------------------------------------------------------------------------9-22

9.3 Functional Description of the DMAC----------------------------------------------------------------------------------9-27

9.3.1 DMA Transfer Request Sources----------------------------------------------------------------------------9-27

9.3.2 DMA Transfer Processing Procedure ---------------------------------------------------------------------9-33

9.3.3 Starting DMA ---------------------------------------------------------------------------------------------------- 9-34

9.3.4 DMA Channel Priority -----------------------------------------------------------------------------------------9-34

9.3.5 Gaining and Releasing Control of the Internal Bus ----------------------------------------------------9-34

9.3.6 Transfer Units ---------------------------------------------------------------------------------------------------9-35

9.3.7 Transfer Counts-------------------------------------------------------------------------------------------------9-35

9.3.8 Address Space--------------------------------------------------------------------------------------------------9-35

9.3.9 Transfer Operation --------------------------------------------------------------------------------------------- 9-35

9.3.10 End of DMA and Interrupt ------------------------------------------------------------------------------------ 9-37

9.3.11 Each Register Status after Completion of DMA Transfer --------------------------------------------9-37

9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------9-38

CHAPTER 10 MULTIJUNCTION TIMERS

10.1 Outline of Multijunction Timers --------------------------------------------------------------------------------------- 10-2

10.2 Common Units of Multijunction Timers -----------------------------------------------------------------------------10-9

10.2.1 MJT Common Unit Register Map--------------------------------------------------------------------------10-10

10.2.2 Prescaler Unit -------------------------------------------------------------------------------------------------- 10-12

10.2.3 Clock Bus and Input/Output Event Bus Control Unit -------------------------------------------------10-13

10.2.4 Input Processing Control Unit ------------------------------------------------------------------------------10-17

10.2.5 Output Flip-flop Control Unit --------------------------------------------------------------------------------10-26

10.2.6 Interrupt Control Unit -----------------------------------------------------------------------------------------10-35

10.3 TOP (Output-Related 16-Bit Timer) ---------------------------------------------------------------------------------10-64

10.3.1 Outline of TOP --------------------------------------------------------------------------------------------------10-64

10.3.2 Outline of Each Mode of TOP -------------------------------------------------------------------------------10-66

10.3.3 TOP Related Register Map ----------------------------------------------------------------------------------10-68

10.3.4 TOP Control Registers ----------------------------------------------------------------------------------------10-70

10.3.5 TOP Counters (TOP0CT–TOP10CT) ---------------------------------------------------------------------10-75

10.3.6 TOP Reload Registers (TOP0RL–TOP10RL)-----------------------------------------------------------10-76

10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) -----------------------------------------------------10-77

10.3.8 TOP Enable Control Registers ------------------------------------------------------------------------------10-78

10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)--------------------------10-80

10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function)--------------10-86

10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) ---------------------10-91

10.4 TIO (Input/Output-Related 16-Bit Timer)---------------------------------------------------------------------------10-94

10.4.1 Outline of TIO ---------------------------------------------------------------------------------------------------10-94

10.4.2 Outline of Each Mode of TIO --------------------------------------------------------------------------------10-96

10.4.3 TIO Related Register Map -----------------------------------------------------------------------------------10-99

10.4.4 TIO Control Registers -----------------------------------------------------------------------------------------10-101

10.4.5 TIO Counters (TIO0CT–TIO9CT) -------------------------------------------------------------------------- 10-109

10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0)--------------------------------------------- 10-110

10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) ----------------------------------------------------------10-111

10.4.8 TIO Enable Control Registers -------------------------------------------------------------------------------10-112

10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes -------------------------------------------- 10-114

(4)

10.4.10 Operation in TIO Noise Processing Input Mode--------------------------------------------------------10-116

10.4.11 Operation in TIO PWM Output Mode----------------------------------------------------------------------10-117

10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function)-----------------------10-120

10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function)-----------10-122

10.4.14 Operation in TIO Continuous Output Mode (without Correction Function)----------------------- 10-124

10.5 TMS (Input-Related 16-Bit Timer) ----------------------------------------------------------------------------------- 10-126

10.5.1 Outline of TMS --------------------------------------------------------------------------------------------------10-126

10.5.2 Outline of TMS Operation ------------------------------------------------------------------------------------ 10-126

10.5.3 TMS Related Register Map ----------------------------------------------------------------------------------10-128

10.5.4 TMS Control Registers----------------------------------------------------------------------------------------10-129

10.5.5 TMS Counters (TMS0CT, TMS1CT) ----------------------------------------------------------------------10-130

10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0) ----------------------------------------------10-130

10.5.7 Operation of TMS Measure Input -------------------------------------------------------------------------- 10-131

10.6 TML (Input-Related 32-Bit Timer)------------------------------------------------------------------------------------10-132

10.6.1 Outline of TML -------------------------------------------------------------------------------------------------- 10-132

10.6.2 Outline of TML Operation ------------------------------------------------------------------------------------ 10-133

10.6.3 TML Related Register Map ----------------------------------------------------------------------------------10-133

10.6.4 TML Control Registers ----------------------------------------------------------------------------------------10-134

10.6.5 TML Counters ---------------------------------------------------------------------------------------------------10-135

10.6.6 TML Measure Registers --------------------------------------------------------------------------------------10-135

10.6.7 Operation of TML Measure Input --------------------------------------------------------------------------- 10-136

10.7 TID (Input-Related 16-Bit Timer)-------------------------------------------------------------------------------------10-138

10.7.1 Outline of TID----------------------------------------------------------------------------------------------------10-138

10.7.2 TID Related Register Map ----------------------------------------------------------------------------------- 10-140

10.7.3 TID Control & Prescaler Enable Registers ---------------------------------------------------------------10-141

10.7.4 TID Counters (TID0CT, TID1CT and TID2CT)---------------------------------------------------------- 10-144

10.7.5 TID Reload Registers (TID0RL, TID0RL and TID2RL) -----------------------------------------------10-144

10.7.6 Outline of Each Mode of TID --------------------------------------------------------------------------------10-145

10.8 TOU (Output-Related 24-Bit Timer) --------------------------------------------------------------------------------- 10-150

10.8.1 Outline of TOU --------------------------------------------------------------------------------------------------10-150

10.8.2 Outline of Each Mode of TOU -------------------------------------------------------------------------------10-152

10.8.3 TOU Related Register Map ----------------------------------------------------------------------------------10-154

10.8.4 TOU Control Registers----------------------------------------------------------------------------------------10-158

10.8.5 TOU Counters---------------------------------------------------------------------------------------------------10-161

10.8.6 TOU Reload Registers ----------------------------------------------------------------------------------------10-164

10.8.7 TOU Enable Protect Registers ------------------------------------------------------------------------------10-168

10.8.8 TOU Count Enable Registers -------------------------------------------------------------------------------10-169

10.8.9 PWMOFF Input Processing Control Registers---------------------------------------------------------- 10-171

10.8.10 PWM Output Control Registers-----------------------------------------------------------------------------10-174

10.8.11 PWM Output Disable Level Control Registers ----------------------------------------------------------10-177

10.8.12 Operation in TOU PWM Output Mode --------------------------------------------------------------------10-179

10.8.13 Operation in TOU Single-shot PWM Output Mode (without Correction Function) -------------10-184

10.8.14 Operation in TOU Delayed Single-shot Output Mode (without Correction Function) --------------10-186

10.8.15 Operation in TOU Single-shot Output Mode (without Correction Function) ---------------------10-188

10.8.16 Operation in TOU Continuous Output Mode (without Correction Function) ---------------------10-190

10.8.17 0 % or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes -10-192

10.8.18 PWM Output Disable Function------------------------------------------------------------------------------10-197

10.8.19 Example Application for Using the 32180 in Motor Control------------------------------------------10-201

(5)

CHAPTER 11 A-D CONVERTERS

11.1 Outline of A-D Converters ---------------------------------------------------------------------------------------------11-2

11.1.1 Conversion Modes ---------------------------------------------------------------------------------------------11-6

11.1.2 Operation Modes -----------------------------------------------------------------------------------------------11-6

11.1.3 Special Operation Modes ------------------------------------------------------------------------------------ 11-9

11.1.4 A-D Converter Interrupt and DMA Transfer Requests ------------------------------------------------11-12

11.1.5 Sample-and-Hold Function-----------------------------------------------------------------------------------11-12

11.2 A-D Converter Related Registers------------------------------------------------------------------------------------11-13

11.2.1 A-D Single Mode Registers 0 ------------------------------------------------------------------------------- 11-16

11.2.2 A-D Single Mode Registers 1 ------------------------------------------------------------------------------- 11-18

11.2.3 A-D Scan Mode Registers 0 ---------------------------------------------------------------------------------11-20

11.2.4 A-D Scan Mode Registers 1 ---------------------------------------------------------------------------------11-22

11.2.5 A-D Conversion Speed Control Registers --------------------------------------------------------------- 11-24

11.2.6 A-D Disconnection Detection Assist Function Control Registers----------------------------------- 11-25

11.2.7 A-D Disconnection Detection Assist Method Select Registers -------------------------------------11-26

11.2.8 A-D Successive Approximation Registers ---------------------------------------------------------------11-29

11.2.9 A-D Comparate Data Registers-----------------------------------------------------------------------------11-30

11.2.10 10-bit A-D Data Registers------------------------------------------------------------------------------------11-31

11.2.11 8-bit A-D Data Registers-------------------------------------------------------------------------------------- 11-32

11.3 Functional Description of A-D Converters -------------------------------------------------------------------------11-33

11.3.1 How to Find Analog Input Voltages ------------------------------------------------------------------------11-33

11.3.2 A-D Conversion by Successive Approximation Method ----------------------------------------------11-34

11.3.3 Comparator Operation ----------------------------------------------------------------------------------------11-35

11.3.4 Calculating the A-D Conversion Time --------------------------------------------------------------------- 11-36

11.3.5 Accuracy of A-D Conversion --------------------------------------------------------------------------------11-39

11.4 Inflow Current Bypass Circuit -----------------------------------------------------------------------------------------11-41

11.5 Precautions on Using A-D Converters------------------------------------------------------------------------------11-43

CHAPTER 12 SERIAL I/O

12.1 Outline of Serial I/O -----------------------------------------------------------------------------------------------------12-2

12.2 Serial I/O Related Registers ------------------------------------------------------------------------------------------12-5

12.2.1 SIO Interrupt Related Registers ----------------------------------------------------------------------------12-6

12.2.2 SIO Transmit Control Registers ----------------------------------------------------------------------------12-14

12.2.3 SIO Transmit/Receive Mode Registers -------------------------------------------------------------------12-15

12.2.4 SIO Transmit Buffer Registers ------------------------------------------------------------------------------12-18

12.2.5 SIO Receive Buffer Registers -------------------------------------------------------------------------------12-19

12.2.6 SIO Receive Control Registers -----------------------------------------------------------------------------12-20

12.2.7 SIO Baud Rate Registers ------------------------------------------------------------------------------------12-23

12.3 Transmit Operation in CSIO Mode ---------------------------------------------------------------------------------- 12-24

12.3.1 Setting the CSIO Baud Rate---------------------------------------------------------------------------------12-24

12.3.2 Initializing CSIO Transmission ------------------------------------------------------------------------------12-25

12.3.3 Starting CSIO Transmission ---------------------------------------------------------------------------------12-27

12.3.4 Successive CSIO Transmission ----------------------------------------------------------------------------12-27

12.3.5 Processing at End of CSIO Transmission---------------------------------------------------------------- 12-28

12.3.6 Transmit Interrupts ---------------------------------------------------------------------------------------------12-28

12.3.7 Transmit DMA Transfer Request ---------------------------------------------------------------------------12-28

12.3.8 Example of CSIO Transmit Operation -------------------------------------------------------------------- 12-30

(6)

12.4 Receive Operation in CSIO Mode -----------------------------------------------------------------------------------12-32

12.4.1 Initialization for CSIO Reception----------------------------------------------------------------------------12-32

12.4.2 Starting CSIO Reception -------------------------------------------------------------------------------------12-34

12.4.3 Processing at End of CSIO Reception --------------------------------------------------------------------12-34

12.4.4 About Successive Reception --------------------------------------------------------------------------------12-35

12.4.5 Flags Showing the Status of CSIO Receive Operation -----------------------------------------------12-36

12.4.6 Example of CSIO Receive Operation ---------------------------------------------------------------------12-37

12.5 Precautions on Using CSIO Mode-----------------------------------------------------------------------------------12-39

12.6 Transmit Operation in UART Mode ---------------------------------------------------------------------------------12-40

12.6.1 Setting the UART Baud Rate --------------------------------------------------------------------------------12-40

12.6.2 UART Transmit/Receive Data Formats-------------------------------------------------------------------12-40

12.6.3 Initializing UART Transmission -----------------------------------------------------------------------------12-42

12.6.4 Starting UART Transmission --------------------------------------------------------------------------------12-44

12.6.5 Successive UART Transmission --------------------------------------------------------------------------- 12-44

12.6.6 Processing at End of UART Transmission ---------------------------------------------------------------12-44

12.6.7 Transmit Interrupts ---------------------------------------------------------------------------------------------12-44

12.6.8 Transmit DMA Transfer Request ---------------------------------------------------------------------------12-45

12.6.9 Example of UART Transmit Operation--------------------------------------------------------------------12-46

12.7 Receive Operation in UART Mode ---------------------------------------------------------------------------------- 12-48

12.7.1 Initialization for UART Reception ---------------------------------------------------------------------------12-48

12.7.2 Starting UART Reception ------------------------------------------------------------------------------------ 12-50

12.7.3 Processing at End of UART Reception -------------------------------------------------------------------12-50

12.7.4 Example of UART Receive Operation -------------------------------------------------------------------- 12-52

12.7.5 Start Bit Detection during UART Reception--------------------------------------------------------------12-54

12.8 Fixed Period Clock Output Function --------------------------------------------------------------------------------12-55

12.9 Precautions on Using UART Mode----------------------------------------------------------------------------------12-56

CHAPTER 13 CAN MODULE

13.1 Outline of the CAN Module --------------------------------------------------------------------------------------------13-2

13.2 CAN Module Related Registers --------------------------------------------------------------------------------------13-4

13.2.1 CAN Control Registers----------------------------------------------------------------------------------------13-15

13.2.2 CAN Status Registers -----------------------------------------------------------------------------------------13-18

13.2.3 CAN Frame Format Select Registers ---------------------------------------------------------------------13-21

13.2.4 CAN Configuration Registers--------------------------------------------------------------------------------13-22

13.2.5 CAN Timestamp Count Registers --------------------------------------------------------------------------13-24

13.2.6 CAN Error Count Registers ----------------------------------------------------------------------------------13-25

13.2.7 CAN Baud Rate Prescalers ----------------------------------------------------------------------------------13-26

13.2.8 CAN Interrupt Related Registers ---------------------------------------------------------------------------13-27

13.2.9 CAN Cause of Error Registers ------------------------------------------------------------------------------13-45

13.2.10 CAN Mode Registers------------------------------------------------------------------------------------------13-46

13.2.11 CAN DMA Transfer Request Select Registers---------------------------------------------------------- 13-47

13.2.12 CAN Mask Registers ------------------------------------------------------------------------------------------13-48

13.2.13 CAN Single-Shot Mode Control Registers ---------------------------------------------------------------13-52

13.2.14 CAN Message Slot Control Registers---------------------------------------------------------------------13-53

13.2.15 CAN Message Slots -------------------------------------------------------------------------------------------13-57

13.3 CAN Protocol -------------------------------------------------------------------------------------------------------------13-72

13.3.1 CAN Protocol Frames -----------------------------------------------------------------------------------------13-72

13.3.2 Data Formats during CAN Transmission/Reception---------------------------------------------------13-73

(7)

13.3.3 CAN Controller Error States ---------------------------------------------------------------------------------13-74

13.4 Initializing the CAN Module-------------------------------------------------------------------------------------------- 13-75

13.4.1 Initializing the CAN Module ----------------------------------------------------------------------------------13-75

13.5 Transmitting Data Frames ---------------------------------------------------------------------------------------------13-78

13.5.1 Data Frame Transmit Procedure ---------------------------------------------------------------------------13-78

13.5.2 Data Frame Transmit Operation ----------------------------------------------------------------------------13-79

13.5.3 Transmit Abort Function --------------------------------------------------------------------------------------13-80

13.6 Receiving Data Frames ------------------------------------------------------------------------------------------------13-81

13.6.1 Data Frame Receive Procedure ----------------------------------------------------------------------------13-81

13.6.2 Data Frame Receive Operation-----------------------------------------------------------------------------13-82

13.6.3 Reading Out Received Data Frames ---------------------------------------------------------------------- 13-84

13.7 Transmitting Remote Frames-----------------------------------------------------------------------------------------13-86

13.7.1 Remote Frame Transmit Procedure -----------------------------------------------------------------------13-86

13.7.2 Remote Frame Transmit Operation------------------------------------------------------------------------13-87

13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission-------------13-89

13.8 Receiving Remote Frames --------------------------------------------------------------------------------------------13-91

13.8.1 Remote Frame Receive Procedure ------------------------------------------------------------------------13-91

13.8.2 Remote Frame Receive Operation ------------------------------------------------------------------------13-92

13.9 Precautions about CAN Module--------------------------------------------------------------------------------------13-94

CHAPTER 14 REAL TIME DEBUGGER (RTD)

14.1 Outline of the Real-Time Debugger (RTD) ------------------------------------------------------------------------14-2

14.2 Pin Functions of the RTD ----------------------------------------------------------------------------------------------14-3

14.3 Functional Description of the RTD-----------------------------------------------------------------------------------14-4

14.3.1 Outline of the RTD Operation ------------------------------------------------------------------------------ 14-4

14.3.2 Operation of RDR (Real-time RAM Content Output) ------------------------------------------------- 14-4

14.3.3 Operation of the WRR (RAM Content Forcible Rewrite)---------------------------------------------14-6

14.3.4 Operation of VER (Continuous Monitor) -----------------------------------------------------------------14-7

14.3.5 Operation of VEI (Interrupt Request) ---------------------------------------------------------------------14-7

14.3.6 Operation of RCV (Recover from Runaway) -----------------------------------------------------------14-8

14.3.7 Method for Setting a Specified Address when Using the RTD -------------------------------------14-9

14.3.8 Resetting the RTD--------------------------------------------------------------------------------------------- 14-10

14.4 Typical Connection with the Host ------------------------------------------------------------------------------------14-11

CHAPTER 15 EXTERNAL BUS INTERFACE

15.1 Outline of the External Bus Interface -------------------------------------------------------------------------------15-2

15.1.1 External Bus Interface Related Signals ------------------------------------------------------------------15-2

15.2 External Bus Interface Related Registers -------------------------------------------------------------------------15-4

15.2.1 Port Operation Mode Registers ----------------------------------------------------------------------------15-4

15.2.2 Port Peripheral Output Select Register ------------------------------------------------------------------15-8

15.2.3 Bus Mode Control Register ---------------------------------------------------------------------------------15-9

15.3 Read/Write Operations -------------------------------------------------------------------------------------------------15-10

15.4 Bus Arbitration ------------------------------------------------------------------------------------------------------------ 15-16

15.5 Typical Connection of External Extension Memory ------------------------------------------------------------- 15-18

15.6 Example of Bus Voltage Settings Using VCC-BUS -------------------------------------------------------------15-21

CHAPTER 16 WAIT CONTROLLER

(8)

16.1 Outline of the Wait Controller -----------------------------------------------------------------------------------------16-2

16.2 Wait Controller Related Registers -----------------------------------------------------------------------------------16-4

16.2.1 CS Area Wait Control Registers ----------------------------------------------------------------------------16-4

16.3 Typical Operation of the Wait Controller ---------------------------------------------------------------------------16-6

CHAPTER 17 RAM BACKUP MODE

17.1 Outline of RAM Backup Mode ----------------------------------------------------------------------------------------17-2

17.2 Example of RAM Backup when Power is Down -----------------------------------------------------------------------17-3

17.2.1 Normal Operating State---------------------------------------------------------------------------------------17-3

17.2.2 RAM Backup State ---------------------------------------------------------------------------------------------17-4

17.3 Example of RAM Backup for Saving Power Consumption ----------------------------------------------------17-5

17.3.1 Normal Operating State---------------------------------------------------------------------------------------17-5

17.3.2 RAM Backup State ---------------------------------------------------------------------------------------------17-6

17.3.3 Precautions to Be Observed at Power-On ---------------------------------------------------------------17-7

17.4 Exiting RAM Backup Mode (Wakeup) ------------------------------------------------------------------------------17-8

CHAPTER 18 OSCILLATOR CIRCUIT

18.1 Oscillator Circuit----------------------------------------------------------------------------------------------------------18-2

18.1.1 Example of an Oscillator Circuit ----------------------------------------------------------------------------18-2

18.1.2 XIN Oscillation Stoppage Detection Circuit --------------------------------------------------------------18-3

18.1.3 Oscillation Drive Capability Select Function -------------------------------------------------------------18-5

18.1.4 System Clock Output Function------------------------------------------------------------------------------18-7

18.1.5 Oscillation Stabilization Time at Power-On -------------------------------------------------------------- 18-7

18.2 Clock Generator Circuit ------------------------------------------------------------------------------------------------18-8

CHAPTER 19 JTAG

19.1 Outline of JTAG ----------------------------------------------------------------------------------------------------------19-2

19.2 Configuration of the JTAG Circuit------------------------------------------------------------------------------------19-3

19.3 JTAG Registers ----------------------------------------------------------------------------------------------------------19-4

19.3.1 Instruction Register (JTAGIR)-------------------------------------------------------------------------------19-4

19.3.2 Data Register----------------------------------------------------------------------------------------------------19-5

19.4 Basic Operation of JTAG ----------------------------------------------------------------------------------------------19-6

19.4.1 Outline of JTAG Operation -----------------------------------------------------------------------------------19-6

19.4.2 IR Path Sequence ---------------------------------------------------------------------------------------------- 19-8

19.4.3 DR Path Sequence -------------------------------------------------------------------------------------------- 19-9

19.4.4 Inspecting and Setting Data Registers -------------------------------------------------------------------- 19-10

19.5 Boundary Scan Description Language -----------------------------------------------------------------------------19-11

19.6 Notes on Board Design when Connecting JTAG----------------------------------------------------------------------19-12

19.7 Processing Pins when Not Using JTAG----------------------------------------------------------------------------19-14

CHAPTER 20 POWER SUPPLY CIRCUIT

20.1 Configuration of the Power Supply Circuit-------------------------------------------------------------------------20-2

20.2 Power-On Sequence----------------------------------------------------------------------------------------------------20-3

20.2.1 Power-On Sequence when Not Using RAM Backup --------------------------------------------------20-3

20.2.2 Power-On Sequence when Using RAM Backup--------------------------------------------------------20-4

20.3 Power-Off Sequence----------------------------------------------------------------------------------------------------20-5

20.3.1 Power-Off Sequence when Not Using RAM Backup --------------------------------------------------20-5

20.3.2 Power-Off Sequence when Using RAM Backup -------------------------------------------------------20-6

(9)

CHAPTER 21 ELECTRICAL CHARACTERISTICS

21.1 Absolute Maximum Ratings -------------------------------------------------------------------------------------------21-2

21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz ----------------------------------------------21-3

21.2.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz)-------------------21-3

21.2.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) -----------------------------------------21-5

21.2.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) --------------------------21-6

21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz ------------------------------------------------21-7

21.3.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 8 MHz) --------------------21-7

21.3.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz)-------------------------------------------21-9

21.3.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz)---------------------------- 21-10

21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz -------------------------------------------- 21-11

21.4.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz)------21-11

21.4.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ---------------------------- 21-13

21.4.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) -------------21-14

21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz----------------------------------------------21-15

21.5.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V f(XIN) = 8 MHz) --------21-15

21.5.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) ------------------------------21-17

21.5.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz)---------------21-18

21.6 Flash Memory Related Characteristics-----------------------------------------------------------------------------21-19

21.7 A.C. Characteristics (when VCCE = 5 V) --------------------------------------------------------------------------21-20

21.7.1 Timing Requirements------------------------------------------------------------------------------------------21-20

21.7.2 Switching Characteristics-------------------------------------------------------------------------------------21-24

21.7.3 A.C. Characteristics--------------------------------------------------------------------------------------------21-27

21.8 A.C. Characteristics (when VCCE = 3.3 V) -----------------------------------------------------------------------21-36

21.8.1 Timing Requirements------------------------------------------------------------------------------------------21-36

21.8.2 Switching Characteristics-------------------------------------------------------------------------------------21-40

21.8.3 A.C. Characteristics--------------------------------------------------------------------------------------------21-43

CHAPTER 22 TYPICAL CHARACTERISTICS

To be written at a later time---------------------------------------------------------------------------------------------------22-2

APPENDIX 1 MECHANICAL SPECIFICAITONS

Appendix 1.1 Dimensional Outline Drawing ------------------------------------------------------------------- Appendix 1-2

APPENDIX 2 INSTRUCTION PROCESSING TIME

Appendix 2.1 32180 Instruction Processing Time------------------------------------------------------------ Appendix 2-2

APPENDIX 3 PROCESSING OF UNUSED PINS

Appendix 3.1 Example Processing of Unused Pins ---------------------------------------------------------- Appendix 3-2

APPENDIX 4 SUMMARY OF PRECAUTIONS

(10)

Appendix 4.1 Precautions about the CPU -------------------------------------------------------------------------- Appendix 4-2

Appendix 4.1.1 Precautions Regarding Data Transfer------------------------------------------------ Appendix 4-2

Appendix 4.2 Precautions about the Address Space ------------------------------------------------------------------ Appendix 4-3

Appendix 4.2.1 Virtual Flash Emulation Function ------------------------------------------------------- Appendix 4-3
Appendix 4.3 Precautions about EIT ------------------------------------------------------------------------------------ Appendix 4-3
Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory -------------------------- Appendix 4-3
Appendix 4.5 Precautions to Be Observed after Reset ---------------------------------------------------------------- Appendix 4-4

Appendix 4.5.1 Input/output Ports -------------------------------------------------------------------------- Appendix 4-4
Appendix 4.6 Precautions about Input/Output Ports ------------------------------------------------------------------- Appendix 4-4

Appendix 4.6.1 When Using Input/Output Ports in Output Mode ----------------------------------- Appendix 4-4

Appendix 4.6.2 About the Port Input Disable Function ------------------------------------------------ Appendix 4-4
Appendix 4.7 Precautions about the DMAC -------------------------------------------------------------------------- Appendix 4-5

Appendix 4.7.1 About Writing to the DMAC Related Registers ------------------------------------- Appendix 4-5

Appendix 4.7.2 Manipulating the DMAC Related Registers by DMA Transfer ------------------ Appendix 4-5

Appendix 4.7.3 About the DMA Interrupt Request Status Register -------------------------------- Appendix 4-5

Appendix 4.7.4 About the Stable Operation of DMA Transfer --------------------------------------- Appendix 4-5
Appendix 4.8 Precautions about the Multijunction Timers ------------------------------------------------------------ Appendix 4-6

Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode ---------------------------- Appendix 4-6

Appendix 4.8.2 Precautions on Using TOP Delayed Single-Shot Output Mode ---------------- Appendix 4-8

Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode ---------------------------- Appendix 4-9

Appendix 4.8.4 Precautions on Using TIO Measure Free-Run/Clear Input Modes ------------ Appendix 4-9

Appendix 4.8.5 Precautions on Using TIO PWM Output Mode ------------------------------------- Appendix 4-9

Appendix 4.8.6 Precautions on Using TIO Single-Shot Output Mode ----------------------------- Appendix 4-9

Appendix 4.8.7 Precautions on Using TIO Delayed Single-Shot Output Mode ----------------- Appendix 4-10

Appendix 4.8.8 Precautions on Using TIO Continuous Output Mode------------------------------ Appendix 4-10

Appendix 4.8.9 Precautions on Using TMS Measure Input ------------------------------------------ Appendix 4-10

Appendix 4.8.10 Precautions on Using TML Measure Input------------------------------------------- Appendix 4-11

Appendix 4.8.11 Precautions on Using TOU PWM Output Mode ------------------------------------ Appendix 4-12

Appendix 4.8.12 Precautions on Using TOU Single-Shot PWM Output Mode -------------------- Appendix 4-12

Appendix 4.8.13 Precautions on Using TOU Delayed Single-Shot Output Mode ---------------- Appendix 4-12

Appendix 4.8.14 Precautions on Using TOU Single-Shot Output Mode ---------------------------- Appendix 4-13

Appendix 4.8.15 Precautions on Using TOU Continuous Output Mode ---------------------------- Appendix 4-13
Appendix 4.9 Precautions about the A-D Converters ---------------------------------------------------------------- Appendix 4-14
Appendix 4.10 Precautions about Serial I/O ---------------------------------------------------------------------------- Appendix 4-17

Appendix 4.10.1 Precautions on Using CSIO Mode ---------------------------------------------------- Appendix 4-17

Appendix 4.10.2 Precautions on Using UART Mode --------------------------------------------------- Appendix 4-18
Appendix 4.11 Precautions about RAM Backup Mode --------------------------------------------------------------- Appendix 4-19

Appendix 4.11.1 Precautions to Be Observed at Power-On ------------------------------------------ Appendix 4-19
Appendix 4.12 Precautions about JTAG ------------------------------------------------------------------------------- Appendix 4-20

Appendix 4.12.1 Notes on Board Design when Connecting JTAG ---------------------------------- Appendix 4-20

Appendix 4.12.2 Processing Pins when Not Using JTAG --------------------------------------------- Appendix 4-22
Appendix 4.13 Precautions about Noise -------------------------------------------------------------------------------- Appendix 4-23

Appendix 4.13.1 Reduction of Wiring Length ------------------------------------------------------------- Appendix 4-23

Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines ------------------- Appendix 4-26

Appendix 4.13.3 Processing Analog Input Pin Wiring -------------------------------------------------- Appendix 4-26

Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin -------------------------------- Appendix 4-27

Appendix 4.13.5 Processing Input/Output Ports --------------------------------------------------------- Appendix 4-31

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This page is blank for reasons of layout.

(12)

CHAPTER 1

OVERVIEW

1.1 Outline of the 32180 Group

1.2 Block Diagram

1.3 Pin Functions

1.4 Pin Assignments

OVERVIEW

1

1.1 Outline of the 32180 Group

1.1 Outline of the 32180 Group

The 32180 group (hereafter simply the 32180) belongs to the M32R/ECU series in the M32R family of
Mitsubishi microcomputers. For details about the current development status of the 32180, please contact
your nearest office of Mitsubishi or its distributor.

Table 1.1.1 Product List

Type Name ROM Size RAM Size Package Type Operating Ambient Temperature
M32180F8VFP 1 Mbyte 48 Kbytes 240-pin QFP: 240P6Y-A (0.5 mm pitch) –40°C to 125°C (@64 MHz)
M32180F8TFP 1 Mbyte 48 Kbytes 240-pin QFP: 240P6Y-A (0.5 mm pitch) –40°C to 85°C (@80 MHz)

1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU)

(1) Based on a RISC architecture

• The 32180 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU in this group of
microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order to materialize
the common instruction set and the high-precision arithmetic operation of the M32R CPU. The 32180
products listed in the above table are built around the M32R-FPU and incorporates flash memory,
RAM and various peripheral functions, all integrated into a single chip.

• The M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store
instructions, and various arithmetic/logic operations are executed using register-to-register operation
instructions.

• The internally has sixteen 32-bit general-purpose registers. The instruction set consists of 100 dis­crete instructions in total (83 instructions common to the M32R family plus 17 FPU and extended
instructions). These instructions are either 16 bits or 32 bits long.

• In addition to the ordinary load/store instructions, the M32R-FPU supports compound instructions
such as Load & Address Update and Store & Address Update. These instructions help to speed up
data transfers.

(2) Five-stage pipelined processing

• The M32R-FPU supports five-stage pipelined instruction processing consisting of Instruction Fetch,
Decode, Execute, Memory Access and Write Back (processed in six stages when performing float­ing-point arithmetic). Not just load/store instructions and register-to-register operation instructions,
but also floating-point arithmetic instructions and compound instructions such as Load & Address
Update and Store & Address Update are executed in one CPUCLK period (which is equivalent to 12.5
ns when f(CPUCLK) = 80 MHz).

• Although instructions are supplied to the execution stage in the order in which they were fetched, it is
possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory
access, the subsequent register-to-register operation instruction will be executed before that instruc­tion. Using such a facility, which is known as the “out-of-order-completion” mechanism, the M32R­FPU is able to control instruction execution without wasting clock cycles.

(3) Compact instruction code

• The M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the
16-bit instruction format especially helps to suppress the code size of a program.

• Moreover, the availability of 32-bit instructions makes programming easier and provides higher per­formance at the same clock speed than in architectures where the address space is segmented. For
example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or backward
from the currently executed address in one instruction, making programming easy.

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32180 Group User’s Manual (Rev.1.0)

1

1.1.2 Built-in Multiplier/Accumulator

(1) Built-in high-speed multiplier

• The M32R-FPU contains a 32 bits × 16 bits high-speed multiplier which enables the M32R-FPU to
execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods.

(2) DSP-comparable sum-of-products instructions

• The M32R-FPU supports the following four types of sum-of-products calculation instructions (or multipli­cation instructions) which each can be executed in one CPUCLK period using a 56-bit accumulator.

(1) 16 high-order bits of register × 16 high-order bits of register
(2) 16 low-order bits of register × 16 low-order bits of register
(3) All 32 bits of register × 16 high-order bits of register
(4) All 32 bits of register × 16 low-order bits of register

• The M32R-FPU has some special instructions to round the value stored in the accumulator to 16 or
32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because
these instructions too are executed in one CPUCLK period, when used in combination with high­speed data transfer instructions such as Load & Address Update or Store & Address Update, they
enable the M32R-FPU to exhibit superior data processing capability comparable to that of a DSP.

OVERVIEW

1.1 Outline of the 32180 Group

1.1.3 Built-in Single-precision FPU

• The M32R-FPU supports single-precision floating-point arithmetic fully compliant with IEEE 754 stan­dards. Specifically, five exceptions specified in IEEE 754 standards (Inexact, Underflow, Division by
Zero, Overflow and Invalid Operation) and four rounding modes (round to nearest, round toward 0,
round toward + Infinity and round toward – Infinity) are supported. What’s more, because general­purpose registers are used to perform floating-point arithmetic, the overhead associated with trans­ferring the operand data can be reduced.

1.1.4 Built-in Flash Memory and RAM

• The 32180 contains a RAM that can be accessed with zero wait state, allowing to design a high-speed
embedded system.

• The internal flash memory can be written to while mounted on a printed circuit board (on-board writ­ing). Use of flash memory facilitates development work, because the chip used at the development
stage can be used directly in mass-production, allowing for a smooth transition from prototype to
mass-production without the need to change the printed circuit board.

• The internal flash memory can be rewritten as many as 100 times.

• The internal flash memory has a virtual flash emulation function, allowing the internal RAM to be
superficially mapped into part of the internal flash memory. When combined with the internal Real­Time Debugger (RTD) and the M32R family’s common debug interface (Scalable Debug Interface or
SDI), this function makes the ROM table data tuning easy.

• The internal RAM can be accessed for reading or rewriting data from an external device indepen­dently of the M32R-FPU by using the Real-Time Debugger. The external device is communicated
using the Real-Time Debugger’s exclusive clock-synchronized serial I/O.

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32180 Group User’s Manual (Rev.1.0)

1

1.1.5 Built-in Clock Frequency Multiplier

• The 32180 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below.

OVERVIEW

1.1 Outline of the 32180 Group

XIN pin

(8MHz-10MHz)

Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier

Table 1.1.2 Clock

Functional Block Features
CPUCLK • CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for

BCLK • Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency

Clock output (BCLK pin output) • A clock with the same frequency as f(BCLK) is output from this pin.

X8

PLL

1/4

the M32R-FPU core, internal flash memory and internal RAM.

for the internal peripheral I/O and external data bus.

CPUCLK (CPU clock)
(64MHz-80MHz)

BCLK (peripheral clock)
(16MHz-20MHz)

1.1.6 Powerful Peripheral Functions Built-in

(1) Multijunction timer (MJT)
(2) 10-channel DMAC
(3) Two 16-channel A-D converters (ADC)
(4) 6-channel high-speed serial I/O (SIO)
(5) Real-time debugger (RTD)
(6) 8-level interrupt controller (ICU)
(7) Three operation modes
(8) Wait controller
(9) 2-channel Full-CAN
(10) M32R family’s common debug function (Scalable Debug Interface or SDI)

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32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

1.2 Block Diagram

1.2 Block Diagram

Figure 1.2.1 shows a block diagram of the 32180. The features of each block are described in Table 1.2.1.

Internal Bus

M32R-FPU Core

(80 MHz)

Interface

Multiplier/Accumulator

(32 bits × 16 bits + 56 bits)

Single-precision FPU

(fully IEEE 754 compliant)

Internal Flash Memory

(1 Mbytes = 1,024 Kbytes)

Internal RAM

(48 Kbytes)

Real-Time Debugger

(RTD)

DMAC

(10 channels)

Multijunction Timer

(64 channels)

Internal 32-bit bus

Internal 32-bit bus

A-D Converter × 2

(A-D0 : 10-bit converter, 16 channels)
(A-D1 : 10-bit converter, 16 channels)

Serial I/O

(6 channels)

Interrupt Controller

Internal 16-bit bus

(32 sources, 8 levels)

Wait Controller

PLL Clock Generator

Internal Power Supply

Generator (VDC)

Figure 1.2.1 Block Diagram of the 32180

Full CAN

(2 channels)

External Bus

Interface

AddressData

Input/output ports, 158 lines

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32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

Table 1.2.1 Features of the 32180 (1/2)

Functional Block Features
M32R-FPU CPU core • Implementation: Five-stage pipelined instruction processing (processed in six stages when

performing floating-point arithmetic)

• Internal 32-bit structure of the core

• Register configuration
General-purpose registers: 32 bits × 16 registers
Control registers: 32 bits × 6 registers

• Instruction set
16 and 32-bit instruction formats
100 discrete instructions and six addressing modes

• Internal multiplier/accumulator (32 bits × 16 bits + 56 bits)

• Internal single-precision floating-point arithmetic unit (FPU)

RAM • Capacity: 48 Kbytes, accessible with zero wait state

• The internal RAM can be accessed for reading or rewriting data from the outside independently of

the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to
decrease.

Flash memory • Capacity: 1 Mbytes (1,024 Kbytes), accessible with one wait state

• Durability: Rewritable 100 times

Bus specification • Fundamental bus cycle: 12.5 ns (when f(CPUCLK = 80 MHz)

• Logical address space : 4 Gbytes linear

• Internal bus specification: Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access)

(or accessed in 64 bits when accessing the internal flash memory for
instructions)
: Internal 16-bit data bus (for internal peripheral I/O access)

• External area: Maximum 8 Mbytes (during processor mode)

• Extended external area: Maximum 8 Mbytes (1 Mbytes + 2 Mbytes × 3 blocks during external

extension mode)

• External data address: 20-bit address

• External data bus: 16-bit data bus

• Shortest external bus access: 1 BCLK period during read, 1 BCLK period during write

Multijunction timer (MJT) • 64-channel multi-functional timer

16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels,
16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels,
16-bit input related up/down timer × 3 channels, and 24-bit output related timer × 24 channels

• Flexible timer configuration is possible by interconnecting these timer channels.

• Interrupt request: Counter underflow or overflow and rising or falling or both edges or high or low level

from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.)

• DMA transfer request: Counter underflow or overflow and rising or falling or both edges or high or

low level from the TIN pin (These can be used as external DMA transfer request inputs

irrespective of timer operation.)
DMAC • Number of channels: 10

• Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O

and internal RAM are supported.

• Capable of advanced DMA transfers when used in combination with internal peripheral I/O

• Transfer request: Software or internal peripheral I/O (A-D converter, MJT, serial I/O or CAN)

• DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a

transfer on another channel.)

• Interrupt request: DMA transfer counter register underflow

1.2 Block Diagram

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32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

Table 1.2.1 Features of the 32180 (2/2)

Functional Block Features
A-D converter (ADC) • 16 channels: 10-bit resolution A-D converter × 2 blocks

• Conversion modes: Ordinary conversion modes plus comparator mode

• Operation modes: Single conversion mode and n-channel scan mode (n = 1–16)

• Sample-and-hold function: Sample-and-hold function can be enabled or disabled as necessary.

• A-D disconnection detection assist function: Influences of the analog input voltage wrapping

around from any preceding channel during scan mode operation are suppressed.

• An inflow current bypass circuit is built-in.

• Can generate an interrupt or start DMA transfer upon completion of A-D conversion.

• Either 8 or 10-bit conversion results can be read out.

• Interrupt request: Completion of A-D conversion

• DMA transfer request: Completion of A-D conversion

Serial I/O (SIO) • 6-channel serial I/O

• Can be chosen to be clock-synchronized serial I/O or UART.

• Data can be transferred at high speed (2 Mbits per second during clock-synchronized mode or

156 Kbits per second during UART mode when f(BCLK) = 20 MHz).

• Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed

• DMA transfer request: Reception completed or transmit buffer empty

CAN • 16 message slots × 2 blocks

• Compliant with CAN specification 2.0B active.

• Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off

or single shot

• DMA transfer request: Failed to send, transmission completed or reception completed

Real-Time Debugger • Internal RAM can be rewritten or monitored independently of the CPU by entering a command
(RTD) from the outside.

• Comes with exclusive clock-synchronized serial ports.

• Interrupt request: RTD interrupt command input

Interrupt Controller (ICU) • Controls interrupt requests from the internal peripheral I/O.

• Supports 8-level interrupt priority including an interrupt disabled state.

• External interrupt: 35 sources (SBI# and TIN0–TIN33)

• TIN pin input sensing: Rising, falling or both edges or high or low level

Wait Controller • Controls wait states for access to the extended external area.

• Insertion of 0–7 wait states by setting up in software + wait state extension by entering WAIT# signal

PLL • A multiply-by-8 clock generating circuit
Clock • Maximum external input clock frequency (XIN) is 10.0 MHz.

• CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM
The maximum CPU clock is 80 MHz (when f(XIN) = 10 MHz).

• BCLK: Operating clock for the internal peripheral I/O and external data bus
The maximum peripheral clock is 20 MHz (peripheral module access when
f(XIN) = 10 MHz).

• Clock output (BCLK pin output): A clock with the same frequency as BCLK is output from this pin.

JTAG • Boundary scan function
VDC • Internal power supply generating circuit: Generates the internal power supply (2.5 V) from an

external single power supply (5 or 3.3 V).

Ports • Input/output pins: 158 pins

• The port input threshold can be set in a program to one of three levels individually for each port

group (with or without Schmitt circuit, selectable).

Note 1: The maximum external input clock frequency (XIN) for the M32180F8VFP is 8.0 MHz.

(Note 1)

1.2 Block Diagram

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32180 Group User’s Manual (Rev.1.0)

1

1.3 Pin Functions

1.3 Pin Functions

Figure 1.3.1 shows the 32180’s pin function diagram. Pin functions are described in Table 1.3.1.

OVERVIEW

Clock

Reset

Mode

Data bus

Address bus

Bus control

Serial I/O

Bus control

RTD

Serial I/O

Interrupt
controller

A-D converter

Port 0
Port 1
Port 2
Port 3

Port 4

Port 6

Port 7

Port 8

XIN
XOUT

VCNT
OSC-VCC

OSC-VSS
RESET#
MOD0

MOD1
FP

P00/DB0-P07/DB7
P10/DB8-P17/DB15
P20/A23-P27/A30
P30/A15-P37/A22
P41/BLW#/BLE#

P42/BHW#/BHE#
P43/RD#
P44/CS0#
P45/CS1#
P46/A13, P47/A14

P61-P63
P65/SCLKI4/SCLKO4
P66/SCLKI5/SCLKO5
P67

P70/BCLK/WR#
P71/WAIT#
P72/HREQ#
P73/HACK#
P74/RTDTXD
P75/RTDRXD
P76/RTDACK
P77/RTDCLK

P82/TXD0
P83/RXD0
P84/SCLKI0/SCLKO0
P85/TXD1
P86/RXD1
P87/SCLKI1/SCLKO1
SBI#
AD0IN0-AD0IN15
AD1IN0-AD1IN15
AVCC0, AVCC1
AVSS0, AVSS1
VREF0, VREF1

VDDE
EXCVDD
VCC-BUS

5

P93/TO16-P97/TO20
P100/TO8

P101/TO9/TXD3

2

VCCE

8
8
8
8

VCC-BUSVCC-BUSVCCE

2
3

VCCE OSC-VCC

M32180F8VFP, M32180F8TFP

16
16

2
2
2

4

P102/TO10/CTX1

5

P103/TO11-P107/TO15

8

P110/TO0-P117/TO7

4

P124/TCLK0-P127/TCLK3
P130/TIN16/PWMOFF0
P131/TIN17/PWMOFF1

6

P132/TIN18-P137/TIN23

8

P140/TIN8-P147/TIN15

8

P150/TIN0-P157/TIN7

8

P160/TO21-P167/TO28

2

P172/TIN24, P173/TIN25
P174/TXD2

VCCE

P175/RXD2
P176/TXD3
P177/RXD3

8

P180/TO29-P187/TO36

7

P190/TIN26-P196/TIN32
P197/TIN33/PWMOFF2

P200/TXD4
P201/RXD4
P202/TXD5
P203/RXD5

8

P210/TO37-P217/TO44
P220/CTX0

P221/CRX0
P222/CTX1
P223/CRX1
P224/A11/CS2#
P225/A12/CS3#
P226/CS2#

VCC-BUSVCCE

P227/CS3#
JTMS

JTCK
JTRST
JTDO
JTDI

13

VSS

7

VCCE

2

EXCVCC

Port 9

Port 10

Port 11
Port 12

Port 13

Port 14
Port 15
Port 16

Port 17

Port 18

Port 19

Port 20

Port 21

Port 22

Serial I/O

CAN

Multijunction
timer

Serial I/O

Multijunction
timer

Serial I/O

Multijunction
timer

CAN

Address bus
Bus control

JTAG

Notes: • The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low.

• : Operates with the VCCE power supply.

VCCE

VCC-BUS

: Operates with the VCC-BUS power supply.

OSC-VCC

: Operates with the OSC-VCC power supply.

Figure 1.3.1 Pin Function Diagram

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OVERVIEW

1

Table 1.3.1 Description of Pin Functions (1/5)

Type Pin Name Signal Name Input/Output Description
Power supply VCCE Main power supply – Power supply for the device (5.0 V ± 0.5 V or 3.3 V ± 0.3 V).

EXCVCC Internal power supply – This pin connects an external capacitor.
VCC-BUS Bus power supply – Power supply for the bus control pins (5.0 V ± 0.5 V or 3.3 V

± 0.3 V).

VDDE RAM power supply – Backup power supply for the internal RAM (5.0 V ± 0.5 V or

3.3 V ± 0.3 V).

EXCVDD Internal power – This pin connects an external capacitor for the internal power

supply of RAM supply of the internal RAM.

VSS Ground – Connect all VSS pins to ground (GND).

Clock XIN, Clock input Input These are clock input/output pins. A PLL-based ×8 frequency

XOUT Clock output Output multiplier is included, which accepts as input a clock whose

frequency is 1/8 of the internal CPU clock frequency. (XIN
input is 10 MHz when f(CPUCLK) = 80 MHz.)

BCLK System clock Output This pin outputs a clock whose frequency is twice that of the

external input clock (XIN). (BCLK output is 20 MHz when
f(CPUCLK) = 80 MHz.) Use this clock to synchronize the
operation of external devices.

OSC-VCC Clock power supply – Power supply for the oscillator circuit. Connect OSC-VCC to

the main power supply.
OSC-VSS Clock ground – Connect OSC-VSS to ground.
VCNT PLL control – Connect a resistor and capacitor for control of the PLL circuit.

Reset RESET# Reset Input Reset input pin for the internal circuit.
Mode MOD0, Mode Input Set the microcomputer’s operation mode.

MOD1 MOD0 MOD1 Mode

0 0 Single-chip mode
0 1 External extension mode
1 0 Processor mode

(Boot mode) (Note 1)

1 1 (Settings inhibited)

Flash protect FP Flash protect Input This special pin protects the flash memory against rewrites

in hardware.

Address bus A11–A30 Address bus Output Twenty address lines (A11–A30) are included, allowing four

blocks each up to 2 MB memory space to be connected

external to the chip. A31 is not output.

Note 1: Boot mode requires that the FP pin should be at the high level. For details about boot mode, see Chapter 6, “Internal

Memory.”

1.3 Pin Functions

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32180 Group User’s Manual (Rev.1.0)

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Table 1.3.1 Description of Pin Functions (2/5)

Type Pin Name Signal Name Input/Output Description
Data bus DB0–DB15 Data bus Input/output This 16-bit data bus is used to connect external devices.

When writing in byte units during a write cycle, the output

data at the invalid byte position is undefined. During a

read cycle, data on the entire 16-bit bus is always read in.

However, only the data at the valid byte position is

transferred into the internal circuit.

Bus control CS0#–CS3# Chip select Output These are chip select signals for external devices.

RD# Read Output This signal is output when reading an external device.
WR# Write Output This signal is output when writing to an external device.
BHW#/BLW# Byte high/low write Output When writing to an external device, this signal indicates the

valid byte position to which data is transferred. BHW# and

BLW# correspond to the upper address side (bits 0–7 are

valid) and the lower address side (bits 8–15 are valid),

respectively.
BHE# Byte high enable Output During an external device access, this signal indicates that

the high-order data (bits 0–7) is valid.
BLE# Byte low enable Output During an external device access, this signal indicates that

the low-order data (bits 8–15) is valid.
WAIT# Wait Input When accessing an external device, a low-level input on

WAIT# pin extends the wait cycle.
HREQ# Hold request Input This input is used by an external device to request control

of the external bus. A low-level input on HREQ# pin places

the CPU in a hold state.
HACK# Hold acknowledge Output This signal notifies that the CPU has entered a hold state

and relinquished control of the external bus.

Multijunction TIN0–TIN33 Timer input Input Input pins for the multijunction timer.
timer TO0–TO44 Timer output Output Output pins for the multijunction timer.

TCLK0 Timer clock Input Clock input pins for the multijunction timer.
–TCLK3

1.3 Pin Functions

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32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

Table 1.3.1 Description of Pin Functions (3/5)

Type Pin Name Signal Name Input/Output Description
A-D converter AVCC0, Analog power supply – AVCC0 and AVCC1 are the power supply for the A-D0 and

AVCC1 the A-D1 converter, respectively. Connect AVCC0 and AVCC1

to the power supply rail.
AVSS0, Analog ground – AVSS0 and AVSS1 are the analog ground for the A-D0 and

AVSS1 the A-D1 converter, respectively. Connect AVSS0 and AVSS1

to ground.
AD0IN0 Analog input Input 16-channel analog input pins for the A-D0 converter, i.e.,

–AD0IN15 the first block A-D converter.
AD1IN0 Analog input Input 16-channel analog input pins for the A-D1 converter, i.e.,

–AD1IN15 the second block A-D converter.
VREF0, Reference voltage Input VREF0 and VREF1 are the reference voltage input pin for

VREF1 input the A-D0 and the A-D1 converter, respectively.

Interrupt SBI# System break Input This is the system break interrupt (SBI) input pin for the
controller interrupt interrupt controller.

Serial I/O SCLKI0/ UART transmit/receive Input/output When channel 0 is in UART mode:

SCLKO0 clock output or CSIO This pin outputs a clock derived from BRG output by

transmit/receive clock dividing it by 2.
input/output When channel 0 is in CSIO mode:

This pin accepts as input a transmit/receive clock when
external clock is selected or outputs a transmit/receive
clock when internal clock is selected.

SCLKI1/ UART transmit/receive Input/output When channel 1 is in UART mode:
SCLKO1 clock output or CSIO This pin outputs a clock derived from BRG output by

transmit/receive clock dividing it by 2.
input/output When channel 1 is in CSIO mode:

This pin accepts as input a transmit/receive clock when
external clock is selected or outputs a transmit/receive
clock when internal clock is selected.

SCLKI4/ UART transmit/receive Input/output When channel 4 is in UART mode:
SCLKO4 clock output or CSIO This pin outputs a clock derived from BRG output by

transmit/receive clock dividing it by 2.
input/output When channel 4 is in CSIO mode:

This pin accepts as input a transmit/receive clock when
external clock is selected or outputs a transmit/receive
clock when internal clock is selected.

SCLKI5/ UART transmit/receive Input/output When channel 5 is in UART mode:
SCLKO5 clock output or CSIO This pin outputs a clock derived from BRG output by

transmit/receive clock dividing it by 2.
input/output When channel 5 is in CSIO mode:

This pin accepts as input a transmit/receive clock when
external clock is selected or outputs a transmit/receive
clock when internal clock is selected.

1.3 Pin Functions

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1

Table 1.3.1 Description of Pin Functions (4/5)

Type Pin Name Signal Name Input/Output Description
Serial I/O TXD0 Transmit data Output Transmit data output pin for serial I/O channel 0.

RXD0 Received data Input Received data input pin for serial I/O channel 0.
TXD1 Transmit data Output Transmit data output pin for serial I/O channel 1.
RXD1 Received data Input Received data input pin for serial I/O channel 1.
TXD2 Transmit data Output Transmit data output pin for serial I/O channel 2.
RXD2 Received data Input Received data input pin for serial I/O channel 2.
TXD3 Transmit data Output Transmit data output pin for serial I/O channel 3.
RXD3 Received data Input Received data input pin for serial I/O channel 3.
TXD4 Transmit data Output Transmit data output pin for serial I/O channel 4.
RXD4 Received data Input Received data input pin for serial I/O channel 4.
TXD5 Transmit data Output Transmit data output pin for serial I/O channel 5.
RXD5 Received data Input Received data input pin for serial I/O channel 5.

Real-time RTDTXD RTD transmit data Output Serial data output pin for the real-time debugger.
debugger RTDRXD RTD received data Input Serial data input pin for the real-time debugger.
(RTD) RTDCLK RTD clock input Input Serial data transmit/receive clock input pin for the real-time

debugger.
RTDACK RTD acknowledge Output A low-level pulse is output from this pin synchronously with

the start clock for the real-time debugger’s serial data output

word. The low-level pulse width indicates the type of command/

data received by the real-time debugger.

CAN CTX0, CTX1 Transmit data Output This pin outputs data from the CAN module.

CRX0, CRX1 Received data Input This pin accepts as input the data for the CAN module.

JTAG JTMS Test mode select Input Test mode select input to control the state transition of the

test circuit.
JTCK Test clock Input Clock input for the debug module and test circuit.
JTRST Test reset Input Test reset input to initialize the test circuit asynchronously

with device operation.
JTDI Test data input Input This pin accepts as input the test instruction code or test data

that is serially received.
JTDO Test data output Output This pin outp uts the test in struction code or test data serially.

1.3 Pin Functions

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32180 Group User’s Manual (Rev.1.0)

1

Table 1.3.1 Description of Pin Functions (5/5)

Type Pin Name Signal Name Input/Output Description
Input/output P00–P07 Input/output port 0 Input/output Programmable input/output port.
ports P10–P17 Input/output port 1
(Note 1) P20–P27 Input/output port 2

P30–P37 Input/output port 3
P41–P47 Input/output port 4
P61–P63 Input/output port 6

P65–P67
P70–P77 Input/output port 7
P82–P87 Input/output port 8
P93–P97 Input/output port 9
P100–P107 Input/output port 10
P110–P117 Input/output port 11
P124–P127 Input/output port 12
P130–P137 Input/output port 13
P140–P147 Input/output port 14
P150–P157 Input/output port 15
P160–P167 Input/output port 16
P172–P177 Input/output port 17
P180–P187 Input/output port 18
P190–P197 Input/output port 19
P200–P203 Input/output port 20
P210–P217 Input/output port 21
P220–P227 Input/output port 22

Note 1: Input/output port 5 is reserved for future use. P221 and P223 are input-only ports.

OVERVIEW

1.3 Pin Functions

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32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

1.4 Pin Assignments

1.4 Pin Assignments

Figure 1.4.1 shows the 32180’s pin assignment diagram. A pin assignment table is shown in Table 1.4.1.

P82/TXD0

P83/RXD0

P84/SCLKI0/SCLKO0

P85/TXD1

P86/RXD1

P87/SCLKI1/SCLKO1

P65/SCLKI4/SCLKO4

P66/SCLKI5/SCLKO5

P67

P210/TO37

P211/TO38

P212/TO39

P213/TO40

P214/TO41

P215/TO42

P216/TO43

P217/TO44

P160/TO21

P161/TO22

P162/TO23

P163/TO24

P164/TO25

P165/TO26

P166/TO27

P167/TO28

VSS

VCCE

VCC-BUS

P226/CS2#

P227/CS3#

P44/CS0#

P45/CS1#

P224/A11/CS2#

P225/A12/CS3#

P46/A13

P47/A14

P30/A15

P31/A16

P32/A17

P33/A18

P34/A19

P35/A20

P36/A21

P37/A22

VSS

P20/A23

P21/A24

P22/A25

P23/A26

P24/A27

P25/A28

P26/A29

P27/A30

VCC-BUS

VSS

VCCE

P93/TO16

P94/TO17

P95/TO18

P96/TO19

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

P174/TXD2
P175/RXD2
P176/TXD3
P177/RXD3
P173/TIN25
P172/TIN24

MOD0
MOD1

EXCVDD

VSS

EXCVCC

VDDE

VSS

VCCE
VCC-BUS
P17/DB15
P16/DB14
P15/DB13
P14/DB12
P13/DB11
P12/DB10

P11/DB9
P10/DB8
P07/DB7
P06/DB6
P05/DB5
P04/DB4
P03/DB3
P02/DB2
P01/DB1
P00/DB0

VSS

P73/HACK#

P72/HREQ#

P71/WAIT#

P70/BCLK/WR#

P43/RD#

P42/BHW#/BHE#

P41/BLW#/BLE#

VCC-BUS

VSS
AD1IN15
AD1IN14
AD1IN13
AD1IN12
AD1IN11
AD1IN10

AD1IN9
AD1IN8

AVSS1
AD1IN7
AD1IN6
AD1IN5
AD1IN4
AD1IN3
AD1IN2
AD1IN1
AD1IN0

VREF1

181
182
183
184
185
186

FP

187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240

123456789

101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960

M32180F8VFP
M32180F8TFP

121

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61

P97/TO20
P117/TO7
P116/TO6
P115/TO5
P114/TO4
P113/TO3
P112/TO2
P111/TO1
P110/TO0
P147/TIN15
P146/TIN14
P145/TIN13
P144/TIN12
P143/TIN11
P142/TIN10
P141/TIN9
P140/TIN8
P197/TIN33/PWMOFF2
P196/TIN32
P195/TIN31
P194/TIN30
P193/TIN29
P192/TIN28
P191/TIN27
P190/TIN26
P127/TCLK3
P126/TCLK2
P125/TCLK1
P124/TCLK0
EXCVCC
VSS
VCCE
VSS
VSS
VSS
SBI#
P63
P62
P61
AD0IN15
AD0IN14
AD0IN13
AD0IN12
AD0IN11
AD0IN10
AD0IN9
AD0IN8
AVSS0
AD0IN7
AD0IN6
AD0IN5
AD0IN4
AD0IN3
AD0IN2
AD0IN1
AD0IN0
VREF0
AVCC0
VSS
VCCE

VSS

AVCC1

VCCE

P150/TIN0

P151/TIN1

P152/TIN2

P153/TIN3

P154/TIN4

P155/TIN5

P156/TIN6

P157/TIN7

P200/TXD4

P201/RXD4

P202/TXD5

P203/RXD5

P132/TIN18

P133/TIN19

P130/TIN16/PWMOFF0

P131/TIN17/PWMOFF1

P134/TIN20

P135/TIN21

P136/TIN22

P137/TIN23

P220/CTX0

P221/CRX0

VCCE

OSC-VSS

P222/CTX1

P223/CRX1

VCNT

OSC-VCC

XIN

OSC-VSS

XOUT

RESET#

P180/TO29

P181/TO30

P182/TO31

P183/TO32

P184/TO33

P185/TO34

P186/TO35

P187/TO36

JTDI

P77/RTDCLK

P74/RTDTXD

P76/RTDACK

P75/RTDRXD

JTDO

JTRST

Package: 240P6Y-A (0.5-mm pitch)

Note: • The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low.

Figure 1.4.1 Pin Assignment Diagram of the 240QFP (Top View)

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32180 Group User’s Manual (Rev.1.0)

JTCK

JTMS

P100/TO8

P103/TO11

P104/TO12

P105/TO13

P106/TO14

P101/TO9/TXD3

P102/TO10/CTX1

P107/TO15

OVERVIEW

1

The pins directed for input go to a high-impedance state (Hi-z) when reset. The term “when reset” means that
input on RESET# pin is held low (the device remains reset), and that the RESET# pin is released back high
(the device comes out of reset).

Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (1/6)

Pin
No.

1 AVCC1 - AVCC1 - - AVCC1 - - ­2 VSS - VSS - - VSS - - ­3 VCCE - VCCE - - VCCE - - ­4 P150/TIN0 P150 TIN0 - Input/output P150 Input Hi-z Hi-z
5 P151/TIN1 P151 TIN1 - Input/output P151 Input Hi-z Hi-z
6 P152/TIN2 P152 TIN2 - Input/output P152 Input Hi-z Hi-z
7 P153/TIN3 P153 TIN3 - Input/output P153 Input Hi-z Hi-z
8 P154/TIN4 P154 TIN4 - Input/output P154 Input Hi-z Hi-z

9 P155/TIN5 P155 TIN5 - Input/output P155 Input Hi-z Hi-z
10 P156/TIN6 P156 TIN6 - Input/output P156 Input H i-z Hi-z
11 P157/TIN7 P157 TIN7 - Input/output P157 Input H i-z Hi-z
12 P200/TXD4 P200 TXD4 - Input/output P200 Input Hi-z Hi-z
13 P201/RXD4 P201 RXD4 - Input/output P201 Input Hi-z Hi-z
14 P202/TXD5 P202 TXD5 - Input/output P202 Input Hi-z Hi-z
15 P203/RXD5 P203 RXD5 - Input/output P203 Input Hi-z Hi-z

16 P130/TIN16/PWMOFF0 P130

17 P131/TIN17/PWMOFF1 P131
18 P132/TIN18 P132 TIN18 - Input/output P132 Input Hi-z Hi-z

19 P133/TIN19 P133 TIN19 - Input/output P133 Input Hi-z Hi-z
20 P134/TIN20 P134 TIN20 - Input/output P134 Input Hi-z Hi-z
21 P135/TIN21 P135 TIN21 - Input/output P135 Input Hi-z Hi-z
22 P136/TIN22 P136 TIN22 - Input/output P136 Input Hi-z Hi-z
23 P137/TIN23 P137 TIN23 - Input/output P137 Input Hi-z Hi-z
24 P220/CTX0 P220 CTX0 - Input/output P220 Input Hi-z Hi-z
25 P221/CRX0 P221 CRX0 - Input P221 Input Hi-z Hi-z
26 P222/CTX1 P222 CTX1 - Input/output P222 Input Hi-z Hi-z
27 P223/CRX1 P223 CRX1 - Input P223 Input Hi-z Hi-z
28 VCCE - VCCE - - VCCE - - ­29 OSC-VSS - OSC-VSS - - OSC-VSS - - ­30 VCNT - VCNT - - VCNT - - ­31 OSC-VCC - OSC-VCC - - OSC-VCC - - ­32 XIN - XIN - Input XIN Input - ­33 OSC-VSS - OSC-VSS - - OSC-VSS - - ­34 XOUT - XOUT - Output XOU T Output XOUT XOUT
35 RESET# - RESET# - Input RESET# Input Hi-z Hi-z
36 P180/TO29 P180 TO29 - Input/output P180 Input Hi-z Hi-z
37 P181/TO30 P181 TO30 - Input/output P181 Input Hi-z Hi-z
38 P182/TO31 P182 TO31 - Input/output P182 Input Hi-z Hi-z
39 P183/TO32 P183 TO32 - Input/output P183 Input Hi-z Hi-z
40 P184/TO33 P184 TO33 - Input/output P184 Input Hi-z Hi-z
41 P185/TO34 P185 TO34 - Input/output P185 Input Hi-z Hi-z
42 P186/TO35 P186 TO35 - Input/output P186 Input Hi-z Hi-z
43 P187/TO36 P187 TO36 - Input/output P187 Input Hi-z Hi-z
44 P74/RTDTXD P74 RTDTXD - Input/output P74 Input Hi-z Hi-z
45 P75/RTDRXD P75 RTDRXD - Input/output P75 Input Hi-z Hi-z
46 P76/RTDACK P76 RTDACK - Input/output P76 Input Hi-z Hi-z
47 P77/RTDCLK P77 RTDCLK - Input/output P77 Input Hi-z Hi-z
48 JTDI (Note 1) - JTDI - Input JTDI Input Hi-z Hi-z
49 JTDO (Note 1) - JTDO - Output JTDO Output Hi-z Hi-z
50 JTRST (Note 1) - JTRST - Input JTRST Input Hi-z Hi-z

Symbol Type

Port

Note 1: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin.

Function

Other than

port

TIN16 /

PWMOFF0

TIN17 /

PWMOFF1

Other than

port

- Input/output P130 Input Hi-z Hi-z

- Input/output P131 Input Hi-z Hi-z

Condition

1.4 Pin Assignments

Pin State When Reset

Function Type

State during

reset

State at reset

relea se

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32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (2/6)

Pin
No.

51 JTCK (Note 1) - JTCK - Input JTCK Input Hi-z Hi-z
52 JTMS (Note 1) - JTMS - Input JTMS Input Hi-z Hi-z
53 P100/TO8 P100 TO8 - Input/output P100 Input Hi-z Hi-z
54 P101/TO9/TXD3 P101 TO9 TXD3 Input/output P101 Input Hi-z Hi-z
55 P102/TO10/CTX1 P102 TO10 CTX1 Input/output P102 Input Hi-z Hi-z
56 P103/TO11 P103 TO11 - Input/output P103 Input Hi-z Hi-z
57 P104/TO12 P104 TO12 - Input/output P104 Input Hi-z Hi-z
58 P105/TO13 P105 TO13 - Input/output P105 Input Hi-z Hi-z
59 P106/TO14 P106 TO14 - Input/output P106 Input Hi-z Hi-z
60 P107/TO15 P107 TO15 - Input/output P107 Input Hi-z Hi-z
61 VCCE - VCCE - - VCCE - - ­62 VSS - VSS - - VSS - - ­63 AVCC0 - AVCC0 - - AVCC0 - - ­64 VREF0 - VREF0 - - VREF0 - - ­65 AD0IN0 - AD0IN0 - Input AD0IN0 Input H i-z Hi-z
66 AD0IN1 - AD0IN1 - Input AD0IN1 Input H i-z Hi-z
67 AD0IN2 - AD0IN2 - Input AD0IN2 Input H i-z Hi-z
68 AD0IN3 - AD0IN3 - Input AD0IN3 Input H i-z Hi-z
69 AD0IN4 - AD0IN4 - Input AD0IN4 Input H i-z Hi-z
70 AD0IN5 - AD0IN5 - Input AD0IN5 Input H i-z Hi-z
71 AD0IN6 - AD0IN6 - Input AD0IN6 Input H i-z Hi-z
72 AD0IN7 - AD0IN7 - Input AD0IN7 Input H i-z Hi-z
73 AVSS0 - AVSS0 - - AVSS0 - - ­74 AD0IN8 - AD0IN8 - Input AD0IN8 Input H i-z Hi-z
75 AD0IN9 - AD0IN9 - Input AD0IN9 Input H i-z Hi-z
76 AD0IN10 - AD0IN10 - Input AD0IN10 Input Hi-z Hi-z
77 AD0IN11 - AD0IN11 - Input AD0IN11 Input Hi-z Hi-z
78 AD0IN12 - AD0IN12 - Input AD0IN12 Input Hi-z Hi-z
79 AD0IN13 - AD0IN13 - Input AD0IN13 Input Hi-z Hi-z
80 AD0IN14 - AD0IN14 - Input AD0IN14 Input Hi-z Hi-z
81 AD0IN15 - AD0IN15 - Input AD0IN15 Input Hi-z Hi-z
82 P61 P61 - - Input/output P61 Input Hi-z Hi-z
83 P62 P62 - - Input/output P62 Input Hi-z Hi-z
84 P63 P63 - - Input/output P63 Input Hi-z Hi-z
85 SBI# - SBI# - Input SBI# Input Hi-z Hi-z
86 VSS - VSS - - VSS - - ­87 VSS - VSS - - VSS - - ­88 VSS - VSS - - VSS - - ­89 VCCE - VCCE - - VCCE - - ­90 VSS - VSS - - VSS - - ­91 EXCVCC - EXCVCC - - EXCVCC - - ­92 P124/TCLK0 P124 TCLK0 - Input/output P124 Input Hi-z Hi-z
93 P125/TCLK1 P125 TCLK1 - Input/output P125 Input Hi-z Hi-z
94 P126/TCLK2 P126 TCLK2 - Input/output P126 Input Hi-z Hi-z
95 P127/TCLK3 P127 TCLK3 - Input/output P127 Input Hi-z Hi-z
96 P190/TIN26 P190 TIN26 - Input/output P190 Input Hi-z Hi-z
97 P191/TIN27 P191 TIN27 - Input/output P191 Input Hi-z Hi-z
98 P192/TIN28 P192 TIN28 - Input/output P192 Input Hi-z Hi-z
99 P193/TIN29 P193 TIN29 - Input/output P193 Input Hi-z Hi-z

100 P194/TIN30 P194 TIN30 - Input/output P194 Input H i-z Hi-z

Symbol Type

Port

Note 1: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin.

Function

Other than

port

Other than

port

Condition

1.4 Pin Assignments

Pin State When Reset

Function Type

State during

reset

State at reset

relea se

1-16

32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (3/6)

Pin
No.

101 P195/TIN31 P195 TIN31 - Input/output P195 Input H i-z Hi-z
102 P196/TIN32 P196 TIN32 - Input/output P196 Input H i-z Hi-z

103 P197/TIN33/PWMOFF2 P197
104 P140/TIN8 P140 TIN8 - Input/output P140 Input Hi-z Hi-z

105 P141/TIN9 P141 TIN9 - Input/output P141 Input Hi-z Hi-z
106 P142/TIN10 P142 TIN10 - Input/output P142 Input H i-z Hi-z
107 P143/TIN11 P143 TIN11 - Input/output P143 Input H i-z Hi-z
108 P144/TIN12 P144 TIN12 - Input/output P144 Input H i-z Hi-z
109 P145/TIN13 P145 TIN13 - Input/output P145 Input H i-z Hi-z
110 P146/TIN14 P146 TIN14 - Input/output P146 Input H i-z Hi-z
111 P147/TIN15 P147 TIN15 - Input/output P147 Input H i-z Hi-z
112 P110/TO0 P110 TO0 - Input/output P110 Input H i-z Hi-z
113 P111/TO1 P111 TO1 - Input/output P111 Input H i-z Hi-z
114 P112/TO2 P112 TO2 - Input/output P112 Input H i-z Hi-z
115 P113/TO3 P113 TO3 - Input/output P113 Input H i-z Hi-z
116 P114/TO4 P114 TO4 - Input/output P114 Input H i-z Hi-z
117 P115/TO5 P115 TO5 - Input/output P115 Input H i-z Hi-z
118 P116/TO6 P116 TO6 - Input/output P116 Input H i-z Hi-z
119 P117/TO7 P117 TO7 - Input/output P117 Input H i-z Hi-z
120 P97/TO20 P97 TO20 - Input/output P97 Input Hi-z Hi-z
121 P96/TO19 P96 TO19 - Input/output P96 Input Hi-z Hi-z
122 P95/TO18 P95 TO18 - Input/output P95 Input Hi-z Hi-z
123 P94/TO17 P94 TO17 - Input/output P94 Input Hi-z Hi-z
124 P93/TO16 P93 TO16 - Input/output P93 Input Hi-z Hi-z
125 VCCE - VCCE - - VCCE - - ­126 VSS - VSS - - VSS - - ­127 VCC-BUS - VCC-BUS - - VCC-BUS - - -

128

129

130

131 P24/A27

132 P23/A26 P23 A26

133 P22/A25 P22

134 P21/A24 P21 A24

135 P20/A23

136 VSS - VSS - - VSS - - -

137 P37/A22 P37 A22

138

Symbol

P27/A30

P26/A29

P36/A21 P36 A21

Port

P27 A30

P26 A29

P25P25/A28

P24

P20

Function

Other than

port

TIN33 /

PWMOFF2

A28

A27

A25

A23

Other than

port

- Input/output P197 Input Hi-z Hi-z

- Input/output

-

-

- Input/output

- Input/output

- Input/output

- Input/output

- Input/output

- Input/output

-

- Input/output139 P35/A20 P35 A20

Type Condition

During single-chip and

external extension modes

During processor mode A30 Output Hi-z Undefined

During single-chip and

Input/output

Input/output

Input/output

external extension modes

During processor mode A29 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A28 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A27 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A26 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A25 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A24 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A23 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A22 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A21 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A20 Output Hi-z Undefined

1.4 Pin Assignments

Pin State When Reset

Function Type

P27 Input Hi-z Hi-z

P26 Input Hi-z Hi-z

P25 Input Hi-z Hi-z

P24 Input Hi-z Hi-z

P23 Input Hi-z Hi-z

P22 Input Hi-z Hi-z

P21 Input Hi-z Hi-z

P20 Input Hi-z Hi-z

P37 Input Hi-z Hi-z

P36 Input Hi-z Hi-z

P35 Input Hi-z Hi-z

State during

reset

State at reset

relea se

1-17

32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (4/6)

Pin
No.

140 P34/A19 P34 A19

141 P33/A18 P33 A18

142 P32/A17 P32 A17

143 P31/A16 P31 A16

144 P30/A15

145 P47/A14 P47 A14

146

148 P224/A11/CS2#

149 P45/CS1# P45

150 P44/CS0# P44 CS0# - Input/output

151

152

153 VCC-BUS VCC-BUS - VCC-BUS - - ­154 VCCE - VCCE - - VCCE - - ­155 VSS - VSS - - VSS - - ­156 P167/TO28 P167 TO28 - Input/output P167 Input Hi-z Hi-z
157 P166/TO27 P166 TO27 - Input/output P166 Input Hi-z Hi-z
158 P165/TO26 P165 TO26 - Input/output P165 Input Hi-z Hi-z
159 P164/TO25 P164 TO25 - Input/output P164 Input Hi-z Hi-z
160 P163/TO24 P163 TO24 - Input/output P163 Input Hi-z Hi-z
161 P162/TO23 P162 TO23 - Input/output P162 Input Hi-z Hi-z
162 P161/TO22 P161 TO22 - Input/output P161 Input Hi-z Hi-z
163 P160/TO21 P160 TO21 - Input/output P160 Input Hi-z Hi-z
164 P217/TO44 P217 TO44 - Input/output P217 Input Hi-z Hi-z
165 P216/TO43 P216 TO43 - Input/output P216 Input Hi-z Hi-z
166 P215/TO42 P215 TO42 - Input/output P215 Input Hi-z Hi-z
167 P214/TO41 P214 TO41 - Input/output P214 Input Hi-z Hi-z
168 P213/TO40 P213 TO40 - Input/output P213 Input Hi-z Hi-z
169 P212/TO39 P212 TO39 - Input/output P212 Input Hi-z Hi-z
170 P211/TO38 P211 TO38 - Input/output P211 Input Hi-z Hi-z
171 P210/TO37 P210 TO37 - Input/output P210 Input Hi-z Hi-z
172 P67 P67 - - Input/output P67 Input Hi-z Hi-z
173 P66/SCLKI5/SCLKO5 P66 SCLKI5 SCLKO5 Input/output P66 Input Hi-z Hi-z
174 P65/SCLKI4/SCLKO4 P65 SCLKI4 SCLKO4 Input/output P65 Input Hi-z Hi-z
175 P87/SCLKI1/SCLKO1 P87 SCLKI1 SCLKO1 Input/output P87 Input Hi-z Hi-z

Symbol Type Condition

P46/A13 P46 A13

P225/A12/CS3#147

P227/CS3#

P226/CS2#

Port

P30 A15 -

P225 A12 CS3# Input/output

P224 A11 CS2#

P227

P226

Function

Other than

port

CS3#

CS2# -

Other than

port

-

- Input/output

- Input/output

- Input/output

- Input/output

- Input/output

-CS1#

-

Input/output

Input/output

Input/output

Input/output

Input/output

Input/output

During single-chip and

external extension modes

During processor mode A19 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A18 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A17 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A16 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A15 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A14 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A13 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A12 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode A11 Output Hi-z Undefined

During single-chip and

external extension modes

During processor mode CS1# Output Hi-z High level

During single-chip and

external extension modes

During processor mode CS0# Output Hi-z High level

During single-chip and

external extension modes

During processor mode CS3# Output Hi-z High level

During single-chip and

external extension modes

During processor mode CS2# Output Hi-z High level

1.4 Pin Assignments

Pin State When Reset

Function Type

P34 Input Hi-z Hi-z

P33 Input Hi-z Hi-z

P32 Input Hi-z Hi-z

P31 Input Hi-z Hi-z

P30 Input Hi-z Hi-z

P47 Input Hi-z Hi-z

P46 Input Hi-z Hi-z

P225 Input Hi-z Hi-z

P224 Input Hi-z Hi-z

P45 Input Hi-z Hi-z

P44 Input Hi-z Hi-z

P227 Input Hi-z Hi-z

P226 Input Hi-z Hi-z

State during

reset

State at reset

relea se

1-18

32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (5/6)

Pin
No.

176 P86/RXD1 P86 RXD1 - Input/output P86 Input Hi-z Hi-z
177 P85/TXD1 P85 TXD1 - Input/output P85 Input Hi-z Hi-z
178 P84/SCLKI0/SCLKO0 P84 SCLKI0 SCLKO0 Input/output P84 Input Hi-z Hi-z
179 P83/RXD0 P83 RXD0 - Input/output P83 Input Hi-z Hi-z
180 P82/TXD0 P82 TXD0 - Input/output P82 Input Hi-z Hi-z
181 P174/TXD2 P174 TXD2 - Input/output P174 Input H i-z Hi-z
182 P175/RXD2 P175 RXD2 - Input/output P175 Input H i-z Hi-z
183 P176/TXD3 P176 TXD3 - Input/output P176 Input H i-z Hi-z
184 P177/RXD3 P177 RXD3 - Input/output P177 Input H i-z Hi-z
185 P173/TIN25 P173 TIN25 - Input/output P173 Input H i-z Hi-z
186 P172/TIN24 P172 TIN24 - Input/output P172 Input H i-z Hi-z
187 FP - FP - Input FP Input Hi-z Hi-z
188 MOD0 - MOD0 - Input MOD0 Input Hi-z Hi-z
189 MOD1 - MOD1 - Input MOD1 Input Hi-z Hi-z
190 EXCVDD - EXCVDD - - EXCVDD - - ­191 VSS - VSS - - VSS - - ­192 EXCVCC - EXCVCC - - EXCVCC - - ­193 VDDE - VDDE - - VDDE - - ­194 VSS - VSS - - VSS - - ­195 VCCE - VCCE - - VCCE - - ­196 VCC-BUS - VCC-BUS - - VCC-BUS - - -

197 P17/DB15 P17 DB15

198 P16/DB14 P16 DB14

199 P15/DB13

200 P14/DB12 P14 DB12

201 P13/DB11 P13 DB11

202 P12/DB10 P12 DB10

203 P11/DB9

204 P10/DB8 P10 DB8

205 P07/DB7 P07 DB7

206 P06/DB6 P06 DB6

207 P05/DB5

208 P04/DB4

209 P03/DB3

210 P02/DB2 P02 DB2

Symbol Type Condition

Port

P15 DB13

P11 DB9

P05 DB5

P03 DB3

Function

Other than

port

Other than

port

-

- Input/output

- Input/output

- Input/output

- Input/output

- Input/output

- Input/output

- Input/output

-

- Input/output

- Input/output

- Input/outputP04 DB4

- Input/output

- Input/output

Input/output

Input/output

During single-chip and

external extension modes

During processor mode DB15 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB14 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB13 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB12 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB11 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB10 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB9 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB8 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB7 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB6 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB5 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB4 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB3 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB2 Input/output Hi-z Hi-z

1.4 Pin Assignments

Pin State When Reset

Function Type

P17 Input Hi-z Hi-z

P16 Input Hi-z Hi-z

P15 Input Hi-z Hi-z

P14 Input Hi-z Hi-z

P13 Input Hi-z Hi-z

P12 Input Hi-z Hi-z

P11 Input Hi-z Hi-z

P10 Input Hi-z Hi-z

P07 Input Hi-z Hi-z

P06 Input Hi-z Hi-z

P05 Input Hi-z Hi-z

P04 Input Hi-z Hi-z

P03 Input Hi-z Hi-z

P02 Input Hi-z Hi-z

State during

reset

State at reset

relea se

1-19

32180 Group User’s Manual (Rev.1.0)

OVERVIEW

1

Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (6/6)

Pin
No.

211 P01/DB1

212 P00/DB0 P00 DB0

213 VSS - VSS - - VSS - - ­214 P73/HACK# P73 HACK# - Input/output P73 Input Hi-z Hi-z
215 P72/HREQ# P72 HREQ# - Input/output P72 Input H i-z Hi-z
216 P71/WAIT# P71 WAIT# - Input/output P71 Input Hi-z Hi-z
217 P70/BCLK/WR# P70 BCLK WR# Input/output P70 Input Hi-z Hi-z

218 P43/RD# P43 RD#

220 P41/BLW#/BLE# P41 BLW#

221 VCC-BUS - VCC-BUS - - VCC-BUS - - ­222 VSS - VSS - - - - - ­223 AD1IN15 - AD1IN15 - Input AD1IN15 Input Hi-z Hi-z
224 AD1IN14 - AD1IN14 - Input AD1IN14 Input Hi-z Hi-z
225 AD1IN13 - AD1IN13 - Input AD1IN13 Input Hi-z Hi-z
226 AD1IN12 - AD1IN12 - Input AD1IN12 Input Hi-z Hi-z
227 AD1IN11 - AD1IN11 - Input AD1IN11 Input Hi-z Hi-z
228 AD1IN10 - AD1IN10 - Input AD1IN10 Input Hi-z Hi-z
229 AD1IN9 - AD1IN9 - Input AD1IN9 Input Hi-z Hi-z
230 AD1IN8 - AD1IN8 - Input AD1IN8 Input Hi-z Hi-z
231 AVSS1 - AVSS1 - - AVSS1 - - ­232 AD1IN7 - AD1IN7 - Input AD1IN7 Input Hi-z Hi-z
233 AD1IN6 - AD1IN6 - Input AD1IN6 Input Hi-z Hi-z
234 AD1IN5 - AD1IN5 - Input AD1IN5 Input Hi-z Hi-z
235 AD1IN4 - AD1IN4 - Input AD1IN4 Input Hi-z Hi-z
236 AD1IN3 - AD1IN3 - Input AD1IN3 Input Hi-z Hi-z
237 AD1IN2 - AD1IN2 - Input AD1IN2 Input Hi-z Hi-z
238 AD1IN1 - AD1IN1 - Input AD1IN1 Input Hi-z Hi-z
239 AD1IN0 - AD1IN0 - Input AD1IN0 Input Hi-z Hi-z
240 VREF1 - VREF1 - - VREF1 - - -

Symbol Type

Port

P01 DB1 - Input/output

P42 BHW#

Function

Other than

port

Other than

port

- Input/output

- Input/output

BHE# Input/output219 P42/BHW#/BHE#

BLE# Input/output

Condition

During single-chip and

external extension modes

During processor mode DB1 Input/output Hi-z Hi-z

During single-chip and

external extension modes

During processor mode DB0 Input/output Hi-z Hi-z

During single-chip mode P43 Input Hi-z Hi-z

During external extension and

processor modes

During single-chip mode P42 Input Hi-z Hi-z

During external extension and

processor modes

During single-chip mode P41 Input Hi-z Hi-z

During external extension and

processor modes

BHW#/BHE# Output Hi-z High level

BLW#/BLE# Output Hi-z High level

1.4 Pin Assignments

Pin State When Reset

Function Type

P01 Input Hi-z Hi-z

P00 Input Hi-z Hi-z

RD# Output Hi-z High level

State during

reset

State after

reset

1-20

32180 Group User’s Manual (Rev.1.0)

CHAPTER 2

CPU

2.1 CPU Registers

2.2 General-purpose Registers

2.3 Control Registers

2.4 Accumulator

2.5 Program Counter

2.6 Data Formats

2.7 Supplementary Explanation for BSET, BCLR,
LOCK and UNLOCK Instruction Execution

2.8 Precautions on CPU

2

2.1 CPU Registers

2.1 CPU Registers

The M32R-FPU has 16 general-purpose registers, 6 control registers, an accumulator and a program counter.
The accumulator is of 56-bit configuration, and all other registers are of 32-bit configuration.

2.2 General-purpose Registers

The 16 general-purpose registers (R0–R15) are of 32-bit width and are used to retain data and base address, as
well as for integer calculations, floating-point operations, etc. R14 is used as the link register and R15 as the stack
pointer. The link register is used to store the return address when executing a subroutine call instruction. The
Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depending on
the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW).
After reset, the value of the general-purpose registers is undefined.

CPU

b31

R0
R1
R2
R3
R4
R5
R6
R7

Note 1: The stack pointer functions as either the SPI or the SPU depending on
the value of the SM bit in the PSW.

b0b0 b31

R8
R9
R10
R11
R12
R13
R14 (Link register)
R15 (Stack pointer) (Note 1)

Figure 2.2.1 General-purpose Registers

2.3 Control Registers

There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register
(CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floating­point Status Register (FPSR).
The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.
In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction.

CRn

CR0
CR1
CR2
CR3

b0

PSW

CBR

SPI

SPU

b31

Processor Status Word Register
Condition Bit Register
Interrupt Stack Pointer
User Stack Pointer

Notes: • CRn (n = 0-3, 6 and 7) denotes the control register number.

• The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.

• The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instructions.

Figure 2.3.1 Control Registers

CR6
CR7

BPC

FPSR

Backup PC
Floating-point Status Register

2-2

32180 Group User’s Manual (Rev.1.0)

2

2.3.1 Processor Status Word Register: PSW (CR0)

7654321 8 9 10 11 12 13 14 b15b0

CPU

2.3 Control Registers

0000 000 0000000

BIEBSM

?? 00000?00000000

BPSW field

b Bit Name Function R W
0–15 No function assigned. Fix to "0". 00
16 BSM Saves value of SM bit when EIT occurs R W

Backup SM Bit

17 BIE Saves value of IE bit when EIT occurs R W

Backup IE Bit
18–22 No function assigned. Fix to "0". 00
23 BC Saves value of C bit when EIT occurs R W

Backup C Bit
24 SM 0: Uses R15 as the interrupt stack pointer R W

Stack Mode Bit 1: Uses R15 as the user stack pointer
25 IE 0: Does not accept interrupt R W

Interrupt Enable Bit 1: Accepts interrupt
26–30 No function assigned. Fix to "0". 00
31 C Indicates carry, borrow or overflow resulting R W

Condition Bit from operations (instruction dependent)

0 0

23 24 25 26 27 28 29 30 b3117 18 19 20 21 22b16

BC SM IE C

PSW field

<After reset: B’0000 0000 0000 0000 ??00 000? 0000 0000>

The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field
which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs.
The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit.
The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the
Backup Condition (BC) bit.
After reset, BSM, BIE and BC are undefined. All other bits are "0".

2-3

32180 Group User’s Manual (Rev.1.0)

2

2.3 Control Registers

2.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value
written to the PSW register’s C bit is reflected in this register. The register can only be read. (Writing to the
register with the MVTC instruction is ignored.)
After reset, the value of CBR is H’0000 0000.

b0 b31

0000000000000000000000000000000

CBR

C

2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)

The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack
pointer. These registers can be accessed as the general-purpose register R15. R15 switches between repre­senting the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW.
After reset, the values of the SPI and SPU are undefined.

b0 b31

SPI SPI

CPU

b0 b31

SPU SPU

2.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed
to "0".
When an EIT occurs, the register sets either the PC value when the EIT occurred or the PC value for the next
instruction depending on the type of EIT. The BPC value is loaded to the PC when the RTE instruction is
executed. However, the values of the lower 2 bits of the PC are always "00" when returned. (PC always returns
to the word-aligned address.)
After reset, the value of the BPC is undefined.

b0 b31

BPCBPC

0

2-4

32180 Group User’s Manual (Rev.1.0)

2

2.3 Control Registers

2.3.5 Floating-point Status Register: FPSR (CR7)

2 3 4 5 6 7 8 9 10 11 12 13 14 b151b0

FS FX FU FZ

0000 000 0000000

18 19 20 21 22 23 24 25 26 27 28 29 30 b3117b16

EZ EO

EUEX

00 00000100000000

b Bit Name Function R W
0 FS Reflects the logical sum of FU, FZ, FO and FV. R –

Floating-point Exception Summary Bit
1 FX Set to "1" when an inexact exception occurs (if EIT processing is R W

Inexact Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until

2 FU Set to "1" when an underflow exception occurs (if EIT processing is R W

Underflow Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until

3 FZ Set to "1" when a zero divide exception occurs (if EIT processing is R W

Zero Divide Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until

4 FO Set to "1" when an overflow exception occurs (if EIT processing is R W

Overflow Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until

5 FV Set to "1" when an invalid operation exception occurs (if EIT processing R W

Invalid Operation Exception Flag is unexecuted (Note 1)). Once set, the flag retains the value "1" until

6–16 No function assigned. Fix to "0". 00
17 EX 0: Mask EIT processing to be executed when an inexact exception occurs. R W

Inexact Exception Enable Bit 1: Execute EIT processing when an inexact exception occurs.
18 EU 0: Mask EIT processing to be executed when an underflow exception R W

Underflow Exception Enable Bit occurs.

19 EZ 0: Mask EIT processing to be executed when a zero divide exception R W

Zero Divide Exception Enable Bit occurs.

20 EO 0: Mask EIT processing to be executed when an overflow exception R W

Overflow Exception Enable Bit occurs.

21 EV 0: Mask EIT processing to be executed when an invalid operation R W

Invalid Operation Exception Enable Bit exception occurs.

22 No function assigned. Fix to "0". 00
23 DN 0: Handle the denormalized number as a denormalized number. R W

Denormalized Number Zero Flush Bit 1: Handle the denormalized number as zero.

(Note 2)
24 CE 0: No unimplemented operation exception occurred. R

Unimplemented Operation 1: An unimplemented operation exception occurred. When the bit is

Exception Cause Bit set to "1", the execution of an FPU operation inst r u ctio n will clear it to "0".
25 CX 0: No inexact exception occurred. R

Inexact Exception Cause Bit 1: An inexact exception occurred. When the bit is set to "1",

0FO0

FV

EV

DN CE CX CU CZ CO CV RM

it is cleared to "0" in software.

it is cleared to "0" in software.

it is cleared to "0" in software.

it is cleared to "0" in software.

it is cleared to "0" in software.

1: Execute EIT processing when an underflow exception occurs.

1: Execute EIT processing when a zero divide exception occurs.

1: Execute EIT processing when an overflow exception occurs.

1: Execute EIT processing when an invalid operation exception occurs.

th e execution of an FPU operation instruction will clear it to "0".

<After reset: H’0000 0100>

CPU

(Note 3)

(Note 3)

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32180 Group User’s Manual (Rev.1.0)

2

26 CU 0: No underflow exception occurred R (Note 3)

Underflow Exception Cause Bit 1: An underflow exception occurred. When the bit is set to "1",

the execution of an FPU operation instruction will clear it to "0".

27 CZ 0: No zero divide exception occurred. R

Zero Divide Exception Cause Bit 1: A zero divide exception occurred. When the bit is set to "1",

the execution of an FPU operation instruction will clear it to "0".

28 CO 0: No overflow exception occurred. R

Overflow Exception Cause Bit 1: An overflow exception occurred. When the bit is set to "1",

the execution of an FPU operation instruction will clear it to "0".

29 CV 0: No invalid operation exception occurred. R

Invalid Operation Exception Cause Bit 1: An invalid operation exception occurred. When the bit is set to "1",

the execution of an FPU operation instruction will clear it to "0".

30, 31 RM 00: Round to nearest R W

Rounding Mode Selection Bit 01: Round toward Zero

10: Round toward + Infinity
11: Round toward – Infinity

Note 1: The phrase “If EIT processing unexecuted” means whenever one of the exceptions occurs, enable bits 17 to 21 are set to

"0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their
corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is executed. In

this case, these two flags do not change state regardless of the enable bits settings.
Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented exception occurs.
Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had before the write).

2.3 Control Registers

CPU

(Note 3)

(Note 3)

(Note 3)

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32180 Group User’s Manual (Rev.1.0)

2

2.4 Accumulator

2.4 Accumulator

The Accumulator (ACC) is a 56-bit register used for DSP function instructions.
The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the
accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The
accumulator is also used for the multiply instruction “MUL,” in which case the accumulator value is destroyed by
instruction execution.

Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the high-order 32 bits (bits 0–31) and the low-order 32 bits (bits 32–63), respectively.

Use the MVFACHI, MVFACLO and MVFACMI instructions for reading data from the accumulator. The MVFACHI,
MVFACLO and MVFACMI instructions read data from the high-order 32 bits (bits 0–31), the low-order 32 bits (bits
32–63) and the middle 32 bits (bits 16–47), respectively.
After reset, the value of accumulator is undefined.

CPU

(Note 1)

15b0 167 8 31 32 47 48 b63

ACC

Write and read ranges of MVTACHI

and MVFACHI instructions

Note 1: When read, bits 0 to 7 always show the sign-extended value of the value of bit 8. Writing to this

bit field is ignored.

Read range of MVFACMI instruction

Write and read ranges of MVTACLO

and MVFACLO instructions

2.5 Program Counter

The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the
M32R FPU instruction starts with even-numbered addresses, the LSB (bit 31) is always "0".
After reset, the value of PC is H’0000 0000.

b0 b31

PCPC

0

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32180 Group User’s Manual (Rev.1.0)

2

2.6 Data Formats

2.6 Data Formats

2.6.1 Data Types

The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16 and 32-bit
integers and single-precision floating-point numbers. The signed integers are represented by 2’s complements.

CPU

Signed byte
(8-bit) integer

Unsigned byte
(8-bit) integer

Signed halfword
(16-bit) integer

Unsigned halfword
(16-bit) integer

Signed word
(32-bit) integer

Unsigned word
(32-bit) integer

Single-precision
floating-point number

b0

S

b0

b0

S

b0

b0

S

b0

b0 b1 b8b9 b31

SE F

S: Sign bit; E: Exponent field; F: Fraction field

b7

b7

b15

b15

b31

b31

Figure 2.6.1 Data Types

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2

2.6.2 Data Formats

(1) Data formats in registers

The data sizes in the M32R-FPU registers are always words (32 bits).
When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended
(LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before
being loaded in the register.
When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and the 8­bit data on the LSB side of the register are stored into memory by the ST, STH and STB instructions,
respectively.

CPU

2.6 Data Formats

<Load>

b0 b31

Rn

Sign-extended (LDH instruction) or

zero-extended (LDUH instruction)

b0 b31

Rn

b0 b31

Rn

<Store>

b0 b31

Rn

b0 b31

Rn

b0 b31

Rn

Sign-extended (LDB instruction) or

zero-extended (LDUB instruction)

From memory (LDH, LDUH instructions)

16

From memory (LD instruction)

Word

16

To memory (STH instruction)

Word

(LDB, LDUB instructions)

Halfword

To memory (STB instruction)

Halfword

From memory

24

Byte

24

Byte

Figure 2.6.2 Data Formats in Registers

To memory (ST instruction)

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2

(2) Data formats in memory

The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can
be located at any address, halfword and word data must be located at the addresses aligned with a
halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits =
"00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word bound­ary, an address exception occurs.

CPU

2.6 Data Formats

Address

+0 address +1 address +2 address +3 address

b0 b31

Byte

b0

Halfword

b0 b31

Word

Figure 2.6.3 Data Formats in Memory

(3) Endian

The diagrams below show a general endian system and the endian adopted for the M32R family of
Mitsubishi microcomputers.

7 8 15 16 23 24

Byte

Byte

15

Halfword

Word

Bit endian

(H'01)

Byte

Byte

b31

Halfword

Byte endian

(H'01234567)

Big endian

Little endian

Note: • Even when bits are arranged in big endian, H'01 is not B'10000000.

B'0000001

b0 b7

B'0000001

b7 b0

Figure 2.6.4 General Endian System

2-10

H'01

H'67

H'23 H'45

HH HL LH LL

H'45 H'23 H'01

LL LH HL HH

32180 Group User’s Manual (Rev.1.0)

H'67

2

CPU

2.6 Data Formats

Mitsubishi

microcomputer

7700 and M16C families

family name

Endian

(bit/byte)

Address

Data arrangement

Bit number
Example:

0x01234567

Little/little

+0 +1 +2 +3 +0 +1 +2 +3+0 +1 +2 +3

LL LH HL HH

31–247–023–1615–80–724–318–15 16–23

HH HL LH LL

.byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67

Note: • The M32R family uses the big endian for both bits and bytes.

Figure 2.6.5 Endian Adopted for the M32R Family

(4) Transfer instructions

• Constant transfer

LD24 Rdest, #imm24
LDI Rdest, #imm16
LDI Rdest, #imm8
SETH Rdest, #imm16

LD24 Rdest, #imm24

imm24

SETH Rdest, #imm16

imm16

Little/big

b0

b0

Rdest

7–031–24 15–823–16

b15

M32R family

HH HL LH LL

b23

00

8

Big/big

b31b0

• Register to register transfer

MV Rdest, Rsrc

Rdest

b0

MV Rdest, Rsrc

Rsrc

b0

Rdest

00 00

15

b31

• Control register transfer

MVTC Rsrc, CRdest

MVFC Rdest, CRsrc
MVTC Rsrc, CRdest

Rsrc

b31b0

CRdest

Note: • The condition bit C changes state when data is written to CR0 (PSW) using the MVTC instruction.

Figure 2.6.6 Transfer Instructions

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32180 Group User’s Manual (Rev.1.0)

b31

b31b0

b31b0

2

(5) Transfer from memory (signed) to registers

CPU

2.6 Data Formats

• Signed 32 bits

Memory

LD24 Rsrc, #label
LD Rdest, @Rsrc

label

+0 +1 +2

• Signed 16 bits

label

LD24 Rsrc, #label
LDH Rdest, @Rsrc

• Signed 8 bits

label

+0 +1 +2 +3

Determined by MSB
0: Positive number
1: Negative number

LD24 Rsrc, #label
LDB Rdest, @Rsrc

+0 +1 +2

Determined by MSB
0: Positive number
1: Negative number

Figure 2.6.7 Transfer from Memory (Signed) to Registers

(6) Transfer from memory (unsigned) to registers

Register

Rdest

+3

Rdest

00 00
FF FF

Rdest

+3

00 00 00

FF FF FF

b31b0

b31b0

b31b0

• Unsigned 32 bits

Memory

LD24 Rsrc, #label
LD Rdest, @Rsrc

• Unsigned 16 bits
LD24 Rsrc, #label

LDUH

Rdest, @Rsrc

• Unsigned 8 bits

label

+0 +1 +2 +3

label

+0 +1 +2 +3

label

LD24 Rsrc, #label
LDUB Rdest, @Rsrc

+0 +1 +2 +3

Figure 2.6.8 Transfer from Memory (Unsigned) to Registers

2-12

Register

Rdest

b31b0

Rdest

00 00

b31b0

Rdest

00 00 00

b31b0

32180 Group User’s Manual (Rev.1.0)

2

(7) Notes on data transfer

When transferring data, be aware that data arrangements in registers and memory are different.

• Word data (32 bits)

CPU

2.6 Data Formats

Data in registers Data in memory

(R0–R15)

HH HL LH LL

b0 b31

• Halfword data (16 bits)

(R0–R15)

b0 b31

(R0–R15)

b0 b31

• Byte data (8 bits)

(R0–R15)

b0

(R0–R15)

H L

H L

b31 b0 b7

+0 +1 +2 +3

HH HL LH LL

b0 b31

+0 +1 +2 +3

H L

b0 b15

+0 +1 +2 +3

H L

b16 b31

+0 +1 +2 +3

+0 +1 +2 +3

b0

(R0–R15)

b0

(R0–R15)

b0

Figure 2.6.9 Difference in Data Arrangements

b31 b8 b15

+0 +1 +2 +3

b31 b16 b23

+0 +1 +2 +3

b31 b24 b31

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32180 Group User’s Manual (Rev.1.0)

CPU

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution

2

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK
Instruction Execution

The LOCK bit is set when executing the BSET or BCLR instruction, and is cleared when the BSET or BCLR
instruction finishes.
The LOCK instruction sets the LOCK bit, as well as performs an ordinary load operation. The UNLOCK instruction
is used to clear the LOCK bit.

The LOCK bit is located inside the CPU, and cannot directly be accessed for read or write by users. This bit
controls granting of bus control requested by devices other than the CPU.

• When LOCK bit = "0"
Control of the bus requested by devices other than the CPU is granted

• When LOCK bit = "1"
Control of the bus requested by devices other than the CPU is denied

In the 32180 group, control of the bus may be requested by devices other than the CPU in the following two cases:

• When DMA transfer is requested by the internal DMAC

• When HREQ# input is pulled low to request that the CPU be placed in a hold state

2.8 Precautions on CPU

• Usage Notes for 0 Division Instruction

Problem and Conditions

Inaccurate calculations for the instructions listed in (2) will result from execution of the 0 division instruction
under the conditions described in (1).

(1) If 0 division calculation is executed when the divisor = 0 for instructions DIV, DIVU, REM and REMU,

(2) the result will be inaccurate calculations for any of the following instructions that are executed immedi­ately after 0 division:

ADDV, ADDX, ADD, ADDI, ADDV3, ADD3,
CMP, CMPU, CMPI, CMPUI,
SUBV, SUBX, SUB,
DIV, DIVU,
REM, REMU.

Countermeasure

Assuming that the 0 division occurrence itself is not expected by the system and therefore is the cause of
miscalculations, before executing division or remainder instructions, do a 0 check on the divisor to make sure 0
division does not occur.

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32180 Group User’s Manual (Rev.1.0)

CHAPTER 3

ADDRESS SPACE

3.1 Outline of the Address Space

3.2 Operation Modes

3.3 Internal ROM and Extended External Areas

3.4 Internal RAM and SFR Areas

3.5 EIT Vector Entry

3.6 ICU Vector Table

3.7 Notes on Address Space

ADDRESS SPACE

3

3.1 Outline of the Address Space

3.1 Outline of the Address Space

The logical addresses of the M32R are always handled in 32 bits, providing a linear address space of up to 4
Gbytes. The address space of the M32R/ECU consists of the following:

(1) User space

• Internal ROM area

• Extended external area

• Internal RAM area

• SFR (Special Function Register) area

(2) System space (not open to the user)

(1) User space

The 2 Gbytes from the address H’0000 0000 to the address H’7FFF FFFF comprise the user space.
Located in this space are the internal ROM area, an extended external area, the internal RAM area and the
SFR (Special Function Register) area (in which a set of internal peripheral I/O registers exist). Of these, the
internal ROM and extended external areas are located differently depending on mode settings as will be
described later.

(2) System space

The 2 Gbytes from the address H’8000 0000 to the address H’FFFF FFFF comprise the system space.
This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and
cannot be used by the user.

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3

s

s

(

)

CS0

s

s

Logical address
H'0000 0000

16 Mbyte

ADDRESS SPACE

3.1 Outline of the Address Space

EIT vector entry

Internal ROM area

1 Mbyte

Note 1

area

CS1 area

H'0000 0000

H'000F FFFF
H'0010 0000

H'001F FFFF
H'0020 0000

2 Gbytes

H'7FFF FFFF
H'8000 0000

2 Gbytes

User space

System space

Ghost area

in 16-Mbyte

units

CS2 area

CS3 area

SFR area

16 Kbyte

RAM area

48 Kbyte

Reserved area

64 Kbytes

H'003F FFFF
H'0040 0000

H'005F FFFF
H'0060 0000

H'007F FFFF
H'0080 0000

H'0080 3FFF
H'0080 4000

H'0080 FFFF
H'0081 0000

H'0081 FFFF
H'0082 0000

H'FFFF FFFF

Note 1: This area is located differently depending on how chip mode is set.

Figure 3.1.1 Address Space

3-3

Ghost area in

128-Kbyte units

H'00FF FFFF

32180 Group User’s Manual (Rev.1.0)

ADDRESS SPACE

l

)

l

)

3

3.2 Operation Modes

3.2 Operation Modes

The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by
MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately
in Section 6.5, “Programming the Internal Flash Memory.”

Table 3.2.1 Operation Mode Settings

MOD0 MOD1 Operation mode (Note 2)
VSS VSS Single-chip mode
VSS VCCE External extension mode
VCCE VSS Processor mode (FP = VSS)
VCCE VCCE Reserved (use inhibited)

Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively.
Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above

table, see Section 6.5, “Programming the Internal Flash Memory.”

The internal ROM and extended external areas are located differently depending on how operation mode is set.
(All other areas in the address space are located the same way.) The diagram below shows how the internal ROM
and extended external areas are mapped into the address space in each operation mode. (For flash rewrite mode,
see Section 6.5, “Programming the Internal Flash Memory.”)

Non-CS0 area

H'0000 0000

H'000F FFFF
H'0010 0000

H'001F FFFF
H'0020 0000

H'003F FFFF
H'0040 0000

H'005F FFFF
H'0060 0000

H'007F FFFF

Interna
ROM area
(1 Mbytes

<Single-chip mode>

Interna

ROM area

(1 Mbytes

CS0 area

CS1 area

CS2 area

Extended external area

CS3 area

<External extension mode>

CS0 area

CS1 area

CS2 area

Extended external area

CS3 area

<Processor mode>

Figure 3.2.1 Internal ROM and Extended External Area Address Mapping of the M32180F8 in Each Operation Mode

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ADDRESS SPACE

3

3.3 Internal ROM and Extended External Areas

3.3 Internal ROM and Extended External Areas

The 8-Mbyte area in the user space from the address H’0000 0000 to the address H’007F FFFF comprise the
internal ROM and extended external areas. For the address mapping of these areas that differs with each opera­tion mode, see Section 3.2, “Operation Modes.”

3.3.1 Internal ROM Area

The internal ROM is allocated to the addresses shown below. Located at the beginning of this area is the EIT
vector entry (and the ICU vector table).

Table 3.3.1 Internal ROM Allocation Address

Type Name Size Allocation Address
M32180F8 1 Mbytes H’0000 0000 to H’000F FFFF

3.3.2 Extended External Area

The extended external area is only available when external extension or processor mode is selected by opera­tion mode settings. When accessing the extended external area, the control signals necessary to access exter­nal devices are output.

The CS0# through CS3# signals are output corresponding to the address mapping of the extended external
area. The CS0#, CS1#, CS2# and CS3# signals are output for the CS0, CS1, CS2 and CS3 areas, respectively.

Table 3.3.2 Address Mapping of the Extended External Area in Each Operation Mode

Operation Mode Address Mapping of Extended External Area
Single-chip mode None
External extension mode Addresses H’0010 0000 to H’001F FFFF (CS0 area: 1 Mbytes)

Addresses H’0020 0000 to H’003F FFFF (CS1 area: 2 Mbytes)
Addresses H’0040 0000 to H’005F FFFF (CS2 area: 2 Mbytes)
Addresses H’0060 0000 to H’007F FFFF (CS3 area: 2 Mbytes)

Processor mode Addresses H’0000 0000 to H’001F FFFF (CS0 area: 2 Mbytes)

Addresses H’0020 0000 to H’003F FFFF (CS1 area: 2 Mbytes)
Addresses H’0040 0000 to H’005F FFFF (CS2 area: 2 Mbytes)
Addresses H’0060 0000 to H’007F FFFF (CS3 area: 2 Mbytes)

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ADDRESS SPACE

3

3.4 Internal RAM and SFR Areas

3.4 Internal RAM and SFR Areas

The 8-Mbyte area from the address H’0080 0000 to the address H’00FF FFFF comprise the internal RAM and
SFR (Special Function Register) areas. Of these, the space that the user can actually use is a 128-Kbyte area
from the address H’0080 0000 to the address H’0081 FFFF. The other areas here are ghosts in 128-Kbyte units.
(Do not use the ghost area intentionally during programming.)

3.4.1 Internal RAM Area

The internal RAM area is allocated to the addresses shown below.

Table 3.4.1 Internal RAM Allocation Address

Type Name Size Allocation Address
M32180F8 48 Kbytes H’0080 4000 to H’0080 FFFF

3.4.2 SFR (Special Function Register) Area

The addresses H’0080 0000 to H’0080 3FFFF comprise the SFR (Special Function Register) area. Located in
this area are the internal peripheral I/O registers.

H'0080 0000

SFR area

(16 Kbytes)

H'0080 3FFF
H'0080 4000

H'0080 7FFF
H'0080 8000

Internal RAM

(48 Kbytes)

Virtual flash emulation areas
separated in 4-Kbyte units
can be allocated here.
For details, see Section 6.6.

H'0080 FFFF

Figure 3.4.1 Internal RAM and SFR (Special Function Register) Areas of the M32180F8

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32180 Group User’s Manual (Rev.1.0)

3

r

(

)

r

0

3

r

l

)

JT

(

OP

)

O

)

JT

(

)

JT

(

0

)

C

t

4

5

r

JT

(

)

JT

(

OU1

)

JT

(

)

JT

(

0

)

JT

(

OU0

)

JT

(

OU2

)

JT

(

)

CAN0

CAN1

0080 0AEE

0080 0B8C

0080 0C8C

E

0080 0CE2

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

H'0080 0000

H'0080 007E

H'0080 0080
H'0080 00EE

H'0080 0100
H'0080 0146
H'0080 0180

H'0080 0186
H'0080 01E0

H'0080 01F8
H'0080 0200

H'0080 023E
H'0080 0240

H'0080 02FE
H'0080 0300

H'0080 03BE
H'0080 03C0

H'0080 03D8
H'0080 03E0

H'0080 03FE
H'0080 0400

H'0080 0478

07815

+0 address +1 address

Interrupt Controlle

ICU

A-D0 Converte

Serial I/O

Wait Controlle

Flash contro

MJT (common part

M

T

MJT(TI

M

M

DMA

TMS

TML

Multijunction

timer (MJT)

H'0080 078C
H'0080 078E

H'0080 0790
H'0080 07E2

H'0080 0A00
H'0080 0A26

H'0080 0A80
H'

H'
H'0080 0B8E

H'0080 0B90

H'0080 0BE2

H'
H'0080 0C8

H'0080 0C90

H'

H'0080 0FE0
H'0080 0FFE

H'0080 1000

H'0080 11FE

07815

+0 address +1 address

M

TID

M

T

Serial I/O

A-D1 Converte

M

M

T

M

M

T

M

Multijunction

timer (MJT)

Multijunction

timer (MJT)

H'0080 0700

Input/output por

H'0080 077F

Note: • The Real-time Debugger (RTD) is an independent module that is operated from the outside, and is transparent to
the CPU.

H'0080 1400

H'0080 15FE

Figure 3.4.2 Outline Mapping of the SFR Area

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32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (1/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0000 Interrupt Vector Register 5-5
H'0080 0002 (Use inhibited area)
H'0080 0004 Interrupt Request Mask Register (Use inhibited area) 5-6
H'0080 0006 SBI Control Register (SBICR) (Use inhibited area) 5-7

H'0080 0060 CAN0 Transmit/Receive & Error Interrupt Control Register TIN30–33 Input Interrupt Control Register 5-8
H'0080 0062 TID2 Output Interrupt Control Register A-D1 Conversion Interrupt Control Register 5-8
H'0080 0064 SIO4, 5 Transmit/Receive Interrupt Control Register TOU1, 2 Output Interrupt Control Register 5-8
H'0080 0066 TID1 Output Interrupt Control Register RTD Interrupt Control Register 5-8
H'0080 0068 SIO2, 3 Transmit/Receive Interrupt Control Register DMA5–9 Interrupt Control Register 5-8
H'0080 006A TOU0 Output Interrupt Control Register TID0 Output Interrupt Control Register 5-8
H'0080 006C A-D0 Conversion Interrupt Control Register SIO0 Transmit Interrupt Control Register 5-8
H'0080 006E SIO0 Receive Interrupt Control Register SIO1 Transmit Interrupt Control Register 5-8
H'0080 0070 SIO1 Receive Interrupt Control Register DMA0–4 Interrupt Control Register 5-8
H'0080 0072 TIO0–3 Output Interrupt Control Register TOP6, 7 Output Interrupt Control Register 5-8
H'0080 0074 TOP0–5 Output Interrupt Control Register TIO8, 9 Output Interrupt Control Register 5-8
H'0080 0076 TIO4–7 Output Interrupt Control Register TOP10 Output Interrupt Control Register 5-8
H'0080 0078 TOP8, 9 Output Interrupt Control Register TMS0, 1 Output Interrupt Control Register 5-8
H'0080 007A TIN7–11 Input Interrupt Control Register TIN0–2 Input Interrupt Control Register 5-8
H'0080 007C TIN12 –19 Input Interrupt Control Register TIN20–29 Input Interrupt Control Register 5-8
H'0080 007E TIN3–6 Input Interrupt Control Register CAN1 Transmit/Receive & Error Interrupt Control Register 5-8
H'0080 0080 A-D0 Single Mode Register 0 A-D0 Single Mode Register 1 11-16
H'0080 0082 (Use inhibited area)
H'0080 0084 A-D0 Scan Mode Register 0 A-D0 Scan Mode Register 1 11-20
H'0080 0086 A-D0 Disconnection Detection Assist Function Control Register A-D0 Conversion Speed Control Register 11-25
H'0080 0088 A-D0 Successive Approximation Register 11-29
H'0080 008A A-D0 Disconnection Detection Assist Method Select Register 11-26
H'0080 008C A-D0 Comparate Data Register 11-30
H'0080 008E (Use inhibited area)
H'0080 0090 10-bit A-D0 Data Register 0 11-31
H'0080 0092 10-bit A-D0 Data Register 1 11-31
H'0080 0094 10-bit A-D0 Data Register 2 11-31
H'0080 0096 10-bit A-D0 Data Register 3 11-31
H'0080 0098 10-bit A-D0 Data Register 4 11-31
H'0080 009A 10-bit A-D0 Data Register 5 11-31

b0 b7 b8 b15

(IVECT)

(IMASK)

|

(SBICR)

(Use inhibited area)

(ICAN0CR) (ITIN3033CR)

(ITID2CR) (IAD1CCR)

(ISIO45CR) (ITOU12CR)

(ITID1CR) (IRTDCR)

(ISIO23CR) (IDMA59CR)

(ITOU0CR) (ITID0CR)

(IAD0CCR) (ISIO0TXCR)
(ISIO0RXCR) (ISIO1TXCR)
(ISIO1RXCR) (IDMA04CR)

(ITIO03CR) (ITOP67CR)

(ITOP05CR) (ITIO89CR)

(ITIO47CR) (ITOP10CR)
(ITOP89CR) (ITMS01CR)
(ITIN711CR) (ITIN02CR)

(ITIN1219CR) (ITIN2029CR)

(ITIN36CR) (ICAN1CR)

(AD0SIM0) (AD0SIM1) 11-18

(AD0SCM0) ( AD0SCM1) 11-22

(AD0DDACR) (AD0CVSCR) 11-24

(AD0SAR)

(AD0DDASEL)

(AD0CMP)

(AD0DT0)
(AD0DT1)
(AD0DT2)
(AD0DT3)
(AD0DT4)
(AD0DT5)

3-8

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (2/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 009C 10-bit A-D0 Data Register 6 11-31
H'0080 009E 10-bit A-D0 Data Register 7 11-31
H'0080 00A0 10-bit A-D0 Data Register 8 11-31
H'0080 00A2 10-bit A-D0 Data Register 9 11-31
H'0080 00A4 10-bit A-D0 Data Register 10 11-31
H'0080 00A6 10-bit A-D0 Data Register 11 11-31
H'0080 00A8 10-bit A-D0 Data Register 12 11-31
H'0080 00AA 10-bit A-D0 Data Register 13 11-31
H'0080 00AC 10-bit A-D0 Data Register 14 11-31
H'0080 00AE 10-bit A-D0 Data Register 15 11-31

H'0080 00D0 (Use inhibited area) 8-bit A-D0 Data Register 0 11-32
H'0080 00D2 (Use inhibited area) 8-bit A-D0 Data Register 1 11-32
H'0080 00D4 (Use inhibited area) 8-bit A-D0 Data Register 2 11-32
H'0080 00D6 (Use inhibited area) 8-bit A-D0 Data Register 3 11-32
H'0080 00D8 (Use inhibited area) 8-bit A-D0 Data Register 4 11-32
H'0080 00DA (Use inhibited area) 8-bit A-D0 Data Register 5 11-32
H'0080 00DC (Use inhibited area) 8-bit A-D0 Data Register 6 11-32
H'0080 00DE (Use inhibited area) 8-bit A-D0 Data Register 7 11-32
H'0080 00E0 (Use inhibited area) 8-bit A-D0 Data Register 8 11-32
H'0080 00E2 (Use inhibited area) 8-bit A-D0 Data Register 9 11-32
H'0080 00E4 (Use inhibited area) 8-bit A-D0 Data Register 10 11-32
H'0080 00E6 (Use inhibited area) 8-bit A-D0 Data Register 11 11-32
H'0080 00E8 (Use inhibited area) 8-bit A-D0 Data Register 12 11-32
H'0080 00EA (Use inhibited area) 8-bit A-D0 Data Register 13 11-32
H'0080 00EC (Use inhibited area) 8-bit A-D0 Data Register 14 11-32
H'0080 00EE (Use inhibited area) 8-bit A-D0 Data Register 15 11-32

H'0080 0100 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Enable Register 12-9
H'0080 0102 SIO03 Interrupt Request Source Select Register (Use inhibited area) 12-11

H'0080 0110 SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register 12-14
H'0080 0112 SIO0 Transmit Buffer Register 12-18
H'0080 0114 SIO0 Receive Buffer Register 12-19

b0 b7 b8 b15

(AD0DT6)
(AD0DT7)
(AD0DT8)

(AD0DT9)
(AD0DT10)
(AD0DT11)
(AD0DT12)
(AD0DT13)
(AD0DT14)

|

|

(SI23STAT) (SI03EN) 12-10

(SI03SEL)

|

(S0TCNT) (S0MOD) 12-15

(AD0DT15)

(Use inhibited area)

(AD08DT0)
(AD08DT1)
(AD08DT2)
(AD08DT3)
(AD08DT4)
(AD08DT5)
(AD08DT6)
(AD08DT7)
(AD08DT8)

(AD08DT9)
(AD08DT10)
(AD08DT11)
(AD08DT12)
(AD08DT13)
(AD08DT14)
(AD08DT15)

(Use inhibited area)

(Use inhibited area)

(S0TXB)

(S0RXB)

3-9

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (3/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0116 SIO0 Receive Control Register SIO0 Baud Rate Register 12-20

H'0080 0120 SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register 12-14
H'0080 0122 SIO1 Transmit Buffer Register 12-18
H'0080 0124 SIO1 Receive Buffer Register 12-19
H'0080 0126 SIO1 Receive Control Register SIO1 Baud Rate Register 12-20

H'0080 0130 SIO2 Transmit Control Register SIO2 Transmit/Receive Mode Register 12-14
H'0080 0132 SIO2 Transmit Buffer Register 12-18
H'0080 0134 SIO2 Receive Buffer Register 12-19
H'0080 0136 SIO2 Receive Control Register SIO2 Baud Rate Register 12-20

H'0080 0140 SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register 12-14
H'0080 0142 SIO3 Transmit Buffer Register 12-18
H'0080 0144 SSIO3 Receive Buffer Register 12-19
H'0080 0146 SIO3 Receive Control Register SIO3 Baud Rate Register 12-20

H'0080 0180 CS0 Area Wait Control Register CS1 Area Wait Control Register 16-4
H'0080 0182 CS2 Area Wait Control Register CS3 Area Wait Control Register 16-4

H'0080 01E0 Flash Mode Register Flash Status Register 1 6-4
H'0080 01E2 Flash Control Register 1 Flash Control Register 2 6-7
H'0080 01E4 Flash Control Register 3 Flash Control Register 4 6-9
H'0080 01E6 (Use inhibited area)
H'0080 01E8 Virtual Flash S Bank Register 0 6-11
H'0080 01EA Virtual Flash S Bank Register 1 6-11
H'0080 01EC Virtual Flash S Bank Register 2 6-11
H'0080 01EE Virtual Flash S Bank Register 3 6-11
H'0080 01F0 Virtual Flash S Bank Register 4 6-11
H'0080 01F2 Virtual Flash S Bank Register 5 6-11
H'0080 01F4 Virtual Flash S Bank Register 6 6-11
H'0080 01F6 Virtual Flash S Bank Register 7 6-11

H'0080 0200 (Use inhibited area) Clock Bus & Input Event Bus Control Register 10-16
H'0080 0202 Prescaler Register 0 Prescaler Register 1 10-12

b0 b7 b8 b15

|

|

|

|

|

|

(S0RCNT) (S0BAUR) 12-23

(Use inhibited area)

(S1TCNT) (S1MOD) 12-15

(S1TXB)

(S1RXB)

(S1RCNT) (S1BAUR) 12-23

(Use inhibited area)

(S2TCNT) (S2MOD) 12-15

(S2TXB)

(S2RXB)

(S2RCNT) (S2BAUR) 12-23

(Use inhibited area)

(S3TCNT) (S3MOD) 12-15

(S3TXB)

(S3RXB)

(S3RCNT) (S3BAUR) 12-23

(Use inhibited area)

(CS0WTCR) (CS1WTCR)
(CS2WTCR) (CS3WTCR)

(Use inhibited area)

(FMOD) (FSTAT1) 6-5
(FCNT1) (FCNT2) 6-8
(FCNT3) (FCNT4)

(FESBANK0)
(FESBANK1)
(FESBANK2)
(FESBANK3)
(FESBANK4)
(FESBANK5)
(FESBANK6)
(FESBANK7)

(Use inhibited area)

(CKIEBCR)

(PRS0) (PRS1)

3-10

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (4/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0204 Prescaler Register 2 Output Event Bus Control Register 10-12

H'0080 0210 TCLK Input Processing Control Register 10-20
H'0080 0212 TIN0–4 Input Processing Control Register 10-21
H'0080 0214 TIN5–8 Input Processing Control Register 10-22
H'0080 0216 TIN9–11 Input Processing Control Register 10-23
H'0080 0218 TIN12–19 Input Processing Control Register 10-24
H'0080 021A TIN20–23, TIN30–33 Input Processing Control Register 10-24

H'0080 0220 F/F6–15 Source Select Register 10-28
H'0080 0222 (Use inhibited area) F/F16–19 Source Select Register 10-29
H'0080 0224 F/F0–15 Protect Register 10-30
H'0080 0226 F/F0–15 Data Register 10-32
H'0080 0228 (Use inhibited area) F/F16–20 Protect Register 10-30
H'0080 022A (Use inhibited area) F/F16–20 Data Register 10-32

H'0080 0230 TOP0–5 Interrupt Request Status Register TOP0–5 Interrupt Request Mask Register 10-39
H'0080 0232 TOP6, 7 Interrupt Request Mask & Status Register TOP8, 9 Interrupt Request Mask & Status Register 10-41
H'0080 0234 TIO0–3 Interrupt Request Mask & Status Register TIO4–7 Interrupt Request Mask & Status Register 10-43
H'0080 0236 TIO8, 9 Interrupt Request Mask & Status Register TMS0, 1 Interrupt Request Mask & Status Register 10-45
H'0080 0238 TIN0–2 Interrupt Request Mask & Status Register TIN3–6 Interrupt Request Mask & Status Register 10-47
H'0080 023A TIN7–11 Interrupt Request Status Register TIN7–11 Interrupt Request Mask Register 10-49
H'0080 023C TIN12–19 Interrupt Request Status Register TIN12–19 Interrupt Request Mask Register 10-51
H'0080 023E TIN20–23 Interrupt Request Mask & Status Register TIN30–33 Interrupt Request Mask & Status Register 10-53
H'0080 0240 TOP0 Counter 10-75
H'0080 0242 TOP0 Reload Register 10-76
H'0080 0244 (Use inhibited area)
H'0080 0246 TOP0 Correction Register 10-77

H'0080 0250 TOP1 Counter 10-75
H'0080 0252 TOP1 Reload Register 10-76
H'0080 0254 (Use inhibited area)
H'0080 0256 TOP1 Correction Register 10-77

b0 b7 b8 b15

|

|

|

|

|

(PRS2) (OEBCR) 10-17

(Use inhibited area)

(TCLKCR)
(TIN04CR)
(TIN58CR)

(TIN911CR)

(TIN1219CR)

(TIN2023_3033CR)

(Use inhibited area)

(FF615S)

(FF1619S)
(FF015P)
(FF015D)

(FF1620P)

(FF1620D)

(Use inhibited area)

(TOP05IST) (TOP05IMA)
(TOP67IMS) (TOP89IMS) 10-42

(TIO03IMS) (TIO47IMS) 10-44
(TIO89IMS) (TMS01IMS) 10-46
(TIN02IMS) (TIN36IMS) 10-48

(TIN711IST) (TIN711IMA)

(TIN1219IST) (TIN1219IMA)

(TIN2023IMS) (TIN3033IMS) 10-57

(TOP0CT)

(TOP0RL)

(TOP0CC)

(Use inhibited area)

(TOP1CT)

(TOP1RL)

(TOP1CC)

(Use inhibited area)

3-11

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (5/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0260 TOP2 Counter 10-75
H'0080 0262 TOP2 Reload Register 10-76
H'0080 0264 (Use inhibited area)
H'0080 0266 TOP2 Correction Register 10-77

H'0080 0270 TOP3 Counter 10-75
H'0080 0272 TOP3 Reload Register 10-76
H'0080 0274 (Use inhibited area)
H'0080 0276 TOP3 Correction Register 10-77

H'0080 0280 TOP4 Counter 10-75
H'0080 0282 TOP4 Reload Register 10-76
H'0080 0284 (Use inhibited area)
H'0080 0286 TOP4 Correction Register 10-77

H'0080 0290 TOP5 Counter 10-75
H'0080 0292 TOP5 Reload Register 10-76
H'0080 0294 (Use inhibited area)
H'0080 0296 TOP5 Correction Register 10-77
H'0080 0298 (Use inhibited area)
H'0080 029A TOP0–5 Control Register 0 10-71
H'0080 029C (Use inhibited area) TOP0–5 Control Register 1 10-71

H'0080 02A0 TOP6 Counter 10-75
H'0080 02A2 TOP6 Reload Register 10-76
H'0080 02A4 (Use inhibited area)
H'0080 02A6 TOP6 Correction Register 10-77
H'0080 02A8 (Use inhibited area)
H'0080 02AA TOP6, 7 Control Register 10-73

H'0080 02B0 TOP7 Counter 10-75
H'0080 02B2 TOP7 Reload Register 10-76
H'0080 02B4 (Use inhibited area)
H'0080 02B6 TOP7 Correction Register 10-77

b0 b7 b8 b15

(TOP2CT)

(TOP2RL)

|

|

|

|

|

|

(TOP2CC)

(Use inhibited area)

(TOP3CT)

(TOP3RL)

(TOP3CC)

(Use inhibited area)

(TOP4CT)

(TOP4RL)

(TOP4CC)

(Use inhibited area)

(TOP5CT)

(TOP5RL)

(TOP5CC)

(TOP05CR0)

(TOP05CR1)

(Use inhibited area)

(TOP6CT)

(TOP6RL)

(TOP6CC)

(TOP67CR)

(Use inhibited area)

(TOP7CT)

(TOP7RL)

(TOP7CC)

(Use inhibited area)

3-12

32180 Group User’s Manual (Rev.1.0)

ADDRESS SPACE

3

3.4 Internal RAM and SFR Areas

SFR Area Register Map (6/27)

Address +0 address +1 address See pages
H'0080 02C0 TOP8 Counter 10-75
H'0080 02C2 TOP8 Reload Register 10-76
H'0080 02C4 (Use inhibited area)
H'0080 02C6 TOP8 Correction Register 10-77

|

H'0080 02D0 TOP9 Counter 10-75
H'0080 02D2 TOP9 Reload Register 10-76
H'0080 02D4 (Use inhibited area)
H'0080 02D6 TOP9 Correction Register 10-77

|

H'0080 02E0 TOP10 Counter 10-75
H'0080 02E2 TOP10 Reload Register 10-76
H'0080 02E4 (Use inhibited area)

b0 b7 b8 b15

(TOP8CT)
(TOP8RL)

(TOP8CC)

(Use inhibited area)

(TOP9CT)
(TOP9RL)

(TOP9CC)

(Use inhibited area)

(TOP10CT)
(TOP10RL)

H'0080 02E6 TOP10 Correction Register 10-77
H'0080 02E8 (Use inhibited area)
H'0080 02EA TOP8–10 Control Register 10-74

|

H'0080 02FA TOP External Enable Permit Register 10-78
H'0080 02FC TOP Enable Protect Register 10-78
H'0080 02FE TOP Count Enable Register 10-79
H'0080 0300 TIO0 Counter 10-109
H'0080 0302 (Use inhibited area)
H'0080 0304 TIO0 Reload 1 Register 10-111
H'0080 0306 TIO0 Reload 0/ Measure Register 10-110

|

H'0080 0310 TIO1 Counter 10-109
H'0080 0312 (Use inhibited area)
H'0080 0314 TIO1 Reload 1 Register 10-111
H'0080 0316 TIO1 Reload 0/ Measure Register 10-110
H'0080 0318 (Use inhibited area)

(TOP10CC)

(TOP810CR)

(Use inhibited area)

(TOPEEN)
(TOPPRO)
(TOPCEN)

(TIO0CT)

(TIO0RL1)
(TIO0RL0)

(Use inhibited area)

(TIO1CT)

(TIO1RL1)
(TIO1RL0)

H'0080 031A TIO0–3 Control Register 0 10-102
H'0080 031C (Use inhibited area) TIO0–3 Control Register 1 10-103

|

H'0080 0320 TIO2 Counter 10-109
H'0080 0322 (Use inhibited area)

(TIO03CR0)

(Use inhibited area)

(TIO2CT)

3-13

(TIO03CR1)

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (7/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0324 TIO2 Reload 1 Register 10-111
H'0080 0326 TIO2 Reload 0/ Measure Register 10-110

H'0080 0330 TIO3 Counter 10-109
H'0080 0332 (Use inhibited area)
H'0080 0334 TIO3 Reload 1 Register 10-111
H'0080 0336 TIO3 Reload 0/ Measure Register 10-110

H'0080 0340 TIO4 Counter 10-109
H'0080 0343 (Use inhibited area)
H'0080 0344 TIO4 Reload 1 Register 10-111
H'0080 0346 TIO4 Reload 0/ Measure Register 10-110
H'0080 0348 (Use inhibited area)
H'0080 034A TIO4 Control Register TIO5 Control Register 10-104

H'0080 0350 TIO5 Counter 10-109
H'0080 0352 (Use inhibited area)
H'0080 0354 TIO5 Reload 1 Register 10-111
H'0080 0356 TIO5 Reload 0/ Measure Register 10-110

H'0080 0360 TIO6 Counter 10-109
H'0080 0362 (Use inhibited area)
H'0080 0364 TIO6 Reload 1 Register 10-111
H'0080 0366 TIO6 Reload 0/ Measure Register 10-110
H'0080 0368 (Use inhibited area)
H'0080 036A TIO6 Control Register TIO7 Control Register 10-107

H'0080 0370 TIO7 Counter 10-109
H'0080 0372 (Use inhibited area)
H'0080 0374 TIO7 Reload 1 Register 10-111
H'0080 0376 TIO7 Reload 0/ Measure Register 10-110

H'0080 0380 TIO8 Counter 10-109
H'0080 0382 (Use inhibited area)
H'0080 0384 TIO8 Reload 1 Register 10-111

b0 b7 b8 b15

(TIO2RL1)

|

|

(TIO4CR) (TIO5CR) 10-106

|

|

(TIO6CR) (TIO7CR) 10-108

|

|

(TIO2RL0)

(Use inhibited area)

(TIO3CT)

(TIO3RL1)
(TIO3RL0)

(Use inhibited area)

(TIO4CT)

(TIO4RL1)
(TIO4RL0)

(Use inhibited area)

(TIO5CT)

(TIO5RL1)
(TIO5RL0)

(Use inhibited area)

(TIO6CT)

(TIO6RL1)
(TIO6RL0)

(Use inhibited area)

(TIO7CT)

(TIO7RL1)
(TIO7RL0)

(Use inhibited area)

(TIO8CT)

(TIO8RL1)

3-14

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (8/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0386 TIO8 Reload 0/ Measure Register 10-110
H'0080 0388 (Use inhibited area)
H'0080 038A TIO8 Control Register TIO9 Control Register 10-108

H'0080 0390 TIO9 Counter 10-109
H'0080 0392 (Use inhibited area)
H'0080 0394 TIO9 Reload 1 Register 10-111
H'0080 0396 TIO9 Reload 0/ Measure Register 10-110

H'0080 03BC TIO Enable Protect Register 10-112
H'0080 03BE TIO Count Enable Register 10-113
H'0080 03C0 TMS0 Counter 10-130
H'0080 03C2 TMS0 Measure 3 Register 10-130
H'0080 03C4 TMS0 Measure 2 Register 10-130
H'0080 03C6 TMS0 Measure 1 Register 10-130
H'0080 03C8 TMS0 Measure 0 Register 10-130
H'0080 03CA TMS0 Control Register TMS1 Control Register 10-129

H'0080 03D0 TMS1 Counter 10-130
H'0080 03D2 TMS1 Measure 3 Register 10-130
H'0080 03D4 TMS1 Measure 2 Register 10-130
H'0080 03D6 TMS1 Measure 1 Register 10-130
H'0080 03D8 TMS1 Measure 0 Register 10-130

H'0080 03E0 TML0 Counter (Upper) 10-135
H'0080 03E2 (Lower)

H'0080 03EA (Use inhibited area) TML0 Control Register 10-134

H'0080 03F0 TML0 Measure 3 Register (Upper) 10-135
H'0080 03F2 (Lower)
H'0080 03F4 TML0 Measure 2 Register (Upper) 10-135
H'0080 03F6 (Lower)
H'0080 03F8 TML0 Measure 1 Register (Upper) 10-135
H'0080 03FA (Lower)

b0 b7 b8 b15

(TIO8RL0)

|

|

|

|

|

|

(TIO8CR) (TIO9CR) 10-109

(Use inhibited area)

(TIO9CT)

(TIO9RL1)
(TIO9RL0)

(Use inhibited area)

(TIOPRO)
(TIOCEN)

(TMS0CT)
(TMS0MR3)
(TMS0MR2)
(TMS0MR1)
(TMS0MR0)

(TMS0CR) (TMS1CR)

(Use inhibited area)

(TMS1CT)
(TMS1MR3)
(TMS1MR2)
(TMS1MR1)
(TMS1MR0)

(Use inhibited area)

(TML0CT)

(Use inhibited area)

(TML0CR)

(Use inhibited area)

(TML0MR3)

(TML0MR2)

(TML0MR1)

3-15

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (9/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 03FC TML0 Measure 0 Register (Upper) 10-135
H'0080 03FE (Lower)
H'0080 0400 DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register 9-24

H'0080 0408 DMA5–9 Interrupt Request Status Register DMA5–9 Interrupt Request Mask Register 9-24

H'0080 0410 DMA0 Channel Control Register 0 DMA0 Channel Control Register 1 9-6
H'0080 0412 DMA0 Source Address Register 9-19
H'0080 0414 DMA0 Destination Address Register 9-20
H'0080 0416 DMA0 Transfer Count Register 9-21
H'0080 0418 DMA5 Channel Control Register 0 DMA5 Channel Control Register 1 9-11
H'0080 041A DMA5 Source Address Register 9-19
H'0080 041C DMA5 Destination Address Register 9-20
H'0080 041E DMA5 Transfer Count Register 9-21
H'0080 0420 DMA1 Channel Control Register 0 DMA1 Channel Control Register 1 9-7
H'0080 0422 DMA1 Source Address Register 9-19
H'0080 0424 DMA1 Destination Address Register 9-20
H'0080 0426 DMA1 Transfer Count Register 9-21
H'0080 0428 DMA6 Channel Control Register 0 DMA6 Channel Control Register 1 9-12
H'0080 042A DMA6 Source Address Register 9-19
H'0080 042C DMA6 Destination Address Register 9-20
H'0080 042E DMA6 Transfer Count Register 9-21
H'0080 0430 DMA2 Channel Control Register 0 DMA2 Channel Control Register 1 9-8
H'0080 0432 DMA2 Source Address Register 9-19
H'0080 0434 DMA2 Destination Address Register 9-20
H'0080 0436 DMA2 Transfer Count Register 9-21
H'0080 0438 DMA7 Channel Control Register 0 DMA7 Channel Control Register 1 9-13
H'0080 043A DMA7 Source Address Register 9-19
H'0080 043C DMA7 Destination Address Register 9-20
H'0080 043E DMA7 Transfer Count Register 9-21
H'0080 0440 DMA3 Channel Control Register 0 DMA3 Channel Control Register 1 9-9
H'0080 0442 DMA3 Source Address Register 9-19
H'0080 0444 DMA3 Destination Address Register 9-20
H'0080 0446 DMA3 Transfer Count Register 9-21
H'0080 0448 DMA8 Channel Control Register 0 DMA8 Channel Control Register 1 9-14

b0 b7 b8 b15

(TML0MR0)

|

(DM04ITST) (DM04ITMK) 9-25

(DM59ITST) (DM59ITMK) 9-25

|

(DM0CNT0) (DM0CNT1 )

(DM5CNT0) (DM5CNT1 )

(DM1CNT0) (DM1CNT1 )

(DM6CNT0) (DM6CNT1 )

(DM2CNT0) (DM2CNT1 )

(DM7CNT0) (DM7CNT1 )

(DM3CNT0) (DM3CNT1 )

(DM8CNT0) (DM8CNT1 )

(Use inhibited area)

(Use inhibited area)

(DM0SA)
(DM0DA)

(DM0TCT)

(DM5SA)
(DM5DA)

(DM5TCT)

(DM1SA)
(DM1DA)

(DM1TCT)

(DM6SA)
(DM6DA)

(DM6TCT)

(DM2SA)
(DM2DA)

(DM2TCT)

(DM7SA)
(DM7DA)

(DM7TCT)

(DM3SA)
(DM3DA)

(DM3TCT)

3-16

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (10/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 044A DMA8 Source Address Register 9-19
H'0080 044C DMA8 Destination Address Register 9-20
H'0080 044E DMA8 Transfer Count Register 9-21
H'0080 0450 DMA4 Channel Control Register 0 DMA4 Channel Control Register 1 9-10
H'0080 0452 DMA4 Source Address Register 9-19
H'0080 0454 DMA4 Destination Address Register 9-20
H'0080 0456 DMA4 Transfer Count Register 9-21
H'0080 0458 DMA9 Channel Control Register 0 DMA9 Channel Control Register 1 9-15
H'0080 045A DMA9 Source Address Register 9-19
H'0080 045C DMA9 Destination Address Register 9-20
H'0080 045E DMA9 Transfer Count Register 9-21
H'0080 0460 DMA0 Software Request Generation Register 9-18
H'0080 0462 DMA1 Software Request Generation Register 9-18
H'0080 0464 DMA2 Software Request Generation Register 9-18
H'0080 0466 DMA3 Software Request Generation Register 9-18
H'0080 0468 DMA4 Software Request Generation Register 9-18

H'0080 0470 DMA5 Software Request Generation Register 9-18
H'0080 0472 DMA6 Software Request Generation Register 9-18
H'0080 0474 DMA7 Software Request Generation Register 9-18
H'0080 0476 DMA8 Software Request Generation Register 9-18
H'0080 0478 DMA9 Software Request Generation Register 9-18

H'0080 0700 P0 Data Register P1 Data Register 8-7
H'0080 0702 P2 Data Register P3 Data Register 8-7
H'0080 0704 P4 Data Register (Use inhibited area) 8-7
H'0080 0706 P6 Data Register P7 Data Register 8-7
H'0080 0708 P8 Data Register P9 Data Register 8-7
H'0080 070A P10 Data Register P11 Data Register 8-7
H'0080 070C P12 Data Register P13 Data Register 8-7
H'0080 070E P14 Data Register P15 Data Register 8-7
H'0080 0710 P16 Data Register P17 Data Register 8-7
H'0080 0712 P18 Data Register P19 Data Register 8-7
H'0080 0714 P20 Data Register P21 Data Register 8-7
H'0080 0716 P22 Data Register (Use inhibited area) 8-7

b0 b7 b8 b15

(DM8SA)
(DM8DA)

(DM8TCT)

(DM4CNT0) (DM4CNT1)

(DM4SA)
(DM4DA)

(DM4TCT)

(DM9CNT0) (DM9CNT1)

(DM9SA)
(DM9DA)

(DM9TCT)

(DM0SRI)
(DM1SRI)
(DM2SRI)
(DM3SRI)

|

|

(P0DATA) (P1DATA)
(P2DATA) (P3DATA)
(P4DATA)
(P6DATA) (P7DATA)

(P8DATA) (P9DATA)
(P10DATA) (P11DATA)
(P12DATA) (P13DATA)
(P14DATA) (P15DATA)
(P16DATA) (P17DATA)
(P18DATA) (P19DATA)
(P20DATA) (P21DATA)
(P22DATA)

(DM4SRI)

(Use inhibited area)

(DM5SRI)
(DM6SRI)
(DM7SRI)
(DM8SRI)
(DM9SRI)

(Use inhibited area)

3-17

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (11/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0720 P0 Direction Register P1 Direction Register 8-8
H'0080 0722 P2 Direction Register P3 Direction Register 8-8
H'0080 0724 P4 Direction Register (Use inhibited area) 8-8
H'0080 0726 P6 Direction Register P7 Direction Register 8-8
H'0080 0728 P8 Direction Register P9 Direction Register 8-8
H'0080 072A P10 Direction Register P11 Direction Register 8-8
H'0080 072C P12 Direction Register P13 Direction Register 8-8
H'0080 072E P14 Direction Register P15 Direction Register 8-8
H'0080 0730 P16 Direction Register P17 Direction Register 8-8
H'0080 0732 P18 Direction Register P19 Direction Register 8-8
H'0080 0734 P20 Direction Register P21 Direction Register 8-8
H'0080 0736 P22 Direction Register (Use inhibited area) 8-8

H'0080 0740 P0 Operation Mode Register P1 Operation Mode Register 8-9
H'0080 0742 P2 Operation Mode Register P3 Operation Mode Register 8-10
H'0080 0744 P4 Operation Mode Register Port Input Special Function Control Register 8-11
H'0080 0746 P6 Operation Mode Register P7 Operation Mode Register 8-11
H'0080 0748 P8 Operation Mode Register P9 Operation Mode Register 8-12
H'0080 074A P10 Operation Mode Register P11 Operation Mode Register 8-13
H'0080 074C P12 Operation Mode Register P13 Operation Mode Register 8-14
H'0080 074E P14 Operation Mode Register P15 Operation Mode Register 8-15
H'0080 0750 P16 Operation Mode Register P17 Operation Mode Register 8-16
H'0080 0752 P18 Operation Mode Register P19 Operation Mode Register 8-17
H'0080 0754 P20 Operation Mode Register P21 Operation Mode Register 8-18
H'0080 0756 P22 Operation Mode Register (Use inhibited area) 8-19

H'0080 0760 Port Group 0, 1 Input Level Setting Register Port Group 2, 3 Input Level Setting Register 8-25
H'0080 0762 Port Group 4, 5 Input Level Setting Register Port Group 6, 7 Input Level Setting Register 8-25
H'0080 0764 Port Group 8 Input Level Setting Register (Use inhibited area) 8-25

H'0080 076A P10 Peripheral Output Select Register (Use inhibited area) 8-20

H'0080 0776 P22 Peripheral Output Select Register (Use inhibited area) 8-20

H'0080 077E (Use inhibited area) Bus Mode Control Register 15-9

b0 b7 b8 b15

(P0DIR) (P1DIR)
(P2DIR) (P3DIR)
(P4DIR)
(P6DIR) (P7DIR)

(P8DIR) (P9DIR)
(P10DIR) (P11DIR)
(P12DIR) (P13DIR)
(P14DIR) (P15DIR)
(P16DIR) (P17DIR)
(P18DIR) (P19DIR)
(P20DIR) (P21DIR)

|

|

|

|

|

(P22DIR)

(Use inhibited area)

(P0MOD) (P1MOD)
(P2MOD) (P3MOD)
(P4MOD) (PICNT) 8-21
(P6MOD) (P7MOD) 8-12
(P8MOD) (P9MOD) 8-13

(P10MOD) (P11MOD) 8-14
(P12MOD) (P13MOD) 8-15
(P14MOD) (P15MOD) 8-16
(P16MOD) (P17MOD) 8-17
(P18MOD) (P19MOD) 8-18
(P20MOD) (P21MOD) 8-19
(P22MOD)

(Use inhibited area)

(PG01LEV) (PG23LEV)
(PG45LEV) (PG67LEV)

(PG8LEV)

(Use inhibited area)

(P10SMOD)

(Use inhibited area)

(P22SMOD)

(Use inhibited area)

(BUSMODC)

3-18

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (12/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0780 PWM Output 0 Disable Control Register PWM Output 0 Disable Level Control Register 10-174
H'0080 0782 PWM Output 1 Disable Control Register PWM Output 1 Disable Level Control Register 10-174
H'0080 0784 PWM Output 2 Disable Control Register PWM Output 2 Disable Level Control Register 10-175
H'0080 0786 Clock Control Register (Use inhibited area) 18-5

H'0080 078C TID0 Counter 10-144
H'0080 078E TID0 Reload Register 10-144
H'0080 0790 TOU0_0 Counter (Upper) 10-161
H'0080 0792 (Lower) 10-163
H'0080 0794 TOU0_0 Reload Register TOU0_0 Reload 1 Register 10-164
H'0080 0796 TOU0_0 Reload 0 Register 10-166
H'0080 0798 TOU0_1 Counter (Upper) 10-161
H'0080 079A (Lower) 10-163
H'0080 079C TOU0_1 Reload Register TOU0_1 Reload 1 Register 10-164
H'0080 079E TOU0_1 Reload 0 Register 10-166
H'0080 07A0 TOU0_2 Counter (Upper) 10-161
H'0080 07A2 (Lower) 10-163
H'0080 07A4 TOU0_2 Reload Register TOU0_2 Reload 1 Register 10-164
H'0080 07A6 TOU0_2 Reload 0 Register 10-166
H'0080 07A8 TOU0_3 Counter (Upper) 10-161
H'0080 07AA (Lower) 10-163
H'0080 07AC TOU0_3 Reload Register TOU0_3 Reload 1 Register 10-164
H'0080 07AE TOU0_3 Reload 0 Register 10-166
H'0080 07B0 TOU0_4 Counter (Upper) 10-161
H'0080 07B2 (Lower) 10-163
H'0080 07B4 TOU0_4 Reload Register TOU0_4 Reload 1 Register 10-164
H'0080 07B6 TOU0_4 Reload 0 Register 10-166
H'0080 07B8 TOU0_5 Counter (Upper) 10-161
H'0080 07BA (Lower) 10-163
H'0080 07BC TOU0_5 Reload Register TOU0_5 Reload 1 Register 10-164
H'0080 07BE TOU0_5 Reload 0 Register 10-166
H'0080 07C0 TOU0_6 Counter (Upper) 10-161
H'0080 07C2 (Lower) 10-163

b0 b7 b8 b15

(PO0DISCR) (PO0LVCR) 10-177
(PO1DISCR) (PO1LVCR) 10-177
(PO2DISCR) (PO2LVCR) 10-177

|

(CLKCR)

(Use inhibited area)

(TID0CT)
(TID0RL)

(TOU00CTW) (TOU00CTH)

(TOU00CT)

(TOU00RLW) (TOU00RL1) 10-167

(TOU00RL0)

(TOU01CTW) (TOU01CTH)

(TOU01CT)

(TOU01RLW) (TOU01RL1) 10-167

(TOU01RL0)

(TOU02CTW) (TOU02CTH)

(TOU02CT)

(TOU02RLW) (TOU02RL1) 10-167

(TOU02RL0)

(TOU03CTW) (TOU03CTH)

(TOU03CT)

(TOU03RLW) (TOU03RL1) 10-167

(TOU03RL0)

(TOU04CTW) (TOU04CTH)

(TOU04CT)

(TOU04RLW) (TOU04RL1) 10-167

(TOU04RL0)

(TOU05CTW) (TOU05CTH)

(TOU05CT)

(TOU05RLW) (TOU05RL1) 10-167

(TOU05RL0)

(TOU06CTW) (TOU06CTH)

(TOU06CT)

3-19

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (13/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 07C4 TOU0_6 Reload Register TOU0_6 Reload 1 Register 10-164
H'0080 07C6 TOU0_6 Reload 0 Register 10-166
H'0080 07C8 TOU0_7 Counter (Upper) 10-161
H'0080 07CA (Lower) 10-163
H'0080 07CC TOU0_7 Reload Register TOU0_7 Reload 1 Register 10-164
H'0080 07CE TOU0_7 Reload 0 Register 10-166
H'0080 07D0 Prescaler Register 3 TID0 Control & Prescaler 3 Enable Register 10-12
H'0080 07D2 TOU0 Interrupt Request Mask Register TOU0 Interrupt Request Status Register 10-58
H'0080 07D4 (Use inhibited area) F/F21–28 Protect Register 10-31
H'0080 07D6 (Use inhibited area) F/F21–28 Data Register 10-33
H'0080 07D8 TOU0 Control Register 1 10-158
H'0080 07DA TOU0 Control Register 0 10-158
H'0080 07DC (Use inhibited area) TOU0 Enable Protect Register 10-168
H'0080 07DE (Use inhibited area) TOU0 Count Enable Register 10-169
H'0080 07E0 PWMOFF0 Input Processing Control Register TIN24, 25 Input Processing Control Register 10-171
H'0080 07E2 TIN24, 25 Interrupt Request Mask Register TIN24, 25 Interrupt Request Status Register 10-53

H'0080 0A00 SIO45 Interrupt Request Status Register SIO45 Interrupt Request Enable Register 12-9
H'0080 0A02 SIO45 Interrupt Source Select Register (Use inhibited area) 12-11

H'0080 0A10 SIO4 Transmit Control Register SIO4 Transmit/Receive Mode Register 12-14
H'0080 0A12 SIO4 Transmit Buffer Register 12-18
H'0080 0A14 SIO4 Receive Buffer Register 12-19
H'0080 0A16 SIO4 Receive Control Register SIO4 Baud Rate Register 12-20

H'0080 0A20 SIO5 Transmit Control Register SIO5 Transmit/Receive Mode Register 12-14
H'0080 0A22 SIO5 Transmit Buffer Register 12-18
H'0080 0A24 SIO5 Receive Buffer Register 12-19
H'0080 0A26 SIO5 Receive Control Register SIO5 Baud Rate Register 12-20

H'0080 0A80 A-D1 Single Mode Register 0 A-D1 Single Mode Register 1 11-16
H'0080 0A82 (Use inhibited area)
H'0080 0A84 A-D1 Scan Mode Register 0 A-D1 Scan Mode Register 1 11-20
H'0080 0A86 A-D1 Disconnection Detection Assist Function Control Register A-D1 Conversion Speed Control Register 11-25
H'0080 0A88 A-D1 Successive Approximation Register 11-29

b0 b7 b8 b15

(TOU06RLW) (TOU06RL1) 10-167

(TOU06RL0)

(TOU07CTW) (TOU07CTH)

(TOU07CT)

(TOU07RLW) (TOU07RL1) 10-167

(TOU07RL0)

(PRS3) (TID0PRS3EN) 10-141

(TOU0IMA) (TOU0IST)

(FF2128P)

(FF2128D)
(TOU0CR1)
(TOU0CR0)

(TOU0PRO)

(TOU0CEN)

(PWMOFF0CR) (TIN2425CR) 10-25

|

(TIN2425IMA) (TIN2425IST)

(SI45STAT) (SI45EN) 12-10

(SI45SEL)

|

(S4TCNT) (S4MOD) 12-15

(S4RCNT) (S4BAUR) 12-23

|

(S5TCNT) (S5MOD) 12-15

(S5RCNT) (S5BAUR) 12-23

|

(AD1SIM0) (AD1SIM1) 11-18

(AD1SCM0) (AD1SCM1 ) 11-22

(AD1DDACR) (AD1CVSCR) 11-24

(Use inhibited area)

(Use inhibited area)

(S4TXB)

(S4RXB)

(Use inhibited area)

(S5TXB)

(S5RXB)

(Use inhibited area)

(AD1SAR)

3-20

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (14/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0A8A A-D1 Disconnection Detection Assist Method Select Register 11-26
H'0080 0A8C A-D1 Comparate Data Register 11-30
H'0080 0A8E (Use inhibited area)
H'0080 0A90 10-bit A-D1 Data Register 0 11-31
H'0080 0A92 10-bit A-D1 Data Register 1 11-31
H'0080 0A94 10-bit A-D1 Data Register 2 11-31
H'0080 0A96 10-bit A-D1 Data Register 3 11-31
H'0080 0A98 10-bit A-D1 Data Register 4 11-31
H'0080 0A9A 10-bit A-D1 Data Register 5 11-31
H'0080 0A9C 10-bit A-D1 Data Register 6 11-31
H'0080 0A9E 10-bit A-D1 Data Register 7 11-31
H'0080 0AA0 10-bit A-D1 Data Register 8 11-31
H'0080 0AA2 10-bit A-D1 Data Register 9 11-31
H'0080 0AA4 10-bit A-D1 Data Register 10 11-31
H'0080 0AA6 10-bit A-D1 Data Register 11 11-31
H'0080 0AA8 10-bit A-D1 Data Register 12 11-31
H'0080 0AAA 10-bit A-D1 Data Register 13 11-31
H'0080 0AAC 10-bit A-D1 Data Register 14 11-31
H'0080 0AAE 10-bit A-D1 Data Register 15 11-31

H'0080 0AD0 (Use inhibited area) 8-bit A-D1 Data Register 0 11-32
H'0080 0AD2 (Use inhibited area) 8-bit A-D1 Data Register 1 11-32
H'0080 0AD4 (Use inhibited area) 8-bit A-D1 Data Register 2 11-32
H'0080 0AD6 (Use inhibited area) 8-bit A-D1 Data Register 3 11-32
H'0080 0AD8 (Use inhibited area) 8-bit A-D1 Data Register 4 11-32
H'0080 0ADA (Use inhibited area) 8-bit A-D1 Data Register 5 11-32
H'0080 0ADC (Use inhibited area) 8-bit A-D1 Data Register 6 11-32
H'0080 0ADE (Use inhibited area) 8-bit A-D1 Data Register 7 11-32
H'0080 0AE0 (Use inhibited area) 8-bit A-D1 Data Register 8 11-32
H'0080 0AE2 (Use inhibited area) 8-bit A-D1 Data Register 9 11-32
H'0080 0AE4 (Use inhibited area) 8-bit A-D1 Data Register 10 11-32
H'0080 0AE6 (Use inhibited area) 8-bit A-D1 Data Register 11 11-32
H'0080 0AE8 (Use inhibited area) 8-bit A-D1 Data Register 12 11-32
H'0080 0AEA (Use inhibited area) 8-bit A-D1 Data Register 13 11-32
H'0080 0AEC (Use inhibited area) 8-bit A-D1 Data Register 14 11-32

b0 b7 b8 b15

(AD1DDASEL)

(AD1CMP)

(AD1DT0)
(AD1DT1)
(AD1DT2)
(AD1DT3)
(AD1DT4)
(AD1DT5)
(AD1DT6)
(AD1DT7)
(AD1DT8)

(AD1DT9)
(AD1DT10)
(AD1DT11)
(AD1DT12)
(AD1DT13)
(AD1DT14)

|

(AD1DT15)

(Use inhibited area)

(AD18DT0)
(AD18DT1)
(AD18DT2)
(AD18DT3)
(AD18DT4)
(AD18DT5)
(AD18DT6)
(AD18DT7)
(AD18DT8)

(AD18DT9)
(AD18DT10)
(AD18DT11)
(AD18DT12)
(AD18DT13)
(AD18DT14)

3-21

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (15/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0AEE (Use inhibited area) 8-bit A-D1 Data Register 15 11-32

H'0080 0B8C TID1 Counter 10-144
H'0080 0B8E TID1 Reload Register 10-144
H'0080 0B90 TOU1_0 Counter (Upper) 10-161
H'0080 0B92 (Lower) 10-163
H'0080 0B94 TOU1_0 Reload Register TOU1_0 Reload 1 Register 10-164
H'0080 0B96 TOU1_0 Reload 0 Register 10-166
H'0080 0B98 TOU1_1 Counter (Upper) 10-161
H'0080 0B9A (Lower) 10-163
H'0080 0B9C TOU1_1 Reload Register TOU1_1 Reload 1 Register 10-164
H'0080 0B9E TOU1_1 Reload 0 Register 10-166
H'0080 0BA0 TOU1_2 Counter (Upper) 10-161
H'0080 0BA2 (Lower) 10-163
H'0080 0BA4 TOU1_2 Reload Register TOU1_2 Reload 1 Register 10-164
H'0080 0BA6 TOU1_2 Reload 0 Register 10-166
H'0080 0BA8 TOU1_3 Counter (Upper) 10-161
H'0080 0BAA (Lower) 10-163
H'0080 0BAC TOU1_3 Reload Register TOU1_3 Reload 1 Register 10-164
H'0080 0BAE TOU1_3 Reload 0 Register 10-166
H'0080 0BB0 TOU1_4 Counter (Upper) 10-161
H'0080 0BB2 (Lower) 10-163
H'0080 0BB4 TOU1_4 Reload Register TOU1_4 Reload 1 Register 10-164
H'0080 0BB6 TOU1_4 Reload 0 Register 10-166
H'0080 0BB8 TOU1_5 Counter (Upper) 10-161
H'0080 0BBA (Lower) 10-163
H'0080 0BBC TOU1_5 Reload Register TOU1_5 Reload 1 Register 10-164
H'0080 0BBE TOU1_5 Reload 0 Register 10-166
H'0080 0BC0 TOU1_6 Counter (Upper) 10-161
H'0080 0BC2 (Lower) 10-163
H'0080 0BC4 TOU1_6 Reload Register TOU1_6 Reload 1 Register 10-164
H'0080 0BC6 TOU1_6 Reload 0 Register 10-166
H'0080 0BC8 TOU1_7 Counter (Upper) 10-161
H'0080 0BCA (Lower) 10-163

b0 b7 b8 b15

|

(Use inhibited area)

(TID1CT)
(TID1RL)

(TOU10CTW) (TOU10CTH)

(TOU10RLW) (TOU10RL1) 10-167

(TOU11CTW) (TOU11CTH)

(TOU11RLW) (TOU11RL1) 10-167

(TOU12CTW) (TOU12CTH)

(TOU12RLW) (TOU12RL1) 10-167

(TOU13CTW) (TOU13CTH)

(TOU13RLW) (TOU13RL1) 10-167

(TOU14CTW) (TOU14CTH)

(TOU14RLW) (TOU14RL1) 10-167

(TOU15CTW) (TOU15CTH)

(TOU15RLW) (TOU15RL1) 10-167

(TOU16CTW) (TOU16CTH)

(TOU16RLW) (TOU16RL1) 10-167

(TOU17CTW) (TOU17CTH)

(AD18DT15)

(TOU10CT)

(TOU10RL0)

(TOU11CT)

(TOU11RL0)

(TOU12CT)

(TOU12RL0)

(TOU13CT)

(TOU13RL0)

(TOU14CT)

(TOU14RL0)

(TOU15CT)

(TOU15RL0)

(TOU16CT)

(TOU16RL0)

(TOU17CT)

3-22

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (16/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0BCC TOU1_7 Reload Register TOU1_7 Reload 1 Register 10-164
H'0080 0BCE TOU1_7 Reload 0 Register 10-166
H'0080 0BD0 Prescaler Register 4 TID1 Control & Prescaler 4 Enable Register 10-12
H'0080 0BD2 TOU1 Interrupt Request Mask Register TOU1 Interrupt Request Status Register 10-60
H'0080 0BD4 (Use inhibited area) F/F29–36 Protect Register 10-31
H'0080 0BD6 (Use inhibited area) F/F29–36 Data Register 10-33
H'0080 0BD8 TOU1 Control Register 1 10-159
H'0080 0BDA TOU1 Control Register 0 10-159
H'0080 0BDC (Use inhibited area) TOU1 Enable Protect Register 10-168
H'0080 0BDE (Use inhibited area) TOU1 Count Enable Register 10-169
H'0080 0BE0 PWMOFF1 Input Processing Control Register TIN26, 27 Input Processing Control Register 10-171
H'0080 0BE2 TIN26, 27 Interrupt Request Mask Register TIN26, 27 Interrupt Request Status Register 10-54

H'0080 0C8C TID2 Counter 10-144
H'0080 0C8E TID2 Reload Register 10-144
H'0080 0C90 TOU2_0 Counter (Upper) 10-161
H'0080 0C92 (Lower) 10-163
H'0080 0C94 TOU2_0 Reload Register TOU2_0 Reload 1 Register 10-164
H'0080 0C96 TOU2_0 Reload 0 Register 10-166
H'0080 0C98 TOU2_1 Counter (Upper) 10-161
H'0080 0C9A (Lower) 10-163
H'0080 0C9C TOU2_1 Reload Register TOU2_1 Reload 1 Register 10-164
H'0080 0C9E TOU2_1 Reload 0 Register 10-166
H'0080 0CA0 TOU2_2 Counter (Upper) 10-161
H'0080 0CA2 (Lower) 10-163
H'0080 0CA4 TOU2_2 Reload Register TOU2_2 Reload 1 Register 10-164
H'0080 0CA6 TOU2_2 Reload 0 Register 10-166
H'0080 0CA8 TOU2_3 Counter (Upper) 10-161
H'0080 0CAA (Lower) 10-163
H'0080 0CAC TOU2_3 Reload Register TOU2_3 Reload 1 Register 10-164
H'0080 0CAE TOU2_3 Reload 0 Register 10-166
H'0080 0CB0 TOU2_4 Counter (Upper) 10-161
H'0080 0CB2 (Lower) 10-163
H'0080 0CB4 TOU2_4 Reload Register TOU2_4 Reload 1 Register 10-164
H'0080 0CB6 TOU2_4 Reload 0 Register 10-166

b0 b7 b8 b15

(TOU17RLW) (TOU17RL1) 10-167

(TOU17RL0)

(PRS4) (TID1PRS4EN) 10-142

(TOU1IMA) (TOU1IST)

(FF2936P)

(FF2936D)
(TOU1CR1)
(TOU1CR0)

(TOU1PRO)

(TOU1CEN)

(PWMOFF1CR) (TIN2627CR) 10-25

|

(TIN2627IMA) (TIN2627IST)

(Use inhibited area)

(TID2CT)
(TID2RL)

(TOU20CTW) (TOU20CTH)

(TOU20CT)

(TOU20RLW) (TOU20RL1) 10-167

(TOU20RL0)

(TOU21CTW) (TOU21CTH)

(TOU21CT)

(TOU21RLW) (TOU21RL1) 10-167

(TOU21RL0)

(TOU22CTW) (TOU22CTH)

(TOU22CT)

(TOU22RLW) (TOU22RL1) 10-167

(TOU22RL0)

(TOU23CTW) (TOU23CTH)

(TOU23CT)

(TOU23RLW) (TOU23RL1) 10-167

(TOU23RL0)

(TOU24CTW) (TOU24CTH)

(TOU24CT)

(TOU24RLW) (TOU24RL1) 10-167

(TOU24RL0)

3-23

32180 Group User’s Manual (Rev.1.0)

ADDRESS SPACE

3

3.4 Internal RAM and SFR Areas

SFR Area Register Map (17/27)

Address +0 address +1 address See pages
H'0080 0CB8 TOU2_5 Counter (Upper) 10-161
H'0080 0CBA (Lower) 10-163
H'0080 0CBC TOU2_5 Reload Register TOU2_5 Reload 1 Register 10-164
H'0080 0CBE TOU2_5 Reload 0 Register 10-166
H'0080 0CC0 TOU2_6 Counter (Upper) 10-161
H'0080 0CC2 (Lower) 10-163
H'0080 0CC4 TOU2_6 Reload Register TOU2_6 Reload 1 Register 10-164
H'0080 0CC6 TOU2_6 Reload 0 Register 10-166
H'0080 0CC8 TOU2_7 Counter (Upper) 10-161
H'0080 0CCA (Lower) 10-163
H'0080 0CCC TOU2_7 Reload Register TOU2_7 Reload 1 Register 10-164
H'0080 0CCE TOU2_7 Reload 0 Register 10-166
H'0080 0CD0 Prescaler Register 5 TID2 Control & Prescaler 5 Enable Register 10-12
H'0080 0CD2 TOU2 Interrupt Request Mask Register TOU2 Interrupt Request Status Register 10-61
H'0080 0CD4 (Use inhibited area) F/F37–44 Protect Register 10-31
H'0080 0CD6 (Use inhibited area) F/F37–44 Data Register 10-34
H'0080 0CD8 TOU2 Control Register 1 10-160
H'0080 0CDA TOU2 Control Register 0 10-160
H'0080 0CDC (Use inhibited area) TOU2 Enable Protect Register 10-168
H'0080 0CDE (Use inhibited area) TOU2 Count Enable Register 10-169
H'0080 0CE0 PWMOFF2 Input Processing Control Register TIN28, 29 Input Processing Control Register 10-172
H'0080 0CE2 TIN28, 29 Interrupt Request Mask Register TIN28, 29 Interrupt Request Status Register 10-54

|

b0 b7 b8 b15

(TOU25CTW) (TOU25CTH)

(TOU25CT)

(TOU25RLW) (TOU25RL1) 10-167

(TOU25RL0)

(TOU26CTW) (TOU26CTH)

(TOU26CT)

(TOU26RLW) (TOU26RL1) 10-167

(TOU26RL0)

(TOU27CTW) (TOU27CTH)

(TOU27CT)

(TOU27RLW) (TOU27RL1) 10-167

(TOU27RL0)

(PRS5) (TID2PRS5EN) 10-143

(TOU2IMA) (TOU2IST)

(FF3744P)

(FF3744D)
(TOU2CR1)
(TOU2CR0)

(TOU2PRO)
(TOU2CEN)

(PWMOFF2CR) (TIN2829CR) 10-25

(TIN2829IMA) (TIN2829IST)

(Use inhibited area)
H'0080 0FE0 TML1 Counter (Upper) 10-135
H'0080 0FE2 (Lower)

|

H'0080 0FEA (Use inhibited area) TML1 Control Register 10-134

|

H'0080 0FF0 TML1 Measure 3 Register (Upper) 10-135
H'0080 0FF2 (Lower)
H'0080 0FF4 TML1 Measure 2 Register (Upper) 10-135
H'0080 0FF6 (Lower)
H'0080 0FF8 TML1 Measure 1 Register (Upper) 10-135
H'0080 0FFA (Lower)

(TML1CT)

(Use inhibited area)

(Use inhibited area)

(TML1MR3)

(TML1MR2)

(TML1MR1)

3-24

(TML1CR)

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (18/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 0FFC TML1 Measure 0 Register (Upper) 10-135
H'0080 0FFE (Lower)

H'0080 1000 CAN0 Control Register 13-15
H'0080 1002 CAN0 Status Register 13-18
H'0080 1004 CAN0 Frame Format Select Register 13-21
H'0080 1006 CAN0 Configuration Register 13-22
H'0080 1008 CAN0 Timestamp Count Register 13-24
H'0080 100A CAN0 Receive Error Count Register CAN0 Transmit Error Count Register 13-25
H'0080 100C CAN0 Slot Interrupt Request Status Register 13-29
H'0080 100E (Use inhibited area)
H'0080 1010 CAN0 Slot Interrupt Request Enable Register 13-30
H'0080 1012 (Use inhibited area)
H'0080 1014 CAN0 Error Interrupt Request Status Register CAN0 Error Interrupt Request Enable Register 13-31
H'0080 1016 CAN0 Baud Rate Prescaler CAN0 Cause of Error Register 13-26
H'0080 1018 CAN0 Mode Register CAN0 DMA Transfer Request Select Register 13-46

H'0080 1028 CAN0 Global Mask Register Standard ID 0 CAN0 Global Mask Register Standard ID 1 13-48
H'0080 102A CAN0 Global Mask Register Extended ID 0 CAN0 Global Mask Register Extended ID 1 13-49
H'0080 102C CAN0 Global Mask Register Extended ID 2 (Use inhibited area) 13-50
H'0080 102E (Use inhibited area)
H'0080 1030 CAN0 Local Mask Register A Standard ID 0 CAN0 Local Mask Register A Standard ID 1 13-48
H'0080 1032 CAN0 Local Mask Register A Extended ID 0 CAN0 Local Mask Register A Extended ID 1 13-49
H'0080 1034 CAN0 Local Mask Register A Extended ID 2 (Use inhibited area) 13-50
H'0080 1036 (Use inhibited area)
H'0080 1038 CAN0 Local Mask Register B Standard ID 0 CAN0 Local Mask Register B Standard ID 1 13-48
H'0080 103A CAN0 Local Mask Register B Extended ID 0 CAN0 Local Mask Register B Extended ID 1 13-49
H'0080 103C CAN0 Local Mask Register B Extended ID 2 (Use inhibited area) 13-50
H'0080 103E (Use inhibited area)
H'0080 1040 CAN0 Single Shot Mode Control Register 13-52
H'0080 1042 (Use inhibited area)
H'0080 1044 CAN0 Single-Shot Interrupt Request Status Register 13-33
H'0080 1046 (Use inhibited area)
H'0080 1048 CAN0 Single-Shot Interrupt Request Enable Register 3-34
H'0080 1050 CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register 13-53

b0 b7 b8 b15

(TML1MR0)

|

(CAN0REC) (CAN0TEC)

(CAN0ERIST) (CAN0ERIEN) 13-32

(CAN0BRP) (CAN0EF) 13-45
(CAN0MOD) (CAN0DMARQ) 13-47

|

(C0GMSKS0) (C0GMSKS1)
(C0GMSKE0) (C0GMSKE1)
(C0GMSKE2)

(C0LMSKAS0) (C0LMSKAS1)
(C0LMSKAE0) (C0LMSKAE1)
(C0LMSKAE2)

(C0LMSKBS0) (C0LMSKBS1)
(C0LMSKBE0) (C0LMSKBE1)
(C0LMSKBE2)

(C0MSL0CNT) (C0MSL1CNT)

(Use inhibited area)

(CAN0CNT)

(CAN0STAT)

(CAN0FFS)

(CAN0CONF)

(CAN0TSTMP)

(CAN0SLIST)

(CAN0SLIEN)

(Use inhibited area)

(CAN0SSMODE)

(CAN0SSIST)

(CAN0SSIEN)

3-25

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (19/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 1052 CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register 13-53
H'0080 1054 CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register 13-53
H'0080 1056 CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register 13-53
H'0080 1058 CAN0 Message Slot 8 Control Register CAN0 Message Slot 9 Control Register 13-53
H'0080 105A CAN0 Message Slot 10 Control Register CAN0 Message Slot 11 Control Register 13-53
H'0080 105C CAN0 Message Slot 12 Control Register CAN0 Message Slot 13 Control Register 13-53
H'0080 105E CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register 13-53

H'0080 1100 CAN0 Message Slot 0 Standard ID 0 CAN0 Message Slot 0 Standard ID 1 13-57
H'0080 1102 CAN0 Message Slot 0 Extended ID 0 CAN0 Message Slot 0 Extended ID 1 13-59
H'0080 1104 CAN0 Message Slot 0 Extended ID 2 CAN0 Message Slot 0 Data Length Register 13-61
H'0080 1106 CAN0 Message Slot 0 Data 0 CAN0 Message Slot 0 Data 1 13-63
H'0080 1108 CAN0 Message Slot 0 Data 2 CAN0 Message Slot 0 Data 3 13-65
H'0080 110A CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 13-67
H'0080 110C CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 13-69
H'0080 110E CAN0 Message Slot 0 Timestamp 13-71
H'0080 1110 CAN0 Message Slot 1 Standard ID 0 CAN0 Message Slot 1 Standard ID 1 13-57
H'0080 1112 CAN0 Message Slot 1 Extended ID 0 CAN0 Message Slot 1 Extended ID 1 13-59
H'0080 1114 CAN0 Message Slot 1 Extended ID 2 CAN0 Message Slot 1 Data Length Register 13-61
H'0080 1116 CAN0 Message Slot 1 Data 0 CAN0 Message Slot 1 Data 1 13-63
H'0080 1118 CAN0 Message Slot 1 Data 2 CAN0 Message Slot 1 Data 3 13-65
H'0080 111A CAN0 Message Slot 1 Data 4 CAN0 Message Slot 1 Data 5 13-67
H'0080 111C CAN0 Message Slot 1 Data 6 CAN0 Message Slot 1 Data 7 13-69
H'0080 111E CAN0 Message Slot 1 Timestamp 13-71
H'0080 1120 CAN0 Message Slot 2 Standard ID 0 CAN0 Message Slot 2 Standard ID 1 13-57
H'0080 1122 CAN0 Message Slot 2 Extended ID 0 CAN0 Message Slot 2 Extended ID 1 13-59
H'0080 1124 CAN0 Message Slot 2 Extended ID 2 CAN0 Message Slot 2 Data Length Register 13-61
H'0080 1126 CAN0 Message Slot 2 Data 0 CAN0 Message Slot 2 Data 1 13-63
H'0080 1128 CAN0 Message Slot 2 Data 2 CAN0 Message Slot 2 Data 3 13-65
H'0080 112A CAN0 Message Slot 2 Data 4 CAN0 Message Slot 2 Data 5 13-67
H'0080 112C CAN0 Message Slot 2 Data 6 CAN0 Message Slot 2 Data 7 13-69
H'0080 112E CAN0 Message Slot 2 Timestamp 13-71
H'0080 1130 CAN0 Message Slot 3 Standard ID 0 CAN0 Message Slot 3 Standard ID 1 13-57
H'0080 1132 CAN0 Message Slot 3 Extended ID 0 CAN0 Message Slot 3 Extended ID 1 13-59
H'0080 1134 CAN0 Message Slot 3 Extended ID 2 CAN0 Message Slot 3 Data Length Register 13-61

b0 b7 b8 b15

(C0MSL2CNT) (C0MSL3CNT)
(C0MSL4CNT) (C0MSL5CNT)
(C0MSL6CNT) (C0MSL7CNT)

(C0MSL8CNT) (C0MSL9CNT)
(C0MSL10CNT) (C0MSL11CNT)
(C0MSL12CNT) (C0MSL13CNT)

|

(C0MSL14CNT) (C0MSL15CNT)

(Use inhibited area)

(C0MSL0SID0) (C0MSL0SID1) 13-58
(C0MSL0EID0) (C0MSL0EID1) 13-60
(C0MSL0EID2) (C0MSL0DLC) 13-62

(C0MSL0DT0) (C0MSL0DT1) 13-64

(C0MSL0DT2) (C0MSL0DT3) 13-66

(C0MSL0DT4) (C0MSL0DT5) 13-68

(C0MSL0DT6) (C0MSL0DT7) 13-70

(C0MSL0TSP)
(C0MSL1SID0) (C0MSL1SID1) 13-58
(C0MSL1EID0) (C0MSL1EID1) 13-60
(C0MSL1EID2) (C0MSL1DLC) 13-62

(C0MSL1DT0) (C0MSL1DT1) 13-64
(C0MSL1DT2) (C0MSL1DT3) 13-66
(C0MSL1DT4) (C0MSL1DT5) 13-68
(C0MSL1DT6) (C0MSL1DT7) 13-70

(C0MSL1TSP)
(C0MSL2SID0) (C0MSL2SID1) 13-58
(C0MSL2EID0) (C0MSL2EID1) 13-60
(C0MSL2EID2) (C0MSL2DLC) 13-62

(C0MSL2DT0) (C0MSL2DT1) 13-64
(C0MSL2DT2) (C0MSL2DT3) 13-66
(C0MSL2DT4) (C0MSL2DT5) 13-68
(C0MSL2DT6) (C0MSL2DT7) 13-70

(C0MSL2TSP)
(C0MSL3SID0) (C0MSL3SID1) 13-58
(C0MSL3EID0) (C0MSL3EID1) 13-60
(C0MSL3EID2) (C0MSL3DLC) 13-62

3-26

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (20/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 1136 CAN0 Message Slot 3 Data 0 CAN0 Message Slot 3 Data 1 13-63
H'0080 1138 CAN0 Message Slot 3 Data 2 CAN0 Message Slot 3 Data 3 13-65
H'0080 113A CAN0 Message Slot 3 Data 4 CAN0 Message Slot 3 Data 5 13-67
H'0080 113C CAN0 Message Slot 3 Data 6 CAN0 Message Slot 3 Data 7 13-69
H'0080 113E CAN0 Message Slot 3 Timestamp 13-71
H'0080 1140 CAN0 Message Slot 4 Standard ID 0 CAN0 Message Slot 4 Standard ID 1 13-57
H'0080 1142 CAN0 Message Slot 4 Extended ID 0 CAN0 Message Slot 4 Extended ID 1 13-59
H'0080 1144 CAN0 Message Slot 4 Extended ID 2 CAN0 Message Slot 4 Data Length Register 13-61
H'0080 1146 CAN0 Message Slot 4 Data 0 CAN0 Message Slot 4 Data 1 13-63
H'0080 1148 CAN0 Message Slot 4 Data 2 CAN0 Message Slot 4 Data 3 13-65
H'0080 114A CAN0 Message Slot 4 Data 4 CAN0 Message Slot 4 Data 5 13-67
H'0080 114C CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 13-69
H'0080 114E CAN0 Message Slot 4 Timestamp 13-71
H'0080 1150 CAN0 Message Slot 5 Standard ID 0 CAN0 Message Slot 5 Standard ID 1 13-57
H'0080 1152 CAN0 Message Slot 5 Extended ID 0 CAN0 Message Slot 5 Extended ID 1 13-59
H'0080 1154 CAN0 Message Slot 5 Extended ID 2 CAN0 Message Slot 5 Data Length Register 13-61
H'0080 1156 CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 13-63
H'0080 1158 CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3 13-65
H'0080 115A CAN0 Message Slot 5 Data 4 CAN0 Message Slot 5 Data 5 13-67
H'0080 115C CAN0 Message Slot 5 Data 6 CAN0 Message Slot 5 Data 7 13-69
H'0080 115E CAN0 Message Slot 5 Timestamp 13-71
H'0080 1160 CAN0 Message Slot 6 Standard ID 0 CAN0 Message Slot 6 Standard ID 1 13-57
H'0080 1162 CAN0 Message Slot 6 Extended ID 0 CAN0 Message Slot 6 Extended ID 1 13-59
H'0080 1164 CAN0 Message Slot 6 Extended ID 2 CAN0 Message Slot 6 Data Length Register 13-61
H'0080 1166 CAN0 Message Slot 6 Data 0 CAN0 Message Slot 6 Data 1 13-63
H'0080 1168 CAN0 Message Slot 6 Data 2 CAN0 Message Slot 6 Data 3 13-65
H'0080 116A CAN0 Message Slot 6 Data 4 CAN0 Message Slot 6 Data 5 13-67
H'0080 116C CAN0 Message Slot 6 Data 6 CAN0 Message Slot 6 Data 7 13-69
H'0080 116E CAN0 Message Slot 6 Timestamp 13-71
H'0080 1170 CAN0 Message Slot 7 Standard ID 0 CAN0 Message Slot 7 Standard ID 1 13-57
H'0080 1172 CAN0 Message Slot 7 Extended ID 0 CAN0 Message Slot 7 Extended ID 1 13-59
H'0080 1174 CAN0 Message Slot 7 Extended ID 2 CAN0 Message Slot 7 Data Length Register 13-61
H'0080 1176 CAN0 Message Slot 7 Data 0 CAN0 Message Slot 7 Data 1 13-63
H'0080 1178 CAN0 Message Slot 7 Data 2 CAN0 Message Slot 7 Data 3 13-65
H'0080 117A CAN0 Message Slot 7 Data 4 CAN0 Message Slot 7 Data 5 13-67

b0 b7 b8 b15

(C0MSL3DT0) (C0MSL3DT1) 13-64
(C0MSL3DT2) (C0MSL3DT3) 13-66
(C0MSL3DT4) (C0MSL3DT5) 13-68
(C0MSL3DT6) (C0MSL3DT7) 13-70

(C0MSL3TSP)

(C0MSL4SID0) (C0MSL4SID1) 13-58
(C0MSL4EID0) (C0MSL4EID1) 13-60
(C0MSL4EID2) (C0MSL4DLC) 13-62

(C0MSL4DT0) (C0MSL4DT1) 13-64
(C0MSL4DT2) (C0MSL4DT3) 13-66
(C0MSL4DT4) (C0MSL4DT5) 13-68
(C0MSL4DT6) (C0MSL4DT7) 13-70

(C0MSL4TSP)

(C0MSL5SID0) (C0MSL5SID1) 13-58
(C0MSL5EID0) (C0MSL5EID1) 13-60
(C0MSL5EID2) (C0MSL5DLC) 13-62

(C0MSL5DT0) (C0MSL5DT1) 13-64
(C0MSL5DT2) (C0MSL5DT3) 13-66
(C0MSL5DT4) (C0MSL5DT5) 13-68
(C0MSL5DT6) (C0MSL5DT7) 13-70

(C0MSL5TSP)

(C0MSL6SID0) (C0MSL6SID1) 13-58
(C0MSL6EID0) (C0MSL6EID1) 13-60
(C0MSL6EID2) (C0MSL6DLC) 13-62

(C0MSL6DT0) (C0MSL6DT1) 13-64
(C0MSL6DT2) (C0MSL6DT3) 13-66
(C0MSL6DT4) (C0MSL6DT5) 13-68
(C0MSL6DT6) (C0MSL6DT7) 13-70

(C0MSL6TSP)

(C0MSL7SID0) (C0MSL7SID1) 13-58
(C0MSL7EID0) (C0MSL7EID1) 13-60
(C0MSL7EID2) (C0MSL7DLC) 13-62

(C0MSL7DT0) (C0MSL7DT1) 13-64
(C0MSL7DT2) (C0MSL7DT3) 13-66
(C0MSL7DT4) (C0MSL7DT5) 13-68

3-27

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (21/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 117C CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 13-69
H'0080 117E CAN0 Message Slot 7 Timestamp 13-71
H'0080 1180 CAN0 Message Slot 8 Standard ID 0 CAN0 Message Slot 8 Standard ID 1 13-57
H'0080 1182 CAN0 Message Slot 8 Extended ID 0 CAN0 Message Slot 8 Extended ID 1 13-59
H'0080 1184 CAN0 Message Slot 8 Extended ID 2 CAN0 Message Slot 8 Data Length Register 13-61
H'0080 1186 CAN0 Message Slot 8 Data 0 CAN0 Message Slot 8 Data 1 13-63
H'0080 1188 CAN0 Message Slot 8 Data 2 CAN0 Message Slot 8 Data 3 13-65
H'0080 118A CAN0 Message Slot 8 Data 4 CAN0 Message Slot 8 Data 5 13-67
H'0080 118C CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 13-69
H'0080 118E CAN0 Message Slot 8 Timestamp 13-71
H'0080 1190 CAN0 Message Slot 9 Standard ID 0 CAN0 Message Slot 9 Standard ID 1 13-57
H'0080 1192 CAN0 Message Slot 9 Extended ID 0 CAN0 Message Slot 9 Extended ID 1 13-59
H'0080 1194 CAN0 Message Slot 9 Extended ID 2 CAN0 Message Slot 9 Data Length Register 13-61
H'0080 1196 CAN0 Message Slot 9 Data 0 CAN0 Message Slot 9 Data 1 13-63
H'0080 1198 CAN0 Message Slot 9 Data 2 CAN0 Message Slot 9 Data 3 13-65
H'0080 119A CAN0 Message Slot 9 Data 4 CAN0 Message Slot 9 Data 5 13-67
H'0080 119C CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 13-69
H'0080 119E CAN0 Message Slot 9 Timestamp 13-71
H'0080 11A0 CAN0 Message Slot 10 Standard ID 0 CAN0 Message Slot 10 Standard ID 1 13-57
H'0080 11A2 CAN0 Message Slot 10 Extended ID 0 CAN0 Message Slot 10 Extended ID 1 13-59
H'0080 11A4 CAN0 Message Slot 10 Extended ID 2 CAN0 Message Slot 10 Data Length Register 13-61
H'0080 11A6 CAN0 Message Slot 10 Data 0 CAN0 Message Slot 10 Data 1 13-63
H'0080 11A8 CAN0 Message Slot 10 Data 2 CAN0 Message Slot 10 Data 3 13-65
H'0080 11AA CAN0 Message Slot 10 Data 4 CAN0 Message Slot 10 Data 5 13-67
H'0080 11AC CAN0 Message Slot 10 Data 6 CAN0 Message Slot 10 Data 7 13-69
H'0080 11AE CAN0 Message Slot 10 Timestamp 13-71
H'0080 11B0 CAN0 Message Slot 11 Standard ID 0 CAN0 Message Slot 11 Standard ID 1 13-57
H'0080 11B2 CAN0 Message Slot 11 Extended ID 0 CAN0 Message Slot 11 Extended ID 1 13-59
H'0080 11B4 CAN0 Message Slot 11 Extended ID 2 CAN0 Message Slot 11 Data Length Register 13-61
H'0080 11B6 CAN0 Message Slot 11 Data 0 CAN0 Message Slot 11 Data 1 13-63
H'0080 11B8 CAN0 Message Slot 11 Data 2 CAN0 Message Slot 11 Data 3 13-65
H'0080 11BA CAN0 Message Slot 11 Data 4 CAN0 Message Slot 11 Data 5 13-67
H'0080 11BC CAN0 Message Slot 11 Data 6 CAN0 Message Slot 11 Data 7 13-69
H'0080 11BE CAN0 Message Slot 11 Timestamp 13-71
H'0080 11C0 CAN0 Message Slot 12 Standard ID 0 CAN0 Message Slot 12 Standard ID 1 13-57

b0 b7 b8 b15

(C0MSL7DT6) (C0MSL7DT7) 13-70

(C0MSL7TSP)
(C0MSL8SID0) (C0MSL8SID1) 13-58
(C0MSL8EID0) (C0MSL8EID1) 13-60
(C0MSL8EID2) (C0MSL8DLC) 13-62

(C0MSL8DT0) (C0MSL8DT1) 13-64
(C0MSL8DT2) (C0MSL8DT3) 13-66
(C0MSL8DT4) (C0MSL8DT5) 13-68
(C0MSL8DT6) (C0MSL8DT7) 13-70

(C0MSL8TSP)
(C0MSL9SID0) (C0MSL9SID1) 13-58
(C0MSL9EID0) (C0MSL9EID1) 13-60
(C0MSL9EID2) (C0MSL9DLC) 13-62

(C0MSL9DT0) (C0MSL9DT1) 13-64
(C0MSL9DT2) (C0MSL9DT3) 13-66
(C0MSL9DT4) (C0MSL9DT5) 13-68
(C0MSL9DT6) (C0MSL9DT7) 13-70

(C0MSL9TSP)

(C0MSL10SID0) (C0MSL10SID1) 13-58
(C0MSL10EID0) (C0MSL10EID1) 13-60
(C0MSL10EID2) (C0MSL10DLC) 13-62

(C0MSL10DT0) (C0MSL10DT1) 13-64
(C0MSL10DT2) (C0MSL10DT3) 13-66
(C0MSL10DT4) (C0MSL10DT5) 13-68
(C0MSL10DT6) (C0MSL10DT7) 13-70

(C0MSL10TSP)
(C0MSL11SID0) (C0MSL11SID1) 13-58
(C0MSL11EID0) (C0MSL11EID1) 13-60
(C0MSL11EID2) (C0MSL11DLC) 13-62

(C0MSL11DT0) (C0MSL11DT1) 13-64
(C0MSL11DT2) (C0MSL11DT3) 13-66
(C0MSL11DT4) (C0MSL11DT5) 13-68
(C0MSL11DT6) (C0MSL11DT7) 13-70

(C0MSL11TSP)
(C0MSL12SID0) (C0MSL12SID1) 13-58

3-28

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (22/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 11C2 CAN0 Message Slot 12 Extended ID 0 CAN0 Message Slot 12 Extended ID 1 13-59
H'0080 11C4 CAN0 Message Slot 12 Extended ID 2 CAN0 Message Slot 12 Data Length Register 13-61
H'0080 11C6 CAN0 Message Slot 12 Data 0 CAN0 Message Slot 12 Data 1 13-63
H'0080 11C8 CAN0 Message Slot 12 Data 2 CAN0 Message Slot 12 Data 3 13-65
H'0080 11CA CAN0 Message Slot 12 Data 4 CAN0 Message Slot 12 Data 5 13-67
H'0080 11CC CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 13-69
H'0080 11CE CAN0 Message Slot 12 Timestamp 13-71
H'0080 11D0 CAN0 Message Slot 13 Standard ID 0 CAN0 Message Slot 13 Standard ID 1 13-57
H'0080 11D2 CAN0 Message Slot 13 Extended ID 0 CAN0 Message Slot 13 Extended ID 1 13-59
H'0080 11D4 CAN0 Message Slot 13 Extended ID 2 CAN0 Message Slot 13 Data Length Register 13-61
H'0080 11D6 CAN0 Message Slot 13 Data 0 CAN0 Message Slot 13 Data 1 13-63
H'0080 11D8 CAN0 Message Slot 13 Data 2 CAN0 Message Slot 13 Data 3 13-65
H'0080 11DA CAN0 Message Slot 13 Data 4 CAN0 Message Slot 13 Data 5 13-67
H'0080 11DC CAN0 Message Slot 13 Data 6 CAN0 Message Slot 13 Data 7 13-69
H'0080 11DE CAN0 Message Slot 13 Timestamp 13-71
H'0080 11E0 CAN0 Message Slot 14 Standard ID 0 CAN0 Message Slot 14 Standard ID 1 13-57
H'0080 11E2 CAN0 Message Slot 14 Extended ID 0 CAN0 Message Slot 14 Extended ID 1 13-59
H'0080 11E4 CAN0 Message Slot 14 Extended ID 2 CAN0 Message Slot 14 Data Length Register 13-61
H'0080 11E6 CAN0 Message Slot 14 Data 0 CAN0 Message Slot 14 Data 1 13-63
H'0080 11E8 CAN0 Message Slot 14 Data 2 CAN0 Message Slot 14 Data 3 13-65
H'0080 11EA CAN0 Message Slot 14 Data 4 CAN0 Message Slot 14 Data 5 13-67
H'0080 11EC CAN0 Message Slot 14 Data 6 CAN0 Message Slot 14 Data 7 13-69
H'0080 11EE CAN0 Message Slot 14 Timestamp 13-71
H'0080 11F0 CAN0 Message Slot 15 Standard ID 0 CAN0 Message Slot 15 Standard ID 1 13-57
H'0080 11F2 CAN0 Message Slot 15 Extended ID 0 CAN0 Message Slot 15 Extended ID 1 13-59
H'0080 11F4 CAN0 Message Slot 15 Extended ID 2 CAN0 Message Slot 15 Data Length Register 13-61
H'0080 11F6 CAN0 Message Slot 15 Data 0 CAN0 Message Slot 15 Data 1 13-63
H'0080 11F8 CAN0 Message Slot 15 Data 2 CAN0 Message Slot 15 Data 3 13-65
H'0080 11FA CAN0 Message Slot 15 Data 4 CAN0 Message Slot 15 Data 5 13-67
H'0080 11FC CAN0 Message Slot 15 Data 6 CAN0 Message Slot 15 Data 7 13-69
H'0080 11FE CAN0 Message Slot 15 Timestamp 13-71

H'0080 1400 CAN1 Control Register 13-15
H'0080 1402 CAN1 Status Register 13-18
H'0080 1404 CAN1 Frame Format Select Register 13-21

b0 b7 b8 b15

(C0MSL12EID0) (C0MSL12EID1) 13-60
(C0MSL12EID2) (C0MSL12DLC) 13-62

(C0MSL12DT0) (C0MSL12DT1) 13-64
(C0MSL12DT2) (C0MSL12DT3) 13-66
(C0MSL12DT4) (C0MSL12DT5) 13-68
(C0MSL12DT6) (C0MSL12DT7) 13-70

(C0MSL12TSP)
(C0MSL13SID0) (C0MSL13SID1) 13-58
(C0MSL13EID0) (C0MSL13EID1) 13-60
(C0MSL13EID2) (C0MSL13DLC) 13-62

(C0MSL13DT0) (C0MSL13DT1) 13-64
(C0MSL13DT2) (C0MSL13DT3) 13-66
(C0MSL13DT4) (C0MSL13DT5) 13-68
(C0MSL13DT6) (C0MSL13DT7) 13-70

(C0MSL13TSP)
(C0MSL14SID0) (C0MSL14SID1) 13-58
(C0MSL14EID0) (C0MSL14EID1) 13-60
(C0MSL14EID2) (C0MSL14DLC) 13-62

(C0MSL14DT0) (C0MSL14DT1) 13-64
(C0MSL14DT2) (C0MSL14DT3) 13-66
(C0MSL14DT4) (C0MSL14DT5) 13-68
(C0MSL14DT6) (C0MSL14DT7) 13-70

(C0MSL14TSP)
(C0MSL15SID0) (C0MSL15SID1) 13-58
(C0MSL15EID0) (C0MSL15EID1) 13-60
(C0MSL15EID2) (C0MSL15DLC) 13-62

(C0MSL15DT0) (C0MSL15DT1) 13-64
(C0MSL15DT2) (C0MSL15DT3) 13-66
(C0MSL15DT4) (C0MSL15DT5) 13-68
(C0MSL15DT6) (C0MSL15DT7) 13-70

|

(C0MSL15TSP)

(Use inhibited area)

(CAN1CNT)

(CAN1STAT)

(CAN1FFS)

3-29

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (23/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 1406 CAN1 Configuration Register 13-22
H'0080 1408 CAN1 Timestamp Count Register 13-24
H'0080 140A CAN1 Receive Error Count Register CAN1 Transmit Error Count Register 13-25
H'0080 140C CAN1 Slot Interrupt Request Status Register 13-29
H'0080 140E (Use inhibited area)
H'0080 1410 CAN1 Slot Interrupt Request Enable Register 13-30
H'0080 1412 (Use inhibited area)
H'0080 1414 CAN1 Error Interrupt Request Status Register CAN1 Error Interrupt Request Enable Register 13-31
H'0080 1416 CAN1 Baud Rate Prescaler CAN1 Cause of Error Register 13-26
H'0080 1418 CAN1 Mode Register (Use inhibited area) 13-46

H'0080 1428 CAN1 Global Mask Register Standard ID 0 CAN1 Global Mask Register Standard ID 1 13-48
H'0080 142A CAN1 Global Mask Register Extended ID 0 CAN1 Global Mask Register Extended ID 1 13-49
H'0080 142C CAN1 Global Mask Register Extended ID 2 (Use inhibited area) 13-50
H'0080 142E (Use inhibited area)
H'0080 1430 CAN1 Local Mask Register A Standard ID 0 CAN1 Local Mask Register A Standard ID 1 13-48
H'0080 1432 CAN1 Local Mask Register A Extended ID 0 CAN1 Local Mask Register A Extended ID 1 13-49
H'0080 1434 CAN1 Local Mask Register A Extended ID 2 (Use inhibited area) 13-50
H'0080 1436 (Use inhibited area)
H'0080 1438 CAN1 Local Mask Register B Standard ID 0 CAN1 Local Mask Register B Standard ID 1 13-48
H'0080 143A CAN1 Local Mask Register B Extended ID 0 CAN1 Local Mask Register B Extended ID 1 13-49
H'0080 143C CAN1 Local Mask Register B Extended ID 2 (Use inhibited area) 13-50
H'0080 143E (Use inhibited area)
H'0080 1440 CAN1 Single-Shot Mode Control Register 13-52
H'0080 1442 (Use inhibited area)
H'0080 1444 CAN1 Single-Shot Interrupt Request Status Register 13-33
H'0080 1446 (Use inhibited area)
H'0080 1448 CAN1 Single-Shot Interrupt Request Enable Register 13-34

H'0080 1450 CAN1 Message Slot 0 Control Register CAN1 Message Slot 1 Control Register 13-53
H'0080 1452 CAN1 Message Slot 2 Control Register CAN1 Message Slot 3 Control Register 13-53
H'0080 1454 CAN1 Message Slot 4 Control Register CAN1 Message Slot 5 Control Register 13-53
H'0080 1456 CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register 13-53
H'0080 1458 CAN1 Message Slot 8 Control Register CAN1 Message Slot 9 Control Register 13-53
H'0080 145A CAN1 Message Slot 10 Control Register CAN1 Message Slot 11 Control Register 13-53

b0 b7 b8 b15

(CAN1CONF)

(CAN1TSTMP)

(CAN1REC) (CAN1TEC)

(CAN1SLIST)

(CAN1SLIEN)

(CAN1ERIST) (CAN1ERIEN) 13-32

(CAN1BRP) (CAN1EF) 13-45

|

|

(CAN1MOD)

(Use inhibited area)

(C1GMSKS0) (C1GMSKS1)
(C1GMSKE0) (C1GMSKE1)
(C1GMSKE2)

(C1LMSKAS0) (C1LMSKAS1)
(C1LMSKAE0) (C1LMSKAE1)

(C1LMSKAE2)

(C1LMSKBS0) (C1LMSKBS1)
(C1LMSKBE0) (C1LMSKBE1)
(C1LMSKBE2)

(CAN1SSMODE)

(CAN1SSIST)

(CAN1SSIEN)

(Use inhibited area)

(C1MSL0CNT) (C1MSL1CNT)
(C1MSL2CNT) (C1MSL3CNT)
(C1MSL4CNT) (C1MSL5CNT)
(C1MSL6CNT) (C1MSL7CNT)
(C1MSL8CNT) (C1MSL9CNT)

(C1MSL10CNT) (C1MSL11CNT)

3-30

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (24/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 145C CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register 13-53
H'0080 145E CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register 13-53

H'0080 1500 CAN1 Message Slot 0 Standard ID 0 CAN1 Message Slot 0 Standard ID 1 13-57
H'0080 1502 CAN1 Message Slot 0 Extended ID 0 CAN1 Message Slot 0 Extended ID 1 13-59
H'0080 1504 CAN1 Message Slot 0 Extended ID 2 CAN1 Message Slot 0 Data Length Register 13-61
H'0080 1506 CAN1 Message Slot 0 Data 0 CAN1 Message Slot 0 Data 1 13-63
H'0080 1508 CAN1 Message Slot 0 Data 2 CAN1 Message Slot 0 Data 3 13-65
H'0080 150A CAN1 Message Slot 0 Data 4 CAN1 Message Slot 0 Data 5 13-67
H'0080 150C CAN1 Message Slot 0 Data 6 CAN1 Message Slot 0 Data 7 13-69
H'0080 150E CAN1 Message Slot 0 Timestamp 13-71
H'0080 1510 CAN1 Message Slot 1 Standard ID 0 CAN1 Message Slot 1 Standard ID 1 13-57
H'0080 1512 CAN1 Message Slot 1 Extended ID 0 CAN1 Message Slot 1 Extended ID 1 13-59
H'0080 1514 CAN1 Message Slot 1 Extended ID 2 CAN1 Message Slot 1 Data Length Register 13-61
H'0080 1516 CAN1 Message Slot 1 Data 0 CAN1 Message Slot 1 Data 1 13-63
H'0080 1518 CAN1 Message Slot 1 Data 2 CAN1 Message Slot 1 Data 3 13-65
H'0080 151A CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 13-67
H'0080 151C CAN1 Message Slot 1 Data 6 CAN1 Message Slot 1 Data 7 13-69
H'0080 151E CAN1 Message Slot 1 Timestamp 13-71
H'0080 1520 CAN1 Message Slot 2 Standard ID 0 CAN1 Message Slot 2 Standard ID 1 13-57
H'0080 1522 CAN1 Message Slot 2 Extended ID 0 CAN1 Message Slot 2 Extended ID 1 13-59
H'0080 1524 CAN1 Message Slot 2 Extended ID 2 CAN1 Message Slot 2 Data Length Register 13-61
H'0080 1526 CAN1 Message Slot 2 Data 0 CAN1 Message Slot 2 Data 1 13-63
H'0080 1528 CAN1 Message Slot 2 Data 2 CAN1 Message Slot 2 Data 3 13-65
H'0080 152A CAN1 Message Slot 2 Data 4 CAN1 Message Slot 2 Data 5 13-67
H'0080 152C CAN1 Message Slot 2 Data 6 CAN1 Message Slot 2 Data 7 13-69
H'0080 152E CAN1 Message Slot 2 Timestamp 13-71
H'0080 1530 CAN1 Message Slot 3 Standard ID 0 CAN1 Message Slot 3 Standard ID 1 13-57
H'0080 1532 CAN1 Message Slot 3 Extended ID 0 CAN1 Message Slot 3 Extended ID 1 13-59
H'0080 1534 CAN1 Message Slot 3 Extended ID 2 CAN1 Message Slot 3 Data Length Register 13-61
H'0080 1536 CAN1 Message Slot 3 Data 0 CAN1 Message Slot 3 Data 1 13-63
H'0080 1538 CAN1 Message Slot 3 Data 2 CAN1 Message Slot 3 Data 3 13-65
H'0080 153A CAN1 Message Slot 3 Data 4 CAN1 Message Slot 3 Data 5 13-67
H'0080 153C CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 13-69
H'0080 153E CAN1 Message Slot 3 Timestamp 13-71

b0 b7 b8 b15

(C1MSL12CNT) (C1MSL13CNT)

|

(C1MSL14CNT) (C1MSL15CNT)

(C1MSL0SID0) (C1MSL0SID1) 13-58
(C1MSL0EID0) (C1MSL0EID1) 13-60
(C1MSL0EID2) (C1MSL0DLC) 13-62

(C1MSL0DT0) (C1MSL0DT1) 13-64
(C1MSL0DT2) (C1MSL0DT3) 13-66
(C1MSL0DT4) (C1MSL0DT5) 13-68
(C1MSL0DT6) (C1MSL0DT7) 13-70

(C1MSL1SID0) (C1MSL1SID1) 13-58
(C1MSL1EID0) (C1MSL1EID1) 13-60
(C1MSL1EID2) (C1MSL1DLC) 13-62

(C1MSL1DT0) (C1MSL1DT1) 13-64
(C1MSL1DT2) (C1MSL1DT3) 13-66
(C1MSL1DT4) (C1MSL1DT5) 13-68
(C1MSL1DT6) (C1MSL1DT7) 13-70

(C1MSL2SID0) (C1MSL2SID1) 13-58
(C1MSL2EID0) (C1MSL2EID1) 13-60
(C1MSL2EID2) (C1MSL2DLC) 13-62

(C1MSL2DT0) (C1MSL2DT1) 13-64
(C1MSL2DT2) (C1MSL2DT3) 13-66
(C1MSL2DT4) (C1MSL2DT5) 13-68
(C1MSL2DT6) (C1MSL2DT7) 13-70

(C1MSL3SID0) (C1MSL3SID1) 13-58
(C1MSL3EID0) (C1MSL3EID1) 13-60
(C1MSL3EID2) (C1MSL3DLC) 13-62

(C1MSL3DT0) (C1MSL3DT1) 13-64
(C1MSL3DT2) (C1MSL3DT3) 13-66
(C1MSL3DT4) (C1MSL3DT5) 13-68
(C1MSL3DT6) (C1MSL3DT7) 13-70

(Use inhibited area)

(C1MSL0TSP)

(C1MSL1TSP)

(C1MSL2TSP)

(C1MSL3TSP)

3-31

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (25/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 1540 CAN1 Message Slot 4 Standard ID 0 CAN1 Message Slot 4 Standard ID 1 13-57
H'0080 1542 CAN1 Message Slot 4 Extended ID 0 CAN1 Message Slot 4 Extended ID 1 13-59
H'0080 1544 CAN1 Message Slot 4 Extended ID 2 CAN1 Message Slot 4 Data Length Register 13-61
H'0080 1546 CAN1 Message Slot 4 Data 0 CAN1 Message Slot 4 Data 1 13-63
H'0080 1548 CAN1 Message Slot 4 Data 2 CAN1 Message Slot 4 Data 3 13-65
H'0080 154A CAN1 Message Slot 4 Data 4 CAN1 Message Slot 4 Data 5 13-67
H'0080 154C CAN1 Message Slot 4 Data 6 CAN1 Message Slot 4 Data 7 13-69
H'0080 154E CAN1 Message Slot 4 Timestamp 13-71
H'0080 1550 CAN1 Message Slot 5 Standard ID 0 CAN1 Message Slot 5 Standard ID 1 13-57
H'0080 1552 CAN1 Message Slot 5 Extended ID 0 CAN1 Message Slot 5 Extended ID 1 13-59
H'0080 1554 CAN1 Message Slot 5 Extended ID 2 CAN1 Message Slot 5 Data Length Register 13-61
H'0080 1556 CAN1 Message Slot 5 Data 0 CAN1 Message Slot 5 Data 1 13-63
H'0080 1558 CAN1 Message Slot 5 Data 2 CAN1 Message Slot 5 Data 3 13-65
H'0080 155A CAN1 Message Slot 5 Data 4 CAN1 Message Slot 5 Data 5 13-67
H'0080 155C CAN1 Message Slot 5 Data 6 CAN1 Message Slot 5 Data 7 13-69
H'0080 155E CAN1 Message Slot 5 Timestamp 13-71
H'0080 1560 CAN1 Message Slot 6 Standard ID 0 CAN1 Message Slot 6 Standard ID 1 13-57
H'0080 1562 CAN1 Message Slot 6 Extended ID 0 CAN1 Message Slot 6 Extended ID 1 13-59
H'0080 1564 CAN1 Message Slot 6 Extended ID 2 CAN1 Message Slot 6 Data Length Register 13-61
H'0080 1566 CAN1 Message Slot 6 Data 0 CAN1 Message Slot 6 Data 1 13-63
H'0080 1568 CAN1 Message Slot 6 Data 2 CAN1 Message Slot 6 Data 3 13-65
H'0080 156A CAN1 Message Slot 6 Data 4 CAN1 Message Slot 6 Data 5 13-67
H'0080 156C CAN1 Message Slot 6 Data 6 CAN1 Message Slot 6 Data 7 13-69
H'0080 156E CAN1 Message Slot 6 Timestamp 13-71
H'0080 1570 CAN1 Message Slot 7 Standard ID 0 CAN1 Message Slot 7 Standard ID 1 13-57
H'0080 1572 CAN1 Message Slot 7 Extended ID 0 CAN1 Message Slot 7 Extended ID 1 13-59
H'0080 1574 CAN1 Message Slot 7 Extended ID 2 CAN1 Message Slot 7 Data Length Register 13-61
H'0080 1576 CAN1 Message Slot 7 Data 0 CAN1 Message Slot 7 Data 1 13-63
H'0080 1578 CAN1 Message Slot 7 Data 2 CAN1 Message Slot 7 Data 3 13-65
H'0080 157A CAN1 Message Slot 7 Data 4 CAN1 Message Slot 7 Data 5 13-67
H'0080 157C CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 13-69
H'0080 157E CAN1 Message Slot 7 Timestamp 13-71
H'0080 1580 CAN1 Message Slot 8 Standard ID 0 CAN1 Message Slot 8 Standard ID 1 13-57
H'0080 1582 CAN1 Message Slot 8 Extended ID 0 CAN1 Message Slot 8 Extended ID 1 13-59
H'0080 1584 CAN1 Message Slot 8 Extended ID 2 CAN1 Message Slot 8 Data Length Register 13-61

b0 b7 b8 b15

(C1MSL4SID0) (C1MSL4SID1) 13-58
(C1MSL4EID0) (C1MSL4EID1) 13-60
(C1MSL4EID2) (C1MSL4DLC) 13-62

(C1MSL4DT0) (C1MSL4DT1) 13-64
(C1MSL4DT2) (C1MSL4DT3) 13-66
(C1MSL4DT4) (C1MSL4DT5) 13-68
(C1MSL4DT6) (C1MSL4DT7) 13-70

(C1MSL4TSP)
(C1MSL5SID0) (C1MSL5SID1) 13-58
(C1MSL5EID0) (C1MSL5EID1) 13-60
(C1MSL5EID2) (C1MSL5DLC) 13-62

(C1MSL5DT0) (C1MSL5DT1) 13-64
(C1MSL5DT2) (C1MSL5DT3) 13-66
(C1MSL5DT4) (C1MSL5DT5) 13-68
(C1MSL5DT6) (C1MSL5DT7) 13-70

(C1MSL5TSP)
(C1MSL6SID0) (C1MSL6SID1) 13-58
(C1MSL6EID0) (C1MSL6EID1) 13-60
(C1MSL6EID2) (C1MSL6DLC) 13-62

(C1MSL6DT0) (C1MSL6DT1) 13-64
(C1MSL6DT2) (C1MSL6DT3) 13-66
(C1MSL6DT4) (C1MSL6DT5) 13-68
(C1MSL6DT6) (C1MSL6DT7) 13-70

(C1MSL6TSP)
(C1MSL7SID0) (C1MSL7SID1) 13-58
(C1MSL7EID0) (C1MSL7EID1) 13-60
(C1MSL7EID2) (C1MSL7DLC) 13-62

(C1MSL7DT0) (C1MSL7DT1) 13-64
(C1MSL7DT2) (C1MSL7DT3) 13-66
(C1MSL7DT4) (C1MSL7DT5) 13-68
(C1MSL7DT6) (C1MSL7DT7) 13-70

(C1MSL7TSP)
(C1MSL8SID0) (C1MSL8SID1) 13-58
(C1MSL8EID0) (C1MSL8EID1) 13-60
(C1MSL8EID2) (C1MSL8DLC) 13-62

3-32

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (26/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 1586 CAN1 Message Slot 8 Data 0 CAN1 Message Slot 8 Data 1 13-63
H'0080 1588 CAN1 Message Slot 8 Data 2 CAN1 Message Slot 8 Data 3 13-65
H'0080 158A CAN1 Message Slot 8 Data 4 CAN1 Message Slot 8 Data 5 13-67
H'0080 158C CAN1 Message Slot 8 Data 6 CAN1 Message Slot 8 Data 7 13-69
H'0080 158E CAN1 Message Slot 8 Timestamp 13-71
H'0080 1590 CAN1 Message Slot 9 Standard ID 0 CAN1 Message Slot 9 Standard ID 1 13-57
H'0080 1592 CAN1 Message Slot 9 Extended ID 0 CAN1 Message Slot 9 Extended ID 1 13-59
H'0080 1594 CAN1 Message Slot 9 Extended ID 2 CAN1 Message Slot 9 Data Length Register 13-61
H'0080 1596 CAN1 Message Slot 9 Data 0 CAN1 Message Slot 9 Data 1 13-63
H'0080 1598 CAN1 Message Slot 9 Data 2 CAN1 Message Slot 9 Data 3 13-65
H'0080 159A CAN1 Message Slot 9 Data 4 CAN1 Message Slot 9 Data 5 13-67
H'0080 159C CAN1 Message Slot 9 Data 6 CAN1 Message Slot 9 Data 7 13-69
H'0080 159E CAN1 Message Slot 9 Timestamp 13-71
H'0080 15A0 CAN1 Message Slot 10 Standard ID 0 CAN1 Message Slot 10 Standard ID 1 13-57
H'0080 15A2 CAN1 Message Slot 10 Extended ID 0 CAN1 Message Slot 10 Extended ID 1 13-59
H'0080 15A4 CAN1 Message Slot 10 Extended ID 2 CAN1 Message Slot 10 Data Length Register 13-61
H'0080 15A6 CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 13-63
H'0080 15A8 CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 13-65
H'0080 15AA CAN1 Message Slot 10 Data 4 CAN1 Message Slot 10 Data 5 13-67
H'0080 15AC CAN1 Message Slot 10 Data 6 CAN1 Message Slot 10 Data 7 13-69
H'0080 15AE CAN1 Message Slot 10 Timestamp 13-71
H'0080 15B0 CAN1 Message Slot 11 Standard ID 0 CAN1 Message Slot 11 Standard ID 1 13-57
H'0080 15B2 CAN1 Message Slot 11 Extended ID 0 CAN1 Message Slot 11 Extended ID 1 13-59
H'0080 15B4 CAN1 Message Slot 11 Extended ID 2 CAN1 Message Slot 11 Data Length Register 13-61
H'0080 15B6 CAN1 Message Slot 11 Data 0 CAN1 Message Slot 11 Data 1 13-63
H'0080 15B8 CAN1 Message Slot 11 Data 2 CAN1 Message Slot 11 Data 3 13-65
H'0080 15BA CAN1 Message Slot 11 Data 4 CAN1 Message Slot 11 Data 5 13-67
H'0080 15BC CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 13-69
H'0080 15BE CAN1 Message Slot 11 Timestamp 13-71
H'0080 15C0 CAN1 Message Slot 12 Standard ID 0 CAN1 Message Slot 12 Standard ID 1 13-57
H'0080 15C2 CAN1 Message Slot 12 Extended ID 0 CAN1 Message Slot 12 Extended ID 1 13-59
H'0080 15C4 CAN1 Message Slot 12 Extended ID 2 CAN1 Message Slot 12 Data Length Register 13-61
H'0080 15C6 CAN1 Message Slot 12 Data 0 CAN1 Message Slot 12 Data 1 13-63
H'0080 15C8 CAN1 Message Slot 12 Data 2 CAN1 Message Slot 12 Data 3 13-65
H'0080 15CA CAN1 Message Slot 12 Data 4 CAN1 Message Slot 12 Data 5 13-67

b0 b7 b8 b15

(C1MSL8DT0) (C1MSL8DT1) 13-64
(C1MSL8DT2) (C1MSL8DT3) 13-66
(C1MSL8DT4) (C1MSL8DT5) 13-68
(C1MSL8DT6) (C1MSL8DT7) 13-70

(C1MSL8TSP)

(C1MSL9SID0) (C1MSL9SID1) 13-58
(C1MSL9EID0) (C1MSL9EID1) 13-60
(C1MSL9EID2) (C1MSL9DLC) 13-62

(C1MSL9DT0) (C1MSL9DT1) 13-64
(C1MSL9DT2) (C1MSL9DT3) 13-66
(C1MSL9DT4) (C1MSL9DT5) 13-68
(C1MSL9DT6) (C1MSL9DT7) 13-70

(C1MSL9TSP)

(C1MSL10SID0) (C1MSL10SID1) 13-58
(C1MSL10EID0) (C1MSL10EID1) 13-60
(C1MSL10EID2) (C1MSL10DLC) 13-62

(C1MSL10DT0) (C1MSL10DT1) 13-64
(C1MSL10DT2) (C1MSL10DT3) 13-66
(C1MSL10DT4) (C1MSL10DT5) 13-68
(C1MSL10DT6) (C1MSL10DT7) 13-70

(C1MSL10TSP)
(C1MSL11SID0) (C1MSL11SID1) 13-58
(C1MSL11EID0) (C1MSL11EID1) 13-60
(C1MSL11EID2) (C1MSL11DLC) 13-62

(C1MSL11DT0) (C1MSL11DT1) 13-64
(C1MSL11DT2) (C1MSL11DT3) 13-66
(C1MSL11DT4) (C1MSL11DT5) 13-68
(C1MSL11DT6) (C1MSL11DT7) 13-70

(C1MSL11TSP)
(C1MSL12SID0) (C1MSL12SID1) 13-58
(C1MSL12EID0) (C1MSL12EID1) 13-60
(C1MSL12EID2) (C1MSL12DLC) 13-62

(C1MSL12DT0) (C1MSL12DT1) 13-64
(C1MSL12DT2) (C1MSL12DT3) 13-66
(C1MSL12DT4) (C1MSL12DT5) 13-68

3-33

32180 Group User’s Manual (Rev.1.0)

3

SFR Area Register Map (27/27)

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Address +0 address +1 address See pages
H'0080 15CC CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 13-69
H'0080 15CE CAN1 Message Slot 12 Timestamp 13-71
H'0080 15D0 CAN1 Message Slot 13 Standard ID 0 CAN1 Message Slot 13 Standard ID 1 13-57
H'0080 15D2 CAN1 Message Slot 13 Extended ID 0 CAN1 Message Slot 13 Extended ID 1 13-59
H'0080 15D4 CAN1 Message Slot 13 Extended ID 2 CAN1 Message Slot 13 Data Length Register 13-61
H'0080 15D6 CAN1 Message Slot 13 Data 0 CAN1 Message Slot 13 Data 1 13-63
H'0080 15D8 CAN1 Message Slot 13 Data 2 CAN1 Message Slot 13 Data 3 13-65
H'0080 15DA CAN1 Message Slot 13 Data 4 CAN1 Message Slot 13 Data 5 13-67
H'0080 15DC CAN1 Message Slot 13 Data 6 CAN1 Message Slot 13 Data 7 13-69
H'0080 15DE CAN1 Message Slot 13 Timestamp 13-71
H'0080 15E0 CAN1 Message Slot 14 Standard ID 0 CAN1 Message Slot 14 Standard ID 1 13-57
H'0080 15E2 CAN1 Message Slot 14 Extended ID 0 CAN1 Message Slot 14 Extended ID 1 13-59
H'0080 15E4 CAN1 Message Slot 14 Extended ID 2 CAN1 Message Slot 14 Data Length Register 13-61
H'0080 15E6 CAN1 Message Slot 14 Data 0 CAN1 Message Slot 14 Data 1 13-63
H'0080 15E8 CAN1 Message Slot 14 Data 2 CAN1 Message Slot 14 Data 3 13-65
H'0080 15EA CAN1 Message Slot 14 Data 4 CAN1 Message Slot 14 Data 5 13-67
H'0080 15EC CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 13-69
H'0080 15EE CAN1 Message Slot 14 Timestamp 13-71
H'0080 15F0 CAN1 Message Slot 15 Standard ID 0 CAN1 Message Slot 15 Standard ID 1 13-57
H'0080 15F2 CAN1 Message Slot 15 Extended ID 0 CAN1 Message Slot 15 Extended ID 1 13-59
H'0080 15F4 CAN1 Message Slot 15 Extended ID 2 CAN1 Message Slot 15 Data Length Register 13-61
H'0080 15F6 CAN1 Message Slot 15 Data 0 CAN1 Message Slot 15 Data 1 13-63
H'0080 15F8 CAN1 Message Slot 15 Data 2 CAN1 Message Slot 15 Data 3 13-65
H'0080 15FA CAN1 Message Slot 15 Data 4 CAN1 Message Slot 15 Data 5 13-67
H'0080 15FC CAN1 Message Slot 15 Data 6 CAN1 Message Slot 15 Data 7 13-69
H'0080 15FE CAN1 Message Slot 15 Timestamp 13-71

b0 b7 b8 b15

(C1MSL12DT6) (C1MSL12DT7) 13-70

(C1MSL12TSP)
(C1MSL13SID0) (C1MSL13SID1) 13-58
(C1MSL13EID0) (C1MSL13EID1) 13-60
(C1MSL13EID2) (C1MSL13DLC) 13-62

(C1MSL13DT0) (C1MSL13DT1) 13-64
(C1MSL13DT2) (C1MSL13DT3) 13-66
(C1MSL13DT4) (C1MSL13DT5) 13-68
(C1MSL13DT6) (C1MSL13DT7) 13-70

(C1MSL13TSP)
(C1MSL14SID0) (C1MSL14SID1) 13-58
(C1MSL14EID0) (C1MSL14EID1) 13-60
(C1MSL14EID2) (C1MSL14DLC) 13-62

(C1MSL14DT0) (C1MSL14DT1) 13-64
(C1MSL14DT2) (C1MSL14DT3) 13-66
(C1MSL14DT4) (C1MSL14DT5) 13-68
(C1MSL14DT6) (C1MSL14DT7) 13-70

(C1MSL14TSP)
(C1MSL15SID0) (C1MSL15SID1) 13-58
(C1MSL15EID0) (C1MSL15EID1) 13-60
(C1MSL15EID2) (C1MSL15DLC) 13-62

(C1MSL15DT0) (C1MSL15DT1) 13-64
(C1MSL15DT2) (C1MSL15DT3) 13-66
(C1MSL15DT4) (C1MSL15DT5) 13-68
(C1MSL15DT6) (C1MSL15DT7) 13-70

(C1MSL15TSP)

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32180 Group User’s Manual (Rev.1.0)

ADDRESS SPACE

3

3.5 EIT Vector Entry

3.5 EIT Vector Entry

The EIT vector entry is located at the beginning of the internal ROM/extended external areas. The branch instruc­tion for jumping to the start address of each EIT event processing handler is written here. Note that it is the branch
instruction and not the jump address itself that is written here. For details, see Chapter 4, “EIT.”

H'0000 0000
H'0000 0004
H'0000 0008
H'0000 000C
H'0000 0010
H'0000 0014
H'0000 0018
H'0000 001C
H'0000 0020
H'0000 0024
H'0000 0028
H'0000 002C
H'0000 0030
H'0000 0034
H'0000 0038
H'0000 003C
H'0000 0040
H'0000 0044
H'0000 0048
H'0000 004C
H'0000 0050
H'0000 0054
H'0000 0058
H'0000 005C
H'0000 0060
H'0000 0064
H'0000 0068
H'0000 006C
H'0000 0070
H'0000 0074
H'0000 0078
H'0000 007C
H'0000 0080
H'0000 0090

0 31

RI (Reset Interrupt)

SBI (System Break Interrupt)

RIE (Reserved Instruction Exception)

AE (Address Exception)

TRAP0
TRAP1
TRAP2
TRAP3
TRAP4
TRAP5
TRAP6

TRAP7
TRAP8
TRAP9
TRAP10
TRAP11
TRAP12

TRAP13
TRAP14

TRAP15
EI (External Interrupt) (Note 1)
FPE (Floating-Point Exception)

Note 1: When flash entry bit = 1 (flash E/W enable mode), the EI vector entry is located at H'0080 4000.

Figure 3.5.1 EIT Vector Entry

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32180 Group User’s Manual (Rev.1.0)

ADDRESS SPACE

3

3.6 ICU Vector Table

3.6 ICU Vector Table

The ICU vector table is used by the internal interrupt controller of the microcomputer. This table has the addresses
shown below, at which the start addresses of interrupt handlers for the interrupt requests from respective internal
peripheral I/Os are set. For details, see Chapter 5, “Interrupt Controller.”

ICU Vector Table Memory Map (1/2)

Address +0 address +1 address

H'0000 0094 TIN3–6 Input Interrupt Handler Start Address (A0–A15)
H'0000 0096 TIN3–6 Input Interrupt Handler Start Address (A16–A31)
H'0000 0098 TIN20–29 Input Interrupt Handler Start Address (A0–A15)
H'0000 009A TIN20–29 Input Interrupt Handler Start Address (A16–A31)
H'0000 009C TIN12–19 Input Interrupt Handler Start Address (A0–A15)
H'0000 009E TIN12–19 Input Interrupt Handler Start Address (A16–A31)
H'0000 00A0 TIN0–2 Input Interrupt Handler Start Address (A0–A15)
H'0000 00A2 TIN0–2 Input Interrupt Handler Start Address (A16–A31)
H'0000 00A4 TIN7–11 Input Interrupt Handler Start Address (A0–A15)
H'0000 00A6 TIN7–11 Input Interrupt Handler Start Address (A16–A31)
H'0000 00A8 TMS0, 1 Output Interrupt Handler Start Address (A0–A15)
H'0000 00AA TMS0, 1 Output Interrupt Handler Start Address (A16–A31)
H'0000 00AC TOP8, 9 Output Interrupt Handler Start Address (A0–A15)
H'0000 00AE TOP8, 9 Output Interrupt Handler Start Address (A16–A31)
H'0000 00B0 TOP10 Output Interrupt Handler Start Address (A0–A15)
H'0000 00B2 TOP10 Output Interrupt Handler Start Address (A16–A31)
H'0000 00B4 TIO4–7 Output Interrupt Handler Start Address (A0–A15)
H'0000 00B6 TIO4–7 Output Interrupt Handler Start Address (A16–A31)
H'0000 00B8 TIO8, 9 Output Interrupt Handler Start Address (A0–A15)
H'0000 00BA TIO8, 9 Output Interrupt Handler Start Address (A16–A31)
H'0000 00BC TOP0–5 Output Interrupt Handler Start Address (A0–A15)
H'0000 00BE TOP0–5 Output Interrupt Handler Start Address (A16–A31)
H'0000 00C0 TOP6, 7 Output Interrupt Handler Start Address (A0–A15)
H'0000 00C2 TOP6, 7 Output Interrupt Handler Start Address (A16–A31)
H'0000 00C4 TIO0–3 Output Interrupt Handler Start Address (A0–A15)
H'0000 00C6 TIO0–3 Output Interrupt Handler Start Address (A16–A31)
H'0000 00C8 DMA0–4 Interrupt Handler Start Address (A0–A15)
H'0000 00CA DMA0–4 Interrupt Handler Start Address (A16–A31)
H'0000 00CC SIO1 Receive Interrupt Handler Start Address (A0–A15)
H'0000 00CE SIO1 Receive Interrupt Handler Start Address (A16–A31)
H'0000 00D0 SIO1 Transmit Interrupt Handler Start Address (A0–A15)
H'0000 00D2 SIO1 Transmit Interrupt Handler Start Address (A16–A31)
H'0000 00D4 SIO0 Receive Interrupt Handler Start Address (A0–A15)
H'0000 00D6 SIO0 Receive Interrupt Handler Start Address (A16–A31)

b0 b7 b8 b15

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3

ICU Vector Table Memory Map (2/2)

ADDRESS SPACE

3.6 ICU Vector Table

Address +0 address +1 address

H'0000 00D8 SIO0 Transmit Interrupt Handler Start Address (A0–A15)
H'0000 00DA SIO0 Transmit Interrupt Handler Start Address (A16–A31)
H'0000 00DC A-D0 Conversion Interrupt Handler Start Address (A0 –A15)
H'0000 00DE A-D0 Conversion Interrupt Handler Start Address (A16–A31)
H'0000 00E0 TID0 Input Interrupt Handler Start Address (A0–A15)
H'0000 00E2 TID0 Input Interrupt Handler Start Address (A16–A31)
H'0000 00E4 TOU0 Output Interrupt Handler Start Address (A0–A15)
H'0000 00E6 TOU0 Output Interrupt Handler Start Address (A16–A31)
H'0000 00E8 DMA5–9 Interrupt Handler Start Address (A0–A15)
H'0000 00EA DMA5–9 Interrupt Handler Start Address (A16–A31)
H'0000 00EC SIO2, 3 Transmit/receive Interrupt Handler Start Address (A0–A15)
H'0000 00EE SIO2, 3 Transmit/receive Interrupt Handler Start Address (A16–A31)
H'0000 00F0 RTD Interrupt Handler Start Address (A0–A15)
H'0000 00F2 RTD Interrupt Handler Start Address (A16–A31)
H'0000 00F4 TID1 Input Interrupt Handler Start Address (A0–A15)
H'0000 00F6 TID1 Input Interrupt Handler Start Address (A16–A31)
H'0000 00F8 TOU1 + TOU2 Output Interrupt Handler Start Address (A0–A15)
H'0000 00FA TOU1 + TOU2 Output Interrupt Handler Start Address (A16–A31)
H'0000 00FC SIO4, 5 Transmit/receive Interrupt Handler Start Address (A0–A15)
H'0000 00FE SIO4, 5 Transmit/receive Interrupt Handler Start Address (A16–A31)
H'0000 0100 A-D1 Conversion Interrupt Handler Start Address (A0–A15)
H'0000 0102 A-D1 Conversion Interrupt Handler Start Address (A16–A31)
H'0000 0104 TID2 Input Interrupt Handler Start Address (A0–A15)
H'0000 0106 TID2 Input Interrupt Handler Start Address (A16–A31)
H'0000 0108 TIN30–33 Input Interrupt Handler Start Address (A0–A15)
H'0000 010A TIN30–33 Input Interrupt Handler Start Address (A16–A31)
H'0000 010C CAN0 Transmit/receive & Error Interrupt Handler Start Address (A0–A15)
H'0000 010E CAN0 Transmit/receive & Error Interrupt Handler Start Address (A16–A31)
H'0000 0110 CAN1 Transmit/receive & Error Interrupt Handler Start Address (A0–A15)
H'0000 0112 CAN1 Transmit/receive & Error Interrupt Handler Start Address (A16–A31)

b0 b7 b8 b15

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ADDRESS SPACE

3

3.7 Notes about Address Space

3.7 Notes about Address Space

• Virtual flash emulation function

The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000
into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as
the virtual flash emulation function.
This function allows the data located in 4-Kbyte blocks of the internal RAM to be changed with the flash memory
contents at the addresses specified by the Virtual Flash Bank Register. For details about this function, see
Section 6.6, “Virtual Flash Emulation Function.”

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32180 Group User’s Manual (Rev.1.0)

CHAPTER 4

EIT

4.1 Outline of EIT

4.2 EIT Events

4.3 EIT Processing Procedure

4.4 EIT Processing Mechanism

4.5 Acceptance of EIT Events

4.6 Saving and Restoring the PC and PSW

4.7 EIT Vector Entry

4.8 Exception Processing

4.9 Interrupt Processing

4.10 Trap Processing

4.1 1 EIT Priority Levels

4.12 Example of EIT Processing

4.13 Precautions on EIT

4

4.1 Outline of EIT

4.1 Outline of EIT

If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the
program being executed and execute another program. Events like this one are referred to by a generic name as
EIT (Exception, Interrupt and Trap).

(1) Exception

This is an event related to the context being executed. It is generated by an error or violation during instruction
execution. This type of event includes Address Exception (AE), Reserved Instruction Exception (RIE) and Floating­Point Exception (FPE).

(2) Interrupt

This is an event generated irrespective of the context being executed. It is generated by a hardware-derived signal
from an external source, as well as by the internal peripheral I/O. This type of event includes Reset Interrupt (RI),
System Break Interrupt (SBI) and External Interrupt (EI).

(3) Trap

This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally
generated in a program as in the OS’s system call by the programmer.

EIT

EIT

Figure 4.1.1 Classification of EITs

Exception (Exception) Reserved Instruction Exception (RIE)

Address Exception (AE)
Floating-Point Exception (FPE)

Interrupt (Interrupt)

Trap (Trap)

Reset Interrupt (RI)
System Break Interrupt (SBI)

External Interrupt (EI)

Trap (TRAP)

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4.2 EIT Events

4.2.1 Exception

(1) Reserved Instruction Exception (RIE)

Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented
instruction) is detected.

(2) Address Exception (AE)

Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store
instructions.

(3) Floating-point Exception (FPE)

Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions
specified in the IEEE 754 standard (OVF/UDF/IXCT/DIV0/IVLD) is detected. Each exception processing is
outlined below.

1) Overflow Exception (OVF)

The exception occurs when the absolute value of the operation result exceeds the largest describable
precision in the floating-point format. The following table shows the operation results when an OVF oc­curs.

EIT

4.2 EIT Events

Table 4.2.1 Operation Results When an OVF Occurred

Operation Result (Content of the Destination Register)

Sign of the Result

+ +MAX

- -Infinity
+ +I nfinity

- -MAX
+ +MAX

- -MAX
+ +I nfinity

- -Infinity

Operation Result (Content of the Destination Register)

When the OVF EIT processing is

masked (Note 1)

No change

When the OVF EIT processing is

executed (Note 2)

No change

Rounding Mode

-Infinity

+Infinity

0

Nearest

Note 1: When the overflow exception enable (EO) bit (FPSR register bit 20) = "0"
Note 2: When the overflow exception enable (EO) bit (FPSR register bit 20) = "1"
Note: • If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time.

• +MAX = H’7F7F FFFF, –MAX = H’FF7F FFFF

2) Underflow Exception (UDF)

The exception occurs when the absolute value of the operation result is less than the largest describable
precision in the floating-point format. The following table shows the operation results when a UDF occurs.

Table 4.2.2 Operation Results when a UDF Occurred

When UDF EIT processing is masked (Note 1) When UDF EIT processing is executed (Note 2)

DN = 0: An unimplemented exception occurs
DN = 1: 0 is returned

Note 1: When the underflow exception enable (EU) bit (FPSR register bit 18) = "0"
Note 2: When the underflow exception enable (EU) bit (FPSR register bit 18) = "1"

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

4.2 EIT Events

3) Inexact Exception (IXCT)

The exception occurs when the operation result differs from a result led out with an infinite range of
precision. The following table shows the operation results and the respective conditions in which each
IXCT occurs.

Table 4.2.3 Operation Results when an IXCT Occurred

Operation Result (Content of the Destination Register)

Occ urren c e Con dition

When the IXCT EIT processing for is

masked (Note 1)

When the IXCT EIT processing is

executed (Note 2)

EIT

Overflow occurs in OVF masked
condition

Rounding occurs Rounded value No change

Note 1: When the inexact exception enable (EX) bit (FPSR register bit 17) = "0"
Note 2: When the inexact exception enable (EX) bit (FPSR register bit 17) = "1"

4) Zero Division Exception (DIV0)

The exception occurs when a finite nonzero value is divided by zero. The following table shows the
operation results when a DIV0 is occurs.

Table 4.2.4 Operation Results When a DIV0 Occurred

Dividend

Nonzero finite value

Note 1: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "0"
Note 2: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "1"

Please note that the DIV0 EIT processing does not occur in the following conditions.

Table 4.2.5 Cases in Which No DIV0 Occur

Dividend Behavior
0 An invalid operation exception occurs
Infinity No exceptions occur (with the result = "Infinity")

When the DIV0 EIT processing is masked

Reference OVF operation results No change

Operation Result (Content of the Destination Register)

(Note 1)

+-Infinity (Sign is derived by exclusive
ORing the signs of the divisor and
dividend.)

When the DIV0 EIT processing is

executed (Note 2)

No change

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4.2 EIT Events

5) Invalid Operation Exception (IVLD)

The exception occurs when an invalid operation is executed. The following table shows the operation
results and the respective conditions in which each IVLD occurs.

Table 4.2.6 Operation Results When an IVLD Occurred

Operation Result (Content of the Destination Register)

Occ urrence Condition

Operation for SNaN operand
+Infinity-(+Infinity), -Infinity-(-Infinity)
0 x In finity
0 / 0, Infini ty / Infi n ity

When FTOI
When an integer conversion
overflowed
When NaN or Infinity was converted
into an integer

When < or > com parison was performed on NaN

Note 1: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "0"
Note 2: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "1"
Note: • NaN (Not a Number)

SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction is "0". When SNaN is used as the
source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used
as the initial value in a variable. However, SNaNs cannot be generated by hardware.
QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction is "1". Even when QNaN is used as the
source operand in an operation, an IVLD will not occur (excluding comparison and format conversion).
Because a result can be checked by the arithmetic operations, QNaN allows the user to debug without
executing an EIT processing. QNaNs are created by hardware.

instruction was

executed

When FTOS

instruction was

executed

When the IVLD EIT processing is mask ed (Note 1)

QNaN

Return value when pre-conversion signed bit is:
"0": H7FFF FFFF
"1": H 8000 0000

Return value when pre-conversion signed bit is:
"0": H 0000 7FFF
"1": HFFFF 8000

Comparison results (comparison invalid)

When the IVLD EIT

processing is executed

(Note 2)

No change

EIT

6) Unimplemented Exception (UIPL)

The exception occurs when the denormalized number zero flush (DN) bit (FPSR register bit 23) = "0" and
a denormalized number is given as an operation operand. (Note 1)
Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination
register remains unchanged.

Note 1: A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if

the DN bit (FPSR register bit 23) = "0", an UIPL occurs.

4.2.2 Interrupt

(1) Reset Interrupt (RI)

Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the
highest priority.
For details about the reset interrupt, see Chapter 7, “Reset.”

(2) System Break Interrupt (SBI)

System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault
condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt
processing, control will not return to the program that was being executed when the interrupt occurred.

(3) External Interrupt (EI)

External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The
interrupt controller manages these interrupts by assigning each one of eight priority levels including an
interrupt-disabled state.

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4.2 EIT Events

4.2.3 Trap

Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector
addresses are provided corresponding to TRAP instruction operands 0–15.

4.3 EIT Processing Procedure

EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which
they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted,
except for a rest interrupt, is shown below.

EIT request

Instruction

A

generated

InstructionBInstruction

C

Program suspended
and EIT request
accepted

processing-canceled

Program execution restarted

InstructionCInstruction

Instruction

type (RIE, AE)

D

Instruction processing-completed
type (FPE, EI, TRAP)

EIT

RTE

instruction

(Note 1)
BPSW→PSW

BPC→PC

PC→BPC

PSW→BPSW

Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.

Hardware preprocessing

(Note 1)

EIT vector

entry

Branch

instruction

(SBI)

BPC, PSW, FPSR

and general-purpose

registers are saved

to the stack

SBI

(System Break

Interrupt processing)

Hardware postprocessing

User-created EIT handler

EIT handler except for SBI

General-purpose

Processing

by handler

registers, PSW, FPSR
and BPC are restored

from the stack

Program terminated
or system is reset

Figure 4.3.1 Outline of the EIT Processing Procedure

When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described
later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for
the EIT handler (not the jump address itself) is written.

In the hardware preprocessing, the PC is transferred to the BPC (backup PC), and the content of the PSW register’s
PSW field is transferred to the BPSW field in that register.
Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC and
PSW registers (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the
stack. In addition, the accumulator and the FPSR register must be saved to the stack as necessary. Remember
that all these registers must be saved to the stack in a program by the user.

When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute
the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed
when the EIT occurred. (This does not apply to the System Break Interrupt, however.)
In the hardware postprocessing, the BPC is returned to the PC, and the content of the PSW register’s BPSW field
is returned to the PSW field in that register. Note that the values stored in the BPC and the PSW register’s BPSW
field after executing the RTE instruction are undefined.

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4.4 EIT Processing Mechanism

4.4 EIT Processing Mechanism

The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/
Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW
register). The EIT processing mechanism is shown below.

M32R/ECU

M32R CPU core

EIT

RESET#

SBI#

Internal

peripheral

I/Os

Interrupt

controller

(ICU)

RI

SBI

EI

AE, RIE, FPE, TRAP

IE flag
(PSW)

PSWBPSW

PSW register

RI

Priority

SBI

EI

BPC register

PC register

High

Low

Figure 4.4.1 EIT Processing Mechanism

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4.5 Acceptance of EIT Events

4.5 Acceptance of EIT Events

When an EIT event occurs, the CPU suspends the program it has hitherto been executing and branches to EIT
processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are
accepted are shown below.

Table 4.5.1 Acceptance of EIT Events

EIT Event Type of Processing Acceptance Timing Values Set in BPC Register
Reserved Instruction Instruction processing- During instruction execution PC value of the instruction that

Exception (RIE) canceled type generated RIE
Address Exception (AE) Instruction processing- During instruction execution PC value of the instruction that

canceled type generated AE

Floating-Point Exception Instruction processing- Break in instructions PC value of the instruction that
(FPE) completed type generated FPE + 4

Reset Interrupt (RI) Instruction processing- Each machine cycle Undefined value

aborted type

System Break Interrupt Instruction processing- Break in instructions PC value of the next instructi o n
(SBI) completed type (word boundary only)

External Interrupt (EI) Instruction processing- Break in instructions PC value of the next instruction

completed type (word boundary only)

Trap (TRAP) Instruction processing- Break in instructions PC value of TRAP instruction + 4

completed type

EIT

4.6 Saving and Restoring the PC and PSW

The following describes operation of the microcomputer at the time when it accepts an EIT and when it executes the
RTE instruction.

(1) Hardware preprocessing when an EIT is accepted

[1] Save the PSW register’s SM, IE and C bits in its backup field.

BSM ← SM
BIE ← IE
BC ← C

[2] Update the PSW register’s SM, IE and C bits

SM ← Remains unchanged (RIE, AE, FPE, TRAP) or cleared to "0" (SBI, EI, RI)
IE ← Cleared to "0"
C ← Cleared to "0"

[3] Save the PC register

BPC ← PC

[4] Set the vector address in the PC register

Branches to the EIT vector and executes the branch (BRA) instruction written in it, thereby transferring
control to the user-created EIT handler.

(2) Hardware postprocessing when the RTE instruction is executed

[A] Restore the PSW register’s SM, IE and C bits from its backup field.

SM ← BSM
IE ← BIE
C ← BC

[B] Restore the PC register from the BPC register.

PC ← BPC

Note: • The values stored in the BPC and the PSW register’s BSM, BIE and BC bits after executing the RTE

instruction are undefined.

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[1] Saving the SM, IE and C bits

BSM
BIE
BC

[2] Updating the SM, IE and C bits

SM
IE
C

[A] Restoring the SM, IE and C bits from the
backup field

SM
IE
C

The values stored in the BSM, BIE
and BC bits after executing the RTE
instruction are undefined.

SM

←

IE

←

C

←

Unchanged or 0

←

0

←

0

←

BSM

←

BIE

←

BC

←

PSW BPC PC

4.6 Saving and Restoring the PC and PSW

[3] Saving the PC

BPC

[4] Setting the vector address in the PC

PC

[B] Restoring the PC from the BPC register

The value stored in the BPC register
after executing the RTE instruction is
undefined.

PC←

Vector address←

When EIT is accepted

When RTE instruction

is executed

PSW

[1]

[2]

[A] [B]

Figure 4.6.1 Saving and Restoring the PC and PSW

[3]

[4]

BPSW field PSW field

16 17 23 24 25 31(LSB)15870(MSB)

00000000000000000000000000

SM IE CBCBSM BIE

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4.7 EIT Vector Entry

4.7 EIT Vector Entry

The EIT vector entry is located in the user space beginning with the address H’0000 0000. The table below lists the
EIT vector entry.

Table 4.7.1 EIT Vector Entry

Name Abbreviation Vector Address SM IE BPC
Reset Interrupt RI H'0000 0000 (Note 1) 0 0 Undefined
System Break SBI H'0000 0010 0 0 PC of the next instruction

Interrupt

Reserved Instruction RIE H'0000 0020 Unchanged 0 PC of the instruction that generated RIE
Exception

Address Exception AE H'0000 0030 Unchanged 0 PC of the instruction that generated RIE
Trap TRAP0 H'0000 0040 Unchanged 0 PC of TRAP instruction + 4

TRAP1 H'0000 0044 Unchanged 0 PC of TRAP instruction + 4
TRAP2 H'0000 0048 Unchanged 0 PC of TRAP instruction + 4
TRAP3 H'0000 004C Unchanged 0 PC of TRAP instruction + 4
TRAP4 H'0000 0050 Unchanged 0 PC of TRAP instruction + 4
TRAP5 H'0000 0054 Unchanged 0 PC of TRAP instruction + 4
TRAP6 H'0000 0058 Unchanged 0 PC of TRAP instruction + 4
TRAP7 H'0000 005C Unchanged 0 PC of TRAP instruction + 4
TRAP8 H'0000 0060 Unchanged 0 PC of TRAP instruction + 4
TRAP9 H'0000 0064 Unchanged 0 PC of TRAP instruction + 4
TRAP10 H'0000 0068 Unchanged 0 PC of TRAP instruction + 4
TRAP11 H'0000 006C Unchanged 0 PC of TRAP instruction + 4
TRAP12 H'0000 0070 Unchanged 0 PC of TRAP instruction + 4
TRAP13 H'0000 0074 Unchanged 0 PC of TRAP instruction + 4
TRAP14 H'0000 0078 Unchanged 0 PC of TRAP instruction + 4

TRAP15 H'0000 007C Unchanged 0 PC of TRAP instruction + 4
External Interrupt EI H'0000 0080 (Note 2) 0 0 PC of the next instruction
Floating-Point Exception FPE H'0000 0090 Unchanged 0 PC of the instruction that generated FPE + 4

Note 1: During boot mode, the CPU starts executing the boot program after reset. For details, see Section 6.5,

“Programming the Internal Flash Memory.”

Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H’0080

4000). For details, see Section 6.5, “Programming the Internal Flash Memory.”

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4.8 Exception Processing

4.8.1 Reserved Instruction Exception (RIE)

[Occurrence Conditions]

Reserved Instruction Exception (RIE) occurs when a reserved instruction (unimplemented instruction) is
detected. Instruction check is performed on the op-code part of the instruction.
When a reserved instruction exception occurs, the instruction that generated it is not executed. If an exter­nal interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved
instruction exception that is accepted.

[EIT Processing]

(1) Saving SM, IE and C bits

The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.

BSM ← SM
BIE ← IE
BC ← C

(2) Updating SM, IE and C bits

The PSW register’s SM, IE and C bits are updated as shown below.

SM ← Unchanged
IE ← 0
C ← 0

EIT

4.8 Exception Processing

(3) Saving the PC

The PC value of the instruction that generated the reserved instruction exception is set in the BPC register.
For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4
is set in the BPC register. Similarly, if the instruction that generated the reserved instruction exception is at
address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates
whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC
register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1").
However, in either case of the above, the address to which the RTE instruction returns after the EIT handler
has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned
to the PC.)

+0 +1 +2 +3

Address

Return

address

Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE)

H'00
H'04
H'08
H'0C

RIE occurred

BPC

H'04

Return

address

Address

H'00
H'04
H'08
H'0C

+0 +1 +2 +3

BPC

RIE occurred

H'06

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