RENESAS M16C, M28, M28B Technical data

OCO

REJ09B0047-0200

M16C/28 Group

(M16C/28, M16C/28B)

Hardware Manual

RENESAS 16-BIT SINGLE-CHIP MICR

M16C FAMILY / M16C/T iny SERIE

MPUTE

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).

Rev. 2.00 Revision Date: Jan.31, 2007

www.renesas.com

Notes regarding these materials

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.  The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

How to Use This Manual

1. Purpose and Target Readers

This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes.

Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section.

The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details.

The following documents apply to the M16C/28 Group (M16C/28 and M16C/28B). Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site.

Document Type Description Document Title Document No.

Hardware manual Hardware specifications (pin assignments,

memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions.

Software manual Description of CPU instruction set M16C/60,

Application note Information on using peripheral functions and

application examples Sample programs Information on writing programs in assembly

language and C Renesas technical update

Product specifications, updates on documents,

etc.

M16C/28 Group (M16C/28, M16C/28B) Hardware Manual

M16C/20, M16C/Tiny Series Software Manual

Available from Renesas Technology Web site.

This hardware manual

REJ09B0137

2. Notation of Numbers and Symbols

The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below.

(1) Register Names, Bit Names, and Pin Names

Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories. Examples the PM03 bit in the PM0 register

5 pin, VCC pin

(2) Notation of Numbers

The indication “ values of single bits. The indication “ is appended to numeric values given in decimal format. Examples Binary: 11

2” is appended to numeric values given in binary format. However, nothing is appended to the

16” is appended to numeric values given in hexadecimal format. Nothing

Hexadecimal: EFA016 Decimal: 1234

3. Register Notation

The symbols and terms used in register diagrams are described below.

XXX Register

b7 b6 b5 b4 b3 b2 b1 b0

XXX0

XXX1

(b2)

(b3)

XXX4

XXX5

XXX6

XXX7

Symbol Address After Reset XXX XXX 00

Bit NameBit Symbol

XXX bits

Nothing is assigned. If necessary, set to 0. When read, the content is undefined.

Reserved bits

XXX bits

XXX bit

b1 b0

1 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX

Set to 0.

Function varies according to the operating mode.

0: XXX 1: XXX

Function

Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Nothing is assigned.

RW: Read and write. RO: Read only. WO: Write only.

−: Nothing is assigned.

• Reserved bit Reserved bit. Set to specified value.

• Nothing is assigned Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.

• Do not set to a value Operation is not guaranteed when a value is set.

• Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes.

4. List of Abbreviations and Acronyms

Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bps bits per second CRC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment bus I/O Input/Output IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit NC Non-Connection PLL Phase Locked Loop PWM Pulse Width Modulation SFR Special Function Registers SIM Subscriber Identity Module UART Universal Asynchronous Receiver/Transmitter VCO Voltage Controlled Oscillator

All trademarks and registered trademarks are the property of their respective owners. IEBus is a registered trademark of NEC Electronics Corporation.

Quick Reference by Address........................................................................... B-1

1. Overview ......................................................................................................... 1

1.1 Features ...........................................................................................................................1

1.1.1 Applications ................................................................................................................ 1

1.1.2 Specifications ............................................................................................................. 2

1.2 Block Diagram ..................................................................................................................4

1.3 Product Information ..........................................................................................................6

1.4 Pin Assignment...............................................................................................................10

1.5 Pin Description ...............................................................................................................19

2. Central Processing Unit (CPU) ......................................................................22

2.1 Data Registers (R0, R1, R2 and R3) ..............................................................................22

2.2 Address Registers (A0 and A1) ......................................................................................22

2.3 Frame Base Register (FB)..............................................................................................23

2.4 Interrupt Table Register (INTB).......................................................................................23

2.5 Program Counter (PC)....................................................................................................23

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP).......................................... 23

2.7 Static Base Register (SB)...............................................................................................23

2.8 Flag Register (FLG)........................................................................................................ 23

2.8.1 Carry Flag (C Flag) ..................................................................................................23

2.8.2 Debug Flag (D Flag).................................................................................................23

2.8.3 Zero Flag (Z Flag) ...................................................................................................23

2.8.4 Sign Flag (S Flag) ....................................................................................................23

2.8.5 Register Bank Select Flag (B Flag).......................................................................... 23

2.8.6 Overflow Flag (O Flag)............................................................................................. 23

2.8.7 Interrupt Enable Flag (I Flag) ...................................................................................23

2.8.8 Stack Pointer Select Flag (U Flag)...........................................................................23

2.8.9 Processor Interrupt Priority Level (IPL) .................................................................... 23

2.8.10 Reserved Area .......................................................................................................23

3. Memory ..........................................................................................................24

4. Special Function Register (SFR)....................................................................25

A-1

5. Reset..............................................................................................................32

5.1 Hardware Reset..............................................................................................................32

5.1.1 Hardware Reset 1 ....................................................................................................32

5.1.2 Hardware Reset 2 ....................................................................................................32

5.2 Software Reset ...............................................................................................................33

5.3 Watchdog Timer Reset ...................................................................................................33

5.4 Oscillation Stop Detection Reset ....................................................................................33

5.5 Voltage Detection Circuit ................................................................................................35

5.5.1 Low Voltage Detection Interrupt...............................................................................38

5.5.2 Limitations on Stop Mode.........................................................................................40

5.5.3 Limitations on WAIT Instruction................................................................................40

6. Processor Mode .............................................................................................41

7. Clock Generation Circuit ................................................................................44

7.1 Main Clock......................................................................................................................51

7.2 Sub Clock .......................................................................................................................52

7.3 On-chip Oscillator Clock .................................................................................................53

7.4 PLL Clock .......................................................................................................................53

7.5 CPU Clock and Peripheral Function Clock.....................................................................55

7.5.1 CPU Clock................................................................................................................55

7.5.2 Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)........... 55

7.6 Power Control.................................................................................................................56

7.6.1 Normal Operation Mode........................................................................................... 56

7.6.2 Wait Mode ................................................................................................................57

7.6.3 Stop Mode...............................................................................................................59

7.7 System Clock Protective Function.................................................................................. 63

7.8 Oscillation Stop and Re-oscillation Detect Function....................................................... 63

7.8.1 Operation when CM27 bit is set to "0" (Oscillation Stop Detection Reset) ..............64

7.8.2

7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function............................. 65

Operation when CM27 bit is set to "1" (Oscillation Stop and Re-oscillation Detect Interrupt) ....

8. Protection .......................................................................................................66

9. Interrupts ........................................................................................................67

9.1 Type of Interrupts............................................................................................................67

9.1.1 Software Interrupts...................................................................................................68

9.1.2 Hardware Interrupts .................................................................................................69

A-2

9.2 Interrupts and Interrupt Vector........................................................................................70

9.2.1 Fixed Vector Tables.................................................................................................. 70

9.2.2 Relocatable Vector Tables........................................................................................71

9.3 Interrupt Control..............................................................................................................72

9.3.1 I Flag ........................................................................................................................75

9.3.2 IR Bit ........................................................................................................................75

9.3.3 ILVL2 to ILVL0 Bits and IPL......................................................................................75

9.4 Interrupt Sequence .........................................................................................................76

9.4.1 Interrupt Response Time..........................................................................................77

9.4.2 Variation of IPL when Interrupt Request is Accepted ...............................................77

9.4.3 Saving Registers ......................................................................................................78

9.4.4 Returning from an Interrupt Routine.........................................................................80

9.5 Interrupt Priority ..............................................................................................................80

9.5.1 Interrupt Priority Resolution Circuit ..........................................................................80

______

9.6 INT Interrupt ...................................................................................................................82

______

9.7 NMI Interrupt...................................................................................................................83

9.8 Key Input Interrupt ..........................................................................................................83

9.9 Address Match Interrupt .................................................................................................84

10. Watchdog Timer ...........................................................................................86

10.1 Count Source Protective Mode.....................................................................................87

11. DMAC...........................................................................................................88

11.1 Transfer Cycles............................................................................................................93

11.1.1 Effect of Source and Destination Addresses .........................................................93

11.1.2 Effect of Software Wait..........................................................................................93

11.2. DMA Transfer Cycles ...................................................................................................95

11.3 DMA Enable..................................................................................................................96

11.4 DMA Request................................................................................................................96

11.5 Channel Priority and DMA Transfer Timing..................................................................97

12. Timer ............................................................................................................98

12.1 Timer A ......................................................................................................................100

12.1.1 Timer Mode ..........................................................................................................103

12.1.2 Event Counter Mode ............................................................................................104

12.1.3 One-shot Timer Mode ..........................................................................................109

12.1.4 Pulse Width Modulation (PWM) Mode ................................................................. 111

A-3

12.2 Timer B ......................................................................................................................114

12.2.1 Timer Mode .........................................................................................................116

12.2.2 Event Counter Mode ............................................................................................ 117

12.2.3 Pulse Period and Pulse Width Measurement Mode............................................ 118

12.2.4 A/D Trigger Mode ................................................................................................120

12.3 Three-phase Motor Control Timer Function................................................................122

12.3.1 Position-Data-Retain Function .............................................................................133

13. Timer S.......................................................................................................135

13.1 Base Timer .................................................................................................................146

13.1.1 Base Timer Reset Register(G1BTRR) ................................................................. 150

13.2 Interrupt Operation .....................................................................................................151

13.3 DMA Support ..............................................................................................................151

13.4 Time Measurement Function......................................................................................152

13.5 Waveform Generating Function.................................................................................. 156

13.5.1 Single-Phase Waveform Output Mode.................................................................157

13.5.2 Phase-Delayed Waveform Output Mode..............................................................159

13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode.................................161

13.6 I/O Port Function Select .............................................................................................163

13.6.1 INPC17 Alternate Input Pin Selection ..................................................................164

13.6.2 Digital Debounce Function for Pin P17/INT5/INPC17.......................................... 164

________

14. Serial I/O ....................................................................................................165

14.1 UARTi (i=0 to 2) .......................................................................................................... 165

14.1.1 Clock Synchronous serial I/O Mode..................................................................... 175

14.1.2 Clock Asynchronous Serial I/O (UART) Mode .....................................................183

14.1.3 Special Mode 1 (I2C bus mode)(UART2) .............................................................191

14.1.4 Special Mode 2 (UART2) .....................................................................................201

14.1.5 Special Mode 3 (IEBus mode)(UART2) ..............................................................205

14.1.6 Special Mode 4 (SIM Mode) (UART2).................................................................207

14.2 SI/O3 and SI/O4 ........................................................................................................212

14.2.1 SI/Oi Operation Timing........................................................................................215

14.2.2 CLK Polarity Selection ........................................................................................215

14.2.3 Functions for Setting an SOUTi Initial Value .......................................................216

15. A/D Converter.............................................................................................217

15.1 Operating Modes ........................................................................................................223

15.1.1 One-Shot Mode.................................................................................................... 223

15.1.2 Repeat mode........................................................................................................225

A-4

15.1.3 Single Sweep Mode ............................................................................................227

15.1.4 Repeat Sweep Mode 0.........................................................................................229

15.1.5 Repeat Sweep Mode 1.........................................................................................231

15.1.6 Simultaneous Sample Sweep Mode ....................................................................233

15.1.7 Delayed Trigger Mode 0.......................................................................................236

15.1.8 Delayed Trigger Mode 1.......................................................................................242

15.2 Resolution Select Function.........................................................................................248

15.3 Sample and Hold ........................................................................................................248

15.4 Power Consumption Reducing Function ....................................................................248

15.5 Output Impedance of Sensor under A/D Conversion .................................................249

16. Multi-master I2C bus Interface....................................................................250

16.1 I2C0 Data Shift Register (S00 register).......................................................................259

16.2 I2C0 Address Register (S0D0 register).......................................................................259

16.3 I2C0 Clock Control Register (S20 register) ................................................................260

16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4).....................................260

16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE) ..............................................260

16.3.3 Bit 6: ACK Bit (ACKBIT) ......................................................................................260

16.3.4 Bit 7: ACK Clock Bit (ACK-CLK)..........................................................................260

16.4 I2C0 Control Register 0 (S1D0) .................................................................................262

16.4.1 Bits 0 to 2: Bit Counter (BC0–BC2).....................................................................262

16.4.2 Bit 3: I2C Interface Enable Bit (ES0)....................................................................262

16.4.3 Bit 4: Data Format Select Bit (ALS)..................................................................... 262

16.4.4 Bit 6: I2C bus Interface Reset Bit (IHR) ...............................................................262

16.4.5 Bit 7: I2C bus Interface Pin Input Level Select Bit (TISS) ....................................263

16.5 I2C0 Status Register (S10 register) ...........................................................................264

16.5.1 Bit 0: Last Receive Bit (LRB)...............................................................................264

16.5.2 Bit 1: General Call Detection Flag (ADR0).......................................................... 264

16.5.3 Bit 2: Slave Address Comparison Flag (AAS)..................................................... 264

16.5.4 Bit 3: Arbitration Lost Detection Flag (AL)........................................................... 264

16.5.5 Bit 4: I2C bus Interface Interrupt Request Bit (PIN) .............................................265

16.5.6 Bit 5: Bus Busy Flag (BB)....................................................................................265

16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX).......266

16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) ................266

16.6 I2C0 Control Register 1 (S3D0 register) ....................................................................267

16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM )......................................... 267

16.6.2 Bit 1: Interrupt Enable Bit at the Completion of Data Receive (WIT) ..................267

16.6.3 Bits 2,3 : Port Function Select Bits PED, PEC ....................................................268

A-5

16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM ....................269

16.6.5 Bits 6,7 : I2C System Clock Select Bits ICK0, ICK1 ............................................269

16.6.6 Address Receive in STOP/WAIT Mode...............................................................269

16.7 I2C0 Control Register 2 (S4D0 Register) ...................................................................270

16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) ..........................................271

16.7.2 Bit1: Time-Out Detection Flag (TOF )..................................................................271

16.7.3 Bit2: Time-Out Detection Period Select Bit (TOSEL) .......................................... 271

16.7.4 Bits 3,4,5: I2C System Clock Select Bits (ICK2-4)...............................................271

16.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN)..........................271

16.8 I2C0 START/STOP Condition Control Register (S2D0 Register)...............................272

16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4)............................272

16.8.2 Bit5: SCL/SDA Interrupt Pin Polarity Select Bit (SIP).......................................... 272

16.8.3 Bit6 : SCL/SDA Interrupt Pin Select Bit (SIS)...................................................... 272

16.8.4 Bit7: START/STOP Condition Generation Select Bit (STSPSEL).......................272

16.9 START Condition Generation Method .......................................................................273

16.10 START Condition Duplicate Protect Function...........................................................274

16.11 STOP Condition Generation Method ........................................................................274

16.12 START/STOP Condition Detect Operation...............................................................276

16.13 Address Data Communication................................................................................. 277

16.13.1 Example of Master Transmit .............................................................................277

16.13.2 Example of Slave Receive ................................................................................278

16.14 Precautions...............................................................................................................279

17. Programmable I/O Ports ............................................................................282

17.1 Port Pi Direction Register (PDi Register, i = 0 to 3, 6 to 10).......................................282

17.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10)......................................................... 282

17.3 Pull-up Control Register 0 to 2 (PUR0 to PUR2 Registers)........................................282

17.4 Port Control Register (PCR Register).........................................................................282

17.5 Pin Assignment Control Register (PACR)...................................................................283

17.6 Digital Debounce Function .........................................................................................283

18. Flash Memory Version ...............................................................................296

18.1 Flash Memory Performance .......................................................................................296

18.1.1 Boot Mode...........................................................................................................297

18.2 Memory Map...............................................................................................................298

18.3 Functions To Prevent Flash Memory from Rewriting .................................................. 302

18.3.1 ROM Code Protect Function ................................................................................ 302

18.3.2 ID Code Check Function ......................................................................................302

A-6

18.4 CPU Rewrite Mode.....................................................................................................304

18.4.1 EW Mode 0 ..........................................................................................................305

18.4.2 EW Mode 1 ..........................................................................................................305

18.5 Register Description ...................................................................................................306

18.5.1 Flash Memory Control Register 0 (FMR0) ...........................................................306

18.5.2 Flash Memory Control Register 1 (FMR1) ...........................................................307

18.5.3 Flash Memory Control Register 4 (FMR4) ...........................................................307

18.6 Precautions in CPU Rewrite Mode .............................................................................312

18.6.1 Operation Speed ..................................................................................................312

18.6.2 Prohibited Instructions..........................................................................................312

18.6.3 Interrupts ..............................................................................................................312

18.6.4 How to Access......................................................................................................312

18.6.5 Writing in the User ROM Area..............................................................................312

18.6.6 DMA Transfer .......................................................................................................313

18.6.7 Writing Command and Data................................................................................. 313

18.6.8 Wait Mode ............................................................................................................313

18.6.9 Stop Mode............................................................................................................313

18.6.10

18.7 Software Commands ..................................................................................................314

18.7.1 Read Array Command (FF16)...............................................................................314

18.7.2 Read Status Register Command (7016)...............................................................314

18.7.3 Clear Status Register Command (5016)...............................................................315

18.7.4 Program Command (4016) ...................................................................................315

18.7.5 Block Erase ..........................................................................................................316

18.8 Status Register ...........................................................................................................318

18.8.1 Sequence Status (SR7 and FMR00 Bits )............................................................ 318

18.8.2 Erase Status (SR5 and FMR07 Bits) ...................................................................318

18.8.3 Program Status (SR4 and FMR06 Bits) ............................................................... 318

18.8.4 Full Status Check .................................................................................................319

18.9 Standard Serial I/O Mode ...........................................................................................321

18.9.1 ID Code Check Function ......................................................................................321

18.9.2 Example of Circuit Application in Standard Serial I/O Mode ................................ 325

Low Power Consumption Mode and On-Chip Oscillator-Low Power Consumption Mode...

313

18.10 Parallel I/O Mode......................................................................................................327

18.10.1 ROM Code Protect Function ..............................................................................327

19. Electrical Characteristics............................................................................328

A-7

20. Precautions ............................................................................................... 350

20.1 SFR ............................................................................................................................350

20.1.1 For 80-Pin and 85-Pin Package ........................................................................... 350

20.1.2 For 64-Pin Package .............................................................................................350

22.1.3 Register Setting....................................................................................................350

20.1.4 For Flash Memory (128K+4K) Version and Mask ROM Version..........................351

20.2 Clock Generation Circuit.............................................................................................352

20.2.1 PLL Frequency Synthesizer .................................................................................352

20.2.2 Power Control ......................................................................................................353

20.3 Protection ...................................................................................................................355

20.4 Interrupts ....................................................................................................................356

20.4.1 Reading Address 0000016.....................................................................................................356

20.4.2 Setting the SP ......................................................................................................356

_______

20.4.3 NMI Interrupt .......................................................................................................356

20.4.4 Changing the Interrupt Generate Factor ..............................................................356

______

20.4.5 INT Interrupt .........................................................................................................357

20.4.6 Rewrite the Interrupt Control Register..................................................................358

20.4.7 Watchdog Timer Interrupt.....................................................................................358

20.5 DMAC ......................................................................................................................... 359

20.5.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) ................................................ 359

20.6 Timer...........................................................................................................................360

20.6.1 Timer A .................................................................................................................360

20.6.2 Timer B.................................................................................................................363

20.6.3 Three-phase Motor Control Timer Function ......................................................... 364

20.7 Timer S .......................................................................................................................365

20.7.1 Rewrite the G1IR Register ..................................................................................365

20.7.2 Rewrite the ICOCiIC Register .............................................................................366

20.7.3 Waveform Generating Function ..........................................................................366

20.7.4 IC/OC Base Timer Interrupt..................................................................................366

20.8 Serial I/O.....................................................................................................................367

20.8.1 Clock-Synchronous Serial I/O ..............................................................................367

20.8.2 UART Mode..........................................................................................................368

20.8.3 SI/O3, SI/O4.........................................................................................................368

20.9 A/D Converter .............................................................................................................369

20.10 Multi-master I2C bus Interface .................................................................................371

20.10.1 Writing to the S00 Register ................................................................................371

20.10.2 AL Flag ...............................................................................................................371

A-8

20.11 Programmable I/O Ports ...........................................................................................372

20.12

20.13 Mask ROM Version...................................................................................................374

20.14 Flash Memory Version..............................................................................................375

Electric Characteristic Differences Between Mask ROM and Flash Memory Version ...

20.13.1 Internal ROM Area .............................................................................................374

20.13.2 Reserved Bit.......................................................................................................374

20.14.1 Functions to Inhibit Rewriting Flash Memory Rewrite ........................................ 375

20.14.2 Stop Mode..........................................................................................................375

20.14.3 Wait Mode ..........................................................................................................375

20.14.4

20.14.5 Writing Command and Data...............................................................................375

20.14.6 Program Command............................................................................................375

20.14.7 Operation Speed ................................................................................................375

20.14.8 Instructions Inhibited Against Use...................................................................... 375

20.14.9 Interrupts ............................................................................................................376

20.14.10 How to Access..................................................................................................376

20.14.11 Writing in the User ROM Area ..........................................................................376

Low Power Dissipation Mode, On-Chip Oscillator Low Power Dissipation Mode ...

373

375

20.14.12 DMA Transfer ...................................................................................................376

20.14.13 Regarding Programming/Erasure Times and Execution Time .........................376

20.14.14 Definition of Programming/Erasure Times .......................................................377

20.14.15

20.14.16 Boot Mode........................................................................................................377

20.14.17 Standard Serial I/O Mode................................................................................377

20.15 Noise ........................................................................................................................378

20.15.1 Trace of Print Board (85-pin Package)...............................................................378

20.16 Instruction for a Device Use .....................................................................................379

Flash Memory Version Electrical Characteristics 10,000 E/W cycle products (U7, U9)...

377

Appendix 1. Package Dimensions .................................................................. 380

Appendix 2. Functional Comparison ................................................................382

Appendix 2.1

Appendix 2.2 Difference between M16C/28 Group and M16C/29 Group (Normal-ver.) ....383

Difference between M16C/28 Group Normal-ver. and M16C/28 Group T-ver./V-ver. ....

382

A-9

Quick Reference by Address

Address

0000

0001

0002

0003

Processor mode register 0 PM0

0004

Processor mode register 1 PM1

0005

System clock control register 0 CM0

0006

System clock control register 1 CM1

0007

0008

0009

Address match interrupt enable register AIER

000A

Protect register PRCR

000B

000C

Oscillation stop detection register CM2

000D

000E

Watchdog timer start register WDTS

000F

Watchdog timer control register WDC

0010

Address match interrupt register 0 RMAD0

0011

0012

0013

0014

Address match interrupt register 1 RMAD1

0015

0016

0017

0018

0019

Voltage detection register 1 VCR1

001A

Voltage detection register 2 VCR2

001B

001C

PLL control register 0 PLC0

001D

001E

Processor mode register 2 PM2

001F

Low voltage detection interrupt register D4INT

0020

0021

DMA0 source pointer SAR0

0022

0023

0024

DMA0 destination pointer DAR0

0025

0026

0027

0028

DMA0 transfer counter TCR0

0029

002A

002B

002C

DMA0 control register DM0CON

002D

002E

002F

0030

0031

DMA1 source pointer SAR1

0032

0033

0034

0035

DMA1 destination pointer DAR1

0036

0037

0038

DMA1 transfer counter TCR1

0039

003A

003B

003C

DMA1 control register DM1CON

003D

003E

003F

NOTES:

1. The blank areas are reserved and cannot be accessed by users.

41 41

46 47

85 66

87 87

36 36

49 37

Address

0040

0041

0042

0043

INT3 interrupt control register INT3IC

0044

IC/OC 0 interrupt control register ICOC0IC

0045

0046

IC/OC 1 interrupt control register, ICOC1IC,

C-BUS interface interrupt control register IICIC

0047

IC/OC base timer interrupt control register, BTIC,

CLSDA interrupt control register SCLDAIC

0048

SI/O4 interrupt control register, S4IC, INT5 interrupt control register INT5IC

0049

SI/O3 interrupt control register, S3IC,

INT4 interrupt control register INT4IC

004A

UART2 Bus collision detection interrupt control register BCNIC

004B

DMA0 interrupt control register DM0IC

004C

DMA1 interrupt control register DM1IC

004D

Key input interrupt control register KUPIC

004E

A/D conversion interrupt control register ADIC

004F

UART2 transmit interrupt control register

0050

UART2 receive interrupt control register

0051

UART0 transmit interrupt control register

0052

UART0 receive interrupt control register UART1 transmit interrupt control register

0053

UART1 receive interrupt control register

0054

0055

Timer A0 interrupt control register TA0IC

0056

Timer A1 interrupt control register TA1IC

0057

Timer A2 interrupt control register TA2IC

0058

Timer A3 interrupt control register TA3IC

0059

Timer A4 interrupt control register TA4IC

005A

Timer B0 interrupt control register TB0IC

005B

Timer B1 interrupt control register TB1IC

005C

Timer B2 interrupt control register TB2IC

005D

INT0 interrupt control register INT0IC

005E

INT1 interrupt control register INT1IC

005F

INT2 interrupt control register INT2IC

0060

0061

0062

0063

0064

0065

0066

0067

0068

0069

006A

006B

006C

006D

006E

006F

0070

0071

0072

0073

0074

0075

0076

0077

0078

0079

007A

007B

007C

007D

007E

007F

S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC

73 73

73 73 73

73 73

73 73 73 73 73 73 73 73 73 73

73 73 73 73 73 73 73 73 73 73 73

B-1

Quick Reference by Address

Address

01B0

01B1

01B2

01B3

Flash memory control register 4

01B4

01B5

Flash memory control register 1 FMR1

01B6

01B7

Flash memory control register 0

01B8

01B9

0210

Low-power Consumption Control 0 LPCC0

0211

0212

0213

0214

0215

0216

0217

0218

0219

0250

0251

0252

0253

0254

0255

0256

0257

0258

0259

025A

025B

025C

On-chip oscillator control register ROCR

025D

Pin assignment control register PACR

025E

Peripheral clock select register PCLKR

025F

Low-power Consumption Control 1 LPCC1

02E0

C0 data shift register S00

02E1

02E2

C0 address register S0D0

02E3

C0 control register 0 S1D0

02E4

C0 clock control register S20

02E5

C0 start/stop condition control register S2D0

02E6

C0 control register 1 S3D0

02E7

C0 control register 2 S4D0

02E8

C0 status register S10

02E9

02EA

02FE

02FF

(2)

FMR4

(2)

FMR0

NOTES:

1. The blank areas are reserved and cannot be accessed by users.

2. This register is included in the flash memory version.

309 308

308

351

172,292

351

253 252

254 253 258 256 257 255

Address

0300

TM, WG register 0

0301

0302

TM, WG register 1

0303

0304

TM, WG register 2

0305

0306

TM, WG register 3

0307

0308

TM, WG register 4

0309

030A

TM, WG register 5

030B

030C

TM, WG register 6

030D

030E

TM, WG register 7

030F

WG control register 0 G1POCR0

0310

WG control register 1 G1POCR1

0311

WG control register 2 G1POCR2

0312

WG control register 3 G1POCR3

0313

WG control register 4 G1POCR4

0314

WG control register 5 G1POCR5

0315

WG control register 6 G1POCR6

0316

WG control register 7 G1POCR7

0317

TM control register 0 G1TMCR0

0318

TM control register 1 G1TMCR1

0319

TM control register 2 G1TMCR2

031A

TM control register 3 G1TMCR3

031B

TM control register 4 G1TMCR4

031C

TM control register 5 G1TMCR5

031D

TM control register 6 G1TMCR6

031E

TM control register 7 G1TMCR7

031F

0320

Base timer register G1BT

0321

Base timer control register 0 G1BCR0

0322

Base timer control register 1 G1BCR1

0323

TM prescale register 6 G1TPR6

0324

TM prescale register 7 G1TPR7

0325

Function enable register G1FE

0326

Function select register G1FS

0327

0328

Base timer reset register G1BTRR

0329

Divider register G1DV

032A

032B

032C

032D

032E

032F

Interrupt request register G1IR

0330

Interrupt enable register 0 G1IE0

0331

Interrupt enable register 1 G1IE1

0332

0333

0334

0335

0336

0337

0338

0339

033A

033B

033C

033D

033E

NMI digital debounce register NDDR

digital debounce register P17DDR

033F

G1TM0, G1PO0

G1TM1, G1PO1

G1TM2, G1PO2

G1TM3, G1PO3

G1TM4, G1PO4

G1TM5, G1PO5

G1TM6, G1PO6

G1TM7, G1PO7

141,142

141 141 141 141 141 141 141 141 140 140 140 140 140 140 140 140

137 137

138 140 140 143 143

139 138

144 145

145

293 293

B-2

Quick Reference by Address

Address

0340

0341

0342

Timer A1-1 register TA11

0343

0344

Timer A2-1 register TA21

0345

0346

Timer A4-1 register TA41

0347

Three-phase PWM control register 0 INVC0

0348

Three-phase PWM control register 1 INVC1

0349

Three-phase output buffer register 0 IDB0

034A

Three-phase output buffer register 1 IDB1

034B

Dead time timer DTT

034C

Timer B2 interrupt occurrence frequency set counter

034D

Position-data-retain function contol register PDRF

034E

034F

0350

0351

0352

0353

0354

0355

0356

0357

0358

0359

035A

035B

035C

035D

Interrupt request cause select register 2 IFSR2A

035E

Interrupt request cause select register IFSR

035F

SI/O3

0360

0361

0362

SI/O3 control register S3C

0363

0364

0365

0366

0367

0368

0369

036A

036B

036C 036D 036E

036F

0370

0371

0372

0373

0374

0375

0376

0377

0378

0379

037A

037B

037C 037D 037E

037F

NOTE:

1. The blank areas are reserved and cannot be accessed by users.

bit rate generator

SI/O3 SI/O4

SI/O4 control register S4C SI/O4

bit rate generator

UART2 special mode register 4 U2SMR4 UART2 special mode register 3 U2SMR3 UART2 special mode register 2 U2SMR2 UART2 special mode register U2SMR

UART2 transmit/receive mode register UART2 bit rate generator

UART2 transmit buffer register UART2 transmit/receive control register 0

UART2 transmit/receive control register 1

UART2 receive buffer register

transmit/receive register

ICTB2

S3TRR

S3BRG S4TRR

S4BRG

U2MR U2BRG

U2TB U2C0

U2C1 U2RB

127

127 124

125 126 126 126 126

134

74, 82

213

213 213 213

213 213

174 174 173 173 170 169

169 171

172 169

Address

Count start flag TABSR

0380

Clock prescaler reset flag CPSRF

0381

One-shot start flag ONSF

0382

Trigger select register TRGSR

0383

Up-down flag UDF

0384

0385

0386

Timer A0 register TA0

0387

0388

Timer A1 register TA1

0389

038A

Timer A2 register TA2

038B

038C

Timer A3 register TA3

038D

038E

Timer A4 register TA4

038F

0390

Timer B0 register TB0

0391

0392

Timer B1 register TB1

0393

0394

Timer B2 register TB2

0395

Timer A0 mode register TA0MR

0396

Timer A1 mode register TA1MR

0397

Timer A2 mode register TA2MR

0398

Timer A3 mode register TA3MR

0399

Timer A4 mode register TA4MR

039A

Timer B0 mode register TB0MR

039B

Timer B1 mode register TB1MR

039C

Timer B2 mode register TB2MR

039D

Timer B2 special mode register TB2SC

039E

039F

UART0 transmit/receive mode register

03A0

UART0 bit rate generator U0BRG

03A1

03A2

UART0 transmit buffer register U0TB

03A3

03A4

UART0 transmit/receive control register 0

UART0 transmit/receive control register 1

03A5

03A6

UART0 receive buffer register U0RB

03A7

UART1 transmit/receive mode register

03A8

03A9

UART1 bit rate generator U1BRG

03AA

UART1 transmit buffer register U1TB

03AB

UART1 transmit/receive control register 0

03AC

03AD

UART1 transmit/receive control register 1

03AE

UART1 receive buffer register U1RB

03AF

UART transmit/receive control register 2

03B0

03B1

03B2

03B3

03B4

03B5

03B6

03B7

DMA0 request cause select register DM0SL

03B8

03B9

DMA1 request cause select register DM1SL

03BA

03BB

03BC

03BD

03BE

03BF

U0MR

U0C0 U0C1

U1MR

U1C0 U1C1

UCON

101,115 102,115

102

102,129

101

101,127 101,127

101

101,127

115

115,129

100 100,130 100,130

100 100,130

114

114 114,130

128,222

170

169

171

172

169

170

169

171

172

169

171

B-3

Quick Reference by Address

Address

03C0

A/D register 0 AD0

03C1

03C2

A/D register 1 AD1

03C3

03C4

A/D register 2 AD2

03C5

03C6

A/D register 3 AD3

03C7

03C8

A/D register 4 AD4

03C9

03CA

A/D register 5 AD5

03CB

03CC

A/D register 6 AD6

03CD

03CE

A/D register 7 AD7

03CF

03D0

03D1

03D2

A/D trigger control register ADTRGCON

03D3

A/D convert status register 0 ADSTAT0

03D4

A/D control register 2 ADCON2

03D5

03D6

A/D control register 0 ADCON0

03D7

A/D control register 1 ADCON1

03D8

03D9

03DA

03DB

03DC

03DD

03DE

03DF

03E0

Port P0 register P0

03E1

Port P1 register P1

03E2

Port P0 direction register PD0

03E3

Port P1 direction register PD1 Port P2 register P2

03E4

Port P3 register P3

03E5

Port P2 direction register PD2

03E6

03E7

Port P3 direction register PD3

03E8

03E9

03EA

03EB

03EC

Port P6 register P6

03ED

Port P7 register P7 Port P6 direction register PD6

03EE

Port P7 direction register PD7

03EF

03F0

Port P8 register P8

03F1

Port P9 register P9

03F2

Port P8 direction register PD8

03F3

Port P9 direction register PD9

Port P10 register P10

03F4

03F5

03F6

Port P10 direction register PD10

03F7

03F8

03F9

03FA

03FB

03FC

Pull-up control register 0 PUR0

03FD

Pull-up control register 1 PUR1

03FE

Pull-up control register 2 PUR2

03FF

Port control register PCR

NOTE:

1. The blank areas are reserved and cannot be accessed by users.

221

221 221

221

221 221

221

220 221 219

219 219

290 290 289 289 290 290 289 289

290 290 289 289 290 290 289 289 290

289

291 291 291 292

B-4

M16C/28 Group (M16C/28, M16C/28B)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

1. Overview

1.1 Features

The M16C/28 Group (M16C/28, M16C/28B) of single-chip control MCUs incorporates the M16C/60 series CPU core, employing the high-performance silicon gate CMOS technology and sophisticated instructions for a high level of efficiency. The M16C/28 Group (M16C/28, M16C/28B) are housed in 64-pin and 80-pin plastic molded LQFP packages and also in 85-pin plastic molded TFLGA (Thin Fine Pitch Land Grid Array) package. This MCU is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier and DMAC for high-speed operation processing to make adequate for office automation, communication devices, and other high-speed processing applications. The M16C/28 Group has normal version, T version, and V version. This hardware manual only describes the normal version. For information on T version and V version, please contact Renesas Technology Corp.

1.1.1 Applications

Audio, cameras, office equipment, communication equipment, portable equipment, home appliances (inverter solution), motor control, industrial equipment, etc.

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0020-7400B90JER

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1. Overview

1.1.2 Specifications

Table 1.1 and 1.2 list specification outline.

Table 1.1 Specifications (80/85-Pin Package)

Item Function Specification

CPU Number of basic instructions 91 instructions

Minimum instruction

41.7 ns (f(BCLK) = 24 MHZ, V

excution time 50 ns (f(BCLK) = 20 MHZ, VCC= 3.0 V to 5.5 V) (M16C/28,M16C/28B)

100 ns (f(BCLK) = 10 MHZ, VCC= 2.7 V to 5.5 V) (M16C/28,M16C/28B) Operation mode Single chip mode Address space 1 Mbyte Memory capacity See Tables 1.3 and 1.4

Peripheral I/O port Input/Output: 71 lines Function Multifunction timer TimerA: 16 bits x 5 channels, TimerB: 16 bits x 3 channels

Three-phase motor control timer

TimerS (Input Capture/Output Compare):

16bit base timer x 1 channel (Input/Output x 8 channels)

Serial I/O 2 channels (UART0, UART1)

UART, clock synchronous

1 channel (UART2)

UART, clock synchronous, I2C bus, or IEbus 2 channels (SI/O3, SI/O4) Clock synchronous 1 channel (Multi-Master I2C bus)

A/D converter 10 bits x 24 channels DMAC 2 channels Watchdog timer 15 bits x 1 (with prescaler) Interrupt 25 internal and 8 external sources, 4 software sources, 7 levels Clock generation circuit 4 circuits







• Main clock

• Sub-clock

(These circuits contain a built-in feedback







resistor)







• On-chip oscillator

• PLL frequency synthesizer

Oscillation stop detect function Main clock oscillation stop, re-oscillation detect function

Voltage detection circuit Available Electrical Power supply voltage V Characteristics

CC = 4.2 V to 5.5 V (f(BCLK) = 24 MHZ) (M16C/28B)

VCC = 3.0 V to 5.5 V (f(BCLK) = 20 MHZ) (M16C/28, M16C/28B) VCC = 2.7 V to 5.5 V (f(BCLK) = 10 MHZ) (M16C/28, M16C/28B)

Power consumption 23 mA (VCC = 5 V, f(BCLK) = 24 MHz) (M16C/28B)

18 mA (V 25 µA (f(X

3.0 µA (V

CC = 5 V, f(BCLK) = 20 MHz)

CIN) = 32 KHz on RAM)

CC = 3 V, f(XCIN) = 32 KHz, in wait mode)

0.7 µA (VCC = 3 V, in stop mode)

Flash Memory Program/erase supply voltage 2.7 V to 5.5 V

Program and erase endurance 100 times (all space) or 1,000 times (Blocks 0 to 5)

/10,000 times (Block A, Block B

Operating Ambient Temperature -20 to 85°C/-40 to 85°C Package 80-pin plastic mold LQFP, 85-pin plastic mold TFLGA

NOTES:

1. IEBus is a trademark of NEC Electronics Corporation.

2. Refer to Tables 1. 5 to 1.7 Product Code for number of program/erase and operating ambient temperature.

3. PLL frequency synthesizer is required to use the M16C/28B at f(BCLK) = 24 MHz.

= 4.2 V to 5.5 V) (M16C/28B)

(2)

)

(1)

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1. Overview

Table 1.2 Specifications (64-Pin Package)

Item Function Specification

CPU Number of basic instructions 91 instructions

Minimum instruction

excution time

Operation mode Single chip mode

Address space 1 Mbyte

Memory capacity See Tables 1.3 and 1.4 Peripheral I/O Port Input/Output: 55 lines Function Multifunction timer TimerA: 16 bits x 5 channels, TimerB: 16 bits x 3 channels

Serial I/O 2 channels (UART0, UART1)

A/D converter 10 bits x 13 channels

DMAC 2 channels

Watchdog timer 15 bits x 1 (with prescaler)

Interrupt 24 internal and 8 external sources, 4 software sources, 7 levels

Clock generation circuit 4 circuits

Oscillation stop detect function Main clock oscillation stop, re-oscillation detect function

Voltage detection circuit Available Electrical Power supply voltage V Characteristics

Power consumption 23 mA (V

Flash Memory Program/erase supply voltage 2.7V to 5.5V

Program and erase endurance 100 times (all space) or 1,000 times (Blocks 0 to 5)

Operating Ambient Temperature -20 to 85C°/-40 to 85C° Package 64-pin plastic mold LQFP NOTES:

1. IEBus is a trademark of NEC Electronics Corporation.

2. Refer to Tables 1. 5 to 1.7 Product Code for number of program/erase and operating ambient temperature.

3. PLL frequency synthesizer is required to use the M16C/28B at f(BCLK) = 24 MHz.

41.7 ns (f(BCLK) = 24 MHz, VCC = 4.2 V to 5.5 V) (M16C/28B) 50 ns (f(BCLK) = 20 MHz, VCC = 3.0 V to 5.5 V) (M16C/28,M16C/28B) 100 ns (f(BCLK) = 10 MHz, VCC = 2.7 V to 5.5 V) (M16C/28,M16C/28B)

Three-phase motor control timer TimerS (Input Capture/Output Compare):

16bit base timer x 1 channel (Input/Output x 8 channels)

UART, clock synchronous 1 channel (UART2) UART, clock synchronous, I

C bus, or IEbus

(1)

1 channels (SI/O3, SI/O4) Clock synchronous 1 channel (Multi-Master I2C bus)







• Main clock

• Sub-clock

(These circuits contain a built-in feedback







resistor)







• On-chip oscillator

• PLL frequency synthesizer

CC = 4.2 V to 5.5 V (f(BCLK) = 24 MHZ) (M16C/28B)

VCC = 3.0 V to 5.5 V (f(BCLK) = 20 MHZ) (M16C/28, M16C/28B) VCC = 2.7 V to 5.5 V (f(BCLK) = 10 MHZ) (M16C/28, M16C/28B)

CC = 5 V, f(BCLK) = 24 MHz) (M16C/28B)

16 mA (V 25 µA (f(X

3.0 µA (V

CC = 5 V, f(BCLK) = 20 MHz)

CIN) = 32 KHz on RAM)

CC = 3 V, f(XCIN) = 32 KHz, in wait mode)

0.7 µA (VCC = 3 V, in stop mode)

/10,000 times (Block A, Block B

(2)

)

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1.2 Block Diagram

Figure 1.1 is a block diagram of the M16C/28 Group, 80-pin and 85-pin packages. Figure 1.2 is a block diagram of the M16C/28 Group, 64-pin package.

1. Overview

I/O Ports

Internal Peripheral Functions

Timer (16 bits)

Output (Timer A) : 5

Input (Timer B) : 3

3-phase PWM

Timer S

Input capture/

(

Output compare

Time measurement : 8 channels

Waveform generating : 8 channels

A/D converter

(10 bits x 24 channels)

Watchdog timer

(15 bits)

DMAC

(2 channels)

)

Port P0

UART/clock synchronous SI/O

(8 bits x 3 channels)

Clock synchronous SI/O

(8 bits x 2 channels)

Multi-master I2C bus

Port P1

M16C/60 Series CPU Core

R0LR0H

R1H R1L

R2 R3

A0 A1 FB

Port P2

System clock generator

On-chip oscillator

PLL frequency synthesizer

USP

ISP

INTB

FLG

IN-XOUT

XCIN-XCOUT

Memory

ROM

RAM

Multiplier

Port P3

(1)

(2)

Port P6

Port P7

Port P8

Port P9

Port P10

NOTES:

1. ROM size depends on MCU type.

2. RAM size depends on MCU type.

Figure 1.1 M16C/28 Group Block Diagram (80-Pin Package and 85-Pin Package)

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1. Overview

I/O Ports

Internal Peripheral Functions

Timer (16 bits)

Output (Timer A) : 5

Input (Timer B) : 3

3-phase PWM

Timer S

Input capture/

(

Output compare

Time measurement : 8 channels

Waveform generating : 8 channels

A/D converter

(10 bits x 13 channels)

Watchdog timer

(15 bits)

DMAC

(2 channels)

)

Port P0

UART/Clock synchronous SI/O

(8 bits x 3 channels)

Clock synchronous SI/O

(8 bits x 1 channel)

Multi-master I2C bus

Port P1

M16C/60 Series CPU Core

R0H

R0L

R1H

R1L R2 R3

A0 A1 FB

Port P2

System clock generator

On-chip oscillator

PLL frequency synthesizer

USP

ISP

INTB

FLG

IN-XOUT

XCIN-XCOUT

Memory

ROM

RAM

Multiplier

Port P3

(1)

(2)

Port P6

Port P7

Port P8

Port P9

Port P10

Figure 1.2 M16C/28 Group Block Diagram (64-Pin Package)

NOTES:

1. ROM size depends on MCU type.

2. RAM size depends on MCU type.

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1. Overview

1.3 Product Information

Tables 1.3 and 1.4 list the M16C/28 Group product information and Figure 1.3 shows the product number-

ing system. The specifications are partially different between normal-ver.and T/ V-ver..

Table 1.3 M16C/28 Group Product List -Normal-ver. As of January, 2007

rebmuNtraP

GW6F08203M)N(K4+K84K4

MOR

yticapaC

MAR

yticapaC

epyTegakcaPskrameRedoCtcudorP

(N): New

GW8F08203M)N(K4+K46K4

GWAF08203M)N(K4+K69K8 PH6F08203M)N(K4+K84K4 PH8F08203M)N(K4+K46K4

PHAF08203M)N(K4+K69K8

PHCF08203M)N(K4+K821K21 PH6F18203M)N(K4+K84K4 PH8F18203M)N(K4+K46K4

PHAF18203M)N(K4+K69K8

PHCF18203M)N(K4+K821K21

PHXXX-8M08203M)N(K46K4

PHXXX-AM08203M)N(K69K8 PHXXX-CM08203M)N(K821K21

PHXXX-8M18203M)N(K46K4

PHXXX-CM18203M)N(K821K21

)G0F58(A-BJ5800GLTP

)A-Q6P08(A-BK0800PQLP

)A-Q6P46(A-BK4600PQLP

)A-Q6P08(A-BK0800PQLP

)A-Q6P46(A-BK4600PQLPPHXXX-AM18203M)N(K69K8

hsalF

yromeM

ksaM

MOR

9U,7U,5U,3U

5U,3U

Table 1.4 M16C/28B Group Product List -Normal-ver. As of January, 2007

rebmuNtraP

PHBCF08203M)D(K4+K821K21)A-Q6P08(A-BK0800PQLP PHBCF18203M)D(K4+K821K21)A-Q6P46(A-BK4600PQLP

tnempolevedrednU:)D(

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MOR

yticapaC

583fo7002,13.naJ00.2.veR

MAR

yticapaC

epyTegakcaPskrameRedoCtcudorP

hsalF

yromem

)B82/C61M,82/C61M(puorG82/C61M

Part No. M 3 0 2 8 0 F C B H P - U 7

1. Overview

Product code Package type:

HP : Package PLQP0080KB-A(80P6Q-A) PLQP0064KB-A(64P6Q-A) WG : Package PTLG0085JB-A(85F0G)

Version (no): M16C/28 B: M16C/28B

ROM capacity / RAM capacity

6 : (48K+4K) bytes / 4K bytes 8 : (64K + 4K) bytes / 4K bytes A : (96K + 4K) bytes / 8K bytes C : (128K + 4K) bytes / 12K bytes

Memory type: F : Flash memory version M : Mask ROM version

(1)

NOTE:

1. "+4K bytes" is available only in flash memory ver..

Figure 1.3 Product Numbering System

Pin count (The value itself has no specific meaning)

M16C/28 Group

M16C Family

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1. Overview

Table 1.5 Product Code (Flash Memory Version) - M16C/28 Normal Version, 64-, 80-, and 85-Pin Packages

MORlanretnI

tcudorP

edoC

3U 5U Cº58ot027U 9U Cº58ot02-Cº58ot02-

egakcaP

eerfdaeL

dnamargorP

esare

ecnarudne

001

000,1000,01

)5ot0skcolB:ecapSmargorP(

erutarepmeT

egnar

Cº06ot0

dnamargorP

esare

ecnarudne

001Cº06ot0

MORlanretnI

)BdnaAskcolB:ecapSataD(

erutarepmeT

egnar

Cº58ot04-Cº58ot04-

tneibmAgnitarepO

erutarepmeT

Cº58ot04-

NOTE:

1. The lead contained products, D3, D5, D7 and D9, are put together with U3, U5, U7 and U9 respectively. Lead-free (Sn-Ag-Cu plating) products can be mounted by both conventional Sn-Pb paste and Leadfree paste.

Table 1.6 Product Code (Flash Memory-ver.) - M16C/28B Normal Version, 64- and 80-Pin Package

MORlanretnI

tcudorP

edoC

7Ueerf-daeL000,1Cº06ot0000,01Cº58ot04-Cº58ot04-

egakcaP

margorP

esaredna

ecnarudne

)5ot0skcolB:ecapSmargorP(

margorP

egnarerutarepmeT

esaredna ecnarudne

MORlanretnI

)BdnaAskcolB:ecapSataD(

erutarepmeT

egnar

tneibmAgnitarepO

erutarepmeT

Table 1.7 Product Code (Mask ROM Version) - M16C/28 Normal Version

tcudorP

edoC

egakcaP

tneibmAgnitarepO

erutarepmeT

Cº58ot04-

eerf-daeL

5UCº58ot02-

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(1) Flash Memory Version, PTLG0085JB-A (85F0G), Normal-ver.

1. Overview

M30280FA

B U5

XXXXXXX

(2) Flash Memory Version, PLQP0080KB-A (80P6Q-A), Normal-ver.

Type No. M30280FAWG Chip version and product code

B : Chip version.

The first edition is shown to be blank and continues with A, B, and C.

U5: Product code. (See Table 1.5)

Date code seven digits Manufacturing management code

M16C

M30280FAHP

A U5

XXXXXXX

(3) Flash Memory Version, PLQP0064KB-A (64P6Q-A), Normal-ver.

30281FA

A U5

XXXXXXX

Type No. M30280FAHP Chip version and product code

A : Chip version and product code The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.5)

Date code seven digits Manufacturing management code

Type No. M30281FAHP Chip version and product code

A : Chip version and product code The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.5)

(1)

Date code seven digits Manufacturing management code

(4) Mask ROM Version, PLQP0080KB-A (80P6Q-A), Normal-ver.

M16C

Type No. M30280MAHP

M30280MA-

XXXHP A U5

XXXXXXX

(5) Mask ROM Version, PLQP0064-KB-A (64P6Q-A), Normal-ver.

XXXXXXX

M30281MA-

XXXHP A U5

NOTES:

Chip version and product code XXX : ROM No.

A : Chip version and product code The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.7)

Date code seven digits Manufacturing management code

Type No. M30281MAHP Chip version and product code

XXX: ROM No. A : Chip version and product code

The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.7)

(1)

1. The following functinos are not available in the first version and version A products.

-Delay trigger mode 0 of A/D conversion

-Delay trigger mode 1 of A/D conversion

Figure 1.4 Marking Diagram-M16C/28 Group Normal-ver.

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1.4 Pin Assignment

Figures 1.5 to 1.7 show the pin Assignments (top view).

BCDEFG

61 60 58

P06 P07 P11

P10

REF

P10

(11)

4 (Vss)

P10

AVss

AVcc79P9

CNVss

(2)

(11)

(2)

(Vss)

RESE

P87/XCIN

P86/XCOUT

5 (Vss)

11 Vss14P8

OUT

(11)

(2)

Vcc16P8

Vcc15P8

1. Overview

(11)

(2)

(Vss)

NOTES:

1. The numbers in each grid (circle) show the pin numbers of the M30280FAHP (PLQP0080KB-A (80P6Q-A))

2. Connect grids written as (Vss) to Vss(GND) or leave them open.

3. Set PACR2 to PACR0 bits in the PACR register to "0112" before you input and output it after resetting to each pin. When the PACR register is not set, the input and output function of some pins are disabled.

Package: PTLG0085JB-A(85F0G)

Figure 1.5 Pin Assignment (Top View) of 85-pin Package

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+ 393 hidden pages

RENESAS M16C, M28, M28B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Notes regarding these materials

General Precautions in the Handling of MPU/MCU Products

How to Use This Manual

Table of Contents

1. Overview

1.1 Features

1.1.1 Applications

1.1.2 Specifications

1.2 Block Diagram

1.3 Product Information

1.4 Pin Assignment