Page 1
REJ09B0062-0120
R8C/11 Group
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY/R8C/Tiny SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev. 1.20
Revision date: Jan 27, 2006
www.renesas.com
Page 2
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Renesas Technology Corp. or a third party.
2.
Renesas Technology Corp. assumes no responsibility for any damage, or infringement of
any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corp. without notice due to
product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://
www.renesas.com).
4.
When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information
and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
5.
Renesas Technology Corp. semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at
stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology
Corp. product distributor when considering the use of a product contained herein for any
specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
6.
The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7.
If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
8.
Please contact Renesas Technology Corp. for further details on these materials or the
products contained therein.
Page 3
How to Use This Manual
0
1. Introduction
This hardware manual provides detailed information on the R8C/11 Group of microcomputers.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
X X X r e g i s t e r
b 7b 6b 5b 4b 3b2b 1b 0
0
d d r e s
f t e r r e s e
X
S y m b o lA
X X XX
X X X
XXX1
(b2)
( b 3 )
XXX4
XXX5
X X X 6
X X X 7
Bit NameBit symbol
X X X B i t
N o t h i n g i s a s s i g n e d .
W h e n w r i t e , s h o u l d s e t t o " 0 " . W h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e .
R e s e r v e d B i t
X X X B i t
XXX Bit
sA
X0
b 1 b 0
1 0 : X X X
0 1 : X X X
1 0 : A v o i d t h i s s e t t i n g
1 1 : X X X
Must set to “0”
Function varies depending on each
operation mode
0: XXX
1: XXX
0
h
t
Function
*5
*1
Blank:Set to “0” or “1” according to the application
0: Set to “0”
1: Set to “1”
X: Nothing is assigned
*2
RW: Read and write
RO: Read only
WO: Write only
−: Nothing is assigned
*3
•Reserved bit
Reserved bit. Set to specified value.
*4
•Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to “0” when writing to this bit.
•Do not set to this value
The operation is not guaranteed when a value is set.
•Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
*5
Follow the text in each manual for binary and hexadecimal notations.
*1
RW
RW
RW
RW
R W
W O
R W
RO
*2
*3
*4
Page 4
3. M16C Family Documents
The following documents were prepared for the M16C family.
(1)
Document
Short Sheet
Data Sheet
Hardware Manual
Software Manual
Application Note
RENESAS TECHNICAL UPDATE
NOTES:
1. Before using this material, please visit the our website to verify that this is the most updated
document available.
Hardware overview
Hardware overview and electrical characteristics
Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts).
*Refer to the application note for how to use peripheral functions.
Detailed description of assembly instructions and microcomputer
performance of each instruction
• Usage and application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
Preliminary report about the specification of a product, a document,
etc.
Contents
Page 5
Table of Contents
SFR Page Reference
Chapter 1. Overview..............................................................1
1.1 Applications ....................................................................................................................1
1.2 Performance Overview...................................................................................................2
1.3 Block Diagram ................................................................................................................ 3
1.4 Product Information .......................................................................................................4
1.5 Pin Assignments.............................................................................................................5
1.6 Pin Description ...............................................................................................................6
Chapter 2. Central Processing Unit (CPU)..........................7
2.1 Data Registers (R0, R1, R2 and R3) ..............................................................................7
2.2 Address Registers (A0 and A1) .....................................................................................8
2.3 Frame Base Register (FB)..............................................................................................8
2.4 Interrupt Table Register (INTB)......................................................................................8
2.5 Program Counter (PC)....................................................................................................8
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ...................................... 8
2.7 Static Base Register (SB) .............................................................................................. 8
2.8 Flag Register (FLG) ........................................................................................................8
2.8.1 Carry Flag (C Flag) .................................................................................................... 8
2.8.2 Debug Flag (D Flag)...................................................................................................8
2.8.3 Zero Flag (Z Flag) ......................................................................................................8
2.8.4 Sign Flag (S Flag) ......................................................................................................8
2.8.5 Register Bank Select Flag (B Flag) ..........................................................................8
2.8.6 Overflow Flag (O Flag) .............................................................................................. 8
2.8.7 Interrupt Enable Flag (I Flag)....................................................................................8
2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 8
2.8.9 Processor Interrupt Priority Level (IPL) .................................................................. 8
2.8.10 Reserved Area..........................................................................................................8
Chapter 3. Memory................................................................ 9
Chapter 4. Special Function Registers (SFR)................... 10
Chapter 5. Reset.................................................................. 14
5.1 Hardware Reset ............................................................................................................ 14
5.1.1 Hardware Reset 1.................................................................................................................................. 14
5.1.2 Hardware Reset 2.................................................................................................................................. 17
5.1.3 Power-on Reset Function.....................................................................................................................18
5.2 Software Reset..............................................................................................................20
5.3 Watchdog Timer Reset.................................................................................................20
A-1
Page 6
5.4 Voltage Detection Circuit .............................................................................................21
5.4.1 Voltage Detection Interrupt ..................................................................................................................26
5.4.2 Exiting Stop Mode on a Voltage Detection Interrupt .........................................................................28
Chapter 6. Clock Generation Circuit..................................29
6.1 Main Clock.....................................................................................................................34
6.2 On-Chip Oscillator Clock ............................................................................................. 35
6.2.1 Low-Speed On-Chip Oscillator ............................................................................................................35
6.2.2 High-Speed On-Chip Oscillator ...........................................................................................................35
6.3 CPU Clock and Peripheral Function Clock ................................................................ 36
6.3.1 CPU Clock..............................................................................................................................................36
6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO) .......................................................36
6.3.3 fRING and fRING128 ...................................................................................................................................................................36
6.3.4 fRING-fast ......................................................................................................................................................................................36
6.4 Power Control ...............................................................................................................37
6.4.1 Normal Operation Mode .......................................................................................................................37
6.4.2 Wait Mode ..............................................................................................................................................39
6.4.3 Stop Mode..............................................................................................................................................40
6.5 Oscillation Stop Detection Function...........................................................................42
6.5.1 How to Use Oscillation Stop Detection Function ..............................................................................42
Chapter 7. Protection.......................................................... 44
Chapter 8. Processor Mode................................................ 45
8.1 Types of Processor Mode ............................................................................................45
Chapter 9. Bus..................................................................... 46
Chapter 10. Interrupt........................................................... 47
10.1 Interrupt Overview......................................................................................................47
10.1.1 Type of Interrupts................................................................................................................................47
10.1.2 Software Interrupts .............................................................................................................................48
10.1.3 Hardware Interrupts............................................................................................................................49
10.1.4 Interrupts and Interrupt Vector.......................................................................................................... 50
10.1.5 Interrupt Control .................................................................................................................................52
______
10.2 INT Interrupt ................................................................................................................60
10.2.1 INT0 Interrupt ......................................................................................................................................60
10.2.2 INT0 Input Filter...................................................................................................................................61
10.2.3 INT1 Interrupt and INT2 Interrupt ......................................................................................................62
10.2.4 INT3 Interrupt ......................................................................................................................................63
________
_______
______ ______
______
10.3 Key Input Interrupt ..................................................................................................... 65
10.4 Address Match Interrupt ............................................................................................66
Chapter 11. Watchdog Timer.............................................. 68
Chapter 12. Timers.............................................................. 70
12.1 Timer X ........................................................................................................................ 71
12.1.1 Timer Mode ..........................................................................................................................................73
A-2
Page 7
12.1.2 Pulse Output Mode .............................................................................................................................74
12.1.3 Event Counter Mode ...........................................................................................................................75
12.1.4 Pulse Width Measurement Mode....................................................................................................... 76
12.1.5 Pulse Period Measurement Mode.....................................................................................................78
12.2 Timer Y.........................................................................................................................80
12.2.1 Timer Mode.......................................................................................................................................... 83
12.2.2 Programmable Waveform Generation Mode ....................................................................................85
12.3 Timer Z.........................................................................................................................88
12.3.1 Timer Mode.......................................................................................................................................... 91
12.3.2 Programmable Waveform Generation Mode ....................................................................................93
12.3.3 Programmable One-shot Generation Mode......................................................................................95
12.3.4 Programmable Wait One-shot Generation Mode .............................................................................98
12.4 Timer C ...................................................................................................................... 101
12.4.1 Input Capture Mode .........................................................................................................................105
12.4.2 Output Compare Mode ....................................................................................................................107
Chapter 13. Serial Interface.............................................. 109
13.1 Clock Synchronous Serial I/O Mode....................................................................... 114
13.1.1 Polarity Select Function ................................................................................................................... 117
13.1.2 LSB First/MSB First Select Function ..............................................................................................117
13.1.3 Continuous Receive Mode ............................................................................................................... 118
13.2 Clock Asynchronous Serial I/O (UART) Mode ....................................................... 119
13.2.1 TxD10/RxD1 Select Function (UART1)............................................................................................ 122
13.2.2 TxD11 Select Function (UART1) ......................................................................................................122
13.2.3 Bit Rate ..............................................................................................................................................123
Chapter 14. A/D Converter................................................ 124
14.1 One-shot Mode ......................................................................................................... 128
14.2 Repeat Mode ............................................................................................................. 130
14.3 Sample and Hold ......................................................................................................132
14.4 A/D conversion cycles ........................................................................................... 132
14.5 Internal Equivalent Circuit of Analog Input...........................................................133
14.6 Inflow Current Bypass Circuit ................................................................................134
14.7 Output Impedance of Sensor under A/D Conversion...........................................135
Chapter 15. Programmable I/O Ports .............................. 137
15.1 Description................................................................................................................137
15.1.1 Port Pi Direction Register (PDi Register, i=0,1,3,4)........................................................................137
15.1.2 Port Pi Register (Pi Register, i=0 to 4).............................................................................................137
15.1.3 Pull-up Control Register 0, Pull-up Control Register 1 (PUR0 and PUR1 Registers)................. 137
15.1.4 Port P1 Drive Capacity Control Register (DRR Register)..............................................................137
15.2 Port setting................................................................................................................145
15.3 Unassigned Pin Handling ........................................................................................151
Chapter 16. Electrical Characteristics............................. 152
Chapter 17. Flash Memory Version ................................. 164
A-3
Page 8
17.1 Overview....................................................................................................................164
17.2 Memory Map..............................................................................................................165
17.3 Functions To Prevent Flash Memory from Rewriting............................................166
17.3.1 ID Code Check Function ..................................................................................................................166
17.4 CPU Rewrite Mode....................................................................................................167
17.4.1 EW0 Mode..........................................................................................................................................168
17.4.2 EW1 Mode..........................................................................................................................................168
17.4.3 Software Commands ........................................................................................................................174
17.4.4 Status Register..................................................................................................................................178
17.4.5 Full Status Check..............................................................................................................................179
17.5 Standard Serial I/O Mode .........................................................................................181
17.5.1 ID Code Check Function ..................................................................................................................181
Chapter 18. On-chip Debugger ........................................ 185
18.1 Address Match Interrupt ..........................................................................................185
18.2 Single Step Interrupt ................................................................................................185
18.3 UART1........................................................................................................................185
18.4 BRK Instruction ........................................................................................................188
Chapter 19. Usage Notes.................................................. 186
19.1 Stop Mode and Wait Mode.......................................................................................186
19.1.1 Stop Mode..........................................................................................................................................186
19.1.2 Wait Mode ..........................................................................................................................................186
19.2 Interrupts...................................................................................................................187
19.2.1 Reading Address 0000016 ............................................................................................................................................ 187
19.2.2 SP Setting ..........................................................................................................................................187
19.2.3 External Interrupt and Key Input Interrupt .....................................................................................187
19.2.4 Watchdog Timer Interrupt ................................................................................................................187
19.2.5 Changing Interrupt Factor................................................................................................................188
19.2.6 Changing Interrupt Control Register ..............................................................................................189
19.3 Clock Generation Circuit ......................................................................................... 190
19.3.1 Oscillation Stop Detection Function ...............................................................................................190
19.3.2 Oscillation Circuit Constants...........................................................................................................190
19.4 Timers........................................................................................................................191
19.3.1 Timers X, Y and Z..............................................................................................................................191
19.3.2 Timer X.................................................................................................................................................19
19.3.3 Timer Y ...............................................................................................................................................191
19.3.4 Timer Z ...............................................................................................................................................191
19.3.5 Timer C...............................................................................................................................................191
19.5 Serial Interface..........................................................................................................192
19.6 A/D Converter............................................................................................................193
19.7 Flash Memory Version .............................................................................................194
19.7.1 CPU Rewrite Mode ............................................................................................................................194
19.8 Noise..........................................................................................................................197
Chapter 20. Usage Notes for On-chip Debugger............ 198
A-4
Page 9
Appendix 1 Package Dimensions.................................... 199
Appendix 2 Connecting Examples for Serial Writer and
On-chip Debugging Emulator .......................................... 200
Appendix 3 Example of Oscillation Evaluation Circuit.. 202
Register Index ................................................................... 203
A-5
Page 10
SFR Page Reference
A d d r e s s R
0 0 0 01
6
0 0 0 11
6
0 0 0 21
6
0 0 0 31
6
M
P r o c e s s o r m o d e r e g i s t e r 0P
0 0 0 41
6
M
0 0 0 51
6
P r o c e s s o r m o d e r e g i s t e r 1P
M
0 0 0 61
6
S y s t e m c l o c k c o n t r o l r e g i s t e r 0C
M
0 0 0 71
6
S y s t e m c l o c k c o n t r o l r e g i s t e r 1C
H R
0 0 0 81
6
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 0
0 0 0 91
6
A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e rA I E R6 7
R C
0 0 0 A1
6
P r o t e c t r e g i s t e rP
R
0 0 0 B1
6
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 1 H
C
0 0 0 C1
6
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO
D T
0 0 0 D1
6
W a t c h d o g t i m e r r e s e t r e g i s t e rW
D T
0 0 0 E1
6
W a t c h d o g t i m e r s t a r t r e g i s t e rW
D
0 0 0 F1
6
W a t c h d o g t i m e r c o n t r o l r e g i s t e rW
M A D
0 0 1 01
6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0R
0 0 1 11
6
0 0 1 21
6
0 0 1 31
6
M A D
0 0 1 41
6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R
0 0 1 51
6
0 0 1 61
6
0 0 1 71
6
0 0 1 81
6
C R
0 0 1 91
6
V o l t a g e d e t e c t i o n r e g i s t e r 1V
C R
0 0 1 A1
6
V o l t a g e d e t e c t i o n r e g i s t e r 2V
0 0 1 B1
6
0 0 1 C1
6
0 0 1 D1
6
N T 0
0 0 1 E1
6
I N T 0 i n p u t f i l t e r s e l e c t r e g i s t e rI
4 I N
0 0 1 F1
6
V o l t a g e d e t e c t i o n i n t e r r u p t r e g i s t e rD
0 0 2 01
6
0 0 2 11
6
0 0 2 21
6
0 0 2 31
6
0 0 2 41
6
0 0 2 51
6
0 0 2 61
6
0 0 2 71
6
0 0 2 81
6
0 0 2 91
6
0 0 2 A1
6
0 0 2 B1
6
0 0 2 C1
6
0 0 2 D1
6
0 0 2 E1
6
0 0 2 F1
6
0 0 3 01
6
0 0 3 11
6
0 0 3 21
6
0 0 3 31
6
0 0 3 41
6
0 0 3 51
6
0 0 3 61
6
0 0 3 71
6
0 0 3 81
6
0 0 3 91
6
0 0 3 A1
6
0 0 3 B1
6
0 0 3 C1
6
0 0 3 D1
6
0 0 3 E1
6
0 0 3 F1
6
e g i s t e
rS
y m b o l
P a g e
04 5
14 5
03 1
13 1
0 3 3
R4 4
1 3 3
D3 2
R6 9
S6 9
C6 9
06 7
16 7
12 2
22 2
F6 0
T2 3
Blank columns are all reserved space. No use is allowed.
A d d r e s s R
0 0 4 01
6
0 0 4 11
6
0 0 4 21
6
0 0 4 31
6
0 0 4 41
6
0 0 4 51
6
0 0 4 61
6
0 0 4 71
6
0 0 4 81
6
0 0 4 91
6
0 0 4 A1
6
0 0 4 B1
6
0 0 4 C1
6
U P I
0 0 4 D1
6
K e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e rK
0 0 4 E1
6
A D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e rA D I C5 3
0 0 4 F1
6
M P 1 I
0 0 5 01
6
C o m p a r e 1 i n t e r r u p t c o n t r o l r e g i s t e r C
0 T I
0 0 5 11
6
U A R T 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S
0 R I
0 0 5 21
6
U A R T 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S
1 T I
0 0 5 31
6
U A R T 1 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S
1 R I
0 0 5 41
6
U A R T 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S
N T 2 I
0 0 5 51
6
I N T 2 i n t e r r u p t c o n t r o l r e g i s t e rI
X I
0 0 5 61
6
T i m e r X i n t e r r u p t c o n t r o l r e g i s t e rT
Y I
0 0 5 71
6
T i m e r Y i n t e r r u p t c o n t r o l r e g i s t e rT
Z I
0 0 5 81
6
T i m e r Z i n t e r r u p t c o n t r o l r e g i s t e rT
N T 1 I
0 0 5 91
6
I N T 1 i n t e r r u p t c o n t r o l r e g i s t e rI
N T 3 I
0 0 5 A1
6
I N T 3 i n t e r r u p t c o n t r o l r e g i s t e rI
C I
0 0 5 B1
6
T i m e r C i n t e r r u p t c o n t r o l r e g i s t e rT
M P 0 I
0 0 5 C1
6
C o m p a r e 0 i n t e r r u p t c o n t r o l r e g i s t e r C
N T 0 I
0 0 5 D1
6
I N T 0 i n t e r r u p t c o n t r o l r e g i s t e rI
0 0 5 E1
6
0 0 5 F1
6
0 0 6 01
6
0 0 6 11
6
0 0 6 21
6
0 0 6 31
6
0 0 6 41
6
0 0 6 51
6
0 0 6 61
6
0 0 6 71
6
0 0 6 81
6
0 0 6 91
6
0 0 6 A1
6
0 0 6 B1
6
0 0 6 C1
6
0 0 6 D1
6
0 0 6 E1
6
0 0 6 F1
6
0 0 7 01
6
0 0 7 11
6
0 0 7 21
6
0 0 7 31
6
0 0 7 41
6
0 0 7 51
6
0 0 7 61
6
0 0 7 71
6
0 0 7 81
6
0 0 7 91
6
0 0 7 A1
6
0 0 7 B1
6
0 0 7 C1
6
0 0 7 D1
6
0 0 7 E1
6
0 0 7 F1
6
e g i s t e
rS
y m b o l
P a g e
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
C5 3
B-1
Page 11
SFR Page Reference
A d d r e s s R
Y Z M
0 0 8 01
6
T i m e r Y , Z m o d e r e g i s t e rT
R E
Pr e s c a l e r YP
0 0 8 11
6
Y S
T i m e r Y s e c o n d a r yT
0 0 8 21
6
Y P
T i m e r Y p r i m a r yT
0 0 8 31
6
U
T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r P
0 0 8 41
6
R E
Pr e s c a l e r ZP
0 0 8 51
6
Z S
T i m e r Z s e c o n d a r yT
0 0 8 61
6
Z P
T i m e r Z p r i m a r yT
0 0 8 71
6
0 0 8 81
6
0 0 8 91
6
Y Z O
T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e rT
0 0 8 A1
6
X M
T i m e r X m o d e r e g i s t e rT
0 0 8 B1
6
R E
Pr e s c a l e r XP
0 0 8 C1
6
T i m e r X r e g i s t e rT
0 0 8 D1
6
C S S
T i m e r c o u n t s o u r c e s e t t i n g r e g i s t e rT
0 0 8 E1
6
0 0 8 F1
6
0
0 0 9 01
6
T i m e r C r e g i s t e rT
0 0 9 11
6
0 0 9 21
6
0 0 9 31
6
0 0 9 41
6
0 0 9 51
6
N T E
E x t e r n a l i n p u t e n a b l e r e g i s t e rI
0 0 9 61
6
0 0 9 71
6
I E
K e y i n p u t e n a b l e r e g i s t e rK
0 0 9 81
6
0 0 9 91
6
C C
T i m e r C c o n t r o l r e g i s t e r 0T
0 0 9 A1
6
C C
T i m e r C c o n t r o l r e g i s t e r 1T
0 0 9 B1
6
M
0 0 9 C1
6
C a p t u r e a n d c o m p a r e 0 r e g i s t e rT
0 0 9 D1
6
M
0 0 9 E1
6
C o m p a r e 1 r e g i s t e rT
0 0 9 F1
6
0 M
0 0 A 01
6
U A R T 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r U
0 B R
0 0 A 11
6
U A R T 0 b i t r a t e r e g i s t e rU
0 T
0 0 A 21
6
U A R T 0 t r a n s m i t b u f f e r r e g i s t e rU
0 0 A 31
6
0 C
0 0 A 41
6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 U
0 C
0 0 A 51
6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 U
0 R
0 0 A 61
6
U A R T 0 r e c e i v e b u f f e r r e g i s t e r U
0 0 A 71
6
1 M
0 0 A 81
6
U A R T 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r U
1 B R
0 0 A 91
6
U A R T 1 b i t r a t e r e g i s t e rU
1 T
0 0 A A1
6
U A R T 1 t r a n s m i t b u f f e r r e g i s t e rU
0 0 A B1
6
1 C
0 0 A C1
6
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 U
1 C
0 0 A D1
6
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 U
1 R
0 0 A E1
6
U A R T 1 r e c e i v e b u f f e r r e g i s t e r U
0 0 A F1
6
r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r
C O
0 0 B 01
6
U A R T t
0 0 B 11
6
0 0 B 21
6
0 0 B 31
6
0 0 B 41
6
0 0 B 51
6
0 0 B 61
6
0 0 B 71
6
0 0 B 81
6
0 0 B 91
6
0 0 B A1
6
0 0 B B1
6
0 0 B C1
6
0 0 B D1
6
0 0 B E1
6
0 0 B F1
6
e g i s t e
rS
y m b o l
2 U
P a g e
R8 0 / 8 8
Y8 1
C8 1
R8 1
M8 2 / 9 0
Z8 9
C8 9
R8 9
C8 1 / 8 9
R7 1
X7 2
X7 2
7 2 / 8 2 / 9 0
C1
3
N6 0
N6 5
01 0 3
11 0 4
01 0 3
11 0 3
R1 1 2
G1 1 1
B1 1 1
01 1 2
11 1 3
B1 1 1
R1 1 2
G1 1 1
B1 1 1
01 1 2
11 1 3
B1 1 1
N1 1 3
Blank columns are all reserved space. No use is allowed.
A d d r e s s
0 0 C 0
0 0 C 1
0 0 C 2
0 0 C 3
0 0 C 4
0 0 C 5
0 0 C 6
0 0 C 7
0 0 C 8
0 0 C 9
0 0 C A
0 0 C B
0 0 C C
0 0 C D
0 0 C E
0 0 C F
0 0 D 0
0 0 D 1
0 0 D 2
0 0 D 3
0 0 D 4
0 0 D 5
0 0 D 6
0 0 D 7
0 0 D 8
0 0 D 9
0 0 D A
0 0 D B
0 0 D C
0 0 D D
0 0 D E
0 0 D F
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
00E9
00EA
00EB
00EC
00ED
00EE
00EF
00F0
00F1
00F2
00F3
00F4
00F5
00F6
00F7
00F8
00F9
03FA
00FB
00FC
00FD
00FE
00FF
01B3
01B4
01B5
01B6
01B7
1 6
A D r e g i s t e rA
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
D C O N 21 2
A D c o n t r o l r e g i s t e r 2A
1 6
1 6
AD control register 0 ADCON0 126
1 6
D C O N 11 2
A D c o n t r o l r e g i s t e r 1 A
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
Port P0 register P0 143
16
16
P o r t P 1 r e g i s t e rP
16
Port P0 direction register PD0 143
16
Port P1 direction register PD1 143
16
16
Port P3 register P3 143
16
D
P o r t P 3 d i r e c t i o n r e g i s t e rP
16
P o r t P 4 r e g i s t e rP
16
16
16
Port P4 direction register PD4 143
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
U R
16
P u l l - u p c o n t r o l r e g i s t e r 0 P
16
Pull-up control register 1 PUR1 144
P o r t P 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r D R R1 4 4
16
C O U
16
T i m e r C o u t p u t c o n t r o l r e g i s t e r T
M R
16
F l a s h m e m o r y c o n t r o l r e g i s t e r 4 F
16
M R
16
F l a s h m e m o r y c o n t r o l r e g i s t e r 1 F
16
M R
16
F l a s h m e m o r y c o n t r o l r e g i s t e r 0 F
Register Symbol
P a g e
D1 2 7
7
6
11 4 3
31 4 3
41 4 3
01 4 4
T1 0 6
41 7 1
11 7 1
01 7 0
B-2
Page 12
R8C/11 Group
REJ09B0062-0120
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU
core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing
instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial
equipment, audio, etc.
Rev.1.20
Jan 27, 2006
Rev.1.20 Jan 27, 2006 page 1 of 204
REJ09B0062-0120
Page 13
R8C/11 Group
1.2 Performance Overview
Table 1.1. lists the performance outline of this MCU.
Table 1.1 Performance outline
Item Performance
CPU Number of basic instructions 89 instructions
Minimum instruction execution time
Operating mode Single-chip
Address space 1M bytes
Memory capacity See Table 1.2.
Peripheral Port Input/Output: 22 (including LED drive port), Input: 2
function LED drive port I/O port: 8
Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Serial Interface •1 channel
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt Internal: 11 factors, External: 5 factors,
Clock generation circuit 2 circuits
Oscillation stop detection function
Voltage detection circuit Included
Power on reset circuit Included
Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ)
characteristics
Power consumption Typ. 9 mA (VCC = 5.0 V, (f(XIN) = 20 MHZ)
Flash memory Program/erase supply voltage
Program/erase endurance 100 times
Operating ambient temperature -20 to 85 °C
Package 32-pin plastic mold LQFP
50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)
Timer Z: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel
(Circuits of input capture and output compare)
Clock synchronous, UART
•1 channel
UART
Software: 4 factors, Priority level: 7 levels
•Main clock generation circuit (Equipped with a built-in
feedback resistor)
•On-chip oscillator (high speed, low speed)
On High-speed on-chip oscillator the frequency adjustment function is usable.
Main clock oscillation stop detection function
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ)
Typ. 5 mA (VCC = 3.0 V, (f(XIN) = 10 MHZ)
Typ. 35 µA (VCC = 3.0 V, Wait mode, Peripheral clock off)
Typ. 0.7 µA (VCC = 3.0 V, Stop mode)
VCC = 2.7 to 5.5 V
-40 to 85 °C (D-version)
1. Overview
Rev.1.20 Jan 27, 2006 page 2 of 204
REJ09B0062-0120
Page 14
R8C/11 Group
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
1. Overview
I / O p o r t
P o r t P 0
Pe r i p h e r a l f u n c t i o n s
T i m e r
T i m e r X ( 8 b i t s )
T i m e r Y ( 8 b i t s )
T i m e r Z ( 8 b i t s )
T i m e r C ( 1 6 b i t s )
W a t c h d o g t i m e r
( 1 5 b i t s )
ROM
RAM
1 2
Port P4
(1)
(2)
8
8
Port P1
A / D c o n v e r t e r
( 1 0 b i t s ✕ 1 2 c h a n n e l s )
U A R T o r C l o c k s y n c h r o n o u s
s e r i a l I / O
( 8 b i t s ✕ 1 c h a n n e l )
U A R T
( 8 b i t s ✕ 1 c h a n n e l )
R 8 C / T i n y S e r i e s C P U c o r e
R 0 LR 0 H
R1H R1L
R 2
R 3
A 0
A1
FB
5
P o r t P 3
System clock generator
X
H i g h - s p e e d o n - c h i p o s c i l l a t o r
L o w - s p e e d o n - c h i p o s c i l l a t o r
SB
USP
I S P
INTB
P C
FLG
I N
- X
O U T
M e m o r y
M u l t i p l i e r
Figure 1.1 Block Diagram
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Rev.1.20 Jan 27, 2006 page 3 of 204
REJ09B0062-0120
Page 15
R8C/11 Group
1.4 Product Information
Table 1.2 lists the product information.
1. Overview
Table 1.2 Product Information
Type No.
R5F21112FP
R5F21113FP
R5F21114FP
R5F21112DFP
R5F21113DFP
R5F21114DFP
ROM capacity
12K bytes
16K bytes
12K bytes
16K bytes
Type No. R 5 F 21 11 4 D FP
8K bytes
8K bytes
As of January 2006
RAM capacity
512 bytes
768 bytes
1K bytes
512 bytes
768 bytes
1K bytes
Package type:
FP : PLQP0032GB-A
Classification:
D: Operating ambient temperature –40 °C to 85 °C
No symbol: Operating ambient temperature –20 °C to 85 °C
Package type
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
Flash memory version
D version
Remarks
ROM capacity:
2 : 8 KBytes.
3 : 12 KBytes.
4 : 16 KBytes.
R8C/11 group
R8C/Tiny series
Memory type:
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.1.20 Jan 27, 2006 page 4 of 204
REJ09B0062-0120
Page 16
R8C/11 Group
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
A
2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7
P 06/ A N
P05/AN
P 04/ A N
MODE
P03/AN
P02/AN
P01/AN
P 00/ A N7/T x D
2 5
1
2 6
2
2 7
3
2 8
2 9
4
3 0
5
3 1
6
1 1
3 2
1 2 3 4 5 6 7 8
0
1
/
0
R
0
N
/
/
C
0
7
C
3
0
V
C N T
P
C M P
I
P
R8C/11 Group
1. Overview
2
1
1
/
1
1
R
N
I
/
T
O
Z
S
/
S
1
V
3
C M P
T
A
P
U
C
F
T
/
/
3
2
R
T
T
V
/
C
/
/
C
3
2
3
3
V
C N T
I N
I N
C M P
P
P
E
A
P45/INT
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
0
P10/KI0/AN8/CMP0
P11/KI1/AN9/CMP0
P12/KI2/AN10/CMP0
P13/KI3/AN
P14/TxD
P15/RxD
P16/CLK
11
0
0
0
0
1
2
1
D
/
0
1
D
N
/
7
3
P
R x
T x
N O T E S :
1 . P 4
7
f u n c t i o n s o n l y a s a n i n p u t p o r t .
2. W h e n u s i n g O n - c h i p d e b u g g e r , d o n o t u s e p i n s P 0
a n d P 37/ T x D
3 . D o n o t c o n n e c t I V c c t o V c c .
Figure 1.3 Pin Assignments (Top View)
)
6
S
S
V
C
S
T
(
1
S
7
V
4
/
T
R
E S E
O
X
U
P
1 0
/ R x D1.
0
C
4
C
R
V
/
N
I
X
P
/
1
T
/
7
1
P
I N
C N T
0
/ A N7/ T x D
1 1
Package: PLQP0032GB-A (32P6U-A)
Rev.1.20 Jan 27, 2006 page 5 of 204
REJ09B0062-0120
Page 17
R8C/11 Group
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
Signal name Pin name I/O type
Power supply Vcc, I
input Vss
IVcc IVcc O
Analog power AVcc, AVss I
supply input
Reset input
___________
RESET I
CNVss CNVss I
MODE MODE I
Main clock input XIN I
Main clock output XOUT O
_____
INT interrupt input
Key input interrupt
Timer X CNTR0 I/O
_______ _______
INT0 to INT3 I
_____ _____
KI0 to KI3 I
____________
CNTR0 O
Timer Y CNTR1 I/O
Timer Z TZOUT O
Timer C TCIN I
CMP00 to CMP02,
O
CMP10 to CMP12
Serial interface CLK0 I/O
RxD0, RxD1 I
TxD0, TxD10,O
TxD11
Reference voltage VREF I
input
A/D converter AN0 to AN11 I
I/O port P00 to P07, I/O
P10 to P17,
P30 to P33, P37,
P45
Input port P46, P47 I
NOTES :
1. Refer to "19.8 Noise" for the connecting reference resistor value.
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
This pin is to stabilize internal power supply.
Connect this pin to Vss via a capacitor (0.1 µF).
Do not connect to Vcc.
Power supply input pins for A/D converter. Connect the
AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a
capacitor between pins AVcc and AVss.
Input “L” on this pin resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generating circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use
an externally derived clock, input it to the XIN pin and
leave the XOUT pin open.
______
INT interrupt input pins.
Key input interrupt pins.
Timer X I/O pin
Timer X output pin
Timer Y I/O pin
Timer Z output pin
Timer C input pin
Timer C output pins
Transfer clock I/O pin.
Serial data input pins.
Serial data output pins.
Reference voltage input pin for A/D converter. Connect the VREF pin to Vcc.
Analog input pins for A/D converter
These are 8-bit CMOS I/O ports. Each port has an I/O
select direction register, allowing each pin in that port
to be directed for input or output individually.
Any port set to input can select whether to use a pullup resistor or not by program.
P10 to P17 also function as LED drive ports.
Port for input-only
1. Overview
Function
(1)
Rev.1.20 Jan 27, 2006 page 6 of 204
REJ09B0062-0120
Page 18
R8C/11 Group 2. Central Processing Unit (CPU)
g
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
b 3 1
R 2
R 3
b 1 9
I N T B H
T h e 4 - h i g h o r d e r b i t s o f I N T B a r e I N T B H a n d
t h e 1 6 - l o w b i t s o f I N T B a r e I N T B L .
b19
b 1 5 b 0 b7 b 8
I P L
i s t e r b a n k c o m p r i s e s t h e s e r e g i s t e r s . T w o s e t s o f r e g i s t e r b a n k s a r e p r o v i d e
N O T E S :
A r e
1 .
b 1 5 b
R0H (high-order of R0)
R1H (high-order of R1)
8
b7 b 0
R0L (low-order of R0)
R1L (low-order of R1)
R2
D a t a r e g i s t e r s
( 1 )
R3
A0
A1
F B
b 1 5 b
I N T B L
PC
b 1 5 b
U S P
ISP
SB
b15 b0
F L G
A d d r e s s r e g i s t e r s
F r a m e b a s e r e g i s t e r s
0
I n t e r r u p t t a b l e r e g i s t e r
b 0
P r o g r a m c o u n t e r
0
U s e r s t a c k p o i n t e r
Interrupt stack pointer
Static base register
Flag register
( 1 )
( 1 )
CDZSBOIU
Carry flag
D e b u g f l a g
Z e r o f l a g
Sign flag
Register bank select flag
O v e r f l o w f l a g
I n t e r r u p t e n a b l e f l a g
S t a c k p o i n t e r s e l e c t f l a g
R e s e r v e d b i t
Processor interrupt priority level
Reserved bit
d
Figure 2.1 CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0
can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit
data register (R2R0). The same applies to R3R1 as R2R0.
Rev.1.20 Jan 27, 2006 page 7 of 204
REJ09B0062-0120
Page 19
R8C/11 Group 2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be
combined with A0 to be used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to “0”.
2.8.3 Zero Flag (Z)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4 Sign Flag (S)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is
set to “1”.
2.8.6 Overflow Flag (O)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The
I flag is set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
When write to this bit, set to “0”. When read, its content is indeterminate.
Rev.1.20 Jan 27, 2006 page 8 of 204
REJ09B0062-0120
Page 20
R8C/11 Group 3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses
0000016 to FFFFF16.
The internal ROM is allocated lower addresses beginning with address 0FFFF16. For example, a 16-Kbyte
internal ROM is allocated addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte
internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing
data, but for calling subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function
control registers are located them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users.
00000
002FF
00400
0YYYY
0FFFF
16
16
16
16
16
(See Chapter 4 for details.)
SFR
Internal ROM
Figure 3.1 Memory Map
Rev.1.20 Jan 27, 2006 page 9 of 204
REJ09B0062-0120
Page 21
R8C/11 Group 4. Special Function Register (SFR)
(
)
(4)
(3)
(
)
(2)
(4)
(3)
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR
information
Table 4.1 SFR Information(1)
Address
0 0 0 0
1 6
0 0 0 1
1 6
0 0 0 2
1 6
0 0 0 3
1 6
M
P r o c e s s o r m o d e r e g i s t e r 0P
0 0 0 4
1 6
M
0 0 0 5
1 6
P r o c e s s o r m o d e r e g i s t e r 1P
M
1 1 0 1 0 0
0 0 0 6
1 6
S y s t e m c l o c k c o n t r o l r e g i s t e r 0C
M
0 1 0 0 0 0
0 0 0 7
1 6
S y s t e m c l o c k c o n t r o l r e g i s t e r 1C
R
0 0 0 8
1 6
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 0H
I E
X X X X X 0
0 0 0 9
1 6
A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e rA
R C
0 X X X 0 0
0 0 0 A
1 6
P r o t e c t r e g i s t e rP
R
0 0 0 B
1 6
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 1H
C
0 0 0 0 1 0
0 0 0 C
1 6
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO
D T
0 0 0 D
1 6
W a t c h d o g t i m e r r e s e t r e g i s t e rW
0 0 0 E
1 6
Watchdog timer start register WDTS XX
D
0 0 1 1 1 1
0 0 0 F
1 6
W a t c h d o g t i m e r c o n t r o l r e g i s t e rW
0 0 1 0
1 6
Address match interrupt register 0 RMAD0 00
0 0 1 1
1 6
0 0 1 2
1 6
0 0 1 3
1 6
M A D
0 0 1 4
1 6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R
0 0 1 5
1 6
0 0 1 6
1 6
0 0 1 7
1 6
0 0 1 8
1 6
0 0 1 9
1 6
Voltage detection register 1 VCR1 00001000
C R
0 0 1 A
1 6
V o l t a g e d e t e c t i o n r e g i s t e r 2V
0 0 1 B
1 6
0 0 1 C
1 6
0 0 1 D
1 6
0 0 1 E
1 6
INT0 input filter select register INT0F XXXXX000
0 0 1 F
1 6
Voltage detection interrupt register D4INT 00
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
X : U n d e f i n e d
N O T E S :
1 . B l a n k s p a c e s a r e r e s e r v e d . N o a c c e s s i s a l l o w e d .
2 . S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r .
3 . O w i n g t o R e s e t i n p u t .
4 . I n t h e c a s e o f
R E S E T
p i n = H r e t a i n i n g .
(1)
R e g i s t e r Symbol After reset
00
10
00
10
00
RX
R0
14
D0
RX
C0
10
2
2
20
0
1 6
0
1 6
0
1 6
0
1 6
X
1 6
16
16
00
16
X0
16
0
1 6
0 0
1 6
X 0
1 6
0
1 6
1 0 0 0 0 0 0 0
16
01000001
0
2
0
2
0
2
0
2
0
2
1
2
2
2
2
2
Rev.1.20 Jan 27, 2006 page 10 of 204
REJ09B0062-0120
Page 22
R8C/11 Group 4. Special Function Register (SFR)
Table 4.2 SFR Information(2)
A d d r e s s
0 0 4 0
1 6
0 0 4 1
1 6
0 0 4 2
1 6
0 0 4 3
1 6
0 0 4 4
1 6
0 0 4 5
1 6
0 0 4 6
1 6
0 0 4 7
1 6
0 0 4 8
1 6
0 0 4 9
1 6
0 0 4 A
1 6
0 0 4 B
1 6
0 0 4 C
1 6
U P I
X X X X 0 0
0 0 4 D
1 6
K e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e rK
D I
X X X X 0 0
0 0 4 E
1 6
A D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e rA
0 0 4 F
1 6
X X X X 0 0
0 0 5 0
1 6
C o m p a r e 1 i n t e r r u p t c o n t r o l r e g i s t e r
X X X X 0 0
0 0 5 1
1 6
U A R T 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r
X X X X 0 0
0 0 5 2
1 6
U A R T 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r
0 0 5 3
1 6
UART1 transmit interrupt control register
X X X X 0 0
0 0 5 4
1 6
U A R T 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r
0 0 5 5
1 6
INT2 interrupt contro l register INT2IC XXXXX000
0 0 5 6
1 6
Timer X interrupt control register TXIC XXXXX000
0 0 5 7
1 6
Timer Y interrupt control register TYIC XXXXX000
Z I
X X X X 0 0
0 0 5 8
1 6
T i m e r Z i n t e r r u p t c o n t r o l r e g i s t e rT
0 0 5 9
1 6
INT1 interrupt contro l register INT1IC XXXXX000
0 0 5 A
1 6
INT3 interrupt contro l register INT3IC XXXXX000
C I
X X X X 0 0
0 0 5 B
1 6
T i m e r C i n t e r r u p t c o n t r o l r e g i s t e rT
X X X X 0 0
0 0 5 C
1 6
C o m p a r e 0 i n t e r r u p t c o n t r o l r e g i s t e r
0 0 5 D
1 6
INT0 interrupt contro l register INT0IC XX00X000
0 0 5 E
1 6
0 0 5 F
1 6
0 0 6 0
1 6
0 0 6 1
1 6
0 0 6 2
1 6
0 0 6 3
1 6
0 0 6 4
1 6
0 0 6 5
1 6
0 0 6 6
1 6
0 0 6 7
1 6
0 0 6 8
1 6
0 0 6 9
1 6
0 0 6 A
1 6
0 0 6 B
1 6
0 0 6 C
1 6
0 0 6 D
1 6
0 0 6 E
1 6
0 0 6 F
1 6
0 0 7 0
1 6
0 0 7 1
1 6
0 0 7 2
1 6
0 0 7 3
1 6
0 0 7 4
1 6
0 0 7 5
1 6
0 0 7 6
1 6
0 0 7 7
1 6
0 0 7 8
1 6
0 0 7 9
1 6
0 0 7 A
1 6
0 0 7 B
1 6
0 0 7 C
1 6
0 0 7 D
1 6
0 0 7 E
1 6
0 0 7 F
1 6
X : U n d e f i n e d
N O T E S :
1 . B l a n k s p a c e s a r e r e s e r v e d . N o a c c e s s i s a l l o w e d .
(1)
R e g i s t e r Symbol A f t e r r e s e t
CX
CX
C M P 1 I CX
S 0 T I CX
S 0 R I CX
0
0
0
0
0
S1TIC XXXXX000
S 1 R I CX
CX
CX
C M P 0 I CX
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev.1.20 Jan 27, 2006 page 11 of 204
REJ09B0062-0120
Page 23
R8C/11 Group 4. Special Function Register (SFR)
(2)
Table 4.3 SFR Information(3)
A d d r e s s
X : U n d e f i n e d
N O T E S :
1 . B l a n k s p a c e s a r e r e s e r v e d . N o a c c e s s i s a l l o w e d .
2 . W h e n o u t p u t c o m p a r e m o d e ( t h e T C C 1 3 b i t i n t h e T C C 1 r e g i s t e r = 1 ) i s s e l e c t e d , t h e v a l u e a f t e r r e s e t i s s e t t o “ F F F F
Y Z M
0 0 8 0
1 6
T i m e r Y , Z m o d e r e g i s t e rT
R E
0 0 8 1
1 6
P r e s c a l e r Y r e g i s t e rP
Y S
T i m e r Y s e c o n d a r y r e g i s t e rT
0 0 8 2
1 6
Y P
T i m e r Y p r i m a r y r e g i s t e rT
0 0 8 3
1 6
U
T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e rP
0 0 8 4
1 6
R E
P r e s c a l e r Z r e g i s t e rP
0 0 8 5
1 6
Z S
T i m e r Z s e c o n d a r y r e g i s t e rT
0 0 8 6
1 6
Z P
T i m e r Z p r i m a r y r e g i s t e rT
0 0 8 7
1 6
0 0 8 8
1 6
0 0 8 9
1 6
Y Z O
T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e rT
0 0 8 A
1 6
X M
T i m e r X m o d e r e g i s t e rT
0 0 8 B
1 6
R E
P r e s c a l e r X r e g i s t e rP
0 0 8 C
1 6
T i m e r X r e g i s t e rT
0 0 8 D
1 6
C S
T i m e r c o u n t s o u r c e s e t r e g i s t e rT
0 0 8 E
1 6
0 0 8 F
1 6
0 0 9 0
1 6
T i m e r C r e g i s t e rT
0 0 9 1
1 6
0 0 9 2
1 6
0 0 9 3
1 6
0 0 9 4
1 6
0 0 9 5
1 6
N T E
0 0 9 6
1 6
E x t e r n a l i n p u t e n a b l e r e g i s t e rI
0 0 9 7
1 6
I E
K e y i n p u t e n a b l e r e g i s t e rK
0 0 9 8
1 6
0 0 9 9
1 6
Timer C contro l re gi st e r 0 TCC0 00
0 0 9 A
1 6
Timer C contro l re gi st e r 1 TCC1 00
0 0 9 B
1 6
M
0 0 9 C
1 6
C a p t u r e , c o m p a r e 0 r e g i s t e rT
0 0 9 D
1 6
0 0 9 E
1 6
Compare 1 reg ister TM1 FF
0 0 9 F
1 6
0 0 A 0
1 6
U A R T 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r
0 0 A 1
1 6
UART0 bit rate register U0BRG XX
0 0 A 2
1 6
UART0 transmit buffer register U0TB XX
0 0 A 3
1 6
0 0 A 4
1 6
UART0 transmit/receive control register 0
0 0 0 0 0 1
0 0 A 5
1 6
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1
0 R
0 0 A 6
1 6
U A R T 0 r e c e i v e b u f f e r r e g i s t e r U
0 0 A 7
1 6
0 0 A 8
1 6
U A R T 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r
1 B R
0 0 A 9
1 6
U A R T 1 b i t r a t e r e g i s t e rU
1 T
0 0 A A
1 6
U A R T 1 t r a n s m i t b u f f e r r e g i s t e rU
0 0 A B
1 6
0 0 0 1 0 0
0 0 A C
1 6
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0
0 0 A D
1 6
UART1 transmit/receive control register 1
1 R
0 0 A E
1 6
U A R T 1 r e c e i v e b u f f e r r e g i s t e r U
0 0 A F
1 6
0 0 B 0
1 6
UART transmit/receive control register 2
0 0 B 1
1 6
0 0 B 2
1 6
0 0 B 3
1 6
0 0 B 4
1 6
0 0 B 5
1 6
0 0 B 6
1 6
0 0 B 7
1 6
0 0 B 8
1 6
0 0 B 9
1 6
0 0 B A
1 6
0 0 B B
1 6
0 0 B C
1 6
0 0 B D
1 6
0 0 B E
1 6
0 0 B F
1 6
(1)
R e g i s t e r Symbol A f t e r r e s e t
0 0
0 0
FF
XX
1 6
0
F
1 6
F
1 6
F
1 6
0
1 6
F
1 6
F
1 6
F
1 6
0
1 6
0
1 6
F
1 6
F
1 6
0
1 6
0
1 6
1 6
0
1 6
0
1 6
16
16
0
1 6
1 6
16
16
0
1 6
16
16
16
R0
YF
CF
RF
M0
ZF
CF
RF
C0
R0
XF
XF
S0
C0
N0
N0
00
U 0 M R0
U0C0 00001000
U 0 C 10
BX
U 1 M R0
GX
BX
X X
X X
X
1 6
1 6
0
1 6
X
1 6
X
1 6
1 6
U 1 C 00
U1C1 00000010
BX
UCON 00
X X
X
1 6
1 6
16
2
0
2
0
2
2
1 6
”.
Rev.1.20 Jan 27, 2006 page 12 of 204
REJ09B0062-0120
Page 24
R8C/11 Group 4. Special Function Register (SFR)
A d d r e s s
0 0 C 01
0 0 C 11
0 0 C 21
0 0 C 31
0 0 C 41
0 0 C 51
0 0 C 61
0 0 C 71
0 0 C 81
0 0 C 91
0 0 C A1
0 0 C B1
0 0 C C1
0 0 C D1
0 0 C E1
0 0 C F1
0 0 D 01
0 0 D 11
0 0 D 21
0 0 D 31
0 0 D 41
0 0 D 51
0 0 D 61
0 0 D 71
0 0 D 81
0 0 D 91
0 0 D A1
0 0 D B1
0 0 D C1
0 0 D D1
0 0 D E1
0 0 D F1
0 0 E 01
0 0 E 11
0 0 E 21
0 0 E 31
0 0 E 41
0 0 E 51
0 0 E 61
0 0 E 71
0 0 E 81
0 0 E 91
0 0 E A1
0 0 E B1
0 0 E C1
0 0 E D1
0 0 E E1
0 0 E F1
0 0 F 01
0 0 F 11
0 0 F 21
0 0 F 31
0 0 F 41
0 0 F 51
0 0 F 61
0 0 F 71
0 0 F 81
0 0 F 91
0 3 F A1
0 0 F B1
0 0 F C1
0 0 F D1
0 0 F E1
0 0 F F1
6
A D r e g i s t e rA
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
D C O N
6
A D c o n t r o l r e g i s t e r 2A
6
D C O N
0 0 0 0 X X
6
A D c o n t r o l r e g i s t e r 0A
D C O N
6
A D c o n t r o l r e g i s t e r 1 A
6
6
6
6
6
6
6
6
6
Port P0 register P0 XX
6
P o r t P 1 r e g i s t e rP
6
Port P0 direction register PD0 00
D
6
P o r t P 1 d i r e c t i o n r e g i s t e rP
6
6
P o r t P 3 r e g i s t e rP
6
D
6
P o r t P 3 d i r e c t i o n r e g i s t e rP
6
P o r t P 4 r e g i s t e rP
6
D
6
P o r t P 4 d i r e c t i o n r e g i s t e rP
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
U R
0 X X 0 0 0
6
P u l l - u p c o n t r o l r e g i s t e r 0 P
U R
X X X X X 0
6
P u l l - u p c o n t r o l r e g i s t e r 1 P
R
6
P o r t P 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r D
C O U
6
T i m e r C o u t p u t c o n t r o l r e g i s t e r T
R e g i s t e r
Symbol After reset
DX
20
00
10
1X
10
3X
30
4X
40
00
1X
R0
T0
X X
X
1 6
1 6
0
1 6
X
0
2
1 6
16
X
1 6
16
0
1 6
X
1 6
0
1 6
X
1 6
0
1 6
0
2
X
0
1 6
0
1
2
0 1 B 31
6
0 1 B 41
6
M R
1 0 0 X X 0
0 1 B 51
6
F l a s h m e m o r y c o n t r o l r e g i s t e r 1 F
0 1 B 61
6
M R
0 0 0 0 0 0
0 1 B 71
6
F l a s h m e m o r y c o n t r o l r e g i s t e r 0 F
Rev.1.20 Jan 27, 2006 page 13 of 204
REJ09B0062-0120
10
00
1
X
2
2
Page 25
R8C/11 Group
5. Reset
There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset.
5.1 Hardware Reset
There are three kinds of hardware reset: hardware reset 1, hardware reset 2, and power-on reset.
After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the
CPU.
5.1 Hardware Reset
5.1.1 Hardware Reset 1
____________ ____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while
the power supply voltage is within the recommended operating condition, the pins are initialized (see Table 5.1 “Pin Status When RESET Pin Level is 'L'”). When the input level at the
____________
____________
RESET pin is released from “L” to “H”, the CPU and SFR are initialized, and the program is
executed starting from the address indicated by the reset vector. Figure 5.1 shows the CPU
register status after reset and figure 5.2 shows the reset sequence. The internal RAM is not
____________
initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM
becomes indeterminate.
Figures 5.3 to 5.4 show the reset circuit example using the hardware reset 1. Refer to Chapter
4, “Special Function Register (SFR)” for the status of SFR after reset.
• When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin.
(2) Wait for 500 µs (1/fRING-S ✕ 20).
____________
(3) Apply an “H” signal to the RESET pin.
• Power on
____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condi-
tion.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Wait for 500 µs (1/fRING-S ✕ 20).
____________
(5) Apply an “H” signal to the RESET pin.
Table 5.1 Pin Status When RESET Pin Level is “L”
____________
Pin name
P0
P1
P3
0
to P33, P3
P45
to P47
Rev.1.20 Jan 27, 2006 page 14 of 204
REJ09B0062-0120
7
Input port
Input port
Input port
Input port
Status
Page 26
R8C/11 Group
5.1 Hardware Reset
b15
0000
16
0000
16
0000
16
0000
16
0000
16
0000
16
0000
16
b19
00000
16
Content of addresses 0FFFE16 to 0FFFC
b15
16
0000
0000
16
0000
16
16
b0
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
b0
Interrupt table register(INTB)
Program counter(PC)
b0
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
b15
0000
b15
b7 b8
IPL
Figure 5.1 CPU Register Status After Reset
f
R I N G - S
I n t e r n a l o n - c h i p
o s c i l l a t i o n
C P U c l o c k
A d d r e s s
( I n t e r n a l a d d r e s s s i g n a l )
N O T E S :
1 . T h i s s h o w s h a r d w a r e r e s e t
M o r e t h a n 2 0 c y c l e s a r e n e e d e d
F l a s h m e m o r y a c t i v a t e d t i m e
( C P U c l o c k ✕ 6 4 c y c l e s )
( 1 )
16
C P U c l o c k ✕ 2 8 c y c l e s
b0
b0
CDZSBOIU
0FFFC16
Flag register(FLG)
0 F F F E1
6
1 6
0 F F F D
Content of reset vector
Figure 5.2 Reset Sequence
Rev.1.20 Jan 27, 2006 page 15 of 204
REJ09B0062-0120
Page 27
R8C/11 Group
5.1 Hardware Reset
V
C C
2 . 7 V
0 V
V
R E S E T
C C
RESET
0 V
Figure 5.3 Example Reset Circuit Using The Hardware Reset 1
5V
2.7V
RESET
V
CC
Supply voltage
detection circuit
V
CC
0V
5V
Equal to or less
than 0.2V
CC
M o r e t h a n t d ( P - R ) + 5 0 0 µ s a r e
n e e d e d .
RESET
0V
More than td(P-R) + 500 µs
are needed.
Example when V
CC
= 5V
.
Figure 5.4 Example Reset Circuit Using The Hardware Reset 1 (Voltage Check Circuit)
Rev.1.20 Jan 27, 2006 page 16 of 204
REJ09B0062-0120
Page 28
R8C/11 Group
5.1.2 Hardware Reset 2
This is the reset generated by the voltage detection circuit which is built-in to the microcomputer. The
voltage detection circuit monitors the input voltage at Vcc input pin. The microcomputer is reset when
the voltage at the VCC input pin drops below Vdet if all of the following conditions hold true.
• The VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled)
• The D40 bit in the D4INT register is set to “1” (voltage detection interrupt enabled)
• The D46 bit in the D4INT register is set to “1” (hardware reset 2 when going through Vdet)
When using a digital filter (D41 bit in the D4INT register is set to “1”), set the CM14 bit in the CM1
register to “0”(low-speed on-chip oscillator oscillates).
Conversely, when the input voltage at the VCC pin rises to Vdet or more, the pins, CPU, and SFR are
initialized and counting the low-speed on-chip oscillator starts. When counting the low-speed on-chip
oscillator clock 32 times, the internal reset is exited and the program is executed beginning with the
address indicated by the reset vector. The initialized pins and registers and the status thereof are the
same as in hardware reset 1. Refer to Section 5.4 “Voltage Detection Circuit.”
5.1 Hardware Reset
Rev.1.20 Jan 27, 2006 page 17 of 204
REJ09B0062-0120
Page 29
R8C/11 Group
5.1.3 Power-on Reset Function
The power-on reset is the function which can reset the microcomputer without the external reset
circuit. The RESET pin should be connected to the VCC pin via about 5 kΩ pull-up resistance using the
power-on reset function, the function turns to active and the microcomputer has its pins, CPU and
SFR initialized. When a capacitor is connected to the RESET pin, always keep the voltage to the
____________
RESET pin 0.8 VCC or more.
When the input voltage at the VCC pin reaches to the Vdet level, count operation of the low-speed onchip oscillator clock starts. When the operation counts the low-speed on-chip oscillator clock for 32
times, the internal reset is released. Then the program is executed starting from the address indicated by the reset vector. The initialized pins and registers and the status thereof are the same as in
hardware reset 1 excluding the following bits.
• The D40 bit in the D4INT register turns to “1” automatically (voltage detection interrupt enabled)
• The D46 bit in the D4INT register turns to “1” automatically (hardware reset 2 when going through
Vdet)
Additionally, the hardware reset 2 turns to active after the power-on reset. This is because the VC27
bit in the VCR2 register is set to “1” (voltage detection circuit enabled) after the power-on reset same
as the hardware reset 1, so that hardware reset 2 active conditions are all satisfied including above
D40 and D46 bit conditions.
5.1 Hardware Reset
____________
____________
Figure 5.5 shows the power-on reset circuit. Figure 5.6 shows the power-on reset operation.
RESET
fRING-S
VCC ≥ Vdet detection
5-bit
counter
Figure 5.5 Power-on Reset Circuit
Trigger
Internal reset signal
Q
S
R
Rev.1.20 Jan 27, 2006 page 18 of 204
REJ09B0062-0120
Page 30
R8C/11 Group
0.1V to 2.7VV
CC
RESET Vcc
about 5 kΩ
3
V
det
V
por1
t
w(por1)
Internal reset signal
(“L” effective)
t
w(Vpor1–Vdet)
1
f
RING-S
NOTES:
1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time.
2. A sampling clock is selectable. Refer to “5.4 Voltage Detection Circuit” for details.
det
shows the voltage detection level of the voltage detection circuit. Refer to “5.4 Voltage Detection Circuit” for details.
3. V
4. Refer to Table 16.6, 16.7 for electrical characteristics.
0V
RESET
0V
Sampling time
X 32
within td(P-R)
2)
(1,
t
w(por2)tw(Vpor2 –Vdet)
0.8VCC or above
V
cc min
V
por2
f
RING-S
(3)
V
det
1
X 32
Figure 5.6 Power-on Reset Operation
Rev.1.20 Jan 27, 2006 page 19 of 204
REJ09B0062-0120
Page 31
R8C/11 Group
5.2 Software Reset, 5.3 Watchdog Timer Reset
5.2 Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset
vector. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the
CPU. Some SFRs are not initialized by the software reset. Refer to Chapter 4, “SFR.”
5.3 Watchdog Timer Reset
Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed
starting from the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock
divided by 8 is automatically selected for the CPU. Some SFRs are not initialized by the watchdog timer
reset. Refer to Chapter 4, “SFR.”
Rev.1.20 Jan 27, 2006 page 20 of 204
REJ09B0062-0120
Page 32
R8C/11 Group
5.4 Voltage Detection Circuit
5.4 Voltage Detection Circuit
The voltage detection circuit monitors the input voltage at the VCC pin with respect to Vdet. The user
program can check for voltage detection using the VC13 bit or set up the voltage detection interrupt
register to generate a hardware reset 2 or voltage detection interrupt.
Figure 5.7 shows the voltage detection circuit. Figure 5.8 shows VCR1 and VCR2 registers. Figure 5.9
shows the D4INT register. Figure 5.10 shows an operation example of the voltage detection circuit. Figure 5.11 to 5.12 show the operation example of the voltage detection circuit to get out of stop mode.
VC27
VCC
+
Noise canceller
Internal
reference
voltage
Figure 5.7 Voltage Detection Circuit Block
-
Voltage detection
interrupt signal
VCR1 register
b3
VC13 bit
Rev.1.20 Jan 27, 2006 page 21 of 204
REJ09B0062-0120
Page 33
R8C/11 Group
( b
( b
( b
5.4 Voltage Detection Circuit
V o l t a g e d e t e c t i o n r e g i s t e r 1
b 7b 6b 5b 4b 3b 2b 1b 0
0000 000
d d r e s
f t e r r e s e
0 1
S y m b o lA
V C R 10
Bit symbol
2 - b 0 )
VC13
R e s e r v e d b i t
V o l t a g e m o n i t o r f l a g
sA
9
1 6
0 0 0 0 1 0 0 0
B i t n a m eF
(1 )
(2 )
t
2
u n c t i o
Should set to “0”
C C
< V d e t
0 : V
1 : V
C C
≥
V d e t o r v o l t a g e
n
R W
R W
RO
d e t e c t i o n c i r c u i t d i s a b l e d
7 - b 4 )
R e s e r v e d b i t
Should set to “0”
R W
N O T E S :
1 . T h e V C 1 3 b i t i s v a l i d w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o “ 1 ” ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) . T h e
V C 1 3 b i t i s s e t t o “ 1 ” ( V
C C
≥ V d e t o r v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d ) w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t
t o “ 0 ” ( v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d ) .
2 . S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r .
V o l t a g e d e t e c t i o n r e g i s t e r 2
b7 b6 b5 b4 b# b2 b1 b0
00000
00
( 1 )
d d r e s
f t e r r e s e
0 1
S y m b o lA
V C R 20
sA
A
1 6
R e s e t i n p u t : 0 0
(3 )
t
1 6
R E S E T p i n = “ H ” r e t a i n i n g : 1 0 0 0 0 0 0 0
(2)
B i t n a m e
F u n c t i o n
0 : V o l t a g e d e t e c t i o n c i r c u i t
d i s a b l e d
1 : V o l t a g e d e t e c t i o n c i r c u i t
Bit symbol
6 - b 0 )
VC27
R e s e r v e d b i t Should set to “0”
Voltage monitor enable
bit
2
R W
R W
R W
e n a b l e d
N O T E S :
1 . S e t t h e P R C 3 b i t i n t h e P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e d ) b e f o r e w r i t i n g t o t h i s r e g i s t e r .
2 . S e t t h e V C 2 7 b i t t o “ 1 ” ( v o l t a g e d e t e c t c i r c u i t e n a b l e d ) w h e n h a r d w a r e r e s e t 2 i s u s e d .
A f t e r t h e V C 2 7 b i t i s s e t t o “ 1 ” , t h e v o l t a g e d e t e c t i o n c i r c u i t e l a p s e s f o r t
d ( E - A )
b e f o r e s t a r t i n g o p e r a t i o n .
3 . S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r .
Figure 5.8 VCR1 Register and VCR2 Register
Rev.1.20 Jan 27, 2006 page 22 of 204
REJ09B0062-0120
Page 34
R8C/11 Group
Voltage detec tion interrupt regis ter
b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0
Symbol Address After reset
D4INT 001F
RESET pin = "H" retaining : 01000001
B i t s y m b o l
D 4 0
D 4 1
D 4 2
D 4 3
D F 0
D F 1
(1)
16
Reset input : 00
Bit name
V o l t a g e d e t e c t i o n i n t e r r u p t
e n a b l e b i t
V o l t a g e c h a n g e d e t e c t i o n
f l a g
W D T o v e r f l o w d e t e c t
f l a g
S a m p l i n g c l o c k s e l e c t b i t
(7 )
(3 , 4 , 5 )
(3 , 4 )
(10)
16
0 :
Disable
1 :
Enable
0: Not detected
1: Vdet passing detection
0 : N o t d e t e c t e d ( f l a g c l e a r )
1 : D e t e c t e d
0 0 : f
R I N G- S
d i v i d e d b y 1
R I N G - S
R I N G - S
R I N G - S
d i v i d e d b y 2
d i v i d e d b y 4
d i v i d e d b y 8
0 1 : f
1 0 : f
1 1 : f
2
N O T E S :
1 . S e t t h e P R C 3 b i t i n t h e P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r .
2 . I f t h e v o l t a g e d e t e c t i o n i n t e r r u p t n e e d s t o b e u s e d t o g e t o u t o f s t o p m o d e a g a i n a f t e r o n c e u s e d f o r t h a t
p u r p o s e , r e s e t t h e D 4 1 b i t b y w r i t i n g a “ 0 ” a n d t h e n a “ 1 ” .
3. V a l i d w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o “ 1 ” ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) .
4 . I f t h e V C 2 7 b i t i s s e t t o “ 0 ” ( v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d ) , t h e D 4 2 a n d D 4 3 b i t s a r e s e t t o “ 0 ” ( n o t d e t e c t e d ) .
5 . T h i s b i t i s s e t t o “ 0 ” b y w r i t i n g a “ 0 ” i n a p r o g r a m . ( w r i t i n g a “ 1 ” h a s n o e f f e c t . )
6 . V a l i d w h e n t h e D 4 0 b i t i s s e t t o “ 1 ” ( v o l t a g e d e t e c t i o n i n t e r r u p t e n a b l e d ) .
7 . T
Rev.1.20 Jan 27, 2006 page 23 of 204
REJ09B0062-0120
Page 35
R8C/11 Group
5.4 Voltage Detection Circuit
5.0 V
V
det
CC
V
Sampling time
(3 to 4 clock)
Internal reset signal
(D46 bit=1)
VC13 bit
Set to“1” by program (voltage
detection circuit enabled)
VC27 bit
Voltage detection
interrupt request
Interrupt acknowledged
Sampling time
(3 to 4 clock)
(D46 bit=0)
The above applies to the following conditions.
• D4INT register D40 bit = 1 (voltage detection interrupt enabled)
• D4INT register D41 bit = 0 (digital filter enabled mode)
Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
5.0 V
1
x 32
fRING
Interrupt acknowledged
Figure 5.10 Operation Example of Voltage Detection Circuit
Rev.1.20 Jan 27, 2006 page 24 of 204
REJ09B0062-0120
Page 36
R8C/11 Group
V
CC
Internal reset signal(D46 bit = 1)
VC13 bit
VC27 bit
CM 10 bit
Voltage detection
interrupt request
(D46 bit = 0)
5.4 Voltage Detection Circuit
5.0V
V
det
Set to "1" by program (voltage detection circuit enabled)
Interrupt acknowledged
The above applies to the following conditions.
D4INT register D40 = 1 (voltage detection interrupt enabled)
D4INT register D41 = 1 (digital filter disabled mode)
D4INT register D47 = 1 ( Vcc is below Vdet)
CM10 : CM1 register bit
VC13 : VCR1 register bit
VC27 : VCR2 register bit
D46 : D4INT register bit
Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
Figure 5.11 Operation Example of Voltage Detection Circuit to get out of Stop mode (1)
5.0V
V
det
CC
V
VC13 bit
Set to "1" by program (voltage detection circuit enabled)
VC27 bit
CM10 bit
Interrupt acknowledged
Voltage detection
interrupt request
(D46 bit = 0)
The above applies to the following conditions.
D4INT register D40 bit = 1 (voltage detection interrupt enabled)
D4INT register D41 bit = 1 (digital filter disabled mode)
D4INT register D47 bit = 0 (Vcc is over Vdet)
CM10 : CN1 register bit
VC13 : VCR1 register bit
VC27 : VCR2 register bit
D46 : D4INT register bit
Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
Figure 5.12 Operation Example of Voltage Detection Circuit to get out of Stop mode (2)
Rev.1.20 Jan 27, 2006 page 25 of 204
REJ09B0062-0120
Page 37
R8C/11 Group
5.4.1 Voltage Detection Interrupt
Figure 5.13 shows the block diagram of voltage detection interrupt generation circuit.
Refer to 5.4.2, "Exiting Stop Mode on a Voltage Detection Circuit" for Getting out of stop mode due to
the voltage detection interrupt.
A voltage detection interrupt is generated when the input voltage at the VCC pin rises to Vdet or more
or drops below Vdet if all of the following conditions hold true in normal operation mode and wait
mode.
• The VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled)
• The D40 bit in the D4INT register is set to “1” (voltage detection interrupt enabled)
• The D46 bit in the D4INT register is set “0” (voltage detection interrupt selected)
To use the digital filter (D41 bit in the D4INT register is set to “0”), set the CM14 bit in the CM1 register
to "0" (low-speed on-chip oscillator). Figure 5.14 shows an operation example of voltage detection
interrupt generation circuit.
The voltage detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscillation stop detection interrupt.
The D42 bit in the D4INT register becomes “1” when passing through Vdet is detected after the voltage inputted to the VCC pin is up or down.
A voltage detection interrupt request is generated when the D42 bit changes state from “0” to “1”. The
D42 bit needs to be set to “0” in a program.
Table 5.2 lists the voltage detection interrupt request generation conditions.
It takes 4 cycles of sampling clock until the D42 bit is set to "1" since the voltage which inputs to
Vcc pin passes Vdet.
It is possible to set the sampling clock detecting that the voltage applied to the VCC pin has passed
through Vdet with the DF0 to DF1 bitsf0.3337 0 TD(1)Tj/Ftsf0.3337 0 TD72 1 m.1
Rev.1.20 Jan 27, 2006 page 26 of 204
REJ09B0062-0120
Page 38
R8C/11 Group
Rev.1.20 Jan 27, 2006 page 27 of 204
REJ09B0062-0120
Page 39
R8C/11 Group
Rev.1.20 Jan 27, 2006 page 28 of 204
REJ09B0062-0120
Page 40
R8C/11 Group
q
y
y
p
pp
p
p
r
p
g
pp
g
p
p
g
g
(N
)
(N
)
6. Clock Generating Circuit
6. Clock Generation Circuit
The clock generation circuit contains two oscillator circuits as follows:
• Main clock oscillation circuit
• On-chip oscillator (with oscillation stop detection function)
Table 6.1 lists the clock generation circuit specifications. Figure 6.1 shows the clock generation circuit.
Figures 6.2 to 6.4 show the clock-related registers.
Table 6.1 Clock Generation Circuit Specifications
I t e m
U s e o f c l o c k
u e n c
C l o c k f r e
U s a b l e o s c i l l a t o r
• C P U c l o c k s o u r c e
• P e r i p h e r a l f u n c t i o n
0 t o 2 0 M H z
s t a l o s c i l l a t o
• C e r a m i c r e s o n a t o r
• C r
P i n s t o c o n n e c t
X
o s c i l l a t o r
Oscillation starts
and sto
s
Oscillator status
Present
Sto
after reset
Other
Externally derived
clock can be in
N O T E S :
1 . C a n b e u s e d a s P 4
c i r c u i t i s n o t u s e d .
Main clock
oscillation circuit
c l o c k s o u r c e
r
, X
OUT
(1)
IN
ed
ut
6
a n d P 47 w h e n t h e o n - c h i p o s c i l l a t o r c l o c k i s u s e d f o r C P U c l o c k w h i l e t h e m a i n c l o c k o s c i l l a t i o n
h - s p e e d o n - c h i p o s c i l l a t o
H i
s o s c i l l a t i n
• C P U c l o c k s o u r c e
• P e r i p h e r a l f u n c t i o n c l o c k s o u r c e
• C P U a n d p e r i p h e r a l f u n c t i o n
c l o c k s o u r c e s w h e n t h e m a i n
c l o c k s t o
Approx. 8 MHz
ote 1
Present
Sto
ed
o s c i l l a t o
O n - c h i
Low-s
r
eed on-chip oscillator
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function
clock sources when the main
clock sto
s oscillatin
Approx. 125 kHz
ote 1
Present
Oscillatin
Rev.1.20 Jan 27, 2006 page 29 of 204
REJ09B0062-0120
Page 41
R8C/11 Group
j
k
RQScR
S
R
T
8
O
8
8
O
2
k
t
t
S
6. Clock Generating Circuit
R E S E T
H a r d w a r e r e s e t 2
P o w e r o n r e s e
u d g m e n t o u t p u
I n t e r r u p t r e q u e s t l e v e l
V o l t a g e d e t e c t i v e
i n t e r r u p t
C M 1 0 = 1 ( S t o p m o d e )
t
W A I T i n s t r u c t i o n
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 1 ( 7 - b i t )
F r e q u e n c y a d j u s t a b l e
f R I N G -
V o l t a g e
d e t e c t i o n
c i r c u i t
O s c i l l a t i o n
s t o p
d e t e c t i o n
O n - c h i p
o s c i l l a t o r
c l o c k
O C D 2 = 1
O C D 2 = 0
C M 0 2
H i g h - s p e e d
o n - c h i p
o s c i l l a t o r
H R 0 1 = 1
H R 0 1 = 0
L o w - s p e e d
o n - c h i p
o s c i l l a t o r
M a i n
c l o c
C M 1 3
U
XO
H R 0 0
C M 1 4
Q
XI
N
C M 0 5
e
a
1 / 2 1 / 2 1 / 2 1 / 2
a
1 / 1 2
e
b
D i v i d e r
b
I N G - f a s
fR
I N
fR
G
I N G 1 2
fR
f1
S I
f1
fA
D
f
S I
f8
2 S I
f3
P e r i p h e r a l
f u n c t i o n c l o c k
O
f
f3
2
c
d
C P U c l o c k
c
1 / 2
C M 0 2 , C M 0 5 , C M 0 6 : B i t s i n C M 0 r e g i s t e r
C M 1 0 , C M 1 3 , C M 1 4 , C M 1 6 , C M 1 7 : B i t s i n C M 1 r e g i s t e r
O C D 0 , O C D 1 , O C D 2 : B i t s i n O C D r e g i s t e r
H R 0 0 , H R 0 1 : B i t s i n H R 0 r e g i s t e r
O s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t
F o r c i b l e d i s c h a r g e w h e n O C D 0
P u l s e g e n e r a t i o n
M a i n c l o c
c i r c u i t f o r c l o c k
e d g e d e t e c t i o n
a n d c h a r g e ,
d i s c h a r g e c o n t r o l
c i r c u i t
N O T E S :
1 . S e t t h e s a m e v a l u e t o t h e O C D 1 b i t a n d O C D 0 b i t .
Figure 6.1 Clock Generation Circuit
C h a r g e ,
d i s c h a r g e
c i r c u i t
O C D 1
C M 0 6 = 0
C M 1 7 t o C M 1 6 = 1 12
d
C M 0 6 = 0
C M 1 7 t o C M 1 6 = 0 0
C M 0 6 = 0
C M 1 7 t o C M 1 6 = 0 1
2
C M 0 6 = 0
C M 1 7 t o C M 1 6 = 1 0
2
C M 0 6 = 1
2
D e t a i l s o f d i v i d e r
(1 )
= 0
O s c i l l a t i o n s t o p
d e t e c t i o n i n t e r r u p t
(1 )
g e n e r a t i o n c i r c u i t
W a t c h d o g
t i m e r
i n t e r r u p t
O C D 2 b i t s w i t c h s i g n a l
C M 1 4 b i t s w i t c h s i g n a l
O s c i l l a t i o n s t o p
d e t e c t i o n ,
W a t c h d o g t i m e r ,
V o l t a g e
d e t e c t i o n
i n t e r r u p t
Rev.1.20 Jan 27, 2006 page 30 of 204
REJ09B0062-0120
Page 42
R8C/11 Group
6
S y s t e m c l o c k c o n t r o l r e g i s t e r 0
b 7b 6b 5b 4b 3b 2b 1b 0
( 1 )
d d r e s
0 0
S y m b o lA
C M 00
sA f t e r r e s e t
6
1 6
6 8
1 6
Bit name F u n c t i o nB i t s y m b o l
( b 1 - b 0 )
C M 0 2
( b 3 )
R e s e r v e d b i t
W A I T p e r i p h e r a l f u n c t i o n
c l o c k s t o p b i t
R e s e r v e d b i tS
R e s e r v e d b i t
C M 0 5
C M 0
M a i n c l o c k ( X
s t o p b i t
C P U c l o c k d i v i s i o n s e l e c t
b i t 0
I N
- X
(2 , 4 )
(5 )
O U T
R e s e r v e d b i tS
f
N O T E S :
1 . S e t t h e P R C 0 b i t o f P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r .
2 . T h e C M 0 5 b i t i s p r o v i d e d t o s t o p t h e m a i n c l o c k w h e n t h e o n - c h i p o s c i l l a t o r m o d e i s s e l e c t e d . T h i s b i t c a n n o t b e u s e d f o r d e t e c t i o n
a s t o w h e t h e r t h e m a i n c l o c k s t o p p e d o r n o t . T o s t o p t h e m a i n c l o c k , t h e f o l l o w i n g s e t t i n g i s r e q u i r e d :
( 1 ) S e t t h e O C D 0 a n d O C D 1 b i t s i n t h e O C D r e g i s t e r t o “ 0 0
2
( 2 ) S e t t h e O C D 2 b i t t o “ 1 ” ( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) .
3 . S e t t h e C M 0 5 b i t t o “ 1 ” ( m a i n c l o c k s t o p s ) a n d t h e C M 1 3 b i t i n t h e C M 1 r e g i s t e r t o “ 1 ” ( X
i n p u t .
4 . W h e n t h e C M 0 5 b i t i s s e t t o “ 1 ” ( m a i n c l o c k s t o p ) , P 4
6
a n d P 4
S e t t o “ 0 ”
0 : D o n o t s t o p p e r i p h e r a l f u n c t i o n c l o c k i n w a i t m o d e
1 : S t o p p e r i p h e r a l f u n c t i o n c l o c k i n w a i t m o d e
e t t o “ 1
”
S e t t o “ 0 ”
)
0 : O n
(3 )
1 : O f f
0 : C M 1 6 a n d C M 1 7 v a l i d
1 : D i v i d e - b y - 8 m o d e
e t t o “ 0
”
” ( d i s a b l i n g o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n ) .
I N
- X
O U T
p i n ) w h e n t h e e x t e r n a l c l o c k i s
7
c a n b e u s e d a s i n p u t p o r t s .
Rev.1.20 Jan 27, 2006 page 31 of 204
REJ09B0062-0120
Page 43
R8C/11 Group
W
W
W
b
W
6. Clock Generating Circuit
O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e r
b 7b 6b 5b 4b 3b 2b 1b0
0000
Symbol Address A fter reset
OCD
B i t s y m b o l
OCD0
OCD1
OCD2
OCD3
(b7-b4)
( 1 )
0 0 0 C
Bit name
O s c i l l a t i o n s t o p
d e t e c t i o n e n a b l e b i t
S y s t e m c l o c k s e l e c t b i t
C l o c k m o n i t o r b i t
Reserved bit
(3 , 5 )
1 6
04
16
1 b
0
Function
0 0 : T h e f u n c t i o n i s d i s a b l e d
0 1 : A v o i d t h i s s e t t i n g
1 0 : A v o i d t h i s s e t t i n g
1 1 : T h e f u n c t i o n i s e n a b l e d
0 : S e l e c t m a i n c l o c k
(6 )
1 : S e l e c t o n - c h i p o s c i l l a t o r c l o c k
0 : M a i n c l o c k o n
1 : M a i n c l o c k o f f
Set to "0"
(4 )
(7 )
(7 )
N O T E S :
1 . S e t t h e P R C 0 b i t i n t h e P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) b e f o r e r e w r i t i n g t h i s r e g i s t e r .
2 . T h e O C D 2 b i t i s s e t t o “ 1 ” ( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) a u t o m a t i c a l l y i f a m a i n c l o c k o s c i l l a t i o n s t o p
i s d e t e c t e d w h i l e t h e O C D 1 t o O C D 0 b i t s a r e s e t t o “ 1 1
2
” ( o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n e n a b l e d ) . I f
t h e O C D 3 b i t i s s e t t o “ 1 ” ( m a i n c l o c k s t o p ) , t h e O C D 2 b i t r e m a i n s u n c h a n g e d w h e n t r y i n g t o w r i t e “ 0 ”
( s e l e c t i n g m a i n c l o c k ) .
3 . T h e O C D 3 b i t i s e n a b l e d w h e n t h e O C D 1 t o O C D 0 b i t s a r e s e t t o “ 1 1
2
” ( o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n
e n a b l e d ) .
4 . T h e O C D 1 t o O C D 0 b i t s s h o u l d b e s e t t o “ 0 0
2
” ( o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n d i s a b l e d ) b e f o r e
e n t e r i n g s t o p m o d e o r o n - c h i p o s c i l l a t o r ( m a i n c l o c k s t o p s ) .
5 . T h e O C D 3 b i t r e m a i n s s e t t o “ 0 ” ( m a i n c l o c k o n ) i f t h e O C D 1 t o O C D 0 b i t s a r e s e t t o “ 0 0
2
” .
6 . T h e C M 1 4 b i t g o e s t o “ 0 ” ( l o w - s p e e d o n - c h i p o s c i l l a t o r o n ) i f t h e O C D 2 b i t i s s e t t o “ 1 ” ( s e l e c t i n g o n - c h i p
o s c i l l a t o r c l o c k ) .
7 . R e f e r t o F i g u r e 6 . 7 “ s w i t c h i n g c l o c k s o u r c e f r o m l o w - s p e e d o n - c h i p o s c i l l a t o r t o m a i n c l o c k ” f o r t h e
s w i t c h i n g p r o c e d u r e w h e n t h e m a i n c l o c k r e - o s c i l l a t e s a f t e r d e t e c t i n g a n o s c i l l a t i o n s t o p .
(2 )
R
R
R
R O
R
Figure 6.3 OCD Register
Rev.1.20 Jan 27, 2006 page 32 of 204
REJ09B0062-0120
Page 44
R8C/11 Group
6
3
0
0
W
0
0
W
W
W
5
2
W
0
W
00000
6. Clock Generating Circuit
H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 0
b 7b
b 5b 4b
b 2b 1b
d d r e s
0 0
S y m b o lA
H R 00
( 3 )
sA f t e r r e s e t
8
1 6
0 0
1 6
Bit name FunctionB i t s y m b o l
H R 0
H R 0 1
( b 7 - b 2 )
N O T E S :
1 . T h e H R 0 1 b i t s h o u l d b e c h a n g e d u n d e r t h e f o l l o w i n g c o n d i t i o n s .
• H R 0 0 = 1 ( h i g h - s p e e d o n - c h i p o s c i l l a t o r o n )
• C M 1 r e g i s t e r C M 1 4 b i t = 0 ( l o w - s p e e d o n - c h i p o s c i l l a t o r o n )
2 . W h e n w r i t i n g “ 0 ” ( l o w - s p e e d o n - c h i p o s c i l l a t o r s e l e c t e d ) t o t h e H R 0 1 b i t , d o n o t w r i t e “ 0 ” ( h i g h - s p e e d o n - c h i p o s c i l l a t o r s t o p s ) t o
t h e H R 0 0 b i t s i m u l t a n e o u s l y . S e t t h e H R 0 0 b i t t o “ 0 ” a f t e r s e t t i n g t h e H R 0 1 b i t t o “ 0 ” .
3 . S e t t h e P R C 0 b i t i n t h e P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) b e f o r e r e w r i t i n g t h i s r e g i s t e r .
High-speed on-chip oscillator control register 1
b 7b 6b
b 4b 3b
b 1b 0
d d r e s
0 0
S y m b o lA
H R 10
High-speed on-chip
oscillator enable bit
H i g h - s p e e d o n - c h i p
o s c i l l a t o r s e l e c t b i t
Reserved bit
0: High-speed on-chip oscillator off
1: High-speed on-chip oscillator on
(1 )
0: Low-speed on-chip oscillator selected
1: High-speed on-chip oscillator selected
Set to
(1)
sA f t e r r e s e t
B
1 6
4 0
(2)
“0”
1 6
F u n c t i o n
The frequency of high-speed on-chip oscillator is adjusted with bits 0 to bits 6.
Period of high-speed on-chip oscillator
= td(HR offset) + (64 ✕ b6 + 32 ✕ b5 + 16 ✕ b4 + 8 ✕ b3 + 4 ✕ b2 + 2 ✕ b1 + b0) ✕ td(HR)
Bit 7 should be set to “0”.
R
R
R
R
R
R
N O T E S :
1 . S e t t h e P R C 0 b i t i n t h e P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) b e f o r e r e w r i t i n g t h i s r e g i s t e r .
Figure 6.4 HR0 Register and HR1 Register
Rev.1.20 Jan 27, 2006 page 33 of 204
REJ09B0062-0120
Page 45
R8C/11 Group
X
X
E
k
O
X
X
RdCINC
g
The following describes the clocks generated by the clock generation circuit.
6.1 Main Clock
This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU
and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator
between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor, which is
disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally
generated clock to the XIN pin. Figure 6.5 shows examples of main clock connection circuit.
During reset and after reset, the main clock is turned off.
The main clock starts oscillating when the CM05 bit in the CM0 register is set to “0” (main clock on) after
setting the CM13 bit in the CM1 register to “1” (XIN- XOUT pin).
To use the main clock for the CPU clock, set the OCD2 bit in the OCD register to “0” (selecting main clock)
after the main clock becomes oscillating stably.
The power consumption can be reduced by setting the CM05 bit in the CM0 register to “1” (main clock off)
if the OCD2 bit is set to “1” (selecting on-chip oscillator clock).
Note that if an externally generated clock is fed into the XIN pin, the main clock cannot be turned off by
setting the CM05 bit to “1”. If necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to Section 6.4, “Power Control.”
6.1 Main Clock
Microcomputer
(Built-in feedback resistor)
I N
t h e i n s t r u c t i o n
N O T E S :
1 .I n s e r t a d a m p i n g r e s i s t o r i f r e q u i r e d . T h e r e s i s t a n c e w i l l v a r y d e p e n d i n g o n t h e o s c i l l a t o r a n d t h e o s c i l l a t i o n d r i v e
c a p a c i t y s e t t i n g . U s e t h e v a l u e r e c o m m e n d e d b y t h e m a k e r o f t h e o s c i l l a t o r .
W h e n t h e o s c i l l a t i o n d r i v e c a p a c i t y i s s e t t o l o w , c h e c k t h a t o s c i l l a t i o n i s s t a b l e . A l s o , i f t h e o s c i l l a t o r m a n u f a c t u r e r ' s
d a t a s h e e t s p e c i f i e s t h a t a f e e d b a c k r e s i s t o r b e a d d e d e x t e r n a l t o t h e c h i p , i n s e r t a f e e d b a c k r e s i s t o r b e t w e e n X
O U T
a n d X
f o l l o w i n
O U T
(Note 1)
O U T
.
Figure 6.5 Examples of Main Clock Connection Circuit
Microcomputer
(Built-in feedback resistor)
I N
x t e r n a l l y d e r i v e d c l o c
Vcc
V s s
OUT
p e
n
I N
Rev.1.20 Jan 27, 2006 page 34 of 204
REJ09B0062-0120
Page 46
R8C/11 Group
6.2 On-chip Oscillator Clock
6.2 On-chip Oscillator Clock
This clock is supplied by an on-chip oscillator. There are two kinds of on-chip oscillator: high-speed onchip oscillator and low-speed on-chip oscillator. These oscillators are selected by the bit HR01 bit in the
HR0 register.
6.2.1 Low-Speed On-Chip Oscillator Clock
The clock derived from the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fRING, fRING128 and fRING-S.
After reset, the on-chip oscillator clock derived from low-speed on-chip oscillator by divided by 8 is
selected for the CPU clock.
If the main clock stops oscillating when the OCD1 to OCD0 bits in the OCD register are “112” (oscillation stop detection function enabled), the low-speed on-chip oscillator automatically starts operating,
supplying the necessary clock for the microcomputer.
The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the
operation ambient temperature. The application products must be designed with sufficient margin for
the frequency change.
6.2.2 High-Speed On-Chip Oscillator Clock
The clock derived from high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fRING, fRING128, and fRING1-fast.
After reset, the on-chip oscillator clock derived from high-speed on-chip oscillator is halted. The oscillation is started by setting the HR00 bit in the HR0 register to “1” (high-speed on-chip oscillator on).
The frequency can be adjusted by the HR1 register.
The relationship between the value of HR1 register and the period of high-speed on-chip oscillator is
shown below. It is noted that the difference in delay between the bits should be adjusted by changing
each bit. Bit 7 should be set be “0”.
Period of high-speed on-chip oscillator = td(HR offset) + (64 5 b6 + 32 5 b5 + 16 5 b4 + 8 5 b3 + 4
✕ b2 + 2 ✕ b1 + b0)
b0 to b6 : Bits in HR1 register
Rev.1.20 Jan 27, 2006 page 35 of 204
REJ09B0062-0120
Page 47
R8C/11 Group
6.3 CPU Clock and Peripheral Function Clock
6.3 CPU Clock and Peripheral Function Clock
There are two types of clocks: CPU clock to operate the CPU and peripheral function clock to operate the
peripheral functions. Also refer to “Figure 6.1 Clock Generation Circuit”.
6.3.1 CPU Clock
This is an operating clock for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock or on-chip oscillator clock.
The selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use
the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to select the divideby-n value.
After reset, the low-speed on-chip oscillator clock divided by 8 provides the CPU clock.
Note that when entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divideby-8 mode).
6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO, fRING, fRING128)
These are operating clocks for the peripheral functions.
Of these, fi (i=1, 2, 8, 32) is derived from the main clock or on-chip oscillator clock by dividing them by
i. The clock fi is used for timers X, Y, Z and C.
The clock fjSIO (j=1, 8, 32) is derived from the main clock or on-chip oscillator clock by dividing them by
j. The clock fjSIO is used for serial interface.
The fAD clock is produced from the main clock or the on-chip oscillator clock and is used for the A/D
converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral
function clock turned off during wait mode), the clocks fi, fjSIO, and fAD are turned off.
6.3.3 fRING and fRING128
These are operating clocks for the peripheral functions.
The fRING runs at the same frequency as the on-chip oscillator, and can be used as the souce for the
timer Y. The fRING128 is derived from the fRING by dividing it by 128, and can be used for Timer C.
When the WAIT instruction is executed, the clocks fRING and fRING128 are not turned off.
6.3.4 fRING-fast
This is used as the count source for the timer C. The fRING-fast is derived from the high-speed on-chip
oscillator and provided by setting the HR00 bit to “1” (high-speed on-chip oscillator on).
When the WAIT instruction is executed, the clock fRING-fast is not turned off.
Rev.1.20 Jan 27, 2006 page 36 of 204
REJ09B0062-0120
Page 48
R8C/11 Group
6.4 Power Control
6.4 Power Control
There are three power control modes. All modes other than wait and stop modes are referred to as
normal operation mode.
6.4.1 Normal Operation Mode
Normal operation mode is further classified into four modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU
clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower
the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator
circuits are turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which
switched must be oscillating stably. If the new clock source is the main clock, allow a sufficient wait
time in a program until it becomes oscillating stably.
• High-speed Mode
The main clock divided by 1 (undivided) provides the CPU clock. If the CM14 bit is set to “0” (lowspeed on-chip oscillator on) or the HR00 bit in the HR0 register is set to “1” (high-speed on-chip
oscillator on), the f
fRING-fast can be used for timer C.
• Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the CM14 bit is set to “0” (lowspeed on-chip oscillator on) or the HR00 bit in the HR0 register is set to “1” (high-speed on-chip
oscillator on), the fRING and fRING128 can be used for timers Y and C. When the HR00 bit is set to “1”,
fRING-fast can be used for timer C.
• High-speed, Low-speed, On-Chip Oscillator Mode
The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The onchip oscillator clock is also the clock source for the peripheral function clocks. When the HR00 bit is
set to “1”, fRING-fast can be used for timer C.
RING and fRING128 can be used for timers Y and C. When the HR00 bit is set to “1”,
Rev.1.20 Jan 27, 2006 page 37 of 204
REJ09B0062-0120
Page 49
R8C/11 Group
(
)
6.4 Power Control
Table 6.2 Setting Clock Related Bit and Modes
M o d e s
O C D r e g i s t e r
OCD2
H i g h - s p e e d m o d e 0002 00
M e d i u m -
s p e e d
m o d e
H i g h - s p e e d ,
l o w - s p e e d
o n - c h i p
o s c i l l a t o r
1
m o d e
d i v i d e d b y 2
d i v i d e d b y 4
d i v i d e d b y 8
d i v i d e d b y 1 6
n o d i v i s i o n
d i v i d e d b y 2
d i v i d e d b y 4
d i v i d e d b y 8
d i v i d e d b y 1 6
0012 00
0102 00
010
0112 00
1002 00
1012 00
110
110
111
CM1 register
C M 1 7 , C M 1 6
2 00
2 00
C M 1 3
1
1
1
1
1
C M 0 r e g i s t e r
C M 0 6C M 0 5
o r
o r
o r
o r
o r
1
1
1
1
1
N O T E S :
1 . T h e l o w - s p e e d o n - c h i p o s c i l l a t o r i s u s e d a s t h e o n - c h i p o s c i l l a t o r c l o c k w h e n t h e C M 1 r e g i s t e r C M 1 4 b i t = 0
( l o w - s p e e d o n - c h i p o s c i l l a t o r o n ) a n d H R 0 r e g i s t e r H R 0 1 b i t = 0 ( l o w - s p e e d o n - c h i p o s c i l l a t o r s e l e c t e d ) .
T h e h i g h - s p e e d o n - c h i p o s c i l l a t o r i s u s e d a s t h e o n - c h i p o s c i l l a t o r c l o c k w h e n t h e H R 0 r e g i s t e r H R 0 0 b i t = 1
( h i g h - s p e e d o n - c h i p o s c i l l a t o r o n ) a n d H R 0 1 b i t = 1 ( h i g h - s p e e d o n - c h i p o s c i l l a t o r s e l e c t e d ) .
Rev.1.20 Jan 27, 2006 page 38 of 204
REJ09B0062-0120
Page 50
R8C/11 Group
6.4.2 Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU and the watchdog timer because both are
operated by the CPU clock. Because the main clock and on-chip oscillator clock both are on, the
peripheral functions using these clocks keep operating.
• Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,
f8SIO, f32SIO, and fAD clocks are turned off when in wait mode, with the power consumption reduced
that much.
• Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
• Pin Status During Wait Mode
The status before wait mode is retained.
• Exiting Wait Mode
The microcomputer is moved out of wait mode by a hardware reset or peripheral function interrupt.
When using a hardware reset to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function
interrupts to “0002” (interrupts disabled) before executing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait
mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral
functions using the peripheral function clocks stop operating, so that only the peripheral functions
clocked by external signals can be used to exit from wait mode.
Table 6. 3 lists the interrupts to exit wait mode and the usage conditions.
When using a peripheral function interrupt to exit wait mode, set up the following before executing
the WAIT instruction.
1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the
peripheral function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt sequence is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.
Table 6.3 Interrupts to Exit Wait Mode and Usage Conditions
Interrupt CM02=0 CM02=1
Serial interface interrupt
Key input interrupt
A/D conversion interrupt Can be used in one-shot mode
Timer X interrupt Can be used in all modes
Timer Y interrupt
Timer Z interrupt
Timer C interrupt
INT interrupt
Voltage detection interrupt Can be used
Oscillation stop detection
interrupt
Can be used when operating with internal
or external clock
Can be used
Can be used in all modes
Can be used in all modes
Can be used in all modes
Can be used
Can be used
Can be used when operating with external clock
Can be used
(Do not use)
Can be used in event counter mode
Can be used when counting inputs from CNTR1 pin
in timer mode
(Do not use)
(Do not use)
Can be used (INT0 and INT3 can be used if there
is no filter.
Can be used
(Do not use)
6.4 Power Control
Rev.1.20 Jan 27, 2006 page 39 of 204
REJ09B0062-0120
Page 51
R8C/11 Group
6.4.3 Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function
clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The
least amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the
internal RAM is retained.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
TCC13 bit in the TCC1 register is set to “1”))
• Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit of CM10 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the OCD1 to OCD0 bits to “002” (oscillation stop detection function
disable).
• Pin Status in Stop Mode
The status before wait mode is retained.
However, the XOUT(P47) pin is held “H” when the CM13 bit in the CM1 register is set to “1” (XIN-XOUT
pin). The P47(XOUT) is in input state when the CM13 bit is set to “0” (input port P46, P47).
• Exiting Stop Mode
The microcomputer is moved out of stop mode by a hardware reset or peripheral function interrupt.
When using a hardware reset to exit stop mode, set the ILVL2 to ILVL0 bits for the peripheral function
interrupts to “0002” (interrupts disabled) before setting the CM10 bit to “1”.
When using a peripheral function interrupt to exit stop mode, set up the following before setting the
CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
6.4 Power Control
• Key interrupt
______ ______ ______
• INT0 to INT2 interrupts (INT0 can be used only when there is no filter.)
• INT3 interrupt (INT3 can be used when there is no filter and Timer C output compare mode (the
• Timer X interrupt (when counting external pulses in event counter mode)
• Timer Y interrupt (when counting inputs from CNTR1 pin in timer mode)
• Serial interface interrupt (when external clock is selected)
• Voltage detection interrupt
peripheral function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt sequence is executed.
The main clock divided by 8 of the clock which is used right before stop mode is used for the CPU
clock when exiting stop mode by a peripheral function interrupt.
Rev.1.20 Jan 27, 2006 page 40 of 204
REJ09B0062-0120
Page 52
R8C/11 Group
Figure 6.6 shows the state transition of power control.
High-speed Mode,
Middle-speed mode
OCD2=0
CM05=0
CM13=1
01
, HR
0
1
14=
D2=
C
CM
O
HR00=1, HR01=1,
OCD2=1
CM13=1, CM05=0,
OCD2=0
Low-speed On-chip
Oscillator Mode
OCD2=1
0
5=0,
0
HR01=0
CM14=0
=0
M
C
,
3=1, CM
1
CD2=
O
Reset
CM14=0, HR01=0
HR00=1, HR01=1
6.4 Power Control
There are six power control modes.
(1) High-speed mode
(2) Middle-speed mode
(3) High-speed on-chip oscillator mode
(4) Low-speed on-chip oscillator mode
(5) Wait mode
(6) Stop mode
High-speed On-chip
Oscillator Mode
OCD2=1
HR01=1
HR00=1
Interrupt
Wait Mode
WAIT Instruction
Interrupt
Stop Mode
Figure 6.6 State Transition of Power Control
CM05: Bit in CM0 register
CM10, CM13, CM14: Bit in CM1 register
OCD2: Bit in OCD register
HR00, HR01: Bit in HR0 register
CM10=1
(All clocks stop)
Rev.1.20 Jan 27, 2006 page 41 of 204
REJ09B0062-0120
Page 53
R8C/11 Group
6.5 Oscillation Stop Detection Function
6.5 Oscillation Stop Detection Function
The oscillation stop detection function is such that main clock oscillation circuit stop is detected. The
oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD
register.
Table 6.4 lists the specifications of the oscillation stop detection function.
Where the main clock corresponds to the CPU clock source and the OCD1 to OCD0 bits are “112”
(oscillation stop detection function enabled), the system is placed in the following state if the main clock
comes to a halt:
• OCD register OCD2 bit = 1 (selecting on-chip oscillator clock)
• OCD register OCD3 bit = 1 (main clock stopped)
• CM1 register CM14 bit = 0 (low-speed on-chip oscillator oscillating)
• Oscillation stop detection interrupt request occurs
Table 6.4 Oscillation Stop Detection Function Specifications
Item Specification
Oscillation stop detectable clock and f(XIN) ≥ 2 MHz
frequency bandwidth
Enabling condition for oscillation stop Set OCD1 to OCD0 bits to “112” (oscillation stop detection
detection function function enabled)
Operation at oscillation stop detection Oscillation stop detection interrupt occurs
6.5.1 How to Use Oscillation Stop Detection Function
• The oscillation stop detection interrupt shares the vector with the watchdog timer interrupt. If the
oscillation stop detection and watchdog timer interrupts both are used, the interrupt factor must be
determined. Table 6.5 shows how to determine the interrupt factor with the oscillation stop detection
interrupt, watchdog timer interrupt and voltage detection interrupt.
• Where the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and
peripheral functions must be switched to the main clock in the program.
Figure 6.7 shows the procedure for switching the clock source from the low-speed on-chip oscillator
to the main clock.
• To enter wait mode while using the oscillation stop detection function, set the CM02 bit to “0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop detection function is provided in preparation for main clock stop due to
external factors, set the OCD1 to OCD0 bits to “002” (oscillation stop detection function disabled)
where the main clock is stopped or oscillated in the program, that is where the stop mode is selected
or the CM05 bit is altered.
• This function cannot be used when the main clock frequency is below 2 MHz. Set the OCD1 to OCD0
bits to “002” (oscillation stop detection function disabled).
• When using the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral
functions after detecting the oscillation stop, set the HR01 bit in the HR0 register to “0” (low-speed
on-chip oscillator selected) and the OCD1 to OCD0 bits to “112” (oscillation stop detection function
enabled). When using the high-speed on-chip oscillator clock for the CPU clock and clock sources of
peripheral functions after detecting the oscillation stop, set the HR01 bit to “1” (high-speed on-chip
oscillator selected) and the OCD1 to OCD0 bits to “112” (oscillation stop detection function enabled).
Rev.1.20 Jan 27, 2006 page 42 of 204
REJ09B0062-0120
Page 54
R8C/11 Group
Rev.1.20 Jan 27, 2006 page 43 of 204
REJ09B0062-0120
Page 55
R8C/11 Group
7
0
W
W
W
0
0
W
W
W
7. Protection
In the event that a program runs out of control, this function protects the important registers so that they
will not be rewritten easily. Figure 7.1 shows the PRCR register. The following lists the registers protected
by the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1, and OCD, HR0, HR1 registers
• Registers protected by PRC1 bit: PM0 and PM1 registers
• Registers protected by PRC2 bit: PD0 register
• Registers protected by PRC3 bit: VCR2 and D4INT registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts will occur between the instruction in which the PRC2
bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automatically set to “0”
by writing to any address. They can only be set to “0” in a program.
7. Protection
P r o t e c t r e g i s t e r
b
b 6b 5b 4b3b 2b 1b
d d r e s
f t e r r e s e
0 0
S y m b o lA
P R C R0
Bit nameB i t s y m b o l
P R C 0
P R C 1
P R C 2
( b 5 - b 4 )
Protect bit 0
Protect bit 1
P r o t e c t b i t 2
P r o t e c t b i t 3
R e s e r v e d b i t When write, should set to “0”
sA
A
1 6
t
0 0 X X X 0 0 0
2
Function
Enable write to CM0, CM1, OCD,
HR0, HR1 registers
0 : Write protected
1 : Write enabled
Enable write to PM0, PM1
registers
0 : Write protected
1 : Write enabled
E n a b l e w r i t e t o P D 0 r e g i s t e r
0 : W r i t e p r o t e c t e d
1 : W r i t e e n a b l e d
E n a b l e w r i t e t o V C R 2 , D 4 I N T
r e g i s t e r sP R C 3
0 : W r i t e p r o t e c t e d
1 : W r i t e e n a b l e d
1
R
R
R
R
R
R
(b7-b6)
R e s e r v e d b i t
When read, its content is “0”.
RO
N O T E S :
1 . T h e P R C 2 b i t i s s e t t o “ 0 ” b y w r i t i n g t o a n y a d d r e s s a f t e r s e t t i n g i t t o “ 1 ” . O t h e r b i t s a r e n o t s e t t o “ 0 ”
b y w r i t i n g t o a n y a d d r e s s , a n d m u s t t h e r e f o r e b e s e t t o “ 0 ” i n a p r o g r a m .
Figure 7.1 PRCR Register
Rev.1.20 Jan 27, 2006 page 44 of 204
REJ09B0062-0120
Page 56
R8C/11 Group 8. Processor Mode
W
W
W
g
W
W
W
0
0
W
8. Processor Mode
8.1 Types of Processor Mode
The processor mode is single-chip mode. Table 8.1 shows the features of the processor mode. Figure
8.1 shows the PM0 and PM1 register.
Table 8.1 Features of Processor Mode
Processor mode
Single-chip mode SFR, internal RAM, internal ROM
Access space Pins which are assigned I/O ports
All pins are I/O ports or peripheral
function I/O pins
P r o c e s s o r m o d e r e g i s t e r 0
b 7b6b 5b4b 3b2b 1b0
00
0
( b 2 - b 0 )
P M 0 3
( b 7 - b 4 )
i s t e r t o " 1 " ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r
N O T E S :
1 . S e t t h e P R C 1 b i t i n t h e P R C R r e
P r o c e s s o r m o d e r e g i s t e r 1
b7 b 6b 5b4b 3b 2b 1b 0
0
( b 1 - b 0 )
(1 )
Symbol Address After reset
PM0 0004
16
00
16
B i t n a m e FunctionB i t s y m b o l
Reserved bit
S o f t w a r e r e s e t b i t
N o t h i n g i s a s s i g n e d . W h e n w r i t e , s e t t o “ 0 ” . W h e n r e a d , i t s
c o n t e n t i s " 0 " .
(1 )
d d r e s
f t e r r e s e
0 0
S y m b o lA
P M 10
sA
5
1 6
M u s t s e t t o “ 0 ”
S e t t i n g t h i s b i t t o “ 1 ” r e s e t s t h e
m i c r o c o m p u t e r . W h e n r e a d , i t s
c o n t e n t i s “ 0 ” .
t
0 0
1 6
B i t n a m e FunctionB i t s y m b o l
R e s e r v e d b i t
S e t t o “ 0 ”
R
R
R
.
R
R
PM12
( b 6 - b 3 )
(b7)
N O T E S :
1 . S e t t h e P R C 1 b i t i n t h e P R C R r e g i s t e r t o " 1 " ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r .
2 . P M 1 2 b i t i s s e t t o “ 1 ” b y w r i t i n g a “ 1 ” i n a p r o g r a m . ( W r i t i n g a “ 0 ” h a s n o e f f e c t . )
W D T i n t e r r u p t / r e s e t
s w i t c h b i t
Nothing is assigned. When write, set to “0”. When read, its
content is "0".
R e s e r v e d b i t
0 : W a t c h d o g t i m e r i n t e r r u p t
1 : W a t c h d o g t i m e r r e s e t
S e t t o “ 0 ”
(2 )
R
R
Figure 8.1 PM0 Register and PM1 Register
Rev.1.20 Jan 27, 2006 page 45 of 204
REJ09B0062-0120
Page 57
9. Bus
During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for
access space.
The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16
bits) units, these spaces are accessed twice in 8-bit units. Table 9.2 shows bus cycles in each access
space.
Table 9.1 Bus Cycles for Access Space
Access space Bus cycle
SFR/Data flash 2 CPU clock cycles
Program ROM/RAM 1 CPU clock cycles
9. BusR8C/11 Group
Table 9.2 Access Unit and Bus Operation
Space
Even address
byte access
CPU clock
Address
SFR, Data flash
Even
Data
Odd address
byte access
CPU clock
Address
Odd
Data
Even address
word access
Odd address
word access
CPU clock
Address
Data
CPU clock
Address
Even
Data
Odd Odd+1 Odd Odd+1
Data
Data
Even+1
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Program ROM/RAM
Even
Data
Odd
Data
Even
Data
Even+1
Data
Data
Rev.1.20 Jan 27, 2006 page 46 of 204
REJ09B0062-0120
Data
Data
Data
Data
Data
Page 58
R8C/11 Group
10. Interrupt
10.1 Interrupt Overview
10.1.1 Type of Interrupts
Figure 10.1 shows types of interrupts.
Software
(Non-maskable interrupt)
Interrupt
Hardware
Special
(Non-maskable interrupt)
Peripheral function
(Maskable interrupt)
(1)
10.1 Interrupt Overview
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Watchdog timer
Oscillation stop detection
Voltage detection
Single step
Address match
(2)
NOTES:
1. Peripheral function interrupts are generated by the peripheral functions built in the microcomputer system.
2. Avoid using this interrupt because this is a dedicated interrupt for development support tools only.
Figure 10.1 Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Rev.1.20 Jan 27, 2006 page 47 of 204
REJ09B0062-0120
Page 59
R8C/11 Group
10.1.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are nonmaskable interrupts.
• Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the
operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt numbers 0
to 63 can be specified for the INT instruction. Because software interrupt numbers 4 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction.
In software interrupt numbers 0 to 31, the U flag is saved to the stack during instruction execution
and is cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored
from the stack when returning from the interrupt routine. In software interrupt numbers 32 to 63, the
U flag does not change state during instruction execution, and the SP then selected is used.
10.1 Interrupt Overview
Rev.1.20 Jan 27, 2006 page 48 of 204
REJ09B0062-0120
Page 60
R8C/11 Group
10.1.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
(1) Special Interrupts
Special interrupts are non-maskable interrupts.
• Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to Chapter 11, “Watchdog Timer.”
• Oscillation Stop Detection Interrupt
Generated by the oscillation stop detection function. For details about the oscillation stop detection
function, refer to Chapter 6, “Clock Generation Circuit.”
• Voltage Detection Interrupt
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to
Section 5.4, “Voltage Detection Circuit.”
• Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 to RMAD1 register that corresponds to one of the AIER register's AIER0 or
AIER1 bit which is "1" (address match interrupt enabled). For details about the address match interrupt, refer to Section 10.4, “Address Match Interrupt.”
10.1 Interrupt Overview
(2) Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt factors for peripheral function interrupts are listed in Table 10.2.
“Relocatable Vector Tables”. For details about the peripheral functions, refer to the description of
each peripheral function in this manual.
Rev.1.20 Jan 27, 2006 page 49 of 204
REJ09B0062-0120
Page 61
R8C/11 Group
10.1.4 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in
the corresponding interrupt vector. Figure 10.2 shows the interrupt vector.
10.1 Interrupt Overview
Vector address (L)
Vector address (H)
MSB
Low address
Mid address
0 0 0 0 High address
0 0 0 0 0 0 0 0
LSB
Figure 10.2 Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from 0FFDC16 to 0FFFF16. Table 10.1 lists
the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of
fixed vectors are used by the ID code check function. For details, refer to Section 17.3, “Functions to
Prevent Flash Memory from Rewriting.”
Table 10.1 Fixed Vector Tables
Interrupt factor Vector addresses Remarks Reference
Address (L) to address (H)
Undefined instruction 0FFDC16 to 0FFDF16 Interrupt on UND instruction R8C/Tiny series
Overflow 0FFE016 to 0FFE316 Interrupt on INTO instruction software manual
BRK instruction 0FFE416 to 0FFE716
If the contents of address
0FFE716 is FF16, program execution starts from the address
shown by the vector in the
relocatable vector table.
Address match 0FFE816 to 0FFEB16
18.1 Address match
interrupt
Single step
(1)
0FFEC16 to 0FFEF16
• Watchdog timer 0FFF016 to 0FFF316 11. Watchdog timer
• Oscillation stop
detection
• Voltage detection 5.4
6.
Clock generation
circuit
Voltage detection
circuit
(Reserved) 0FFF416 to 0FFF716
(Reserved) 0FFF816 to 0FFFB16
Reset 0FFFC16 to 0FFFF16 5. Reset
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development support tools.
Rev.1.20 Jan 27, 2006 page 50 of 204
REJ09B0062-0120
Page 62
R8C/11 Group
r
p
• Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable
vector table area. Table 10.2 lists interrupts and vector tables located in the relocatable vector table.
Table 10.2 Vector Tables
10.1 Interrupt Overview
I n t e r r u p t f a c t o
A d d r e s s ( L ) t o a d d r e s s ( H )
t o 0 0 0
B R K i n s t r u c t i o n
(2 )
+ 0 t o + 3 ( 0 0 0 0
(Reserved)
t o 0 0 3
K e y i n p u t
A / D C o n v e r s i o n
+ 5 2 t o + 5 5 ( 0 0 3 4
t o 0 0 3
+ 5 6 t o + 5 9 ( 0 0 3 8
( R e s e r v e d )
C o m p a r e 1
UART0 transmit
U A R T 0 r e c e i v e
U A R T 1 t r a n s m i t
UART1 receive
I N T 2
Timer X
Timer Y
Timer Z
INT1
I N T 3
T i m e r C
C o m p a r e 0
INT0
+64 to +67 (0040
t o 0 0 4
+ 6 8 t o + 7 1 ( 0 0 4 41
+72 to +75 (0048
t o 0 0 4
+ 7 6 t o + 7 9 ( 0 0 4 C
t o 0 0 5
+ 8 0 t o + 8 3 ( 0 0 5 0
+84 to +87 (005416 to 005716)
+88 to +91 (0058
+92 to +95 (005C
t o 0 0 6
+ 9 6 t o + 9 9 ( 0 0 6 01
t o 0 0 6
+ 1 0 0 t o + 1 0 3 ( 0 0 6 4
t o 0 0 6
+ 1 0 4 t o + 1 0 7 ( 0 0 6 8
+108 to +111 (006C
t o 0 0 7
+ 1 1 2 t o + 1 1 5 ( 0 0 7 0
+116 to +119 (0074
(Reserved)
(Reserved)
t o 0 0 8
S o f t w a r e i n t e r r u p t
(2 )
+ 1 2 8 t o + 1 3 1 ( 0 0 8 0
t o 0 0 F
+ 2 5 2 t o + 2 5 5 ( 0 0 F C
NOTES:
1. Address relative to address in INTB.
2. These interru
ts cannot be dis abled using the I flag.
V e c t o r a d d r e s s
1 6
1 6
1 6
16 to 004316)
6
16 to 004B16)
1 6
1 6
16 to 005B16)
16 to 005F16)
6
1 6
16 to 006F16)
1 6
16 to 007716)
1 6
to
1 6
1 6
(1 )
31
Software interrupt
6)
71
6)
B1
6)
71
6)
F1
6)
31
6)
31
6)
71
6)
B1
6)
31
6)
31
6)
F1
6)
number
0
1 t o 1 2
13
14
1 5
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
to
63
Reference
R 8 C / T i n y S e r i e s
s o f t w a r e m a n u a l
1 0 . 3 K e y i n p u t i n t e r r u p t
1 4 . A / D c o n v e r t e r
1 2 . 4 T i m e r C
1 3 . S e r i a l I n t e r f a c e
10.2.3 INT2 interrupt
1 2 . 1 T i m e r X
12.2 Timer Y
12.3 Timer Z
10.2.3 INT1 interrupt
1 0 . 2 . 4 I N T 3 i n t e r r u p t
1 2 . 4 T i m e r C
1 2 . 4 T i m e r C
1 0 . 2 . 1 I N T 0 i n t e r r u p t
R 8 C / T i n y S e r i e s
s o f t w a r e m a n u a l
Rev.1.20 Jan 27, 2006 page 51 of 204
REJ09B0062-0120
Page 63
R8C/11 Group
10.1.5 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in
which order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each
interrupt control register.
Figure 10.3 shows the interrupt control registers.
10.1 Interrupt Overview
Rev.1.20 Jan 27, 2006 page 52 of 204
REJ09B0062-0120
Page 64
R8C/11 Group
10.1 Interrupt Overview
I n t e r r u p t c o n t r o l r e g i s t e r
b 7b 6b 5b 4b 3b 2b 1b 0
( 2 )
d d r e s
f t e r r e s e t
0 4
0 5
0 5
0 4
0 5
0 5
0 5
0 5
0 5
0 5
0 5
0 5
0 5
S y m b o lA
K U P I C0
A D I C0
C M P 1 I C0
S 0 T I C , S 1 T I C0
S 0 R I C , S 1 R I C0
I N T 2 I C0
T X I C0
T Y I C0
T Z I C0
I N T 1 I C0
I N T 3 I C0
T C I C0
C M P 0 I C0
sA
D
1 6
E
1 6
0
1 6
1
1 6
, 0 0 5 3
1 6
, 0 0 5 4
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
2
5
6
7
8
9
A
B
C
Bit name F u n c t i o nB i t s y m b o l
I L V L 0
I L V L 1
I L V L 2
I R
( b 7 - b 4 )
I n t e r r u p t p r i o r i t y l e v e l
s e l e c t b i t
b2 b1 b0
0 0 0 : L e v e l 0 ( i n t e r r u p t d i s a b l e d )
0 0 1 : L e v e l 1
0 1 0 : L e v e l 2
0 1 1 : L e v e l 3
1 0 0 : L e v e l 4
1 0 1 : L e v e l 5
1 1 0 : L e v e l 6
1 1 1 : L e v e l 7
I n t e r r u p t r e q u e s t b i t
0 : I n t e r r u p t n o t r e q u e s t e d
1 : I n t e r r u p t r e q u e s t e d
Nothing is assigned.
When write, set to “0”. When read, its content is indeterminate.
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
X X X X X 0 0 0
2
2
2
2
2
2
2
2
2
2
2
2
2
R W
R W
R W
R W
(1)
RW
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol Address After reset
INT0IC 005D
16
Bit name FunctionBit symbol
ILVL0
I n t e r r u p t p r i o r i t y l e v e l
s e l e c t b i t
b2 b1 b0
0 0 0 : L e v e l 0 ( i n t e r r u p t d i s a b l e d )
XX00X000
2
RW
RW
0 0 1 : L e v e l 1
I L V L 1
0 1 0 : L e v e l 2
0 1 1 : L e v e l 3
1 0 0 : L e v e l 4
RW
1 0 1 : L e v e l 5
I L V L 2
IR
POL
( b 5 )
( b 7 - b 6 )
I n t e r r u p t r e q u e s t b i t
Polarity select bit
(3, 4)
Reserved bit
N o t h i n g i s a s s i g n e d .
W h e n w r i t e , s e t t o “ 0 ” . W h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e .
1 1 0 : L e v e l 6
1 1 1 : L e v e l 7
0 : I n t e r r u p t n o t r e q u e s t e d
1 : I n t e r r u p t r e q u e s t e d
0 : Selects falling edge
1 : Selects rising edge
Set to “0”
R W
R W
RW
RW
(1 )
NOTES:
1. Only "0" can be written to the IR bit. (Do not write "1").
2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
Refer to the paragraph 19.2.6 “Changing Interrupt Control Registers”.
3. If the INTOPL bit in the INTEN register is set to “1” (both edges), set the POL bit to "0 " (selecting falling edge).
4. The IR bit may be set to “1” (interrupt requested) when the POL bit is rewritten. Refer to the paragraph 19.2.5
“Changing Interrupt Factor” .
Figure 10.3 Interrupt Control Registers
Rev.1.20 Jan 27, 2006 page 53 of 204
REJ09B0062-0120
Page 65
R8C/11 Group
• I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the
maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
• IR Bit
The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit
is cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
• ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 10.3 shows the settings of interrupt priority levels and Table 10.4 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
10.1 Interrupt Overview
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect
one another.
Table 10.4 Interrupt Priority Levels Enabled
Table 10.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 bits
0002
0012
0102
0112
1002
1012
1102
1112
Interrupt priority
level
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Priority
order
Lowest
Highest
by IPL
IPL
000
2
0012
0102
0112
1002
1012
1102
1112
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Enabled interrupt priority levels
Rev.1.20 Jan 27, 2006 page 54 of 204
REJ09B0062-0120
Page 66
R8C/11 Group
• Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted
to the instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when
the execution of the instruction is completed, and transfers control to the interrupt sequence from the
next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA
instruction, the processor temporarily suspends the instruction being executed, and transfers control
to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 10.4 shows time required for executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by read-
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU internal
(3) The I, D and U flags in the FLG register become as follows:
(4) The CPU’s internal temporary register
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
10.1 Interrupt Overview
ing the address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt
not requested).
temporary register
(1)
.
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt numbers 32 to
63 is executed.
(1)
is saved to the stack.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
NOTES:
1. This register cannot be used by user.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CPU clock
Address bus
Data bus
RD
WR
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready
to accept instructions.
Address
0000
16
Interrupt
information
Indeterminate
Indeterminate
Indeterminate
SP-2 SP-4
SP-1 SP-3
SP-2
contents
SP-1
contents
contents
SP-4
SP-3
contents
VEC
VEC
contents
VEC+1
VEC+1
contents
VEC+2
VEC+2
contents
Figure 10.4 Time Required for Executing Interrupt Sequence
19
20
PC
Rev.1.20 Jan 27, 2006 page 55 of 204
REJ09B0062-0120
Page 67
R8C/11 Group
• Interrupt Response Time
Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed (see #a in Figure 10.5) and a time during
which the interrupt sequence is executed (20 cycles, see #b in Figure 10.5).
10.1 Interrupt Overview
Interrupt request acknowledgedInterrupt request generated
Time
Instruction Interrupt sequence
(a) 20 cycles (b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) 21 cycles for address match and single-step interrupts.
Figure 10.5 Interrupt Response Time
• Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is
set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels
listed in Table 10.5 is set in the IPL. Shown in Table 10.5 are the IPL values of software and special
interrupts when they are accepted.
Instruction in
interrupt routine
Table 10.5 IPL Level That Is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt factor
Watchdog timer, oscillation stop detection, voltage detection
Software, address match, single-step
Rev.1.20 Jan 27, 2006 page 56 of 204
REJ09B0062-0120
Level that is set to IPL
7
Not changed
Page 68
R8C/11 Group
k
L
• Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits in the PC are saved.
Figure 10.6 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine.
The PUSHM instruction can save several registers in the register bank being currently used
a single instruction.
NOTES:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
10.1 Interrupt Overview
(1)
with
Address
MSB LSB
m – 4
m – 3
m – 2
m – 1
m
m + 1
Stack
Content of previous stack
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
SPvalue before
interrupt occurs
Address
MSB LSB
m – 4
m – 3
m – 2
m – 1
m
m + 1
Stack status after interrupt request
is acknowledged
Stack
L
PC
PC
M
FLG
L
FLG
H
Content of previous stack
Content of previous stack
PC
H
[SP]
New SP value
Figure 10.6 Stack Status Before and After Acceptance of Interrupt Request
The registers are saved in four steps, 8 bits at a time. Figure 10.7 shows the operation of the saving
registers.
NOTES:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U flag. Otherwise, it is the ISP.
A d d r e s s
S t a c
S e q u e n c e i n w h i c h o r d e r
r e g i s t e r s a r e s a v e d
[ S P ] – 5
[ S P ] – 4
[ S P ] – 3
[ S P ] – 2
[ S P ] – 1
[ S P ]
N O T E S :
1 .[ S P ] d e n o t e s t h e i n i t i a l v a l u e o f t h e S P w h e n i n t e r r u p t r e q u e s t i s a c k n o w l e d g e d .
A f t e r r e g i s t e r s a r e s a v e d , t h e S P c o n t e n t i s [ S P ] m i n u s 4 .
P C
P CM
F L GL
F L GH P CH
( 3 )
( 4 )
S a v e d , 8 b i t s a t a t i m e
( 1 )
( 2 )
F i n i s h e d s a v i n g r e g i s t e r s
i n f o u r o p e r a t i o n s .
Figure 10.7 Operation of Saving Register
Rev.1.20 Jan 27, 2006 page 57 of 204
REJ09B0062-0120
Page 69
R8C/11 Group
• Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt
routine. Thereafter the CPU returns to the program which was being executed before accepting the
interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
• Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request
that has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the
ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their
interrupt priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 10.8
shows the Hardware Interrupt Priority.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control
branches invariably to the interrupt routine.
10.1 Interrupt Overview
Reset > WDT/Oscillation stop detection/Voltage detection > Peripheral function > Single step > Address match
Figure 10.8 Hardware Interrupt Priority
Rev.1.20 Jan 27, 2006 page 58 of 204
REJ09B0062-0120
Page 70
R8C/11 Group
p
t
L
X
Y
• Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among
those requested.
Figure 10.9 shows the Interrupts Priority Select Circuit.
10.1 Interrupt Overview
P r i o r i t y l e v e l o f e a c h i n t e r r u p t
Compare 0
I N T 3
Timer Z
T i m e r
INT0
Timer C
I N T 1
Timer
UART1 reception
U A R T 0 r e c e p t i o n
Compare 1
A/D conversion
L e v e l 0 ( d e f a u l t v a l u e )
H i g h e s t
P r i o r i t y o f p e r i p h e r a l f u n c t i o n i n t e r r u p t s
( i f p r i o r i t y l e v e l s a r e s a m e )
I N T 2
U A R T 1 t r a n s m i s s i o n
U A R T 0 t r a n s m i s s i o n
Key inpu
I P
I flag
A d d r e s s m a t c h
W a t c h d o g t i m e r
O s c i l l a t i o n s t o p d e t e c t i o n
V o l t a g e d e t e c t i o n
Figure 10.9 Interrupts Priority Select Circuit
Rev.1.20 Jan 27, 2006 page 59 of 204
REJ09B0062-0120
Lowest
Interrupt request level
resolution output signal
Interrupt
request
ted
acce
Page 71
R8C/11 Group
______
10.2 INT Interrupt
10.2.1 INT0 Interrupt
________
_______
INT0 interrupt is triggered by an INT0 input. When using INT0 interrupts, the INT0EN bit in the INTEN
register must be set to “1” (enabling). The edge polarity is selected using the INT0PL bit in the INTEN
register and the POL bit in the INT0IC register.
Inputs can be passed through a digital filter with three different sampling clocks.
_______
The INT0 pin is shared with the external trigger input pin of Timer Z.
Figure 10.10 shows the INTEN and INT0F registers.
E x t e r n a l i n p u t e n a b l e r e g i s t e r
b 7b 6b 5b4b 3b 2b 1b 0
0000
00
d d r e s
f t e r r e s e
0 0 9
S y m b o lA
I N T E N
sA
6
1 6
0 0
______
10.2 INT Interrupt
t
1 6
Bit symbol
I N T 0 E N
I N T 0 P L
I N T 0 i n p u t e n a b l e b i t
I N T 0 i n p u t p o l a r i t y s e l e c t b i t
Reserved bit
Bit name F u n c t i o n
(1 )
0 : D i s a b l e d
1 : E n a b l e d
(2 )
0 : O n e e d g e
1 : B o t h e d g e s
Set to “0”
( b 7 - b 2 )
NOTES:
1. This bit must be set while the INT0STG bit in the PUM register is set to “0” (one-shot trigger disabled).
2. When setting the INT0PL bit to “1” (selecting both edges), the POL bit in the INT0IC must be set to “0”
(selecting falling edge).
3. The IR bit in the INT0IC register may be set to “1” (interrupt requested) when the INT0PL bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.
I N T 0 i n p u t f i l t e r s e l e c t r e g i s t e r
b7 b6 b5 b4 b3 b2 b1 b0
0
d d r e s
f t e r r e s e
0 0 1
S y m b o lA
I N T 0 F
B i t s y m b o l
INT0F0
INT0 input filter select bit
Bit name F u n c t i o n
I N T 0 F 1
(b2)
sA
E
1 6
X X X X X 0 0 0
b 1 b 0
0 0 : N o f i l t e r
0 1 : F i l t e r w i t h f
1 0 : F i l t e r w i t h f
1 1 : F i l t e r w i t h f
Set to “0”Reserved bit
t
2
1
s a m p l i n g
8
s a m p l i n g
3 2
s a m p l i n g
R W
R W
R W
RW
RW
RW
RW
R W
( b 7 - b 3 )
Nothing is assigned.
When write, set to “0”. If read, it content is
Figure 10.10 INTEN Register and INT0F Register
Rev.1.20 Jan 27, 2006 page 60 of 204
REJ09B0062-0120
indeterminate.
Page 72
R8C/11 Group
Rev.1.20 Jan 27, 2006 page 61 of 204
REJ09B0062-0120
Page 73
R8C/11 Group
b
b
b
b
b
b
b
b
b7b
b
b
b
b2b
b
______
10.2 INT Interrupt
10.2.3 INT1 Interrupt and INT2 Interrupt
______ ______
______ ______
INT1 interrupts are triggered by INT1 inputs. The edge polarity is selected with the R0EDG bit in the
TXMR register. The INT1 pin is shared with the CNTR0 pin.
______ ______
INT2 interrupts are triggered by INT2 inputs. The edge polarity is selected with the R1EDG bit in the
TYZMR register. The INT2 pin is shared with the CNTR1 pin.
______
______
______ _____
Figure 10.13 shows the TXMR and TYZMR registers when using INT1 and INT2 interrupts.
T i m e r X m o d e r e g i s t e r
7
6
5
00
00
0
4
3
2
1
0
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T X M R0
B i t n a m e
T X M O D 0
T X M O D 1
R0EDG
T X S
TXOCNT
TXMOD2
TXEDG
O p e r a t i o n m o d e
s e l e c t b i t 0 , 1
0
I N T 1 / C N T R
s w i t c h i n g b i t
T i m e r X c o u n t
s t a r t f l a g
p o l a r i t y
(1 , 2 )
M u s t s e t t o " 0 " i n t i m e r m o d e
O p e r a t i o n m o d e
s e l e c t b i t 2
Must set to "0" in timer mode
sA
B
1 6
t
0 0
1 6
FunctionB i t s y m b o l
b1 b0
0 0 : T i m e r m o d e o r p u l s e p e r i o d
m e a s u r e m e n t m o d e
0 : Rising edge
1 : Falling edge
0 : Stops counting
1 : Starts counting
0 : O t h e r t h a n p u l s e p e r i o d m e a s u r e m e n t
(3 )
m o d e
(3 )
R W
R W
R W
RW
RW
RW
RW
RW
T X U N D
N O T E S :
1 . T h e I R b i t i n t h e I N T 1 I C m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e R 0 E D G b i t i s r e w r i t t e n . R e f e r t o t h e
p a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
2 . T h i s b i t i s u s e d t o s e l e c t t h e p o l a r i t y o f I N T 1 i n t e r r u p t i n t i m e r m o d e .
3 . W h e n u s i n g I N T 1 i n t e r r u p t s , s h o u l d s e l e c t t i m e r m o d e .
T i m e r Y , Z m o d e r e g i s t e r
6
5
4
3
1
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T Y Z M R0
0
T Y M O D 0
R 1 E D G
T Y W C
TYS
T Z M O D 0
Must set to "0" in timer mode
sA
0
1 6
Bit name
Timer Y operation
mode bit
I N T 2 / C N T R 1 p o l a r i t y
s w i t c h i n g b i t
Timer Y write
control bit
Timer Y count
start flag
(2 )
Timer Z-related bit
0 : T i m e r m o d e
0 : R i s i n g e d g e
1 : F a l l i n g e d g e
Function varies
depending on the operation mode
0 : S t o p s c o u n t i n g
1 : S t a r t s c o u n t i n g
t
0 0
1 6
F u n c t i o nB i t s y m b o l
(1 )
T Z M O D 1
T Z W C
T Z S
N O T E S :
1 . W h e n u s i n g I N T 2 i n t e r r u p t s , m u s t s e t t o t i m e r m o d e .
2 . T h e I R b i t i n t h e I N T 2 I C m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e R 1 E D G b i t i s r e w r i t t e n .
R e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
______ ______
RW
R W
R W
RW
R W
RW
RW
R W
R W
R W
Figure 10.13 TXMR Register and TYZMR Register when INT1 and INT2 Interrupt Used
Rev.1.20 Jan 27, 2006 page 62 of 204
REJ09B0062-0120
Page 74
R8C/11 Group
10.2.4 INT3 Interrupt
_____ ______
INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should be se to “0”
______ _______
(INT3). The INT3 input has a digital filter which can be sampled by one of three sampling clocks. The
sampling clock is selected using the TCC11 to TCC10 bits in the TCC1 register. The IR bit in the
INT3IC register is set to “1” (interrupt requested) when the sampled input level matches three times.
The P3_3 bit in the P3 register indicates the previous value before filtering regardless of values set in
the TCC11 to TCC10 bits.
The INT3 pin is shared with the TCIN pin.
When setting the TCC07 bit to “1” (fRING128), INT3 interrupts are triggered by fRING128 clock. The IR
bit in the INT3IC register is set to “1” (interrupt requested) every fRING128 clock cycle or every half
fRING128 clock cycle.
Figure 10.14 shows the TCC0 and TCC1 registers.
______
10.2 INT Interrupt
______
_______
_____
Rev.1.20 Jan 27, 2006 page 63 of 204
REJ09B0062-0120
Page 75
R8C/11 Group
b
b
b
b4b
b
b
b
b
b
b
b
b
b
b
b
______
10.2 INT Interrupt
T i m e r C c o n t r o l r e g i s t e r 0
7
6
5
0
0
3
2
1
d d r e s
f t e r r e s e
0 9
0
S y m b o lA
T C C 00
B i t n a m e
T C C 0 0
T C C 0 1
T C C 0 2
T C C 0 3
T C C 0 4
Timer C control bit
Timer C count source select
(1)
bit
INT3 interrupt and capture
polarity select bit
R e s e r v e d b i t
sA
A
1 6 0
0 : C o u n t s t o p
1 : C o u n t s t a r t
b 2 b 1
(1, 2)
t
01
6
F u n c t i o nBit symbol
I N
f a s
0 0 : f1
0 1 : f8
1 0 : f3
2
1 1 : fR
G-
b4 b3
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Avoid this setting
M u s t s e t t o " 0 "
t
( b 6 - b 5 )
TCC07
I N T 3 i n t e r r u p t / c a p t u r e i n p u t
s w i t c h i n g b i t
(1 , 2 )
0 : I N T 3
1 : f
R I N G 1 2 8
NOTES:
1. Change this bit when TCC00 bit is set to “0” (count stop).
2. The IR bit in the INT3IC may be set to “1” (interrupt requested) when the TCC03, TCC04, or TCC07 bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.
T i m e r C c o n t r o l r e g i s t e r 1
7
6
5
4
3
2
1
d d r e s
f t e r r e s e
0 9
0
S y m b o lA
T C C 10
sA
B
1 6
0 0
t
1 6
R W
R W
R W
R W
R W
R W
R W
R W
T C C 1 0
T C C 1 1
T C C 1 2
T C C 1 3
T C C 1 4
TCC15
TCC16
TCC17
Bit name
INT3 input filter select bit
Timer C counter reload
(2, 3)
select bit
Compare 0/Capture select
bit
C o m p a r e 0 o u t p u t m o d e
(3 )
s e l e c t b i t
Compare 1 output mode
(3)
select bit
FunctionB i t s y m b o l
b1 b0
(1)
0 0 : N o f i l t e r
0 1 : F i l t e r w i t h f
1 0 : F i l t e r w i t h f
1 1 : F i l t e r w i t h f
0: No reload (free-run)
1: Set TC register to “0000
compare 1 match
0: Capture
(input capture mode)
1: Compare 0 output
(output compare mode)
b 5 b 4
0 0: CMP output remains unchanged
even when compare 0 matched
0 1: CMP output is reversed when
compare 0 signal is matched
1 0: CMP output is set to low when
compare 0 signal is matched
1 1: CMP output is set to high when
compare 0 signal is matched
b7 b6
0 0: CMP output remains unchanged
even when compare 1 matched
0 1: CMP output is reversed when
compare 1 signal is matched
1 0: CMP output is set to low when
compare 1 signal is matched
1 1: CMP output is set to high when
compare 1 signal is matched
1
s a m p l i n g
8
s a m p l i n g
3 2
s a m p l i n g
R W
R W
R W
16
” at
(2)
R W
R W
R W
R W
N O T E S :
1 . I n p u t i s r e c o g n i z e d o n l y w h e n t h e s a m e v a l u e f r o m I N T 3 p i n i s s a m p l e d t h r e e t i m e s i n s u c c e s s i o n .
2 . M o d i f y t h e T C C 1 3 b i t w h e n t h e T C C 0 0 b i t i n t h e T C C 0 r e g i s t e r i s s e t t o “ 0 ” ( c o u n t s t o p s )
3 . S e t t h e T C C 1 2 , T C C 1 4 t o T C C 1 7 b i t s t o “ 0 ” w h e n t h e T C C 1 3 b i t i s s e t t o “ 0 ” ( i n p u t c a p t u r e m o d e ) .
Figure 10.14 TCC0 Register and TCC1 Register
Rev.1.20 Jan 27, 2006 page 64 of 204
REJ09B0062-0120
Page 76
R8C/11 Group
10.3 Key Input Interrupt
10.3 Key Input Interrupt
A key input interrupt is generated on an input edge of any of the K10 to K13 pins. Key input interrupts can
_____ _____
_____
be used as a key-on wakeup function to exit wait or stop mode. KIi input can be enabled or disabled
selecting with the KIiEN (i=0 to 3) bit in the KIEN register. The edge polarity can be rising edge or falling
_____
edge selecting with the KIiPL bit in the KIEN register. Note, however, that while input on any KIi pin which
has had the KIiPL bit set to “0” (falling edge) is pulled low, inputs on all other pins of the port are not
_____
detected as interrupts. Similarly, while input on any KIi pin which has had the KIiPL bit set to “1” (rising
edge) is pulled high, inputs on all other pins of the port are not detected as interrupts.
Figure 10.15 shows a block diagram of the key input interrupt.
PU02 bit in PUR0 register
Pull-up
transistor
KI
3
KI
2
KI
1
KI
0
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
PD1_3 bit in PD1 register
KI3PL=0
KI3PL=1
KI2PL=0
KI2PL=1
KI1PL=0
KI1PL=1
KI0PL=0
KI0PL=1
KI3EN bit
PD1_3 bit
KI2EN bit
PD1_2 bit
KI1EN bit
PD1_1 bit
KI0EN bit
PD1_0 bit
KUPIC register
Interrupt control circuit
KI0EN, KI1EN, KI2EN, KI3EN,
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
Key input interrupt
request
Figure 10.15 Key Input Interrupt
K e y i n p u t e n a b l e r e g i s t e r
b 7b 6b 5b 4b 3b 2b 1b 0
B i t s y m b o l
N O T E S :
1 . T h e I R b i t i n t h e K U P I C r e g i s t e r m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e K I E N r e g i s t e r i s r e w r i t t e n .
R e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
Figure 10.16 KIEN Register
d d r e s
f t e r r e s e
0 0 9
S y m b o lA
K I E N
Bit name Function
KI0EN
KI0PL
KI1EN
KI1PL
KI2EN
KI2PL
KI3EN
KI3PL
K I 0 i n p u t e n a b l e b i t 0 : D i s a b l e d
K I 0 i n p u t p o l a r i t y s e l e c t b i t
K I 1 i n p u t e n a b l e b i t
K I 1 i n p u t p o l a r i t y s e l e c t b i t
K I 2 i n p u t e n a b l e b i t
KI2 input polarity select bit 0 : Falling edge
K I 3 i n p u t e n a b l e b i t0
K I 3 i n p u t p o l a r i t y s e l e c t b i t0
sA
8
1 6 0
1 : E n a b l e d
0 : F a l l i n g e d g e
1 : R i s i n g e d g e s
0 : D i s a b l e d
1 : E n a b l e d
0 : F a l l i n g e d g e
1 : R i s i n g e d g e s
0 : D i s a b l e d
1 : E n a b l e d
1 : Rising edges
: D i s a b l e
1 : E n a b l e d
: F a l l i n g e d g
1 : R i s i n g e d g e s
t
0
1 6
R W
R W
R W
R W
R W
RW
R W
d
e
R W
R W
Rev.1.20 Jan 27, 2006 page 65 of 204
REJ09B0062-0120
Page 77
R8C/11 Group
10.4 Address Match Interrupt
10.4 Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMADi register (i=0, 1). Set the start address of any instruction in the RMADi register.
Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt. Note that the
address match interrupt is unaffected by the I flag and IPL.
The value of the PC that is saved to the stack when an address match interrupt is acknowledged varies
depending on the instruction at the address indicated by the RMAD i register (see the paragraph “register
saving” for the value of the PC). Not appropriate return address is pushed on the stack. There are two
ways to return from the address match interrupt as follows:
• Change the content of the stack and use a REIT instruction.
• Use an instruction such as POP to restore the stack as it was before an interrupt request was acknowl-
edged. And then use a jump instruction.
Table 10.6 lists the value of the PC that is saved to the stack when an address match interrupt is acknowledged.
Figure 10.17 shows the AIER, and RMAD1 to RMAD0 registers.
Table 10.6 Value of PC Saved to Stack when Address Match Interrupt Acknowledged
Address indicated by RMADi register (i=0,1) PC value saved
(1)
• 16-bit operation code instruction Address indicated by
• Instruction shown below among 8-bit operation code instructions RMADi register + 2
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest
STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (However, dest = A0 or A1)
• Instructions other than the above Address indicated by
RMADi register + 1
NOTES:
1. See the paragraph “saving registers” for the PC value saved.
Table 10.7 Relationship Between Address Match Interrupt Factors and Associated Registers
Address match interrupt factors Address match interrupt enable bit Address match interrupt register
Address match interrupt 0 AIER0 RMAD0
Address match interrupt 1 AIER1 RMAD1
Rev.1.20 Jan 27, 2006 page 66 of 204
REJ09B0062-0120
Page 78
R8C/11 Group
Address match interrupt enable register
10.4 Address Match Interrupt
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
AIER 0009
AIER0
AIER1
Address match interrupt 0
enable bit
Address match interrupt 1
enable bit
Nothing is assigned.
(b7-b2)
When write, set to “0”.
When read, their contents are indeterminate.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19) (b16)
(b15) (b8)
b0 b7 b0b3
Address setting register for address match interrupt
(b7-b4)
b7 b0
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
16 XXXXXX002
Bit nameBit symbol
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Symbol Address After reset
RMAD0 0012
16 to 001016 X0000016
RMAD1 001616 to 001416 X0000016
Function Setting range
0000016 to FFFFF16
RW
RW
RW
RW
RW
Figure 10.17 AIER Register and RMAD0 to RMAD1 Registers
Rev.1.20 Jan 27, 2006 page 67 of 204
REJ09B0062-0120
Page 79
R8C/11 Group 11. Watchdog Timer
11. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit in the PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it
cannot be set to “0” (watchdog timer interrupt) in a program. Refer to Section 5.3, “Watchdog Timer
Reset” for details.
The divide-by-N value for the prescaler can be chosen to be 16 or 128 with the WDC7 bit in the WDC
register. The period of watchdog timer can be calculated as given below. The period of watchdog timer is,
however, subject to an error due to the prescaler.
Watchdog timer period =
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register. After that, the watchdog timer is initialized by
writing to the WDTR register and the counting continues.
In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from
the held value when the modes or state are released.
Figure 11.1 shows the block diagram of the watchdog timer. Figure 11.2 shows the watchdog timerrelated registers.
CPU clock
Prescaler
1/16
1/128
WDC7 = 0
WDC7 = 1
Watchdog timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog
timer Reset
Write to WDTR register
Internal
reset
signal
Figure 11.1 Watchdog Timer Block Diagram
Rev.1.20 Jan 27, 2006 page 68 of 204
REJ09B0062-0120
Set to
“7FFF
16”
Page 80
R8C/11 Group 11. Watchdog Timer
W
a t c h d o g t i m e r c o n t r o l r e g i s t e
b7 b6 b5 b4 b3 b2 b1 b0
0
0
( b 4 - b 0 )
( b 5 )
( b 6 )
W D C 7
Watchdog timer reset register
b7 b0
The watchdog is initialized after a write instruction to this register.
The watchdog timer value is always initialized to “7FFF
whatever value is written.
r
d d r e s
f t e r r e s e
0 0 0 1 1 1 1
S y m b o lA
W D C
B i t n a m e
H i g h - o r d e r b i t o f w a t c h d o g t i m e r
R e s e r v e d b i tM
R e s e r v e d b i tM
P r e s c a l e r s e l e c t b i t0
Symbol Address After reset
WDTR 000D
sA
1
2
0 0 0 X X X X X
u s t s e t t o “ 0
u s t s e t t o “ 0
: D i v i d e d b y 1
1 : D i v i d e d b y 1 2 8
16 Indeterminate
Function
t
2
F u n c t i o nB i t s y m b o lR
W
R O
”
”
6
R W
R W
R W
RW
16” regardless of
WO
Watchdog timer start register
b7 b0
Symbol Address After reset
WDTS 000E
16 Indeterminate
Function
The watchdog timer starts counting after a write instruction to this register.
Figure 11.2 WDC Register, WDTR Register, and WDTS Register
RW
WO
Rev.1.20 Jan 27, 2006 page 69 of 204
REJ09B0062-0120
Page 81
R8C/11 Group
12. Timers
The microcomputer has three 8-bit timers and one 16-bit timer. The three 8-bit timers are Timer X, Timer Y,
and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has input capture and
output compare. All these timers function independently. The count source for each timer is the operating
clock that regulates the timing of timer operations such as counting and reloading.
Table 12.1 lists functional comparison.
Table 12.1 Functional Comparison
Item Timer X Timer Y Timer Z Timer C
Configuration 8-bit timer 8-bit timer 8-bit timer 16-bit
with 8-bit with 8-bit with 8-bit free-run
prescaler prescaler prescaler timer
Count Down Down Down Up
Count source •f1 •f1 •f1 •f1
•f2 •f8 •f2 •f8
•f8 •fRING •f8 •f32
•f32 •Input from •Timer Y •fRING-fast
CNTR1 pin underflow
Function Timer mode provided provided provided not provided
Pulse output mode provided not provided not provided not provided
Event counter mode provided provided
Pulse width
measurement mode provided not provided not provided not provided
Pulse period
measurement mode provided not provided not provided not provided
Programmable waveform
generation mode not provided provided provided not provided
Programmable one-shot
generation mode not provided not provided provided not provided
Programmable wait
one-shot generation mode not provided not provided provided not provided
Input capture mode not provided not provided not provided provided
Output compare mode not provided not provided not provided provided
Input pin CNTR0 CNTR1
Output pin CNTR0
__________
CNTR0 CNTR1 TZOUT
Related interrupt Timer X int Timer Y int Timer Z int Timer C int
_____
INT1 int
_____
INT2 int
Timer stop provided provided provided provided
NOTES:
1. Select the input from the CNTR
1 pin as a count source of timer mode.
(1)
not provided not provided
_____
INT0 TCIN
CMP00 to CMP02
CMP10 to CMP12
_____
INT0 int
_____
INT3 int
compare 0 int
compare 1 int
12. Timers
Rev.1.20 Jan 27, 2006 page 70 of 204
REJ09B0062-0120
Page 82
R8C/11 Group
0
2
T X C K 1 t o T X C K
= 0 0
f
1
f
8
f
32
f
2
P o l a r i t y
s w i t c h i n g
Toggle flip-flop
Rev.1.20 Jan 27, 2006 page 71 of 204
REJ09B0062-0120
Page 83
R8C/11 Group
b
b
b5b
b
b
b
b
0
0
Prescaler X Register
b7
Symbol Address After reset
b0
PREX 008C
16
FF16
Timer X Register
b7
Internal count source is counted
Internal count source is counted
Externally input pulses are counted
Pulse width of externally input
pulses is measured
(Internal count source is counted)
Pulse period of externally input
pulses is measured
(Internal count source is counted)
b0
Symbol Address After reset
TX 008D
Function
Underflow of Prescaler X is counted
Function
Setting range
0016 to FF
16
to FF
00
16
to FF
00
00
16
to FF
00
16
16
FF16
0016 to FF
RW
16
16
16
16
16
T i m e r c o u n t s o u r c e s e t t i n g r e g i s t e r
7
6
4
3
2
1
0
Symbol Address After reset
TCSS 008E
B i t s y m b o l
T X C K 0
B i t n a m e
T i m e r X c o u n t s o u r c e
s e l e c t b i t
T X C K 1
T Y C K 0
T i m e r Y c o u n t s o u r c e
s e l e c t b i t
T Y C K 1
TZCK0
T i m e r Z c o u n t s o u r c e
s e l e c t b i t
T Z C K 1
( b 7 - b 6 )
R e s e r v e d b i t
(1 )
(1 )
(1 )
16
b 1 b 0
0 0 : f
0 1 : f
1 0 : f
1 1 : f
b 3 b 2
0 0 : f
0 1 : f
1 0 : f
00
1
8
3 2
2
1
8
R I N G
1 1 : S e l e c t s i n p u t f r o m C N T R1 p i n
b 5 b 4
0 0 : f
1
0 1 : f
8
1 0 : S e l e c t s T i m e r Y u n d e r f l o w
1 1 : f
2
Must be set to “0”
N O T E S :
1 . A v o i d s w i t c h i n g a c o u n t s o u r c e , w h i l e a c o u n t e r i s i n p r o g r e s s . T i m e r c o u n t e r m u s t b e s t o p p e d b e f o r e s w i t c h i n g a c o u n t
s o u r c e .
Figure 12.3 PREX Register, TX Register, and TCSS Register
16
Function
R W
R W
R W
R W
R W
R W
R W
R W
Rev.1.20 Jan 27, 2006 page 72 of 204
REJ09B0062-0120
Page 84
R8C/11 Group
b
b
b
b
b
b2b
b
12.1.1 Timer Mode
In this mode, the timer counts an internally generated count source (See “Table 12.2 Timer Mode
Specifications”). Figure 12.4 shows the TXMR register in timer mode.
Table 12.2 Timer Mode Specifications
Item Specification
Count source f1, f2, f8, f32
Count operation • Down-count
• When the timer underflows, the contents in the reload register is reloaded and the count
is continued.
Divide ratio 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request generation timing
INT1/CNTR0 pin function Programmable I/O port, or INT1 interrupt input
CNTR0 pin function Programmable I/O port
Read from timer Count value can be read by reading TX register
Write to timer
When Timer X underflows [Timer X interruption]
Same applies to
PREX
register.
Value written to TX register is written to both reload register and counter.
Same applies to
PREX
register.
12.1 Timer (Timer X)
T i m e r X m o d e r e g i s t e r
7
6
5
4
00
00
0
N O T E S :
1 . T h e I R b i t i n t h e I N T 1 I C r e g i s t e r m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e R 0 E D G b i t i s r e w r i t t e n .
R e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
2 . T h i s b i t i s u s e d t o s e l e c t t h e p o l a r i t y o f I N T 1 i n t e r r u p t i n t i m e r m o d e .
3
1
0
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T X M R0
Bit name
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
TXEDG
T X U N D
O p e r a t i o n m o d e
s e l e c t b i t 0 , 1
INT1/CNTR
switching bit
T i m e r X c o u n t
s t a r t f l a g
S e t t o " 0 " i n t i m e r m o d e
Operation mode
select bit 2
S e t t o " 0 " i n t i m e r m o d e
S e t t o " 0 " i n t i m e r m o d e
0
polarity
(1, 2)
sA
B
1 6
0 0
t
1 6
F u n c t i o nBit symbol
b1 b0
0 0 : T i m e r m o d e o r p u l s e p e r i o d
m e a s u r e m e n t m o d e
0 : Rising edge
1 : Falling edge
0 : Stops counting
1 : Starts counting
0 : O t h e r t h a n p u l s e p e r i o d m e a s u r e m e n t m o d e
RW
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.4 TXMR Register in Timer Mode
Rev.1.20 Jan 27, 2006 page 73 of 204
REJ09B0062-0120
Page 85
R8C/11 Group
b
b
b5b
b
b
b
b
W
W
W
W
W
W
W
W
12.1 Timer (Timer X)
12.1.2 Pulse Output Mode
In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin
a pulse whose polarity is inverted each time the timer underflows (See “Table 12.3 Pulse Output mode
Specifications”). Figure 12.5 shows TXMR register in pulse output mode.
Table 12.3 Pulse Output Mode Specifications
Item Specification
Count source f1, f2, f8, f32
Count operation • Down-count
•
When the timer underflows, the contents in the reload register is reloaded and the count
is continued.
Divide ratio 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request • When Timer X underflows [Timer X interruption]
generation timing
INT1/CNTR0 pin function Pulse output
CNTR0 pin function Programmable I/O port or inverted output of CNTR0
Read from timer Count value can be read by reading TX register.
Same applies to
Write to timer
Select function
Value written to TX register is written to both reload register and counter.
Same applies to
_____
• INT1/CNTR0 polarity switching function
Polarity level at starting of pulse output can be selected with R0EDG bit
• Inverted pulse output function
The inverted pulse of CNTR0 output polarity can be output from the CNTR0 pin
(selected by the TXOCNT bit)
NOTES:
1. The level of the output pulse becomes the level when the pulse output starts when the TX register is written to.
PREX
PREX
register.
register.
(1)
Timer X mode register
7
6
4
3
0
00
2
1
0
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T X M R0
1
Bit name
T X M O D 0
T X M O D 1
R0EDG
TXS
TXOCNT
T X M O D 2
TXEDG
TXUND
O p e r a t i o n m o d e
s e l e c t b i t 0 , 1
INT1/CNTR0 polarity
switching bit
(1)
T i m e r X c o u n t
s t a r t f l a g
0
/ C N T R0
P 3
s e l e c t b i t
M u s t s e t t o " 0 " i n p u l s e o u t p u t m o d e
M u s t s e t t o " 0 " i n p u l s e o u t p u t m o d e
M u s t s e t t o " 0 " i n p u l s e o u t p u t m o d e
sA
B
1 6
0 0
1 6
FunctionB i t s y m b o l
b1 b0
0 1 : P u l s e o u t p u t m o d e
0: CNTR0 output starts at "H"
1: CNTR
0 : Stops counting
1 : Starts counting
0 : Port P3
1 : CNTR0 output
0
output starts at "L"
0
t
N O T E S :
1 . T h e I R b i t i n t h e I N T 1 I C r e g i s t e r m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e R 0 E D G b i t i s r e w r i t t e n .
R e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
Figure 12.5 TXMR Register in Pulse Output Mode
RW
R
R
R
R
R
R
R
R
Rev.1.20 Jan 27, 2006 page 74 of 204
REJ09B0062-0120
Page 86
R8C/11 Group
b
b
b
b
b
b
b
b
p
12.1.3 Event Counter Mode
In this mode, the timer counts an external signal fed to INT1/CNTR0 pin (See “Table 12.4 Event
Counter Mode Specifications”). Figure 12.6 shows TXMR register in event counter mode.
Table 12.4 Event Counter Mode Specifications
Item Specification
Count source External signals fed to CNTR0 pin (Active edge is selected by program)
Count operation • Down count
• When the timer underflows, the contents in the reload register is reloaded and the count
is continued.
Divide ratio 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request • When Timer X underflows [Timer X interrupt]
generation timing
INT1/CNTR0 pin function
Count source input (INT1 interrupt input)
CNTR0 pin function Programmable I/O port
Read from timer Count value can be read by reading TX register
Same applies to
Write to timer
Value written to TX register is written to both reload register and counter.
Same applies to
Select function • INT1/CNTR
Active edge of count source can be selected with R0EDG.
_______
PREX
register.
PREX
register.
0 polarity switching function
12.1 Timer (Timer X)
T i m e r X m o d e r e g i s t e r
7
6
00
5
4
3
0
0
2
1
1
0
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T X M R0
Bit name
T X M O D 0
O p e r a t i o n m o d e
s e l e c t b i t 0 , 1
sA
B
1 6
b1 b0
1 0 : Event counter mode
0 0
t
1 6
F u n c t i o nB i t s y m b o l
T X M O D 1
a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k
N O T E S :
R 0 E D G
T X S
T X O C N T
T X M O D 2
T X E D G
T X U N D
I N T 1 / C N T R
s w i t c h i n g b i t
T i m e r X c o u n t
s t a r t f l a g
S e t t o " 0 " i n e v e n t c o u n t e r m o d e
S e t t o " 0 " i n e v e n t c o u n t e r m o d e
S e t t o " 0 " i n e v e n t c o u n t e r m o d e
S e t t o " 0 " i n e v e n t c o u n t e r m o d e
0
p o l a r i t y
(1 )
0 : R i s i n g e d g e
1 : F a l l i n g e d g e
0 : S t o p s c o u n t i n g
1 : S t a r t s c o u n t i n g
1 . T h e I R b i t i n t h e I N T 1 I C r e g i s t e r m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e R 0 E D G b i t i s r e w r i t t e n .
R e f e r t o t h e
.
RW
R W
R W
RW
R W
R W
R W
R W
R W
Figure 12.6 TXMR Register in Event Counter Mode
Rev.1.20 Jan 27, 2006 page 75 of 204
REJ09B0062-0120
Page 87
R8C/11 Group
b
b
b
b4b
b
b
b
12.1.4 Pulse Width Measurement Mode
In this mode, the timer measures the pulse width of an external signal fed to INT1/CNTR0 pin (See
“Table 12.5 Pulse Width Measurement Mode Specifications”). Figure 12.7 shows the TXMR register
in pulse width measurement mode. Figure 12.8 shows an operation example in pulse width measurement mode.
Table 12.5 Pulse Width Measurement Mode Specifications
Item Specification
Count source f1, f2, f8, f32
Count operation • Down-count
• Continuously counts the selected signal only when the measurement pulse is "H" level,
or conversely only "L" level.
• When the timer underflows, the contents in the reload register is reloaded and the count
is continued.
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request • When Timer X underflows [Timer X interruption]
generation timing • Rising or falling of CNTR0 input (end of measurement period) [INT1 interrupt]
INT1/CNTR0 pin function Measurement pulse input
CNTR0 pin function Programmable I/O port
Read from timer Count value can be read by reading TX register
Write to timer
Select function
Same applies to
Value written to TX register is written to both reload register and counter.
Same applies to
_____
• INT1/CNTR0 polarity switching function
“H” or “L” level duration can be selected with R0EDG bit as the input pulse measurement
PREX
PREX
register.
register.
12.1 Timer (Timer X)
T i m e r X m o d e r e g i s t e r
7
6
5
010
00 1
N O T E S :
1 . I T h e I R b i t i n t h e I N T 1 I C r e g i s t e r m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e R 0 E D G b i t i s r e w r i t t e n .
R e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
3
2
1
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T X M R0
B i t n a m e
T X M O D 0
T X M O D 1
R 0 E D G
T X S
T X O C N T
TXMOD2
T X E D G
T X U N D
O p e r a t i o n m o d e
s e l e c t b i t 0 , 1
I N T 1 / C N T R
s w i t c h i n g b i t
T i m e r X c o u n t
s t a r t f l a g
S e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e
S e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e
S e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e
S e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e
0
p o l a r i t y
(1 )
sA
B
1 6
0 0
t
1 6
F u n c t i o nB i t s y m b o l
b 1 b 0
1 1 : Pulse width measurement mode
[CNTR0]
0 : Measures “H” level width
1 : Measures “L” level width
[INT1]
0 : Rising edge
1 : Falling edge
0 : Stops counting
1 : Starts counting
R W
R W
R W
R W
R W
R W
RW
RW
RW
Figure 12.7 TXMR Register in Pulse Width Measurement Mode
Rev.1.20 Jan 27, 2006 page 76 of 204
REJ09B0062-0120
Page 88
R8C/11 Group
n = high-level: the contents of TX register, low-level: the contents of PREX register
FFFF
16
n
Counter contents (hex)
0000
16
Count stop
Rev.1.20 Jan 27, 2006 page 77 of 204
REJ09B0062-0120
Page 89
R8C/11 Group
b
b
b
b4b
b2b
b
W
W
W
j
W
W
W
W
W
12.1 Timer (Timer X)
12.1.5 Pulse Period Measurement Mode
In this mode, the timer measures the pulse period of an external signal fed to INT1/CNTR0 pin (See
“Table 12.6 Pulse Period Measurement Mode Specifications”). Figure 12.9 shows the TXMR register
in pulse period measurement mode. Figure 12.10 shows an operation example in pulse period measurement mode.
Table 12.6 Pulse Period Measurement Mode Specifications
Item Specification
Count source f1, f2, f8, f32
Count operation • Down-count
• After an active edge of measurement pulse is input, contents in the read-out buffer is
retained in the first underflow of prescaler X. Then the timer X reloads contents in the
reload register in the second underflow of prescaler X and continues counting.
Count start condition Write “1” (count start) to TXS bit in TXMR register
Count stop condition Write “0” (count stop) to TXS bit in TXMR register
Interrupt request • When Timer X underflows or reloads [Timer X interrupt]
generation timing
INT1/CNTR0 pin function Measurement pulse input
• Rising or falling of CNTR0 input (end of measurement period) [INT1 interrupt]
(1)
(INT1 interrupt input)
CNTR0 pin function Programmable I/O port
Read from timer Contents in the read-out buffer can be read by reading TX register. The value retained in
the read-out buffer is released by reading TX register.
Write to timer
Select function
Value written to TX register is written to both reload register and counter.
Same applies to
_____
PREX
register.
• INT1/CNTR0 polarity switching function
Measurement period of input pulse can be selected with R0EDG bit.
NOTES:
1. The period of input pulse must be longer than twice the period of prescaler X. Longer pulse for H width and L width than
the prescaler X period must be input. If shorter pulse than the period is input to the CNTR0 pin, the input may be disabled.
_____
T i m e r X m o d e r e g i s t e r
7
6
5
1
0
N O T E S :
1 . T h e I R b i t i n t h e I N T 1 I C r e g i s t e r m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e R 0 E D G b i t i s r e w r i t t e n .
R e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
2 . T h i s b i t i s s e t t o “ 0 ” b y w r i t i n g “ 0 ” i n a p r o g r a m . ( I t r e m a i n s u n c h a n g e d e v e n i f w r i t i n g “ 1 ” )
3
1
0
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T X M R0
0
B i t n a m e
T X M O D 0
T X M O D 1
R0EDG
T X S
T X O C N T
T X M O D 2
T X E D G
T X U N D
Operation mode
select bit 0, 1
INT1/CNTR0
polarity
switching bit
Timer X count
start flag
S e t t o “ 0 ” i n p u l s e p e r i o d m e a s u r e m e n t m o d e
O p e r a t i o n m o d e
s e l e c t b i t 2
u d g m e n t f l a
A c t i v e e d g e
(2 )
T i m e r X
(2 )
u n d e r f l o w f l a g
(1)
g
sA
B
1 6
0 0
1 6
FunctionBit symbol
b1 b0
0 0 : Timer mode or pulse period
measurement mode
[CNTR0]
0: Measures a measurement pulse from one
rising edge to the next rising edge
1: Measures a measurement pulse from one
falling edge to the next falling edge
[INT1]
0: Rising edge
1: Falling edge
0 : S t o p s c o u n t i n g
1 : S t a r t s c o u n t i n g
1 : P u l s e p e r i o d m e a s u r e m e n t m o d e
0 : No active edge
1 : Active edge found
0 : N o u n d e r f l o w
1 : U n d e r f l o w f o u n d
Figure 12.9 TXMR Register in Pulse Period Measurement Mode
t
RW
R
R
R
R
R
R
R
R
Rev.1.20 Jan 27, 2006 page 78 of 204
REJ09B0062-0120
Page 90
R8C/11 Group
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
U n d e r f l o w s i g n a l
o f p r e s c a l e r X
12.1 Timer (Timer X)
S e t t o " 1 " b y p r o g r a m
T X S b i t i n T X M R
r e g i s t e r
“ 1 ”
“ 0 ”
S t a r t s c o u n t i n g
C N T R 0 p i n
i n p u t
T i m e r X
c o n t e n t s
C o n t e n t s o f
r e a d - o u t b u f f e r
T X E D G b i t i n
T X M R r e g i s t e r
TXUND bit in
TXMR register
IR bit in TXIC
register
“ 1 ”
“ 0 ”
0 E
1
0 F
1
( 7 )(
1
0 F
1
0F
16
R e t a i n e d
(2)
T i m e r X
r e l o a d s
0E
1
0D160 C
0E
1
1
0 A
0 A
1
0 9
1
1
09
1
T i m e r X r e a d
(3)
1 6
0 B
“ 1 ”
0 8
1
Retained
(2)
Timer X
reloads
0F160E
7
08
1
1
0D
)
16
0 D
1 6
Timer X read
(3)
T i m e r X
r e l o a d s
01
1
0 0
0 0
0 1
1
1
0 F
1
0 E
0 F
1
0 E
1
“ 0 ”
Cleared to "0" by program
(4)
(6)
“1”
“ 0 ”
C l e a r e d t o " 0 " b y p r o g r a m
(5)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by program
I R b i t i n I N T 1 I C
r e g i s t e r
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by program
C o n d i t i o n s : A p e r i o d f r o m o n e r i s i n g e d g e t o t h e n e x t r i s i n g e d g e o f m e a s u r e m e n t p u l s e i s m e a s u r e d ( R 0 E D G = 0 )
w i t h T X r e g i s t e r i n i t i a l v a l u e = 0 F
NOTES:
1. The contents of the read-out buffer can be read when the TX register is read in pulse period measurement mode.
2. After an active edge of measurement pulse is input, the TXEDG bit in the TXMR register is set to "1" (active edge found)
when the prescaler X underflows for the second time.
3. The TX register should be read before the next active edge is input after the TXEDG bit is set to "1" (active edge found).
The contents in the read-out buffer is retained until the TX register is read. If the TX register is not read before the next
active edge is input, the measured result of the previous period is retained.
4. When set to "0" by program, use a MOV instruction to write "0" to the TXEDG in the TXMR register. At the same time,
write "1" to the TXUND bit.
5. When set to "0" by program, use a MOV instruction to write "0" to the TXUND in the TXMR register. At the same time,
write "1" to the TXEDG bit.
6. The TXUND and TXEDG bits are both set to "1" if the timer underflows and reloads on an active edge simultaneously. In
this case, the validity of the TXUND bit should be determined by the contents of the read-out buffer.
7. If the CNTR
read buffer. If "L" level, the following count value is the one of the read buffer.
0
active edge is input, when the prescaler X underflow signal is "H" level, its count value is the one of the
1 6
.
1
1
Figure 12.10 Operation Example in Pulse Period Measurement Mode
Rev.1.20 Jan 27, 2006 page 79 of 204
REJ09B0062-0120
Page 91
R8C/11 Group
12.2 Timer Y
Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Y Primary and Timer
Y Secondary. Figure 12.11 shows a block diagram of Timer Y. Figures 12.12 to 12.14 show the TYZMR,
PREY, TYSC, TYPR, TYZOC, PUM, and YCSS registers.
The Timer Y has two operation modes as follows:
• Timer mode: The timer counts an internal count source (clock source).
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
Figure 12.11 Timer Y Block Diagram
Rev.1.20 Jan 27, 2006 page 80 of 204
REJ09B0062-0120
¥
Page 92
R8C/11 Group
b
b
b
b
b
b
b
b
Prescaler Y register
b7
12.2 Timer (Timer Y)
b0
Symbol Address After reset
PREY 0081
16
FF16
Mode
Timer mode
Programmable
waveform generation
Function
Internal count source or CNTR1
input is counted
Internal count source is counted
Setting range
0016 to FF
00
16
to FF
16
16
mode
Timer Y secondary register
b7
NOTES:
b0
Mode
Timer mode
Programmable
waveform generation
mode
Symbol Address After reset
TYSC 0082
Function
16
FF16
Setting range
Disabled
Underflow of Prescaler Y is
(1)
counted
0016 to FF
16
1. The values of TYPR register and TYSC register are reloaded to the counter alternately for counting.
2. The count value can be read out by reading the TYPR register even when the secondary period is being
counted.
Timer Y primary register
b7
b0
Symbol Address After reset
TYPR 0083
16
FF16
RW
WO
RW
RW
RW
(2)
Setting range
00
16
to FF
16
0016 to FF
16
NOTES:
Mode
Timer mode
Programmable
waveform generation
mode
Function
Underflow of Prescaler Y is
counted
Underflow of Prescaler Y is
(1)
counted
1. The values of TYPR register and TYSC register are reloaded to the counter alternately for counting.
T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e r
7
6
5
4
3
2
1
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T Y Z O C0
T Z O S
T Y O C N T
T Z O C N T
( b 7 - b 3 )
N O T E S :
1 . T h i s b i t i s s e t t o " 0 " w h e n t h e o u t p u t o f o n e - s h o t w a v e f o r m i s c o m p l e t e d . T h e T Z O S b i t s h o u l d b e s e t t o " 0 " i f t h e
o n e - s h o t w a v e f o r m o u t p u t i s t e r m i n a t e d b y s e t t i n g t h e T Z S b i t i n t h e T Y Z M R t o " 0 " d u r i n g t h e w a v e f o r m o u t p u t .
2 . T h i s b i t i s e n a b l e d o n l y w h e n o p e r a t i n g i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e .
3 . I f e x e c u t i n g a n i n s t r u c t i o n w h i c h c h a n g e s t h i s r e g i s t e r w h e n t h e T Z O S b i t i s “ 1 ” ( d u r i n g t h e c o u n t ) , t h e T Z O S i s
a u t o m a t i c a l l y s e t t o “ 0 ” w h e n t h e c o u n t c o m p l e t e s w h i l e t h e i n s t r u c t i o n i s e x e c u t e d . I f t h i s c a u s e s s o m e p r o b l e m s ,
e x e c u t e a n i n s t r u c t i o n w h i c h c h a n g e s t h i s r e g i s t e r w h e n t h e T Z O S b i t i s “ 0 ” ( o n e s h o t s t o p ) .
( 3 )
sA
A
1 6
Bit name
T i m e r Z o n e - s h o t
( 1 )
s t a r t b i t
T i m e r Y p r o g r a m m a b l e
w a v e f o r m g e n e r a t i o n
o u t p u t s w i t c h i n g b i t
Timer Z programmable
waveform generation
output switching bit
N o t h i n g i s a s s i g n e d .
W h e n w r i t e , s e t t o " 0 " . W h e n r e a d , i t s c o n t e n t i s " 0 " .
(2)
0 : S t o p s o n e - s h o t
1 : S t a r t s o n e - s h o t
0 : O u t p u t s p r o g r a m m a b l e w a v e f o r m
1 : O u t p u t s t h e v a l u e o f P 3
( 2 )
0 : O u t p u t s p r o g r a m m a b l e w a v e f o r m
1 : O u t p u t s t h e v a l u e o f P 3
t
0 0
1 6
FunctionB i t s y m b o l
2
p o r t r e g i s t e r
1
p o r t r e g i s t e r
RW
RW
RW
R W
R W
R W
R W
Figure 12.13 PREY Register, TYSC Register, TYPR Register, and TYZOC Register
Rev.1.20 Jan 27, 2006 page 81 of 204
REJ09B0062-0120
Page 93
R8C/11 Group
b
b
b
b
b
b
b
b
L
r
T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r
7
6
5
4
3
2
1
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
P U M0
0000
sA
4
1 6
0 0
t
1 6
Bit symbol
( b 3 - b 0 )
T Y O P
TZOPL
I N O S T G
INOSEG
Bit name
R e s e r v e d b i t
T i m e r Y o u t p u t l e v e l
l a t c h
Timer Z output level
latch
I N T 0 p i n o n e - s h o t t r i g g e
c o n t r o l b i t
INT0 pin one-shot trigger
polarity select bit
(2 )
(Timer Z)
(1)
(Timer Z)
Function
Must set to “0”
Function varies depending on the operation mode
Function varies depending on the operation mode
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid
0 : Edge trigger at falling edge
1 : Edge trigger at rising edge
N O T E S :
1 . T h e I N O S E G b i t i s v a l i d o n l y w h e n t h e I N T 0 P L b i t i n t h e I N T E N r e g i s t e r i s " 0 " ( o n e - e d g e ) .
2 . T h e I N O S G T b i t m u s t b e s e t t o " 1 " a f t e r t h e I N T 0 E N b i t i n t h e I N T E N r e g i s t e r a n d t h e I N O S E G b i t i n t h e P U M r e g i s t e r
a r e s e t .
T i m e r c o u n t s o u r c e s e t t i n g r e g i s t e r
d d
S y m b o lA
B i t s y m b o l
TXCK0
TXCK1
B i t n a m e
Timer X count source
select bit
(1)
Function
b 1 b 0
RW
RW
R W
RW
R W
RW
T Y C K 0
T i m e r Y c o u n t s o u r c e
s e l e c t b i t
(1 )
TYCK1
T Z C K 0
Timer Z count source
select bit
(1)
T Z C K 1
s o u r c e
N O T E S :
( b 7 - b 6 )
Reserved bit
S e t t o “ 0 ”
1 . A v o i d s w i t c h i n g a c o u n t s o u r c e , w h i l e a c o u n t e r i s i n p r o g r e s s . T i m e r c o u n t e r m u s t b e s t o p p e d b e f o r e s w i t c h i n g a c o u n t
.
Figure 12.14 PUM Register and TCSS Register
Rev.1.20 Jan 27, 2006 page 82 of 204
REJ09B0062-0120
Page 94
R8C/11 Group
12.2 Timer (Timer Y)
12.2.1 Timer Mode
In this mode, the timer counts an internally generated count source (see “Table 12.7 Timer Mode
Specifications”). An external signal input to the CNTR1 pin can be counted. The TYSC register is
unused in timer mode. Figure 12.15 shows the TYZMR and PUM registers in timer mode.
Table 12.7 Timer Mode Specifications
Item Specification
Count source f1, f8, fRING, external signal fed to CNTR1 pin
Count operation • Down-count
• When the timer underflows, it reloads the reload register contents before continuing
counting (When the Timer Y underflows, the contents of the Timer Y primary reload
register is reloaded.)
Divide ratio 1/(n+1)(m+1) n: set value in PREY register, m: set value in TYPR register
Count start condition Write “1” (count start) to TYS bit in TYZMR register
Count stop condition Write “0” (count stop) to TYS bit in TYZMR register
Interrupt request • When Timer Y underflows [Timer Y interrupt]
generation timing
INT2/CNTR
1 pin function
Programmable I/O port, count source input or INT2 interrupt input
• When the TYCK1 to TYCK0 bits in the TCSS register are set to “00b”, “01b” or “10b”
(Timer Y count source is f1, f8 or fRING), programmable I/O port or INT2 interrupt input
• When the TYCK1 to TYCK0 bits are set to “11b” (Timer Y count source is CNTR
input), count source input (INT2 interrupt input)
_______
Read from timer Count value can be read out by reading TYPR register.
Same applies to PREY register.
Write to timer
(1)
Value written to TYPR register is written to both reload register and counter or written to
only reload register. Selected by program.
Same applies to PREY register.
Select function • Event counter function
When setting TYCK1 to TYCK0 bits to “112”, an external signal fed to CNTR1 pin is
counted.
_______
• INT2/CNTR1 switching bit
Active edge of count source is selected by R1EDG bit.
NOTES:
1. The IR bit in the TYIC register is set to "1" (interrupt requested) if you write to the TYPR or PREY register while both
of the following conditions are met.
Conditions:
• TYWC bit in TYZMR register is "0" (write to reload register and counter simultaneously)
• TYS bit is "1" (count start)
To write to the TYPR or PREY register in the above state, disable interrupts before writing.
______________
_______
1
Rev.1.20 Jan 27, 2006 page 83 of 204
REJ09B0062-0120
Page 95
R8C/11 Group
b
b
b
b
b
b
b
b
g
12.2 Timer (Timer Y)
T i m e r Y , Z m o d e r e g i s t e r
7
6
5
4
3
2
1
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T Y Z M R0
0
Bit name
TYMOD0
R 1 E D G
TYWC
TYS
TZMOD0
Timer Y operation
mode bit
INT2/CNTR1 polarity
switching bit
Timer Y write
control bit
(1)
(2)
Timer Y count
start flag
Timer Z-related bit
sA
0
1 6
0 0
t
1 6
F u n c t i o nBit symbol
0 : T i m e r m o d e
0 : R i s i n g e d g e
1 : F a l l i n g e d g e
0 : W r i t e t o r e l o a d r e g i s t e r a n d c o u n t e r
s i m u l t a n e o u s l y
1 : W r i t e t o r e l o a d r e g i s t e r
0 : S t o p s c o u n t i n g
1 : S t a r t s c o u n t i n g
T Z M O D 1
T Z W C
T Z S
a r d l e s s o f h o w t h e T Y W C b i t i s s e t
N O T E S :
1 . T h e I R b i t i n t h e I N T 2 I C r e g i s t e r m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e R 1 E D G b i t i s r e w r i t t e n .
R e f e r t o t h e p a r a g r a p h 1 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
2 . W h e n T Y S b i t = 1 ( s t a r t s c o u n t i n g ) , t h e v a l u e s e t i n t h e T Y W C b i t i s v a l i d . I f T Y W C b i t = 0 , t h e t i m e r Y c o u n t v a l u e i s
w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r . I f T Y W C b i t = 1 , t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r
o n l y . W h e n T Y S b i t = 0 ( s t o p s c o u n t i n g ) , t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r
r e
.
R W
R W
R W
R W
RW
R W
R W
RW
RW
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
PUM 0084
0000
Bit symbol
(b3-b0)
TYOPL
TZOPL
INOSTG
INOSEG
Reserved bit
Timer Y output level
latch
Timer Z-related bits
Bit name
16
0016
Must set to “0”
Invalid in timer mode
Figure 12.15 TYZMR Register and PUM Register in Timer Mode
Function
RW
RW
RW
RW
RW
RW
Rev.1.20 Jan 27, 2006 page 84 of 204
REJ09B0062-0120
Page 96
R8C/11 Group
12.2 Timer (Timer Y)
12.2.2 Programmable Waveform Generation Mode
In this mode, an signal output from the TYOUT pin is inverted each time the counter underflows, while
the values in the TYPR register and TYSC register are counted alternately (see “Table 12.8 Programmable Waveform Generation Mode Specifications”). A counting starts by counting the set value in the
TYPR register. Figure 12.16 shows the TYZMR register in programmable waveform generation mode.
Figure 12.17 shows the operation example.
Table 12.8 Programmable Waveform Generation Mode Specifications
Item Specification
Count source f1, f8, fRING
Count operation • Down count
• When the timer underflows, it reloads the contents of primary reload register and secondary reload register alternately before continuing counting.
(1)
i
.
(2)
.
(3)
.
Output waveform width Primary period : (n+1)(m+1)/f
and period Secondary period : (n+1)(p+1)/fi
Period : (n+1){(m+1)+(p+1)}/fi
n: set value in PREY register, m: set value in TYPR register, p: set value in TYSC register
fi : Count source frequency
Count start condition Write “1” (count start) to TYS bit in TYZMR register
Count stop condition Write “0” (count stop) to TYS bit in TYZMR register
Interrupt request generation timing
_______
In half of count source, after Timer Y underflows during secondary period (at the same
time as the CNTR1 output change) [Timer Y interrupt].
INT2/CNTR1 pin functions Pulse output
Use timer mode when using this pin as a programmable I/O port.
Read from timer Count value can be read out by reading TYPR register.
Same applies to PREY register
Write to timer
Value written to TYPR register is written to only reload register.
Same applies to TYSC register and PREY register
Select function • Output level latch select function
The output level during primary and secondary periods is selected by the TYOPL bit.
• Programmable waveform generation output switching function
When the TYOCNT bit in the TYZOC register is set to “0”, the output from TYOUT is
inverted synchronously when Timer Y underflows during the secondary period. And
when set to “1”, a value in the P3_2 bit is output from TYOUT synchronously when Timer
Y underflows during the secondary period
NOTES:
1. Even when counting the secondary period, read out the TYPR register.
2. The set value in the TYPR register and TYSC register are made effective by writing a value to the TYPR register. The
written values are reflected to the waveform output from the next primary period after writing to the TYPR register.
3. The TYOCNTbit is enabled in the following timings
• When count starts
• When Timer Y interrupt request is generated
Therefore, pulse is output from the next primary period depending on the setting value of the TYOCNT bit.
Rev.1.20 Jan 27, 2006 page 85 of 204
REJ09B0062-0120
Page 97
R8C/11 Group
b
b
b
b
b
b2b1b
12.2 Timer (Timer Y)
T i m e r Y , Z m o d e r e g i s t e r
7
6
5
4
3
1
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T Y Z M R0
1
B i t n a m e
TYMOD0
R 1 E D G
T Y W C
T Y S
TZMOD0
TZMOD1
TZWC
TZS
Timer Y operation
mode bit
I N T 2 / C N T R
s w i t c h i n g b i t
1
(1 , 3 )
Timer Y write
control bit
Timer Y count
start flag
Timer Z-related bit
sA
0
1 6
t
0 0
1 6
F u n c t i o nBit symbol
1 : P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e
Disabled in programmable waveform
p o l a r i t y
generation mode
Must set to "1" in programmable
waveform generation mode.
0 : S t o p s c o u n t i n g
1 : S t a r t s c o u n t i n g
R W
R W
R W
(2)
R W
R W
RW
R W
R W
R W
NOTES:
1. The IR bit in the INT2IC register may be set to “1” (interrupt requested) when the R1EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.
2 . W h e n T Y S b i t = 1 ( s t a r t s c o u n t i n g ) , t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y .
W h e n T Y S b i t = 0 ( s t o p s c o u n t i n g ) , t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r .
3 . T h e I N T 2 i n t e r r u p t r e q u e s t i s n o t g e n e r a t e d w h e n t h e T Y M O D 0 b i t i s s e t t o “ 1 ” ( p r o g r a m m a b l e w a v e f o r m g e n e r a t i o m o d e ) .
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
PUM 0084
0000
Bit symbol
(b3-b0)
TYOPL
TZOPL
Timer Y output level
latch
Timer Z-related bits
Bit name
Reserved bit
16
INOSTG
INOSEG
0016
Function
Must set to “0”
0 : Outputs "H" for primary period
Outputs "L" for secondary period
Outputs "L" when the timer is stopped
1 : Outputs "L" for primary period
Outputs "H" for secondary period
Outputs "H" when the timer is stopped
RW
RW
RW
RW
RW
RW
Figure 12.16 TYZMR Register and PUM Register in Programmable Waveform Generation Mode
Rev.1.20 Jan 27, 2006 page 86 of 204
REJ09B0062-0120
Page 98
R8C/11 Group
12.2 Timer (Timer Y)
Set to "1" by program
TYS bit in TYZMR
register
Count source
Prescaler Y
underflow signal
Contents of Timer Y
IR bit in TYIC
register
TYOPL bit in PUM
register
"1"
"0"
"1"
"0"
"1"
"0"
Count starts
Set to "0" by program
01
Timer Y
secondary
reloads
16
00
16
02
16
01
16
Timer Y
primary
reloads
00
16
Set to "0" when interrupt request is
accepted, or set by program
01
16
00
16
02
16
CNTR1 pin output
"H"
Waveform output
started
Waveform output
inverted
Waveform output
inverted
"L"
Primary period
Conditions: PREY=0116, TYPR=01
16,
TYSC=02
Secondary period
16
Primary period
TYZOC register TYOCNT bit = 0
Figure 12.17 Timer Y Operation Example in Programmable Waveform Generation Mode
Rev.1.20 Jan 27, 2006 page 87 of 204
REJ09B0062-0120
Page 99
R8C/11 Group
8
2
T
r
r
r
L
t
t
K
b
b
b
b
b
b
b1b
W
W
W
W
W
W
W
W
12.3 Timer (Timer Z)
12.3 Timer Z
Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer
Z Secondary. Figure 12.18 shows a block diagram of Timer Z. Figures 12.19 to 12.21 show the TYZMR,
PREZ, TZSC, TZPR, TYZOC, PUM, and TCSS registers.
Timer Z has the following four operation modes.
• Timer mode: The timer counts an internal count source or Timer Y underflow.
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse.
Da t a b u s
T Z C K 1 t o T Z C K 0
f
1
T i m e r Y u n d e r f l o w
f
f
I N T 0
T Z M O D 1 t o T Z M O D 0 = 0 12, 1 02, 1 1
TZ
OU
= 0 0
= 0 1
= 1 0
= 1 1
T Z S C r e g i s t e r
2
2
2
2
D i g i t a l
f i l t e r
2
TZOCNT=0
T Z O C N T = 1
Reload registe
P R E Z r e g i s t e r
T Z S
I n p u t p o l a r i t y s e l e c t e d t o b e
o n e e d g e o r b o t h e d g e s
INT0P
INT0EN
P3_1 bit in P3 register
R e l o a d r e g i s t e
TZMOD1 to TZMOD0= 10
Polarity
select
INOSEG
T Z O P L = 1
TZOPL=0
2
,
11
Q
Q
R e l o a d r e g i s t e
C o u n t e r C o u n t e r
2
T Z O S
T o g g l e f l i p - f l o p
CLR
T Z P R r e g i s t e r
C
Timer Z interrup
I N T 0 i n t e r r u p
W r i t e t o T Y Z M R r e g i s t e r
TZMOD1 to TZMOD0 bits =01
2
, 102, 11
2
Figure 12.18 Timer Z Block Diagram
T i m e r Y , Z m o d e r e g i s t e r
7
6
5
4
3
2
N O T E S :
1 . T h e I R b i t i n t h e I N T 2 I C r e g i s t e r m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e R 1 E D G b i t i s r e w r i t t e n .
R e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
d d r e s
f t e r r e s e
0 8
0
S y m b o lA
T Y Z M R0
T Y M O D 0
R 1 E D G
T Y W C
TYS
TZMOD0
TZMOD1
T Z W C
T Z S
Bit name
Timer Y operation
mode bit
1
INT2/CNTR
switching bit
Timer Y write
control bit
Timer Y count
start flag
Timer Z operation
mode bit
Timer Z write
control bit
Timer Z count
start flag
polarity
(1)
sA
0
1 6
t
0 0
1 6
FunctionB i t s y m b o l
0 : T i m e r m o d e
1 : P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e
0 : R i s i n g e d g e
1 : F a l l i n g e d g e
F u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n
m o d e
0 : S t o p s c o u n t i n g
1 : S t a r t s c o u n t i n g
b 5 b 4
0 0 : T i m e r m o d e
0 1 : P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e
1 0 : P r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e
1 1 : P r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n
m o d e
F u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n
m o d e
0 : S t o p s c o u n t i n g
1 : S t a r t s c o u n t i n g
R W
R
R
R
R
R
R
R
R
Figure 12.19 TYZMR Register
Rev.1.20 Jan 27, 2006 page 88 of 204
REJ09B0062-0120
Page 100
R8C/11 Group
b
b
b
b
b
b
b
b
b
b
b
b2b
b
12.3 Timer (Timer Z)
P r e s c a l e r Z r e g i s t e r
7
M o d e
T i m e r m o d e
P r o g r a m m a b l e
w a v e f o r m
g e n e r a t i o n m o d e
P r o g r a m m a b l e
o n e - s h o t
g e n e r a t i o n m o d e
P r o g r a m m a b l e w a i t
o n e - s h o t g e n e r a t i o n
m o d e
T i m e r Z S e c o n d a r y r e g i s t e r
7
M o d e
T i m e r m o d e
P r o g r a m m a b l e
w a v e f o r m
g e n e r a t i o n m o d e
P r o g r a m m a b l e
o n e - s h o t
g e n e r a t i o n m o d e
P r o g r a m m a b l e w a i t
o n e - s h o t g e n e r a t i o n
N O T E S :
1 . E a c h v a l u e i n t h e T Z P R r e g i s t e r a n d T Z S C r e g i s t e r i s r e l o a d e d t o t h e c o u n t e r a l t e r n a t e l y f o r c o u n t i n g .
2 . T h e c o u n t v a l u e c a n b e r e a d o u t b y r e a d i n g t h e T Z S C r e g i s t e r e v e n w h e n t h e s e c o n d a r y p e r i o d i s b e i n g
c o u n t e d .
T i m e r Z P r i m a r y r e g i s t e r
7
m o d e
d d r e s
f t e r r e s e t
0 8
S y m b o lA
0
P R E Z0
F u n c t i o nS
I n t e r n a l c o u n t s o u r c e o r T i m e r Y
u n d e r f l o w i s c o u n t e d
I n t e r n a l c o u n t s o u r c e o r T i m e r Y
u n d e r f l o w i s c o u n t e d
I n t e r n a l c o u n t s o u r c e o r T i m e r Y
u n d e r f l o w i s c o u n t e d0
I n t e r n a l c o u n t s o u r c e o r T i m e r Y
u n d e r f l o w i s c o u n t e d
d d r e s
f t e r r e s e t
0 8
S y m b o lA
0
T Z S C0
F u n c t i o nS
sA
5
1 6 F
e t t i n g r a n g
t o F
0 01
t o F
0 0
t o F
t o F
0 0
sA
6
1 6 F
e t t i n g r a n g
I n v a l i d
U n d e r f l o w o f
P r e s c a l e r Z i s c o u n t e d
( 1 )
t o F
0 01
I n v a l i d
U n d e r f l o w o f P r e s c a l e r Z i s
c o u n t e d
( O n e - s h o t w i d t h i s c o u n t e d )
d d r e s
f t e r r e s e t
0 8
S y m b o lA
0
T Z P R0
7
1 6 F
t o F
0 0
sA
F1
6
6
F1
1 6
F1
0
1 6
F1
1 6
F1
F1
6
6
F1
1 6
F1
F1
6
e
R W
6
R W
R W
6
6
R W
R W
6
e
R W
6
( 2 )
W O
W O
6
M o d e
T i m e r m o d e
P r o g r a m m a b l e
w a v e f o r m
g e n e r a t i o n m o d e
P r o g r a m m a b l e
o n e - s h o t
g e n e r a t i o n m o d e
P r o g r a m m a b l e w a i t
o n e - s h o t g e n e r a t i o n
N O T E S :
1 . E a c h v a l u e i n t h e T Z P R r e g i s t e r a n d T Z S C r e g i s t e r i s r e l o a d e d t o t h e c o u n t e r a l t e r n a t e l y f o r c o u n t i n g .
T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e r
7
6
5
4
3
m o d e
d d r e s
f t e r r e s e
0 8
1
0
S y m b o lA
T Y Z O C0
U n d e r f l o w o f P r e s c a l e r Z i s
c o u n t e d
U n d e r f l o w o f
P r e s c a l e r Z i s c o u n t e d
U n d e r f l o w o f P r e s c a l e r Z i s
c o u n t e d
( O n e - s h o t w i d t h i s c o u n t e d )
U n d e r f l o w o f P r e s c a l e r Z i s
c o u n t e d
( W a i t p e r i o d i s c o u n t e d )
( 3 )
F u n c t i o nS
( 1 )
sA
A
1 6
0 0
1 6
Bit name
( b 7 - b 3 )
T i m e r Z o n e - s h o t
( 1 )
s t a r t b i t
T i m e r Y p r o g r a m m a b l e
w a v e f o r m g e n e r a t i o n
o u t p u t s w i t c h i n g b i t
T i m e r Z p r o g r a m m a b l e
w a v e f o r m g e n e r a t i o n
o u t p u t s w i t c h i n g b i t
N o t h i n g i s a s s i g n e d .
W h e n w r i t e , s e t t o " 0 " . W h e n r e a d , i t s c o n t e n t i s " 0 " .
T Z O S
T Y O C N T
T Z O C N T
NOTES:
1. This bit is set to "0" when the output of one-shot waveform is completed. The TZOS bit should be set to "0" if the
one-shot waveform output is terminated by setting the TZS bit in the TYZMR to "0" during the waveform output.
2. This bit is enabled only when operating in programmable waveform generation mode.
3. If executing an instruction which changes this register when the TZOS bit is “1” (during the count), the TZOS is
automatically set to “0” when the count completes while the instruction is executed. If this causes some problems,
execute an instruction which changes this register when the TZOS bit is “0” (one shot stop).
0 : Stops one-shot
1 : Starts one-shot
0 : O u t p u t s p r o g r a m m a b l e w a v e f o r m
1 : O u t p u t s t h e v a l u e o f P 3
( 2 )
0 : Outputs programmable waveform
1 : Outputs the value of P3
( 2 )
e t t i n g r a n g
t o F
0 01
6
F1
t o F
0 01
6
F1
t o F
0 0
1 6
F1
t o F
0 0
1 6
F1
t
FunctionB i t s y m b o l
2
p o r t r e g i s t e r
1
port register
e
R W
6
R W
R W
6
6
R W
R W
6
RW
RW
RW
RW
Figure 12.20 PREZ Register, TZSC Register, TZPR Register, and TYZOC Register
Rev.1.20 Jan 27, 2006 page 89 of 204
REJ09B0062-0120
Loading...