RENESAS M16C-6KA Technical data
M16C/6KA Group
REJ03B0100-0100Z
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Jul 16, 2004
Description
The M16C/6KA group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 144-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. To communicate with host CPU, the LPC bus interface is built in. In this way, this MCU can
work as slave controller in the personal computer system.
Features
• Memory capacity........................................ROM 128K bytes
RAM 5K bytes
• The Min. time of instruction execution .......62.5ns (f(XIN)=16MHz, with 0 wait, Vcc=3.3V)
• Supply voltage ...........................................3.0 to 3.6V (f(XIN)=16MHZ with 0 wait)
• Supply voltage for Program/Erase.............3.0 to 3.6V
(CPU reprogram mode 0, Internal clock=8MHZ with 1 wait)
(CPU reprogram mode 1, Internal clock=4MHZ with 1 wait)
• Low power consumption ............................52.8mW ( f(XIN)=16MHZ, with 0 wait, VCC = 3.3V)
• Interrupts....................................................32 internal and 16 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Key input interrupts ......................................
• Multifunction 16-bit timer............................5 output timers + 6 input timers
• Serial I/O (Serial interface) ........................3 channels (1 for UART or clock synchronous, 2 for clock synchronous)
• Host interface.............................................LPC bus interface X 4
• A-D converter (A/D converter) ...................10 bits X 8 channels (Expandable up to 10 channels)
• PWM ..........................................................8 bits X 6 channels
• Watchdog timer..........................................1
• I2C bus interface ........................................3 channels
• PS/2 interface ............................................3 channels
• Serial interrupt output ................................6 factors (2 fixed factors, 4 programmable factors)
• Programmable I/O .....................................129
• Input port....................................................
• Clock generating circuit .............................1 built-in clock generation circuit
2 (8 inputs shared with 1 interrupt request X 1;
8 inputs (with event latch) shared with1 interrupt request X 1)
_______
1 (P85 shared with NMI pin)
(built-in feedback resistor, and external ceramic)
Rev.1.00
Applications
Notebook PC, others
Rev.1.00 Jul 16, 2004 page 1 of 266
REJ03B0100-0100Z
Specifications written in this manual
are believed to be accurate, but are
not guaranteed to be entirely free of
error.
Specifications in this data sheet may
be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
M16C/6KA Group Description
------Table of Contents------
Central Processing Unit (CPU) .....................13
Reset.............................................................16
Processor Mode............................................ 26
Clock Generating Circuit ...............................29
Protection...................................................... 37
Interrupts....................................................... 38
Watchdog Timer............................................65
Timer............................................................. 67
Serial I/O (Serial interface)............................85
A-D Converter (A/D converter)....................111
PWM Output Circuit ....................................121
LPC Bus Interface....................................... 125
Serial interrupt output..................................143
I2C-BUS Interface........................................154
PS2 Interface ..............................................185
Programmable I/O Ports .............................200
Electrical Characteristics.............................221
Flash Memory Version ................................234
Rev.1.00 Jul 16, 2004 page 2 of 266
REJ03B0100-0100Z
M16C/6KA Group Description
The differences in M16C/6K (144-pin) group
Type name
Pin numbers
M306K7F8LRP(In mass production)
144-pin 144-pin 144-pin
M306K9FCLRP
(In mass production)
M306KAFCLRP(Under development)
RAM
ROM
Built-in ROM area
Address 03B4
Address 03B7
The power supply
for program/erase
FV
CC
16
16
pin
PWM output circuit
2
I
C bus interface
Key input interrupt
3K bytes 5K bytes 5K bytes
NEW DINOR
Flash memory 68K bytes
User ROM area
Address 0EF000
Boot ROM area
Address 0FF000
Flash memory recognition register
After reset 00000000
Flash memory control register
After reset XX000001
16
- 0FFFFF
16
- 0FFFFF
2
2
16
16
Vcc 3.0 - 3.6V
Not exist
NEW DINOR
Flash memory 128K bytes
User ROM area
Address 0E0000
Boot ROM area
Address 0FF000
Flash memory recognition register
After reset XXXXXX10
Flash memory control register
After reset 00000001
Vcc 3.0 - 3.6V
CC
3.0 - 3.6V
FV
The input pin of power supply
for program/erase
16
- 0FFFFF
16
- 0FFFFF
2
16
16
2
NEW DINOR
Flash memory 128K bytes
User ROM area
Address 0E0000
Boot ROM area
Address 0FF000
Flash memory recognition register
After reset XXXXXX11
Flash memory control register
After reset 00000001
Vcc 3.0 - 3.6V
Not exist
14-bit X 4 8-bit X 6 8-bit X 6
2 channels 3 channels
8 inputs shared with 1 interrupt
request X 1
8 inputs (with event latch) shared
with 1 interrupt request X 1
Detected only in the falling edge
Can not be selected with 1 bit unit
8 inputs shared with 1 interrupt
request X 1
8 inputs (with event latch) shared
with 1 interrupt request X 1
Detected in either of the edges by
the edge selection
Can be selected with 1 bit unit
3 channels (I
1 and 2 can changed.)
8 inputs shared with 1 interrupt
request X 1
8 inputs (with event latch) shared
with 1 interrupt request X 1
Detected in either of the edges by
the edge selection
Can be selected with 1 bit unit
16
- 0FFFFF
16
- 0FFFFF
2
C bus interface pin of Channel
16
16
2
2
DMAC
D/A converter
Comparator Circuit
Interrupts
Serial I/O
Clock generation
circuits
Exist (2 channels) Exist (2 channels) Not exist
Exist (8-bit X 2 channels) Exist (8-bit X 2 channels) Not exist
Exist (8 channels) Exist (8 channels) Not exist
31 vector 31 vector
• UART or clock
synchronous X 3
• clock
synchronous X 2
2 circuits 2 circuits
Rev.1.00 Jul 16, 2004 page 3 of 266
REJ03B0100-0100Z
• UART or clock
synchronous X 3
• clock
synchronous X 2
45 vector (add OBE int.)
• UART or clock
synchronous X 1
• clock
synchronous X 2
1 circuit
M16C/6KA Group Description
Pin configuration
Fig. AA-1 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
11
/CLKS
11
/RTS
11
11
11
11
D
D
X
X
/T
/CTS
/CLK
/R
71
81
91
101
/INT
/INT
/INT
/INT
4
5
6
3
P97/AD
P125/INT
P124/INT
P123/INT
P122/INT
P121/INT
P120/INT
P111/F1
P110/F1
P107/AN7/INT
P106/AN6/INT
P105/AN5/INT
P104/AN4/INT
P103/AN3/INT
P102/AN
P101/AN
P100/AN
TRG/SIN40
/INT
P1
P12
P0
P0
P0
P0
P0
P0
P0
P0
P11
P11
P11
P11
P11
P11
OUT1
OUT0
AV
V
AVcc
1
2
P1
P1
P1
108
106
107
0
109
6
110
111
111
112
102
113
92
114
82
115
72
116
61
117
7
118
6
119
5
120
4
121
3
122
2
123
1
124
0
125
7
126
6
127
5
128
4
129
3
130
2
131
132
133
110
100
134
135
90
80
136
137
70
138
2
139
1
140
SS
141
0
142
REF
143
60
144
1 2 3 4 5 6 7 8 910111213141516171819202122232425
0
1
7
P1
P1
P1
P2
P2
P1
100
101
104
105
102
103
M306KAFCLRP
41
/PWM
51
00
/OBF
/PWM
0OUT
5
P13
77
6
P13
76
7
P13
75
TA0
/
0
P4
74
0OUT
/TA1
1
P4
73
72
P4
71
P43/OBF01/SERIRQ
70
P44/PWM01/OBF
69
P4
68
P46/PWM21/OBF3/CLKRUN
V
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
CC
P4
V
SS
P140/KI
P141/KI
P142/KI
P143/KI
P144/KI
P145/KI
P146/KI
P147/KI
P5
P5
P5
P5
P5
P5
P5
P5
P150/TA0
P151/TA1
P152/TA2
P60/SDA
P61/SCL
P62/SDA
P63/SCL
P64/CTS10/RTS10/CLKS
P65/CLK
P66/RXD10/TA3
P67/TXD10/TA4
P70/PS2A
2
/TA2
0OUT/GATEA20
31
10
11
12
13
14
15
16
17
00
01
02
03
04
05
06
OUT
1OUT
1OUT/SIN31
1OUT/SOUT31
0
0
10
10
10
0
1
/KI
07
/CLK
OUT
OUT
5
/PWM11/OBF2/PRST
7
/PWM
0
/KI
/KI
1
/KI
2
/KI
3
/KI
4
/KI
5
/KI
6
/CLK
7
31
10
1
2
0
/LAD
6
7
4
2
3
5
0
SS
P2
P2
V
P2
P2
P2
P2
P3
92
93
94
96
97
95
98
99
3
7
/LAD
/LFRAME
/LRESET
/LCLK
/LAD
/LAD
1
4
5
6
2
3
CC
P12
P3
P3
V
88
89
90
91
7
P3
P3
P3
P3
P3
84
85
86
87
83
26 27 28 29 30 31 32 33 34 35 36
0
P13
82
1
P13
81
2
P13
80
3
P13
79
4
P13
78
10
00
30
20
/PWM
/PWM
/PWM
/PWM
40
0IN
0IN
OUT40
/TB4
/TB3
4
3
P9
P9
/ANEX0/CLK
/ANEX1/S
5
6
P9
P9
Fig. AA-1 Pin configuration (top view)
Rev.1.00 Jul 16, 2004 page 4 of 266
REJ03B0100-0100Z
5
/INT
OUT30
/S
2
P9
4
/INT
IN30
/S
1
P9
3
/INT
30
/CLK
0
P9
40
50
/PWM
/PWM
1IN
1IN
/TB3
/TB4
0
1
P16
P16
IN41
/S
7
P15
OUT41
/S
6
P15
41
/CLK
5
P15
4
P15
3
P15
0
7
1
6
IN
SS
OUT
X
RESET
CC
X
V
V
M
M
P8
P8
/NMI
5
P8
21
/SCL
IN
/TB2
4
P8
21
/SDA
IN
/TB1
3
P8
11
/SCL
IN
/TB0
2
P8
11
/SDA
IN
/TA4
1
P8
20
/ICCK
0
/SCL
IN
P8
/TA3
7
P7
20
/SDA
6
P7
1
2
/PS2B
/PS2B
1
2
/INT
/INT
4
IN
P7
/TA2
5
P7
2
0
/PS2A
/PS2B
2
0
P7
/INT
IN
/TA1
3
P7
1
/PS2A
IN
/TB5
IN
/TA0
1
P7
Package: 144PFB-A
M16C/6KA Group Description
Block Diagram
Fig.AA-2 is a block diagram of the M16C/6KA (144-pin version) group.
I/O ports
Internal peripheral function
Timer
Timer TA0(16 bits)
Timer TA1(16 bits)
Timer TA2(16 bits)
Timer TA3(16 bits)
Timer TA4(16 bits)
Timer TB0(16 bits)
Timer TB1(16 bits)
Timer TB2(16 bits)
Timer TB3(16 bits)
Timer TB4(16 bits)
Timer TB5(16 bits)
Watchdog timer
(15 bits)
PS2 interface
(3 channels)
Serial interrupt output
(6 factors)
Port P0
8
Port P18Port P2
8 8 8 8
A-D converter
(10 bits x 8 channels
Expandable up to 10 channels)
UART/clock synchronous SI/O
(8 bits x 1 channel)
Host interface
(LPC bus interface
x
4 channels)
M16C/60 series 16-bit CPU core
Registers
R0H
R1H R1
R1H R1L
R
R2
R
2
R3
A
3
A0
A
0
A1
FB
1
FB
SB
R0
R0LR0H
L
L
Program counter
PC
Stack pointer
ISP
USP
Vector table
INTB
Flag register
FLG
Port P5Port P4Port P3
System clock generator
IN-XOUT
X
Clock synchronous SI/O
(8 bits x 2channels)
2
I C bus interface
(3 channels)
PWM output
(8 bits x 6channels)
Memory
ROM
(Note1)
RAM
(Note2)
Multiplier
8
Port P6
Port P7
8
Port P8
7
Port P8
5
Port P9
8
Port P10
8
Port P16
2
Note1 : ROM size depends on MCU type.
Note2 : RAM size depends on MCU type.
Port P15
8
Port P14
8
Fig.AA-2 Block diagram of M16C/6KA (144-pin version) group
Rev.1.00 Jul 16, 2004 page 5 of 266
REJ03B0100-0100Z
Port P13
8
Port P12
8
Port P11
8
M16C/6KA Group Description
Performance Outline
Table AA-1 is a performance outline of M16C/6KA (144-pin version) group.
Table AA-1 Performance outline of M16C/6KA (144-pin version) group
Item Performance
Number of basic instructions 91 instructions
The Min. time of instruction execution 62.5ns (f(XIN)=16MHz, with 0 wait, Vcc=3.3V)
Memory ROM (See the figure of ROM Expansion)
capacity RAM 5K bytes
I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1
P11 to P16 8 bitsx5, 2 bitsx1
Input port P85 1 bit x 1
Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5
timer TB0, TB1, TB2, TB3, TB4, TB5 16 bits x 6
Serial I/O UART1 (UART or clock synchronous) x 1
SI/O3, SI/O4 (Clock synchronous) x 2
A-D converter 10 bits x (8 + 2) channels
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 32 internal and 16 external sources, 4 software
sources, 7 levels
Host interface 4 channels (LPC bus interface)
PWM 8 bits x 6
I2C bus interface 3 channels
PS2 interface 3 channels
Serial interrupt output 6 factors (2 fixed factors, 4 programmable factors)
Clock generating circuit 1 built-in clock generation circuit
(built-in feedback resistor, and external ceramic)
Power consumption 52.8mW (3.3V, f(XIN)=16MHz, with 0 wait)
I/O I/O withstand voltage 3.3V
characteristics Output current 5mA
Device configuration CMOS high performance silicon gate
Package 144-pin plastic mold QFP
Rev.1.00 Jul 16, 2004 page 6 of 266
REJ03B0100-0100Z
M16C/6KA Group Description
Renesas plans to release the following products in the M16C/6KA (144-pin version) group:
(1) Support for flash memory version
(2) ROM capacity
(3) Package
144PFB-A : Plastic molded QFP(flash memory version)
ROM Size
(Byte)
External
ROM
256K
128K
96K
80K
64K
32K
Mask ROM version Flash version
M306KAFCLRP
Fig.AA-3 ROM expansion
Table AA-2 Product list From July 2004 up to now
Type No.
M306KAFCLRP
ROM size
128 bytes
RAM size
5K bytes
Package type
144PFB-A
Host Interface
LPC
Remarks
Flash memory (NEW
DINOR) version
Rev.1.00 Jul 16, 2004 page 7 of 266
REJ03B0100-0100Z
M16C/6KA Group Description
Type No.
M30 6KA F C XXX RP
Fig.AA-4 Type No., memory size, and package
Package type
RP : 144PFB-A
ROM No.
ROM type
C : 128Kbytes
Memory type
F : Flash version
M16C/6KA Group
M16C Family
Rev.1.00 Jul 16, 2004 page 8 of 266
REJ03B0100-0100Z
M16C/6KA Group Pin Description
Pin Description
Pin name
Vcc, Vss
____________
RESET
Signal name
Power supply
input
Reset input
I/O type
Input
Function
Apply 3.0 to 3.6 V to VCC . Apply 0V to VSS
A “L” on this input resets the microcomputer.
XIN
XOUT
M0,M1
AVCC
AVSS
VREF
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
Clock input
Clock output
Chip mode
setting
Analog power
supply input
Analog power
supply input
Reference
voltage input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
I/O port P5
Input
Output
Input
Input
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
These pins are provided for the main clock generating circuit.
Connect a ceramic resonator between the XIN and the XOUT
pins. To use an externally derived clock, input it to the XIN pin
and leave the XOUT pin open.
Connect to VSS
This pin is a power supply input for the A-D converter.
Connect this pin to VCC.
This pin is a power supply input for the A-D converter.
Connect this pin to VSS.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port
direction register that allows the user to set each pin for input or output individually. When set for input, the user can
specify in units of four bits via software whether or not they
are tied to a pull-up resistor.
This port supports CMOS input level. And output type supports CMOS 3 state or N channel open drain selectable.
This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as external interrupt pins or UART1 I/O pin selected
by software.
This is an 8-bit I/O port equivalent to P0. (Except that output
type just supports CMOS 3 state only). P20-P27 are available for directly driving LED's.
This is an 8-bit I/O port equivalent to P0. (Except that output
type just supports CMOS 3 state only). The port can be
used for LPC bus interface I/O pins by software selection.
This is an 8-bit I/O port equivalent to P0. (Except that output
type just supports CMOS 3 state only). By software selecting,
the port can also be used for LPC bus interface I/O pins,
Timer A0 to A2 output pins PWM output pins or serial interrupt
output I/O pins. P40 to P46 pins' level can be read regardless
the setting of input port or output port. If P40 or P43 are used
for output ports, the function that clears P40 or P43 to "0" after
the read of output data buffer from host CPU is available.
This is an 8-bit I/O port equivalent to P0. (Except that output type
is CMOS 3 state only). Key on wake interrupt 0 input function
support. P57 in this port outputs a divide-by-8 or divide-by-32
clock of XIN selected by software.
Rev.1.00 Jul 16, 2004 page 9 of 266
REJ03B0100-0100Z
M16C/6KA Group Pin Description
Pin Description
Pin name
P60 to P67
P70 to P77
P80 to P84,
P86,
P87,
P85
P90 to P97
P100 to P107
Signal name
I/O port P6
I/O port P7
I/O port P8
I/O port P85
I/O port P9
I/O port P10
I/O type
Input/output
Input/output
Input/output
Input/output
Input/output
Input
Input/output
Input/output
Function
This is an 8-bit I/O port equivalent to P0. (Except that P60 to
P63's output type is N channel open drain only; P64 to P67's
output type is CMOS 3 state only; P60 to P63 no internal
pull-up register support.) By software selecting, this port
can be used for I2C-BUS interface, UART1 input/output pin,
timerA3, A4 output pin. When P60 to P63 used as I2C-BUS
interface SDA, SCL, the input level of these pins are CMOS/
SMBUS selectable.
This is an 8-bit I/O port equivalent to P0. (Except that P70 to
P77 output type is N channel open drain only; no internal
pull-up register support.) By software selecting, this port
can be used for external interrupt input pin, timerA0 to A3
and timer B5 input pin, PS2 interface input/output pin, I2C
interface input/output pin. P70 to P75 pins' level can be read
regardless of the setting of input port or output port.
P80 to P84, P86, and P87 are I/O ports with the same functions as P0. (Except that P86 to P87's output type is CMOS
3 state only; P80 to P84's output type is N channel open
drain only; P85 is input port only; the P80 to P84 and P85 are
no internal pull-up register support.)
By software selecting, this port can be used for timer A4, B0
to B2, I2C-BUS interface I/O pins. The input level of P81 to
P84 and SDA, SCL inputs can be switched to CMOS/SMBUS
when these pins function as I2C bus interface. P85 is an
______ ______
input-only port that also functions for NMI. The NMI interrupt
is generated when the input at this pin changes from “H” to
______
“L”. The NMI function cannot be cancelled using software.
This is an 8-bit I/O port equivalent to P0. (Except that output
type is CMOS 3 state only.) By software selecting, the port
can be used for external interrupt, timer B3 to B4, A-D converter extended input pins, A-D trigger, SI/O3, SI/O4 I/O
pins, PWM, output pins.
This is an 8-bit I/O port equivalent to P0. (Except that output
type is CMOS 3 state only.) If the ports are set to input
mode, the pull-up resistor can be set in bit unit. By software
selecting, the port can be used for A-D converter, external
interrupt input pins.
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M16C/6KA Group Pin Description
Pin Description
Pin name
P110 to P117
P120 to P127
P130 to P137
P140 to P147
P150 to P157
P160, P161
Signal name
I/O port P11
I/O port P12
I/O port P13
I/O port P14
I/O port P15
I/O port P16
I/O type
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Function
This is an 8-bit I/O port equivalent to P0. By software selecting, P110, P111 also function as clock output pins, which the
frequency is the same with XIN.
This is an 8-bit I/O port equivalent to P0. (Except that outp u t
type is CMOS 3 state only.) By software selecting, this port
can be used for external interrupt input pin.
This is an 8-bit I/O port equivalent to P0. (Except that output
type is N channel open drain only; no internal pull-up register support.)
This is an 8-bit I/O port equivalent to P0. The port can be
used for key on wake-up interrupt 1 input pins. P140 to P143
are available for directly driving LED's. In input mode, the
pull-up register can be set in one bit unit by software.
This is an 8-bit I/O port equivalent to P0. (Except that output
type is CMOS 3 state only.) By software selecting, these
ports can be used for timer A0 to A2's output or SI/O3 and
SI/O4 I/O pins.
This is an 2-bit I/O port equivalent to P0. (Except that output
type is CMOS 3 state only.) By software selecting, this port
can be used for timer B3 and B4 input or PWM output pin.
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M16C/6KA Group Memory
Operation of Functional Blocks
The M16C/6KA (144-pin version) group accommodates certain units in a single chip. These units include
ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/
logic operations. Also peripheral units such as timers, serial I/O, A-D converter, host bus interface, PWM
output, I2C BUS interface, PS2 interface and I/O ports are included.
The following explains each unit.
Memory
Fig.CA-1 is the memory map. The address space extends up to 1M bytes from address 0000016 to FFFFF16.
There is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as
the reset and NMI are mapped from FFFDC16 to FFFFF16. The starting address of the interrupt routine is
stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal
register (INTB). See the section on interrupts for details.
From 0040016 to the address increasing direction RAM is allocated. For example, in the M306KAFCLRP, 5K
bytes of internal RAM is mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM
also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Fig.CA-2 to CA-5 are location of
peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped from FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can
be used as 2-byte instructions, reducing the number of program steps.
_______
00000
16
0040016
017FF16
E000016
FFFFF16
Fig.CA-1 Memory map
Rev.1.00 Jul 16, 2004 page 12 of 266
REJ03B0100-0100Z
SFR area
For details, see
Fig.CA-2 to Fig.CA-4
Internal RAM area
Inhibited
Internal ROM area
FFE0016
FFFDC16
FFFFF16
Special page
vector table
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
M16C/6KA Group CPU
A
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Fig.BA-1 Seven of these registers (R0, R1, R2, R3, A0, A1, and
FB) come in two sets; therefore, these have two register banks.
R0
R1
R2
R3
A0
A1
FB
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
b15
b15
b15
b15
b15
b15
b15
b8 b7 b0
H
b8 b7 b0
H
L
b19
L
PC
b0
Program counter
Data
b0
registers
INTB
b19
H
b0
L
Interrupt table
register
b0
b0
b15
USP
b15
ISP
b0
User stack pointer
b0
Interrupt stack
pointer
Address
b0
registers
b15
SB
b0
Static base
register
b0
Frame base
b15
FLG
b0
Flag register
register
IPL
CDZSBOIU
Note: These registers consist of two register banks.
Fig.BA-1 Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and
low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be u2sed for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.1.00 Jul 16, 2004 page 13 of 266
REJ03B0100-0100Z
M16C/6KA Group CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured
with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This
flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Fig.BA-2 shows the flag register
(FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to
“0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0”
when the interrupt is acknowledged.
Rev.1.00 Jul 16, 2004 page 14 of 266
REJ03B0100-0100Z
M16C/6KA Group CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this
flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt No. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with the three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is
enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
IPL
b0b15
Flag register (FLG)
CDZSBOIU
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level (CPU)
Reserved area
Fig.BA-2 Flag register (FLG)
Rev.1.00 Jul 16, 2004 page 15 of 266
REJ03B0100-0100Z
M16C/6KA Group RESET
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains the hardware reset.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Fig.VB-1 shows the example reset circuit. Fig.VB-2 shows the reset sequence.
RESET
Example when V
Fig.VB-1 Example reset circuit
X
IN
More than 20 cycles are needed
RESET
Internal
clock Φ
Single chip
mode
Address
BCLK 24cycles
V
CC
CC
= 3.3V
RESET
FFFFC
3.3V
V
CC
0V
3.3V
0V
16
FFFFE
3.0V
0.6V
Content of reset vector
16
Fig.VB-2 Reset sequence
Rev.1.00 Jul 16, 2004 page 16 of 266
REJ03B0100-0100Z
M16C/6KA Group RESET
Table VB-1 shows the statuses of the other pins while the RESET pin level is “L”. Fig.VB-3 and VB-4 show
____________
the internal status of the microcomputer immediately after the reset is cancelled.
Table VB-1 Pin status when RESET pin level is “L”
____________
Status
Pin name
P0
P1
P2, P3, P4
P4
4
P45 to P4
P5
0
P5
1
P5
2
0
7
to P4
I/O port (floating)
I/O port (floating)
3
I/O port (floating)
I/O port (floating)
I/O port (floating)
I/O port (floating)
I/O port (floating)
I/O port (floating)
CNVSS = V
(M0)
SS
P5
3
P5
4
P5
5
P5
6
P5
7
P6, P7, P80 to P84,
P86, P87, P9, P10
P11, P12, P13, P14
P15, P16
I/O port (floating)
I/O port (floating)
I/O port (floating)
I/O port (floating)
I/O port (floating)
I/O port (floating)
I/O port (floating)
I/O port (floating)
Rev.1.00 Jul 16, 2004 page 17 of 266
REJ03B0100-0100Z
M16C/6KA Group RESET
(1) (0004
(2) (000516)···Processor mode register 1
(3) (0006
(4) (0007
(5) (0009
Protect register (000A
(6)
(7)
(8) (0010
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Timer A0 interrupt control register
(16)
(17)
(18)
Timer A3 interrupt control register
(19)
(20)
Timer A4 interrupt control register (004E
Timer B0 interrupt control register (004F
(21)
Timer B1 interrupt control register (0050
(22)
(23)
Timer B2 interrupt control register
(24)
Timer B3 interrupt control register
Timer B4 interrupt control register
(25)
(000F16)···Watchdog timer control register
(0011
(0012
(0014
(0015
(0016
(0041
(0044
(0045
(0046
(0047
(0048
(004A
(004B
(004C
(004D
(0051
(0052
(0053
16
)···Processor mode register 0
10000100
16
)···System clock control register 0
00010000
16
)···System clock control register 1
16
)···Address match interrupt enable register
16
)···
00?0????
16
)···Address match interrupt register 0
16
)···
16
)···
16
)···Address match interrupt register 1
16
)···
16
)···
16
)···LRESET interrupt control register
16
)···A-D interrupt control register
16
)···IBF0 interrupt control register
16
)···IBF1 interrupt control register
16
)···IBF2 interrupt control register
16
)···IBF3 interrupt control register
16
)···
16
)···Timer A1 interrupt control register
16
)···Timer A2 interrupt control register
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
00
16
000
00
16
00
16
0
00
16
00
16
0
?000
?000
?000
?000
?000
?000
? 000
? 000
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 000
? 0 0 0
000
0 0 0
0 0 0
000?
(26)
Timer B5 interrupt control register (0054
000
(27)
OBE interrupt control register
(28)
PS20 interrupt control register (0056
PS21 interrupt control register
(29)
(30)
00
PS22 interrupt control register
(31)
UART1 receive interrupt control register
UART1 transmit interrupt control register
(32)
(33)
Key input 0 interrupt control register
(34)
Key input 1 interrupt control register
(35)
SI/O3 interrupt control register
(36)
SI/O4 interrupt control register
2
(37)
C0 interrupt control register
I
(38)
SCL0, SDA0 interrupt control register
2
(39)
C1 interrupt control register
I
(40)
SCL1, SDA1 interrupt control register
2
(41)
C2 interrupt control register
I
(42)
SCL2, SDA2 interrupt control register
(43)
INT0 interrupt control register
(44)
INT1 interrupt control register
(45)
INT2 interrupt control register
(46)
INT3 interrupt control register
(47)
INT4 interrupt control register
(48)
INT5 interrupt control register (006E16)···
(49)
INT6 interrupt control register
(50)
INT7 interrupt control register
(51)
INT8 interrupt control register
(52)
INT9 interrupt control register
(53)
INT10 interrupt control register
(54)
INT11 interrupt control register
(0055
(0057
(0058
(005B
(005C
(005F
(0060
(0061
(0062
(0063
(0064
(0065
(0066
(0067
(0068
(0069
(006A
(006B
(006C
(006D
(006F
(0070
(0071
(0072
(0073
(0074
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
00
00
00
00
00
00
00
00
00
00
00
00
? 000
? 0 0 0
? 0 0 0
? 0 0 0
? 000
? 000
? 000
? 0 0 0
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
? 000
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Fig.VB-3 Device's internal status after a reset is cleared (1)
Rev.1.00 Jul 16, 2004 page 18 of 266
REJ03B0100-0100Z
M16C/6KA Group RESET
(55)
(56)
(57)
(58)
(59)
(60)
PS21 control register (02A6
(61)
(62)
(63)
PS22 control register
(64)
PS2 mode register
(65)
Data bus buffer status register 1
(66)
(67)
Data bus buffer status register 2
(68)
(69)
(70)
GateA20 control register
(71)
Port P11 direction register
(72)
Port P12 direction register
(73)
Port P13 direction register
(74)
Port P14 direction register
(75)
Port P15 direction register
(76)
Port P16 direction register
(77)
Port function selection register 0
(78)
Port function selection register 1
(79)
Port P4 input register
(80)
Port P7 input register
(81)
Pull-up control register 3
(82)
Pull-up control register 4
(83)
Port control register 1
(84)
Port control register 2
(02A0
16
(02A116)···PS20 status register
16
(02A2
16
(02A4
16
(02A5
16
16
(02A8
(02A916)···PS22 status register
16
)···
(02AA
16
(02AC
16
(02C1
(02C3
16
16
(02C5
(02C716)···Data bus buffer status register 3
16
(02C9
(02CA
16
16
(02E2
(02E3
16
(02E616)···
16
(02E7
(02EA
16
)···
(02EB
16
)···
(02F8
16
)···
16
)···
(02F9
(02FA
16
16
(02FB
16
(02FC
16
(02FD
16
(02FE
16
(02FF
00
0
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
0 0
00
16
00
16
00
16
00
16
00
16
00
16
PWM control register 0
(85)
PWM control register 1
(86)
2
I
C2 address register
(87)
2
C2 control register 0
I
(88)
2
I
C2 clock control register
(89)
2
C2 start/stop condition
I
(90)
control register
2
(91)
C2 control register 1
I
2
C2 control register 2
I
(92)
2
(93)
C2 status register
I
2
C0 address register
I
(94)
2
C0 control register 0
I
(95)
2
I
C0 clock control register
(96)
2
I
C0 start/stop condition
(97)
control register
2
I
C0 control register 1
(98)
2
I
C0 control register 2
(99)
2
C0 status register
I
(100)
2
C1 address register
I
(101)
2
C1 control register 0
I
(102)
2
C1 clock control register
I
(103)
2
C1 start/stop condition
I
(104)
control register
2
I
C1 control register 1
(105)
2
I
C1 control register 2
(106)
2
C1 status register
I
(107)
(108)
TimerB3,4,5 count start flag
TimerB3 mode register
(109)
(110)
TimerB4 mode register
(111)
TimerB5 mode register
(112)
Interrupt factor selection register 1
Interrupt factor selection register 0
(113)
(114)
SI/O3 control register
SI/O4 control register
(115)
(030C
(030D
(0312
(0313
(0314
(0315
(0316
(0317
(0318
(0322
(0323
(0324
(0325
(0326
(0327
(0328
(0332
(0333
(0334
(0335
(0336
(0337
(0338
(0340
(035B
(035C
(035D
(035E
(035F
(0362
(0366
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
)···PS20 shift register
)···PS20 control register
)···PS21 shift register
)···PS21 status register
)···
)···PS22 shift register
)···
)···Data bus buffer status register 0
)···
)···
)···Data bus buffer control register 1
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
00
16
00
16
00
16
00
16
00
16
1A
16
30
16
00
16
00 00001
00
16
00
16
00
16
1A
16
30
16
00
16
00 1 0000
00
16
00
16
00
16
1A
16
30
16
00
16
00 1 0000
0 00
00 ? 0000
00 ? 0000
00 ? 0000
00
16
00
16
40
16
40
16
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Fig.VB-4 Device's internal status after a reset is cleared (2)
Rev.1.00 Jul 16, 2004 page 19 of 266
REJ03B0100-0100Z
M16C/6KA Group RESET
Count start flag
(116)
One-shot start flag
(117)
Trigger select flag
(118)
(119)
Up-down flag
Timer A0 mode register
(120)
(121)
Timer A1 mode register
(122)
Timer A2 mode register
(123)
Timer A3 mode register
(124)
Timer A4 mode register
Timer B0 mode register
(125)
(126)
Timer B1 mode register
Timer B2 mode register
(127)
UART1 transmit/receive mode register
(128)
(129)
UART1 transmit/receive control register 0
(130)
UART1 transmit/receive control register 1
(131)
UART transmit/receive control register 2
Flash memory recognition register (Note1)
(132)
(133)
Flash memory control register1 (Note1)
(134)
Flash memory control register0 (Note1)
(135)
A-D control register 2
A-D control register 0
(136)
A-D control register 1
(137)
(038016)···
(0382
16)···
16)···
(0383
(0384
16)···
(0396
16)···
(0397
16)···
16)···
(0398
16)···
(0399
(039A
16)···
(039B
16)···
16)···
(039C
16)···
(039D
(03A8
16)···
16)···
(03AC
16)···
(03AD
(03B0
16)···
16)···
(03B4
(03B5
16)···
16)···
(03B7
16)···
(03D4
(03D6
16)···
16)···
(03D7
0016
0000000
0016
0016
0016
0016
0016
0016
0016
0
0? 0000
00? 0000
00? 0000
0016
000 1000
0
000 0010
0
0
000000
1
0
00
0
000010
0
0
000 00001
000 0???0
0016
(03E2
(03E3
(03E6
(03E7
(03EA
(03EB
(03EE
(03EF
(03F2
(03F3
(03F6
(03FC
(03FD
(03FE
(03FF
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
Port P0 direction register
(138)
Port P1 direction register
(139)
Port P2 direction register
(140)
Port P3 direction register
(141)
Port P4 direction register
(142)
Port P5 direction register
(143)
Port P6 direction register
(144)
Port P7 direction register
(145)
Port P8 direction register
(146)
(147)
Port P9 direction register
Port P10 direction register
(148)
(149)
Pull-up control register 0
(150)
Pull-up control register 1
Pull-up control register 2
(151)
Port control register 0
(152)
(153)
Data registers (R0/R1/R2/R3)
(154)
1
Address registers (A0/A1)
Frame base register (FB)
(155)
Interrupt table register (INTB)
(156)
(157)
User stack pointer (USP)
(158)
Interrupt stack pointer (ISP)
(159)
Static base register (SB)
(160)
Flag register (FLG)
0016
0016
0016
0016
0016
0016
0016
0016
00 00000
0016
0016
0016
0016
0016
0016
000016
000016
000016
0000016
000016
000016
000016
000016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
(Note1) This register exists only in the flash memory version.
Fig.VB-5 Device's internal status after a reset is cleared (3)
Rev.1.00 Jul 16, 2004 page 20 of 266
REJ03B0100-0100Z
M16C/6KA Group RESET
Serial interrupt control register 0
(161)
(162)
Serial interrupt control register 1
(163)
IRQ request register 0
(164)
IRQ request register 1
(165)
IRQ request register 2
(166)
IRQ request register 3
(167)
IRQ request register 4
Serial interrupt control register 2
(168)
LPC1 address register L
(169)
(170)
LPC1 address register H
LPC2 address register L
(171)
(172)
LPC2 address register H
LPC3 address register L
(173)
(174)
LPC3 address register H
(175)
LPC control register
Port function selection register 2
(176)
(177)
Pull-up resistor control register 5
Pull-up resistor control register 6
(178)
(179)
Key input interrupt 1 enable register
(180)
Key input interrupt 1 edge selection register
P14 event register
(181)
Port control register 3
(182)
16
(02B0
(02B116)···
16
(02B2
(02B3
16
16
(02B4
16
(02B5
(02B6
16
16
(02B7
(02D016)···
16
(02D1
16
(02D2
16
(02D3
(02D4
16
16
(02D5
16
(02D6
(02F116)···
(02F2
16
16
(02F3
16
(02F4
16
(02F5
16
(02F6
16
(02F7
00
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
)···
16
00
16
00
16
00
16
00
16
00
16
00
16
10
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must
therefore be set.
Fig.VB-6 Device's internal status after a reset is cleared (4)
Rev.1.00 Jul 16, 2004 page 21 of 266
REJ03B0100-0100Z
M16C/6KA Group SFR
0000
16
0001
16
0002
16
0003
16
Processor mode register 0 (PM0)
0004
16
0005
16
Processor mode register 1(PM1)
0006
16
System clock control register 0 (CM0)
0007
16
System clock control register 1 (CM1)
0008
16
0009
16
Address match interrupt enable register (AIER)
000A
16
Protect register (PRCR)
000B
16
000C
16
000D
16
000E
16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
000F
16
0010
16
Address match interrupt register 0 (RMAD0)
0011
16
0012
16
0013
16
0014
16
Address match interrupt register 1 (RMAD1)
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0040
16
0041
16
LRESET interrupt control register (LRSTIC)
0042
16
0043
16
A-D interrupt control register (A-DIC)
0044
16
0045
16
IBF0 interrupt control register (IBF0IC)
IBF1 interrupt control register (IBF1IC)
0046
16
IBF2 interrupt control register (IBF2IC)
0047
16
IBF3 interrupt control register (IBF3IC)
0048
16
0049
16
Timer A0 interrupt control register (TA0IC)
004A
16
004B
16
Timer A1 interrupt control register (TA1IC)
004C
16
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
004D
16
Timer A4 interrupt control register (TA4IC)
004E
16
Timer B0 interrupt control register (TB0IC)
004F
16
Timer B1 interrupt control register (TB1IC)
0050
16
0051
16
Timer B2 interrupt control register (TB2IC)
Timer B3 interrupt control register (TB3IC)
0052
16
Timer B4 interrupt control register (TB4IC)
0053
16
Timer B5 interrupt control register (TB5IC)
0054
16
OBE interrupt control register (OBEIC)
0055
16
0056
16
PS20 interrupt control register (PS20IC)
PS21 interrupt control register (PS21IC)
0057
16
PS22 interrupt control register (PS22IC)
0058
16
0059
16
005A
16
UART1 receive interrupt control register (S1RIC)
005B
16
UART1 transmit interrupt control register (S1TIC)
005C
16
005D
16
005E
16
Key input interrupt 0 control register (KUP0IC)
005F
16
Key input interrupt 1 control register (KUP1IC)
0060
16
SI/O3 interrupt control register (S3IC)
0061
16
SI/O4 interrupt control register (S4IC)
0062
16
2
I
0063
0064
0065
0066
0067
0068
0069
006A
006B
006C
006D
006E
006F
0070
0071
0072
0073
0074
027E
027F
C0 interrupt control register (IIC0IC)
16
SCL0,SDA0 interrupt control register (SCLDA0IC)
16
I2C1 interrupt control register (IIC1IC)
16
SCL1,SDA1 interrupt control register (SCLDA1IC)
16
I2C2 interrupt control register (IIC2IC)
16
SCL2,SDA2 interrupt control register (SCLDA2IC)
16
INT0 interrupt control register (INT0IC)
16
INT1 interrupt control register (INT1IC)
16
INT2 interrupt control register (INT2IC)
16
INT3 interrupt control register (INT3IC)
16
INT4 interrupt control register (INT4IC)
16
INT5 interrupt control register (INT5IC)
16
INT6 interrupt control register (INT6IC)
16
INT7 interrupt control register (INT7IC)
16
INT8 interrupt control register (INT8IC)
16
INT9 interrupt control register (INT9IC)
16
INT10 interrupt control register (INT10IC)
16
INT11 interrupt control register (INT11IC)
16
16
16
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-2 Location of peripheral unit control registers (1)
Rev.1.00 Jul 16, 2004 page 22 of 266
REJ03B0100-0100Z
M16C/6KA Group SFR
0280
16
0281
16
0282
16
0283
16
0284
16
0285
16
0286
16
0287
16
0288
16
0289
16
028A
16
028B
16
028C
16
028D
16
028E
16
028F
16
0290
16
0291
16
0292
16
0293
16
0294
16
0295
16
0296
16
0297
16
0298
16
0299
16
029A
16
029B
16
029C
16
029D
16
029E
16
029F
16
PS20 shift
02A0
16
PS20 status
02A1
16
PS20 control register (PS20CON)
02A2
16
02A3
16
PS21 shift
02A4
16
PS21 status
02A5
16
PS21 control register (PS21CON)
02A6
16
02A7
16
PS22 shift
02A8
16
PS22 status
02A9
16
PS22 control register (PS22CON)
02AA
16
02AB
16
PS2 mode register (PS2MOD)
02AC
16
02AD
16
02AE
16
02AF
16
Serial Interrupt control register 0 (SERCON0)
02B0
16
Serial Interrupt control register 1 (SERCON1)
02B1
16
IRQ request register 0 (IRQ0)
02B2
16
IRQ request register 1 (IRQ1)
02B3
16
IRQ request register 2 (IRQ2)
02B4
16
IRQ request register 3 (IRQ3)
02B5
16
IRQ request register 4 (IRQ4)
02B6
16
Serial Interrupt control register 2 (SERCON2)
02B7
16
02B8
16
02B9
16
02BA
16
02BB
16
02BC
16
02BD
16
02BE
16
02BF
16
register
register
register
register
register
register
(PS20SR)
(PS21SR)
(PS22SR)
(PS20STS)
(PS21STS)
(PS22STS)
02C0
16
Data bus buffer register0 (DBB0)
02C1
16
Data bus buffer status register0 (DBBSTS0)
02C2
16
Data bus buffer register1 (DBB1)
02C3
16
Data bus buffer status register1 (DBBSTS1)
02C4
16
Data bus buffer register2 (DBB2)
02C5
16
Data bus buffer status register2 (DBBSTS2)
02C6
16
Data bus buffer register3 (DBB3)
02C7
16
Data bus buffer status register3 (DBBSTS3)
02C8
16
02C9
16
Data bus buffer control register1 (DBBCON1)
Gate A20 control register (GA20CON)
02CA
16
02CB
16
02CC
16
02CD
16
02CE
16
02CF
16
LPC1 address registerL (LPC1ADL)
02D0
16
02D1
16
LPC1 address registerH (LPC1ADH)
LPC2 address registerL (LPC2ADL)
02D2
16
LPC2 address registerH (LPC2ADH)
02D3
16
LPC3 address registerL (LPC3ADL)
02D4
16
LPC3 address registerH (LPC3ADH)
02D5
16
LPC control register (LPCCON)
02D6
16
02D7
16
02D8
16
02D9
16
02DA
16
02DB
16
02DC
16
02DD
16
02DE
16
02DF
16
02E0
16
Port P11 (P11)
02E1
16
Port P12 (P12)
02E2
16
Port P11 direction register (PD11)
02E3
16
Port P12 direction register (PD12)
02E4
16
Port P13 (P13)
02E5
16
Port P14 (P14)
Port P13 direction register (PD13)
02E6
16
Port P14 direction register (PD14)
02E7
16
02E8
16
Port P15 (P15)
02E9
16
Port P16 (P16)
Port P15 direction register (PD15)
02EA
16
02EB
16
Port P16 direction register (PD16)
02EC
16
02ED
16
02EE
16
02EF
16
02F0
16
Port function selection register 2 (PSL2)
02F1
16
02F2
16
Pull-up resistor control register 5 (PUR5)
02F3
16
Pull-up resistor control register 6 (PUR6)
Key input interrupt 1 enable register (KIN1EN)
02F4
16
Key input interrupt 1 edge selection regiter (KINSEL)
02F5
16
P14 event register (P14EV)
02F6
16
Port control register3 (PCR3)
02F7
16
Port function selection register0 (PSL0)
02F8
16
Port function selection register1 (PSL1)
02F9
16
Port P4 input register (P4PIN)
02FA
16
02FB
16
Port P7 input register (P7PIN)
02FC
16
Pull-up control register3 (PUR3)
Pull-up control register4 (PUR4)
02FD
16
Port control register1 (PCR1)
02FE
16
Port control register2 (PCR2)
02FF
16
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-3 Location of peripheral unit control registers (2)
Rev.1.00 Jul 16, 2004 page 23 of 266
REJ03B0100-0100Z
M16C/6KA Group SFR
030016
PWM0 prescaler (PREPWM0)
030116
PWM0 register (PWM0)
030216
PWM1 prescaler (PREPWM1)
030316
PWM1 register (PWM1)
PWM2 prescaler (PREPWM2)
030416
030516
PWM2 register (PWM2)
030616
PWM3 prescaler (PREPWM3)
030716
PWM3 register (PWM3)
030816
PWM4 prescaler (PREPWM4)
030916
PWM4 register (PWM4)
030A16
PWM5 prescaler (PREPWM5)
030B16
PWM5 register (PWM5)
030C16
PWM control register 0 (PWMCON0)
030D16
PWM control register 1 (PWMCON1)
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
2
I
C2 data shift register (S02)
2
C2 address register (S0D2)
I
2
C2 control register 0 (S1D2)
I
2
I
C2 clock control register (S22)
2
I
C2 start/stop condition control register (S2D2)
2
C2 control register 1 (S3D2)
I
2
I
C2 control register 2 (S4D2)
2
C2 status register (S12)
I
2
C
0 data
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
shift register (S00)
C0 address register (S0D0)
C0 control register0 (S1D0)
C0 clock control register (S20)
C0 start/stop condition control register (S2D0)
C0 control register1 (S3D0)
C0 control register2 (S4D0)
C0 status register (S10)
C
1 data
shift register (S01)
C1 address register (S0D1)
C1 control register0 (S1D1)
C1 clock control register (S21)
C1 start/stop condition control register (S2D1)
C1 control register1 (S3D1)
C1 control register2 (S4D1)
C1 status register (S11)
034016
TimerB3,4,5 count start flag (TBSR)
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
TimerB3 register (TB3)
035116
035216
TimerB4 register (TB4)
035316
035416
TimerB5 register (TB5)
035516
035616
035716
035816
035916
035A16
TimerB3 mode register (TB3MR)
035B16
TimerB4 mode register (TB4MR)
035C16
TimerB5 mode register (TB5MR)
035D16
Interrupt event select register 1 (IFSR1)
035E16
035F16
Interrupt event select register 0 (IFSR0)
036016
SI/O3 transmit/receive register (S3TRR)
036116
036216
SI/O3 control register (S3C)
036316
SI/O3 communication speed register (S3BRG)
036416
SI/O4 transmit/receive register (S4TRR)
036516
036616
SI/O4 control register (S4C)
036716
SI/O4 communication speed register (S4BRG)
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-4 Location of peripheral unit control registers (3)
Rev.1.00 Jul 16, 2004 page 24 of 266
REJ03B0100-0100Z
M16C/6KA Group SFR
03C0
0380
16
Count start flag
0381
16
One-shot start flag
0382
16
Trigger select register
0383
16
Up-down flag
0384
16
0385
16
0386
16
TimerA0
0387
16
0388
16
TimerA1
0389
16
038A
16
TimerA2
038B
16
038C
16
TimerA3
038D
16
038E
16
TimerA4
038F
16
0390
16
TimerB0
0391
16
0392
16
TimerB1
0393
16
0394
16
TimerB2
0395
16
TimerA0 mode register
0396
16
TimerA1 mode register
0397
16
TimerA2 mode register
0398
16
0399
16
TimerA3 mode register
TimerA4 mode register
039A
16
TimerB0 mode register
039B
16
TimerB1 mode register
039C
16
TimerB2 mode register
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
UART1 transmit/receive mode register (U1MR)
03A8
16
UART1 communication speed register (U1BRG)
03A9
16
03AA
16
UART1 tranmit buffer register (U1TB)
03AB
16
UART1 transmit/receive control register0 (U1C0)
03AC
16
UART1 transmit/receive control register1 (U1C1)
03AD
16
03AE
16
UART1 receive buffer register (U1RB)
03AF
16
UART transmit/receive control register2 (UCON)
03B0
16
03B1
16
03B2
16
03B3
16
Flash memory identification register (FTR)
03B4
16
Flash memory control register1 (FMR1)
03B5
16
03B6
16
Flash memory control register0 (FMR0)
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
(TA0)
(TA1)
(TA2)
(TA3)
(TA4)
(TB0)
(TB1)
(TB2)
(TABSR)
(UDF)
(ONSF)
(TRGSR)
(TA0MR)
(TA1MR)
(TA2MR)
(TA3MR)
(TA4MR)
(TB0MR)
(TB1MR)
(TB2MR)
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
16
A-D register0 (AD0)
03C1
16
03C2
16
A-D register1 (AD1)
03C3
16
03C4
16
A-D register2 (AD2)
03C5
16
03C6
16
A-D register3 (AD3)
03C7
16
03C8
16
A-D register4 (AD4)
03C9
16
03CA
16
A-D register5 (AD5)
03CB
16
03CC
16
A-D register6 (AD6)
03CD
16
03CE
16
A-D register7 (AD7)
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
A-D control register2 (ADCON2)
03D4
16
03D5
16
03D6
16
A-D control register0 (ADCON0)
03D7
16
A-D control register1 (ADCON1)
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
Port P0 (P0)
03E1
16
Port P1 (P1)
Port P0 direction register (P0D)
03E2
16
03E3
16
Port P1 direction register (P1D)
03E4
16
Port P2 (P2)
03E5
16
Port P3 (P3)
Port P2 direction register (P2D)
03E6
16
03E7
16
Port P3 direction register (P3D)
03E8
16
Port P4 (P4)
Port P5 (P5)
03E9
16
Port P4 direction register (P4D)
03EA
16
Port P5 direction register (P5D)
03EB
16
03EC
16
Port P6 (P6)
Port P7 (P7)
03ED
16
Port P6 direction register (P6D)
03EE
16
Port P7 direction register (P7D)
03EF
16
Port P8 (P8)
03F0
16
Port P9 (P9)
03F1
16
Port P8 direction register (P8D)
03F2
16
Port P9 direction register (P9D)
03F3
16
Port P10 (P10)
03F4
16
03F5
16
Port P10 direction register (P10D)
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
Pull-up control register0 (PUR0)
Pull-up control register1 (PUR1)
03FD
16
Pull-up control register2 (PUR2)
03FE
16
Port control register0 (PCR0)
03FF
16
Fig.CA-5 Location of peripheral unit control registers (4)
Rev.1.00 Jul 16, 2004 page 25 of 266
REJ03B0100-0100Z
M16C/6KA Group
Software Reset
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are retained.
Processor Mode
(1) Types of Processor Mode
The single-chip mode is supported in processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed.
Ports P0 to P16 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions.
Fig. BG-1 shows the structure of processor mode register 0 and processor mode register 1.
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol Address When reset
PM0 0004
PM00
PM01
Reserved bit Must always be set to “0”
PM03
Reserved bit Must always be set to “0”
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol Address When reset
PM1 0005
0
Reserved bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out
to be indeterminate.
16
Bit name FunctionBit symbol
Processor mode bit
Software reset bit
16
Bit name FunctionBit symbol
00
16
(Note 2)
b1 b0
0 0: Single-chip mode
0 1: Inhibited
1 0: Inhibited
1 1: Inhibited
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
00000XX0
2
Must always be set to “0”
WR
WR
Reserved bit
PM17 Wait bit
Note 1: Set bit 1 of the protect register (address 000A
Fig.BG-1 Processor mode register 0 and 1
Rev.1.00 Jul 16, 2004 page 26 of 266
REJ03B0100-0100Z
values to this register.
Must always be set to “0”
0 : No wait state
1 : Wait state inserted
16
) to “1” when writing new
M16C/6KA Group
Bus control
Bus control
(1) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) .
A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode
register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle
is executed in 2 BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”.
Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency)
of the electric characteristics.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.
Table.EF-1 shows the software wait and bus cycles. Fig.EF-1 shows example bus timing when using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table.EF-1 Software waits and bus cycles
Area Wait bit
SFR
Internal
ROM/RAM
Invalid 2 BCLK cycles
0 1 BCLK cycle
1 2 BCLK cycles
Bus cycle
Rev.1.00 Jul 16, 2004 page 27 of 266
REJ03B0100-0100Z
M16C/6KA Group
Bus control
No wait
With wait
BCLK
Write signal
Read signal
Data bus
Address bus
Chip select
BCLK
Write signal
Read signal
Bus cycle
(Note 1)
Address
Bus cycle
(Note 1)
Output
Bus cycle
(Note 1)
Input
Address
Bus cycle
(Note 1)
Data bus
Address bus
Address
Chip select
Note 1: This timing sample shows the lenth of bus cycle. It is possible that the read cyles, write cycle
comes after this cycle in succession.
Fig.EF-1 Typical bus timings using software wait
Output
Input
Address
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M16C/6KA Group
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table.WA-1 Main clock generating circuits
Main clock generating circuit
Use of clock • CPU’s operating clock source
• Internal peripheral units’
operating clock source
Usable oscillator Ceramic oscillator
Pins to connect oscillator XIN, XOUT
Oscillation stop/restart function Available
Oscillator status immediately after reset Oscillating
Other Externally derived clock can be input
Example of oscillator circuit
Fig.WA-1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit,
and the other one using an externally derived clock for input. Circuit constants in Fig.WA-1 vary with oscillator used. Use the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
X
IN
C
IN
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Apply the feedback register between X
X
OUT
(Note)
R
d
C
OUT
IN
and X
OUT
if required by oscillator maker.
Fig.WA-1 Examples of main clock
Microcomputer
(Built-in feedback resistor)
X
IN
Externally derived clock
Vcc
Vss
X
OUT
Open
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M16C/6KA Group
Clock Generating Circuit
Clock Control
Fig.WA-2 shows the block diagram of the clock generating circuit.
RESET
Software reset
NMI
Interrupt request
level judgment
output
CM10 “1”
Write signal
WAIT instruction
Q
S
R
QS
R
X
IN
Main clock
X
OUT
CM02
f
1
f
AD
f
8
f
32
c
b
Divider
d
a
f1SIO2
f8SIO2
f32SIO2
BCLK
CM0i : Bit i at address 0006
CM1i : Bit i at address 0007
Fig.WA-2 Clock generating circuit
b
a
16
16
1/2 1/2 1/2 1/2
CM06=0
CM17,CM16=10
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
CM06=1
CM06=0
CM17,CM16=11
Details of divider
c
1/2
d
Rev.1.00 Jul 16, 2004 page 30 of 266
REJ03B0100-0100Z
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