Renesas M16C/62P, M16C/62PT Hardware Manual
OCO
R
6C
6C/60 S
S
REJ09B0185-0230Z
M16C/62P Group
(M16C/62P, M16C/62PT)
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICR
M1
FAMILY / M1
MPUTE
ERIE
Before using this material, please visit our website to verify that this is the most
updated document available.
Rev. 2.30
Revision date: Sep 01, 2004
www.renesas.com
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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How to Use This Manual
1. Introduction
This hardware manual provides detailed information on the M16C/62P Group (M16C/62P, M16C/62PT) of
microcomputers.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol Address After Reset
XXX XXX 00h
Bit Symbol
XXX0
XXX1
(b2)
(b4 - b3)
XXX5
XXX6
XXX7
*1
Bit Name
b1b0
0 0: XXX
XXX Bit
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
Reserved Bit
XXX Bit
XXX Bit
0 1: XXX
1 0: Do not set a value
1 1: XXX
Set to "0"
Function varies depending on mode
of operation
0: XXX
1: XXX
Function
*5
*1
Blank:Set to "0" or "1" according to the application
0: Set to "0"
1: Set to "1"
X: Nothing is assigned
*2
RW: Read and write
RO: Read only
WO: Write only
–: Nothing is assigned
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to "0" when writing to this bit.
• Do not set to this value
The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
*5
Follow the text in each manual for binary and hexadecimal notations.
RW
*2
RW
RW
*3
WO
*4
RW
RW
RO
3. M16C Family Documents
The following documents were prepared for the M16C family.
Document Contents
Short Sheet Hardware overview
Data Sheet Hardware overview and electrical characteristics
Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts)
Software Manual Detailed description of assembly instructions and microcomputer per-
formance of each instruction
Application Note • Application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
RENESAS TECHNICAL UPDATE
Preliminary report about the specification of a product, a document,
etc.
NOTES :
1. Before using this material, please visit the our website to confirm that this is the most current document
available.
(1)
Table of Contents
1. Overview ___________________________________________________ 1
1.1 Applications .................................................................................................................1
1.2 Performance Outline....................................................................................................2
1.3 Block Diagram..............................................................................................................5
1.4 Product List ..................................................................................................................7
1.5 Pin Configuration.......................................................................................................13
1.6 Pin Description...........................................................................................................17
2. Central Processing Unit (CPU) ________________________________ 22
2.1 Data Registers (R0, R1, R2 and R3)..........................................................................22
2.2 Address Registers (A0 and A1) ................................................................................22
2.3 Frame Base Register (FB) .........................................................................................23
2.4 Interrupt Table Register (INTB)................................................................................. 23
2.5 Program Counter (PC) ...............................................................................................23
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)..................................23
2.7 Static Base Register (SB)..........................................................................................23
2.8 Flag Register (FLG)....................................................................................................23
2.8.1 Carry Flag (C Flag)..........................................................................................................................23
2.8.2 Debug Flag (D Flag) ........................................................................................................................ 23
2.8.3 Zero Flag (Z Flag)............................................................................................................................23
2.8.4 Sign Flag (S Flag)............................................................................................................................23
2.8.5 Register Bank Select Flag (B Flag) ............................................................................................... 23
2.8.6 Overflow Flag (O Flag)....................................................................................................................23
2.8.7 Interrupt Enable Flag (I Flag) .........................................................................................................23
2.8.8 Stack Pointer Select Flag (U Flag).................................................................................................23
2.8.9 Processor Interrupt Priority Level (IPL)........................................................................................23
2.8.10 Reserved Area...............................................................................................................................23
3. Memory ___________________________________________________ 24
4. Special Function Register (SFR) ______________________________ 25
5. Reset _____________________________________________________ 31
5.1 Hardware Reset 1.......................................................................................................31
5.1.1 Reset on a Stable Supply Voltage ..................................................................................................31
5.1.2 Power-on Reset................................................................................................................................31
5.2 Voltage Down Detection Reset (Hardware Reset 2)................................................ 31
5.3 Software Reset ...........................................................................................................32
5.4 Watchdog Timer Reset ..............................................................................................32
5.5 Oscillation Stop Detection Reset .............................................................................32
A-1
10.5 System Clock Protection Function ........................................................................85
10.6 Oscillation Stop and Re-oscillation Detect Function ...........................................85
10.6.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) ...........................................86
10.6.2 Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation Detect Interrupt) ............86
10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function............................................ 87
11. Protection ________________________________________________ 88
12. Interrupt _________________________________________________ 89
12.1 Type of Interrupts..................................................................................................... 89
12.2 Software Interrupts..................................................................................................90
12.2.1 Undefined Instruction Interrupt ................................................................................................... 90
12.2.2 Overflow Interrupt.........................................................................................................................90
12.2.3 BRK Interrupt ................................................................................................................................90
12.2.4 INT Instruction Interrupt...............................................................................................................90
12.3 Hardware Interrupts.................................................................................................91
12.3.1 Special Interrupts..........................................................................................................................91
12.3.2 Peripheral Function Interrupts .................................................................................................... 91
12.4 Interrupts and Interrupt Vector ...............................................................................92
12.4.1 Fixed Vector Tables ......................................................................................................................92
12.4.2 Relocatable Vector Tables............................................................................................................93
12.5 Interrupt Control ......................................................................................................94
12.5.1 I Flag...............................................................................................................................................96
12.5.2 IR Bit...............................................................................................................................................96
12.5.3 ILVL2 to ILVL0 Bits and IPL..........................................................................................................96
12.5.4 Interrupt Sequence .......................................................................................................................97
12.5.5 Interrupt Response Time..............................................................................................................98
12.5.6 Variation of IPL when Interrupt Request is Accepted................................................................98
12.5.7 Saving Registers........................................................................................................................... 99
12.5.8 Returning from an Interrupt Routine.........................................................................................101
12.5.9 Interrupt Priority..........................................................................................................................101
12.5.10 Interrupt Priority Resolution Circuit........................................................................................101
______
12.6 INT Interrupt ...........................................................................................................103
______
12.7 NMI Interrupt...........................................................................................................104
12.8 Key Input Interrupt.................................................................................................104
12.9 Address Match Interrupt .......................................................................................105
13. Watchdog Timer __________________________________________ 107
13.1 Count source protective mode .............................................................................108
13.2 Cold start / Warm start ...........................................................................................109
14. DMAC ___________________________________________________110
14.1 Transfer Cycles ......................................................................................................115
14.1.1 Effect of Source and Destination Addresses ...........................................................................115
14.1.2 Effect of BYTE Pin Level ...........................................................................................................115
A-3
14.1.3 Effect of Software Wait............................................................................................................... 115
14.1.4 Effect of RDY Signal ................................................................................................................... 115
_______
14.2 DMA Transfer Cycles ............................................................................................. 117
14.3 DMA Enable ............................................................................................................ 1 1 8
14.4 DMA Request.......................................................................................................... 118
14.5 Channel Priority and DMA Transfer Timing......................................................... 119
15. Timers __________________________________________________ 120
15.1 Timer A....................................................................................................................122
15.1.1 Timer Mode..................................................................................................................................126
15.1.2 Event Counter Mode ...................................................................................................................127
15.1.3 One-shot Timer Mode .................................................................................................................132
15.1.4 Pulse Width Modulation (PWM) Mode.......................................................................................134
15.2 Timer B....................................................................................................................137
15.2.1 Timer Mode..................................................................................................................................140
15.2.2 Event Counter Mode ..................................................................................................................141
15.2.3 Pulse Period and Pulse Width Measurement Mode.................................................................142
16. Three-Phase Motor Control Timer Function ___________________ 144
17. Serial I/O ________________________________________________ 154
17.1 UARTi (i=0 to 2) ......................................................................................................154
17.1.1 Clock Synchronous serial I/O Mode..........................................................................................164
17.1.2 Clock Asynchronous Serial I/O (UART) Mode..........................................................................172
17.1.3 Special Mode 1 (I2C mode) ........................................................................................................180
17.1.4 Special Mode 2 ............................................................................................................................190
17.1.5 Special Mode 3 (IE mode)...........................................................................................................195
17.1.6 Special Mode 4 (SIM Mode) (UART2) ........................................................................................197
17.2 SI/O3 and SI/O4 ......................................................................................................202
17.2.1 SI/Oi Operation Timing ...............................................................................................................205
17.2.2 CLK Polarity Selection ...............................................................................................................205
17.2.3 Functions for Setting an SOUTi Initial Value ............................................................................206
18. A/D Converter ____________________________________________ 207
18.1 Mode Description................................................................................................... 211
18.1.1 One-Shot Mode ............................................................................................................................211
18.1.2 Repeat mode ................................................................................................................................213
18.1.3 Single Sweep Mode ....................................................................................................................215
18.1.4 Repeat Sweep Mode 0 ................................................................................................................217
18.1.5 Repeat Sweep Mode 1 ................................................................................................................219
18.2 Function..................................................................................................................221
18.2.1 Resolution Select Function........................................................................................................221
18.2.2 Sample and Hold.........................................................................................................................221
18.2.3 Extended Analog Input Pins ......................................................................................................221
18.2.4 External Operation Amplifier (Op-Amp) Connection Mode ....................................................221
A-4
18.2.5 Current Consumption Reducing Function ...............................................................................222
18.2.6 Output Impedance of Sensor under A/D Conversion..............................................................222
19. D/A Converter ____________________________________________ 224
20. CRC Calculation __________________________________________ 226
21. Programmable I/O Ports ___________________________________ 228
21.1 Port Pi Direction Register (PDi Register, i = 0 to 13) ..........................................229
21.2 Port Pi Register (Pi Register, i = 0 to 13)..................................................................229
21.3
Pull-up Control Register 0 to Pull-up Control Register 3 (PUR0 to PUR3 Registers) ....
229
21.4 Port Control Register (PCR Register) ..................................................................229
22. Flash Memory Version _____________________________________ 242
22.1 Memory Map ...........................................................................................................244
22.1.1 Boot Mode ...................................................................................................................................245
22.2 Functions To Prevent Flash Memory from Rewriting......................................... 245
22.2.1 ROM Code Protect Function ...................................................................................................... 245
22.2.2 ID Code Check Function ............................................................................................................245
22.3 CPU Rewrite Mode .................................................................................................247
22.3.1 EW0 Mode....................................................................................................................................248
22.3.2 EW1 Mode....................................................................................................................................248
22.3.3 Flash memory Control Register (FIDR, FMR0 and FMR1 registers) ..................................... 248
22.3.4 Precautions on CPU Rewrite Mode ...........................................................................................254
22.3.5 Software Commands ..................................................................................................................256
22.3.6 Data Protect Function.................................................................................................................261
22.3.7 Status Register............................................................................................................................261
22.3.8 Full Status Check........................................................................................................................263
22.4 Standard Serial I/O Mode ......................................................................................265
22.4.1 ID Code Check Function ............................................................................................................265
22.4.2 Example of Circuit Application in the Standard Serial I/O Mode............................................271
22.5 Parallel I/O Mode ....................................................................................................273
22.5.1 User ROM and Boot ROM Areas................................................................................................273
22.5.2 ROM Code Protect Function ...................................................................................................... 273
23. Electrical Characteristics __________________________________ 274
23.1 Electrical Characteristics (M16C/62P)..................................................................274
23.2 Electrical Characteristics (M16C/62PT) ...............................................................313
24. Usage Precaution_________________________________________ 326
24.1 Reset .......................................................................................................................326
24.2 Bus ..........................................................................................................................327
24.3 PLL Frequency Synthesizer..................................................................................328
24.4 Power Control ........................................................................................................329
24.5 Protect.....................................................................................................................330
A-5
Appendix 1. Package Dimensions ______________________________ 359
Appendix 2. Differences Between M16C/62P and M16C/62A _________ 361
Register Index.......................................................... 364
A-7
SFR Page Reference
Address
0000h
0001h
0002h
0003h
Processor mode register 0 PM0
0004h
Processor mode register 1 PM1
0005h
System clock control register 0 CM0
0006h
System clock control register 1 CM1
0007h
Chip select control register CSR
0008h
0009h
Address match interrupt enable register AIER
000Ah
Protect register PRCR
000Bh
Data bank register DBR
000Ch
Oscillation stop detection register CM2
000Dh
000Eh
Watchdog timer start register WDTS
000Fh
Watchdog timer control register WDC
0010h
Address match interrupt register 0 RMAD0
0011h
0012h
0013h
0014h
Address match interrupt register 1 RMAD1
0015h
0016h
0017h
0018h
0019h
Voltage detection register 1 VCR1
001Ah
Voltage detection register 2 VCR2
001Bh
Chip select expansion control register CSE
001Ch
PLL control register 0 PLC0
001Dh
001Eh
Processor mode register 2 PM2
001Fh
Voltage down detection interrupt register D4INT
0020h
0021h
DMA0 source pointer SAR0
0022h
0023h
0024h
DMA0 destination pointer DAR0
0025h
0026h
0027h
0028h
DMA0 transfer counter TCR0
0029h
002Ah
002Bh
002Ch
DMA0 control register DM0CON
002Dh
002Eh
002Fh
0030h
0031h
DMA1 source pointer SAR1
0032h
0033h
0034h
0035h
DMA1 destination pointer DAR1
0036h
0037h
0038h
DMA1 transfer counter TCR1
0039h
003Ah
003Bh
003Ch
DMA1 control register DM1CON
003Dh
003Eh
003Fh
NOTES :
1. The blank areas are reserved and cannot be accessed by users.
Register Symbol Page
43
44
67
68
47
106
88
58
69
108
108
106
106
36
36
53
71
70
36
114
114
114
113
114
114
114
113
Address
0040h
0041h
0042h
0043h
INT3 interrupt control register INT3IC
0044h
Timer B5 interrupt control register TB5IC
0045h
0046h
Timer B4 interrupt control register, TB4IC,
UART1 BUS collision detection interrupt control register U1BCNIC
0047h
Timer B3 interrupt control register, TB3IC,
UART0 BUS collision detection interrupt control register U0BCNIC
0048h
SI/O4 interrupt control register S4IC,
INT5 interrupt control register INT5IC
0049h
SI/O3 interrupt control register, S3IC,
Register Symbol Page
INT4 interrupt control register INT4IC
004Ah
UART2 Bus collision detection interrupt control register BCNIC
004Bh
DMA0 interrupt control register DM0IC
004Ch
DMA1 interrupt control register DM1IC
004Dh
Key input interrupt control register KUPIC
004Eh
A/D conversion interrupt control register ADIC
004Fh
UART2 transmit interrupt control register
0050h
UART2 receive interrupt control register
0051h
UART0 transmit interrupt control register
0052h
UART0 receive interrupt control register
UART1 transmit interrupt control register
0053h
UART1 receive interrupt control register
0054h
0055h
Timer A0 interrupt control register TA0IC
0056h
Timer A1 interrupt control register TA1IC
0057h
Timer A2 interrupt control register TA2IC
0058h
Timer A3 interrupt control register TA3IC
0059h
Timer A4 interrupt control register TA4IC
005Ah
Timer B0 interrupt control register TB0IC
005Bh
Timer B1 interrupt control register TB1IC
005Ch
Timer B2 interrupt control register TB2IC
005Dh
INT0 interrupt control register INT0IC
005Eh
INT1 interrupt control register INT1IC
005Fh
INT2 interrupt control register INT2IC
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
95
B-1
SFR Page Reference
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
to
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
Flash identification register FIDR
01B5h
Flash memory control register 1 FMR1
01B6h
01B7h
Flash memory control register 0 FMR0
01B8h
01B9h
Address match interrupt register 2 RMAD2
01BAh
01BBh
Address match interrupt enable register 2
01BCh
01BDh
Address match interrupt register 3 RMAD3
01BEh
01BFh
01C0h
to
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
Peripheral clock select register PCLKR
025Fh
0260h
to
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
NOTES :
1. The blank areas are reserved and cannot be accessed by users.
2. This register is included in the flash memory version.
Register Symbol Page
(2)
(2)
(2)
AIER2
249
249
249
106
106
106
70
Address
0340h
Timer B3, 4, 5 count start flag TBSR
0341h
0342h
Timer A1-1 register TA11
0343h
0344h
Timer A2-1 register TA21
0345h
0346h
Timer A4-1 register TA41
0347h
Three-phase PWM control register 0 INVC0
0348h
Three-phase PWM control register 1 INVC1
0349h
Three-phase output buffer register 0 IDB0
034Ah
Three-phase output buffer register 1 IDB1
034Bh
Dead time timer DTT
034Ch
Timer B2 interrupt occurrence frequency set counter
034Dh
034Eh
034Fh
0350h
Timer B3 register TB3
0351h
0352h
Timer B4 register TB4
0353h
0354h
Timer B5 register TB5
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
Timer B3 mode register TB3MR
035Ch
Timer B4 mode register TB4MR
035Dh
Timer B5 mode register TB5MR
Interrupt cause select register 2 IFSR2A
035Eh
Interrupt cause select register IFSR
035Fh
SI/O3
0360h
0361h
0362h
SI/O3 control register S3C
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
bit rate generator
SI/O3
SI/O4
SI/O4 control register S4C
SI/O4
bit rate generator
UART0 special mode register 4 U0SMR4
UART0 special ode register 3 U0SMR3
UART0 special mode register 2 U0SMR2
UART0 special mode register U0SMR
UART1 special mode register 4 U1SMR4
UART1 special mode register 3 U1SMR3
UART1 special mode register 2 U1SMR2
UART1 special mode register U1SMR
UART2 special mode register 4 U2SMR4
UART2 special mode register 3 U2SMR3
UART2 special mode register 2 U2SMR2
UART2 special mode register U2SMR
UART2 transmit/receive mode register
UART2 bit rate generator
UART2 transmit buffer register
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
Register Symbol Page
transmit/receive register
transmit/receive register
ICTB2
S3TRR
S3BRG
S4TRR
S4BRG
U2MR
U2BRG
U2TB
U2C0
U2C1
U2RB
139
149
149
149
146
147
148
148
148
149
139
139
139
138
138
138
103
103
203
203
203
203
203
203
163
162
162
161
163
162
162
161
163
162
162
161
159
158
158
159
160
158
B-2
SFR Page Reference
Address
Count start flag TABSR
0380h
Clock prescaler reset flag CPSRF
0381h
One-shot start flag ONSF
0382h
Trigger select register TRGSR
0383h
Up-down flag UDF
0384h
0385h
0386h
Timer A0 register TA0
0387h
0388h
Timer A1 register TA1
0389h
038Ah
Timer A2 register TA2
038Bh
038Ch
Timer A3 register TA3
038Dh
038Eh
Timer A4 register TA4
038Fh
0390h
Timer B0 register TB0
0391h
0392h
Timer B1 register TB1
0393h
0394h
Timer B2 register TB2
0395h
0396h
Timer A0 mode register TA0MR
Timer A1 mode register TA1MR
0397h
Timer A2 mode register TA2MR
0398h
0399h
Timer A3 mode register TA3MR
039Ah
Timer A4 mode register TA4MR
Timer B0 mode register TB0MR
039Bh
039Ch
Timer B1 mode register TB1MR
039Dh
Timer B2 mode register TB2MR
039Eh
Timer B2 special mode register TB2SC
039Fh
03A0h
UART0 transmit/receive mode register
03A1h
UART0 bit rate generator U0BRG
03A2h
UART0 transmit buffer register U0TB
03A3h
03A4h
UART0 transmit/receive control register 0
03A5h
UART0 transmit/receive control register 1
03A6h
UART0 receive buffer register U0RB
03A7h
03A8h
UART1 transmit/receive mode register
03A9h
UART1 bit rate generator U1BRG
03AAh
UART1 transmit buffer register U1TB
03ABh
03ACh
UART1 transmit/receive control register 0
03ADh
UART1 transmit/receive control register 1
03AEh
UART1 receive buffer register U1RB
03AFh
03B0h
UART transmit/receive control register 2
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
DMA0 request cause select register DM0SL
03B8h
03B9h
03BAh
DMA1 request cause select register DM1SL
03BBh
03BCh
CRC data register CRCD
03BDh
03BEh
CRC input register CRCIN
03BFh
NOTES :
1. The blank areas are reserved and cannot be accessed by users.
2. This register is included in the flash memory version.
Register Symbol Page
U0MR
U0C0
U0C1
U1MR
U1C0
U1C1
UCON
124, 139
150
125, 139
125
125, 150
124
124
124, 149
124, 149
124
124, 149
139
139
139, 150
123
123, 151
123, 151
123
123, 151
138
138
138. 151
149
159
158
158
159
160
158
159
158
158
159
160
158
161
112
113
226
226
Address
03C0h
A/D register 0 AD0
03C1h
03C2h
A/D register 1 AD1
03C3h
03C4h
A/D register 2 AD2
03C5h
03C6h
A/D register 3 AD3
03C7h
03C8h
A/D register 4 AD4
03C9h
03CAh
A/D register 5 AD5
03CBh
03CCh
A/D register 6 AD6
03CDh
03CEh
A/D register 7 AD7
03CFh
03D0h
03D1h
03D2h
03D3h
A/D control register 2 ADCON2
03D4h
03D5h
03D6h
A/D control register 0 ADCON0
03D7h
A/D control register 1 ADCON1
D/A register 0 DA0
03D8h
03D9h
D/A register 1 DA1
03DAh
03DBh
03DCh
D/A control register DACON
03DDh
Port P14 control register PC14
03DEh
Pull-up control register 3 PUR3
03DFh
03E0h
Port P0 register P0
03E1h
Port P1 register P1
03E2h
Port P0 direction register PD0
03E3h
Port P1 direction register PD1
Port P2 register P2
03E4h
Port P3 register P3
03E5h
Port P2 direction register PD2
03E6h
03E7h
Port P3 direction register PD3
03E8h
Port P4 register P4
03E9h
Port P5 register P5
03EAh
Port P4 direction register PD4
03EBh
Port P5 direction register PD5
03ECh
Port P6 register P6
03EDh
Port P7 register P7
Port P6 direction register PD6
03EEh
Port P7 direction register PD7
03EFh
03F0h
Port P8 register P8
03F1h
Port P9 register P9
03F2h
Port P8 direction register PD8
03F3h
Port P9 direction register PD9
Port P10 register P10
03F4h
03F5h
Port P11 register P11
03F6h
Port P10 direction register PD10
03F7h
Port P11 direction register PD11
Port P12 register P12
03F8h
03F9h
Port P13 register P13
03FAh
Port P12 direction register PD12
Port P13 direction register PD13
03FBh
03FCh
Pull-up control register 0 PUR0
03FDh
Pull-up control register 1 PUR1
03FEh
Pull-up control register 2 PUR2
03FFh
Port control register PCR
Register Symbol Page
210
210
210
210
210
210
210
210
210
209
209
225
225
225
237
237
236
236
235
235
236
236
235
235
236
236
235
235
236
236
235
235
236
236
235
235
236
236
235
235
236
236
235
235
238
238
238
239
B-3
M16C/62P Group (M16C/62P, M16C/62PT)
1.2 Performance Outline
Table 1.1 to table 1.3 list performance outline of M16C/62P group (M16C/62P, M16C/62PT).
Table 1.1 Performance Outline of M16C/62P group (M16C/62P) (128-pin version)
Item Performance
M16C/62P
CPU
Peripheral
Function
Electric
Characteristics
Flash Memory
Version
Operating Ambient Temperature –20 to 85oC
Package 128-pin plastic mold LQFP
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Sep., 2004. Please inquire about a release schedule.
4. All options are on request basis.
Number of Basic Instructions 91 instructions
Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operation Mode Single-chip, memory expansion and microprocessor mode
Memory Space 1 Mbyte (Available to 4 Mbytes by memory space
expansion function)
Memory Capacity See Table 1.4 and 1.5 Product List
Port Input/Output : 113 pins, Input : 1 pin
Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels
Three phase motor control circuit
Serial I/O 3 channels
Clock synchronous, UART,
2
(1)
C bus
I
2 channels
Clock synchronous
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
Clock Generation Circuit 4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop Detection Function Stop detection of main clock oscillation
function
Voltage Detection Circuit Available (option
Supply Voltage VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=24MHz)
VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=10MHz)
Power Consumption 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8 µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7 µ A (VCC1=VCC2=3V, stop mode)
Program/Erase Supply Voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V
Program and Erase Endurance 100 times (all area)
or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)
–40 to 85oC
, IEBus
(3)
(4)
(2)
, re-oscillation detection
)
(3)
1. Overview
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.2 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (100-pin version)
Item Performance
M16C/62P M16C/62PT
CPU
Number of Basic Instructions 91 instructions
Minimum Instruction Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)
41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operation Mode
Single-chip, memory expansion and
Single-chip mode
microprocessor mode
Memory Space 1 Mbyte (Available to 4 Mbytes by 1 Mbyte
memory space expansion function)
Memory Capacity See Table 1.4 to 1.7 Product List
Peripheral
function
Port Input/Output : 87 pins, Input : 1pin
Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels
Three phase motor control circuit
Serial I/O 3 channels
Clock synchronous, UART,
2
C bus
I
(1)
, IEBus
(2)
2 channels
Clock synchronous
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
Clock Generation Circuit 4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Electric
characteristics
Oscillation Stop Detection Function
Voltage Detection Circuit Available (option
Supply Voltage
Power Consumption
Stop detection of main clock oscillation, re-oscillation detection function
(5)
) Absent
VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1
VCC1=VCC2=4.0V to 5.5 V
(f(BCLK)=24MHz) (f(BCLK)=24MHz)
VCC1=2.7 to 5.5V, V
(f(BCLK)=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
CC2
=2.7V to VCC1
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0 µA (VCC1=VCC2=5V,
1.8 µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
f(XCIN)=32kHz, wait mode) 0.8 µ A (VCC1=VCC2=5V, stop mode)
0.7 µ A (VCC1=VCC2=3V, stop mode)
Flash memory
Version
Program/Erase Supply Voltage
Program and Erase Endurance
3.3 ± 0.3 V or 5.0 ± 0.5 V
100 times (all area)
5.0 ± 0.5 V
or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)
(3)
Operating Ambient Temperature –20 to 85oC T version : –40 to 85oC
–40 to 85oC
(3)
V version : –40 to 125oC
Package 100-pin plastic mold QFP, LQFP
NOTES:
2
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
1. I
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Sep., 2004. Please inquire about a release schedule.
4. Use the M16C/62PT on VCC1 = VCC2.
5. All options are on request basis.
(Note 4)
1. Overview
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.3 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (80-pin version)
Item Performance
M16C/62P M16C/62PT
CPU
Peripheral
function
Electric
characteristics
Flash
memory
Version
Operating Ambient Temperature –20 to 85oC T version : –40 to 85oC
Package 80-pin plastic mold QFP
NOTES :
2
1. I
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Sep., 2004. Please inquire about a release schedule.
4. All options are on request basis.
Number of Basic Instructions 91 instructions
Minimum Instruction Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operation Mode Single-chip mode
Memory Space 1 Mbyte
Memory Capacity See Table 1.4 to 1.7 Product List
Port Input/Output : 70 pins, Input : 1pin
Multifunction Timer Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer)
Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial I/O 2 channels
Clock synchronous, UART,
2
C bus
I
(1)
, IEBus
(2)
1 channel
Clock synchronous,
2
C bus
I
(1)
, IEBus
(2)
2 channels
Clock synchronous (1 channel is only for transmission)
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 29 sources, External: 5 sources, Software: 4 sources,
Priority level: 7 levels
Clock Generating Circuit 4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop Detection Function
Voltage Detection Circuit Available (option
Supply Voltage
Stop detection of main clock oscillation, re-oscillation detection function
(4)
) Absent
VCC1=3.0 to 5.5V, (f(BCLK)=24MHz) VCC1=4.0 to 5.5V, (f(BCLK)=24MHz)
VCC1=2.7 to 5.5V, (f(BCLK)=10MHz)
Power Consumption
14 mA (VCC1=5V, f(BCLK)=24MHz)
14 mA (VCC1=5V, f(BCLK)=24MHz)
8 mA (VCC1=3V, f(BCLK)=10MHz) 2.0 µA (VCC1=5V,
1.8 µA (VCC1=3V,
f(XCIN)=32kHz, wait mode) 0.8 µ A (VCC1=5V, stop mode)
f(XCIN)=32kHz, wait mode)
0.7 µ A (VCC1=3V, stop mode)
Program/Erase Supply Voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V
Program and Erase Endurance
100 times (all area)
or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)
(3)
–40 to 85oC(option) V version : –40 to 125oC
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
1. Overview
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M16C/62P Group (M16C/62P, M16C/62PT)
A
1. Overview
1.3 Block Diagram
Figure 1.1 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version, figure 1.2 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version.
8
Port P0
Internal peripheral functions
Port P18Port P2
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
8 8 8 8
Port P4Port P3
<VCC2 ports>
Expandable up to 26 channels)
CRC arithmetic circuit (CCITT )
(4)
A/D converter
(10 bits X 8 channels
clock synchronous serial I/O
(Polynomial : X
UART or
(8 bits X 3 channels)
16+X12+X5
+1)
M16C/60 series16-bit CPU core
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
INTB
PC
Port P5
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
(8 bits X 2 channels)
SB
USP
ISP
FLG
AAA
8
Port P6
<VCC1 ports>
Memory
(1)
ROM
(2)
RAM
Multiplier
(4)
<VCC1 ports>
(4)
Port P7
8
Port P8
7
Port P8_5
Port P9
8
Port P10
8
<VCC1 ports>
Port P11
(3)
(4)
Port P14
(3) (3)
<VCC2 ports>
Port P12
(4)
Port P13
(3)
8 8 82
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Figure 1.1 M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
8
Port P0
Internal peripheral functions
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
8
Port P28Port P38Port P44Port P58Port P6
(4)
A/D converter
(10 bits X 8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O (2 channels)
UART (1 channel)
CRC arithmetic circuit (CCITT )
(Polynomial : X
16+X12+X5
(3)
+1)
M16C/60 series16-bit CPU core
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
(8 bits X 2 channels)
Memory
ROM
RAM
Multiplier
Port P7
4
Port P8
7
Port P8_5
(4)
(1)
(2)
Port P9
7
Port P10
8
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).
4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Figure 1.2 M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
1.4 Product List
Tables 1.4 to 1.7 list the product list, figure 1.3 shows the type numbers, memory sizes and packages, table
1.8 lists the product code of flash memory version and ROMless version for M16C/62P, and table 1.9 lists
the product code of flash memory version for M16C/62PT. Figure 1.4 shows the marking diagram of flash
memory version and ROMless version for M16C/62P, and figure 1.5 shows the marking diagram of flash
memory version for M16C/62PT. Please specify the mark of the mask ROM version at the time of ROM
order.
Table 1.4 Product List (1) (M16C/62P)
Type No.
M30622M6P-XXXFP
M30622M6P-XXXGP
M30623M6P-XXXGP
M30622M8P-XXXFP
M30622M8P-XXXGP
M30623M8P-XXXGP
M30622MAP-XXXFP
M30622MAP-XXXGP
M30623MAP-XXXGP
M30620MCP-XXXFP
M30620MCP-XXXGP
M30621MCP-XXXGP
M30622MEP-XXXFP
M30622MEP-XXXGP
M30623MEP-XXXGP
M30622MGP-XXXFP
M30622MGP-XXXGP
M30623MGP-XXXGP
M30624MGP-XXXFP
M30624MGP-XXXGP
M30625MGP-XXXGP
M30622MWP-XXXFP
M30622MWP-XXXGP
M30623MWP-XXXGP
M30624MWP-XXXFP
M30624MWP-XXXGP
M30625MWP-XXXGP
M30626MWP-XXXFP
M30626MWP-XXXGP
M30627MWP-XXXGP
(D): Under development
ROM Capacity Package Type
48 Kbytes
(D)
64 Kbytes
(D)
96 Kbytes
(D)
128 Kbytes
(D)
192 Kbytes
(D)
256 Kbytes
320 Kbytes
(D)
(D)
(D)
(D)
RAM Capacity
4 Kbytes
4 Kbytes
5 Kbytes
10 Kbytes
12 Kbytes
12 Kbytes
20 Kbytes
16 Kbytes
24 Kbytes
31 Kbytes
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
As of Sep. 2004
Remarks
Mask ROM version
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.5 Product List (2) (M16C/62P)
ROM Capacity
M30622MHP-XXXFP
M30622MHP-XXXGP
M30623MHP-XXXGP
M30624MHP-XXXFP
M30624MHP-XXXGP
M30625MHP-XXXGP
M30626MHP-XXXFP
M30626MHP-XXXGP
M30627MHP-XXXGP
M30626MJP-XXXFP
M30626MJP-XXXGP
M30627MJP-XXXGP
M30622F8PFP
M30622F8PGP
M30623F8PGP
M30620FCPFP
M30620FCPGP
M30621FCPGP
M30624FGPFP
M30624FGPGP
M30625FGPGP
M30626FHPFP
M30626FHPGP
M30627FHPGP
(D)
384 Kbytes
(D)
(D)
(P)
512 Kbytes
(P)
(P)
64K+4 Kbytes
(D)
(D)
256K+4 Kbytes
ROM Capacity
16 Kbytes
24 Kbytes
31 Kbytes
31 Kbytes
4 Kbytes
10 Kbytes128K+4 Kbytes
20 Kbytes
Package Type
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A31 Kbytes384K+4 Kbytes
128P6Q-A
As of Sep. 2004
RemarksType No.
Mask ROM version
Flash memory version
M30626FJPFP
M30626FJPGP
M30627FJPGP
M30622SPFP
M30622SPGP
M30620SPFP
M30620SPGP
(D): Under development
(P): Under planning
(P)
(P)
31 Kbytes512K+4 Kbytes
4 Kbytes
10 Kbytes
100P6S-A
100P6Q-A
128P6Q-A(P)
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
ROMless version
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.6 Product List (3) (T version (M16C/62PT))
Type No.
M3062CM6T-XXXFP
M3062CM6T-XXXGP
M3062EM6T-XXXGP
M3062CM8T-XXXFP
M3062CM8T-XXXGP
M3062EM8T-XXXGP
M3062CMAT-XXXFP
M3062CMAT-XXXGP
M3062EMAT-XXXGP
M3062AMCT-XXXFP
M3062AMCT-XXXGP
M3062BMCT-XXXGP
M3062CF8TFP
M3062CF8TGP
M3062AFCTFP
M3062AFCTGP
M3062BFCTGP
M3062JFHTFP
M3062JFHTGP
(D): Under development
(P): Under planning
ROM Capacity
(D)
(D)
(P)
(D)
(D)
(P)
(D)
(D)
(P)
(D)
(D)
(P)
(D)
(D)
(D)
128K+4 Kbytes
(P)
(D)
(D)
RAM Capacity
4 Kbytes48 Kbytes
4 Kbytes64 Kbytes
5 Kbytes96 Kbytes
10 Kbytes128 Kbytes
4 Kbytes64 Kbytes
10 Kbytes
31 Kbytes384K+4 Kbytes
Package Type
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A(D)
100P6Q-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
As of Sep. 2004
Remarks
Mask ROM
version
T Version
(High reliability
85 °C Version)
Flash memory
version
Table 1.7 Product List (4) (V version (M16C/62PT))
RAM CapacityROM Capacity
M3062CM6V-XXXFP
M3062CM6V-XXXGP
M3062EM6V-XXXGP
M3062CM8V-XXXFP
M3062CM8V-XXXGP
M3062EM8V-XXXGP
M3062CMAV-XXXFP
M3062CMAV-XXXGP
M3062EMAV-XXXGP
M3062AMCV-XXXFP
M3062AMCV-XXXGP
M3062BMCV-XXXGP
M3062AFCVFP
M3062AFCVGP
M3062BFCVGP
M3062JFHVFP
M3062JFHVGP
(D): Under development
(P): Under planning
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(D)
(D)
(P)
(D)
(D)
(P)
(P)
(P)
4 Kbytes48 Kbytes
4 Kbytes64 Kbytes
5 Kbytes96 Kbytes
10 Kbytes128 Kbytes
31 Kbytes384K+4 Kbytes
Package Type
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A
80P6S-A
100P6S-A
100P6Q-A10 Kbytes128K+4 Kbytes
80P6S-A
100P6S-A
100P6Q-A
RemarksType No.
Mask ROM
version
Flash memory
version
As of Sep. 2004
V Version
(High reliability
125 °C Version)
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M16C/62P Group (M16C/62P, M16C/62PT)
Type No. M 3 0 6 2 6 M H P – X X X F P
1. Overview
Package type:
FP : Package 100P6S-A
GP : Package 80P6Q-A, 100P6Q-A, 128P6Q-A
ROM No.
Omitted for flash memory version and
ROMless version
Classification
P : M16C/62P
T : T version (M16C/62PT)
V : V version (M16C/62PT)
ROM capacity:
6: 48 Kbytes
8: 64 Kbytes
A: 96 Kbytes
C: 128 Kbytes
E: 192 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
S: ROMless version
G: 256 Kbytes
W: 320 Kbytes
H: 384 Kbytes
J: 512 Kbytes
Figure 1.3 Type No., Memory Size, and Package
Shows RAM capacity, pin count, etc
Numeric : M16C/62P
Alphabet : M16C/62PT
M16C/62P Group
M16C Family
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P
1. Overview
Flash Memory
Version
ROMless Version
Product
Code
D3
D5
D7
D9
U3
U5
U7
U9
D3
D5
U3
U5
Package
Lead-included
Lead-free
Lead-included
Lead-free
Internal ROM
(User ROM Area
Without Block 1)
Program
and Erase
Endurance
100
1,000
100
1,000
Temperature
Range
0°C to 60°C
Internal ROM
(Block A, Block 1)
Program
and Erase
Endurance
100
10,000
100
10,000
Temperature
Range
0°C to 60°C
-40°C to 85°C
-20°C to 85°C
0°C to 60°C
-40°C to 85°C
-20°C to 85°C
Operating
Ambient
Temperature
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
M16C
M30626FHPFP
BD5
XXXXXXX
The product without marking of chip version of the flash memory version and the ROMless version
corresponds to the chip version “A”.
Figure 1.4
Marking Diagram of Flash Memory version and ROMless version for M16C/62P (Top View)
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Chip version and product code
B : Shows chip version.
Henceforth, whenever it changes a version, it continues with B, C, and D.
D5 : Shows Product code. (See table 1.8 Product Code)
Date code seven digits
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.9 Product Code of Flash Memory version for M16C/62PT
1. Overview
Flash
Memory
Version
T Version
V Version
T Version
V Version
T Version
V Version
T Version
V Version
Product
Code
B
B7
U
U7
Package
Lead-included
Lead-free
Internal ROM
(User ROM Area
Without Block 1)
Program
and Erase
Endurance
100
1,000
100
1,000
Temperature
Range
0°C to 60°C
Internal ROM
(Block A, Block 1)
Program
and Erase
Endurance
100
10,000
100
10,000
Temperature
Range
0°C to 60°C
-40°C to 85°C
-40°C to 125°C
0°C to 60°C
-40°C to 85°C
-40°C to 125°C
Operating
Ambient
Temperature
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
Figure 1.5
M1 6C
M3062JFHTFP
YYY XXXXXXX
Marking Diagram of Flash Memory version for M16C/62PT (Top View)
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Date code seven digits
Product code. (See table 1.9 Product Code)
“ ” : Product code “B”
“ PBF” : Product code “U”
“ B7 ” : Product code “B7”
“ U7 ” : Product code “U7”
NOTES:
1. : Blank
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M16C/62P Group (M16C/62P, M16C/62PT)
1.5 Pin Configuration
Figures 1.6 to 1.9 show the pin configurations (top view).
PIN CONFIGURATION (top view)
P1_2/D10
P1_1/D9
101102
100
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930
737475767778798081828384858687888990919293949596979899
31 32 33 34 35 36 37
P4_4/CS0
P4_5/CS1
P4_6/CS2
66676869707172
65
38
P4_7/CS3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
1. Overview
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
BYTE
CNVSS
P8_7/XCIN
P9_3/DA0/TB3IN
P9_4/DA1/TB4IN
P9_1/TB1IN/SIN3
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P9_0/TB0IN/CLK3
P9_2/TB2IN/SOUT3
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1 = VCC2.
Figure 1.6 Pin Configuration (Top View)
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463fo4002,10peS03.2.veR
VSS
XOUT
RESET
P8_6/XCOUT
XIN
VCC1
P8_5/NMI
P8_3/INT1
P8_2/INT0
P8_4/INT2/ZP
P8_1/TA4IN/U
P7_7/TA3IN
P7_6/TA3OUT
P7_5/TA2IN/W
P8_0/TA4OUT/U
P7_4/TA2OUT/W
(1)
(1)
P6_7/TXD1/SDA1
P6_6/RXD1/SCL1
P7_2/CLK2/TA1OUT/V
P7_3/CTS2/RTS2/TA1IN/V
P7_0/TXD2/SDA2/TA0OUT
P7_1/RXD2/SCL2/TA0IN/TB5IN
Package: 128P6Q-A
M16C/62P Group (M16C/62P, M16C/62PT)
(
)
PIN CONFIGURATION (top view)
1. Overview
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
P9_7/ADTRG/SIN4
AVCC
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1 = VCC2.
P2_7/AN2_7/A7(/D7/D6)
P2_0/AN2_0/A0(/D0/-)
P1_7/D15/INT5
P1_0/D8
P1_1/D9
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
00
1
1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P1_5/D13/INT3
P1_2/D10
P1_3/D11
P1_4/D12
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_1/TB1IN/SIN3
P9_2/TB2IN/SOUT3
P2_1/AN2_1/A1(/D1/D0)
P1_6/D14/INT4
M16C/62P Group
M16C/62P, M16C/62PT
BYTE
CNVSS
P8_7/XCIN
P9_0/TB0IN/CLK3
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_4/AN2_4/A4(/D4/D3)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
<VCC2>
<VCC1>
VSS
XOUT
RESET
P8_6/XCOUT
XIN
(2)
(2)
VCC1
P3_0/A8(/-/D7)
VSS
P8_5/NMI
P8_4/INT2/ZP
VCC2
P3_1/A9
P3_2/A10
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P3_6/A14
P3_3/A11
P8_0/TA4OUT/U
P3_7/A15
P3_4/A12
P3_5/A13
P7_7/TA3IN
P7_6/TA3OUT
P7_5/TA2IN/W
P7_4/TA2OUT/W
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
515253545556575859606162636465666768697071727374757677787980
50
P4_4/CS0
49
P4_5/CS1
48
P4_6/CS2
47
P4_7/CS3
46
P5_0/WRL/WR
45
P5_1/WRH/BHE
44
P5_2/RD
43
P5_3/BCLK
42
P5_4/HLDA
41
P5_5/HOLD
40
P5_6/ALE
39
P5_7/RDY/CLKOUT
38
P6_0/CTS0/RTS0
37
P6_1/CLK0
36
P6_2/RXD0/SCL0
35
P6_3/TXD0/SDA0
34
P6_4/CTS1/RTS1/CTS0/CLKS1
33
P6_5/CLK1
32
P6_6/RXD1/SCL1
31
P6_7/TXD1/SDA1
(1)
(1)
P7_2/CLK2/TA1OUT/V
P7_3/CTS2/RTS2/TA1IN/V
P7_0/TXD2/SDA2/TA0OUT
P7_1/RXD2/SCL2/TA0IN/TB5IN
Package: 100P6S-A
Figure 1.7 Pin Configuration (Top View)
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M16C/62P Group (M16C/62P, M16C/62PT)
(
)
PIN CONFIGURATION (top view)
1. Overview
P1_2/D10
P1_1/D9
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
AVCC
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P1_3/D11
P1_4/D12
P1_5/D13/INT3
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
00
1
1 2 3 4 5 6 7 8 9 10111213141516171819202122232425
P2_1/AN2_1/A1(/D1/D0)
P2_0/AN2_0/A0(/D0/-)
P1_6/D14/INT4
P2_2/AN2_2/A2(/D2/D1)
P1_7/D15/INT5
M16C/62P Group
M16C/62P, M16C/62PT
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
<VCC2>
<VCC1>
P3_1/A9
VSS
VCC2
P3_0/A8(/-/D7)
(2)
(2)
P3_2/A10
P3_3/A11
P3_4/A12
57585960616263646566676869707172737475
P3_7/A15
P3_5/A13
P3_6/A14
P4_0/A16
P4_1/A17
515253545556
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT
P7_1/RXD2/SCL2/TA0IN/TB5IN
P7_2/CLK2/TA1OUT/V
(1)
(1)
P9_4/DA1/TB4IN
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1 = VCC2.
Figure 1.8 Pin Configuration (Top View)
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Z0320-5810B90JER
BYTE
P9_3/DA0/TB3IN
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
P9_2/TB2IN/SOUT3
463fo4002,10peS03.2.veR
CNVSS
P8_7/XCIN
P8_6/XCOUT
XOUT
RESET
VSS
XIN
VCC1
P8_5/NMI
P8_2/INT0
P8_3/INT1
P8_4/INT2/ZP
P7_7/TA3IN
P8_1/TA4IN/U
P7_6/TA3OUT
P7_5/TA2IN/W
P8_0/TA4OUT/U
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
Package: 100P6Q-A
M16C/62P Group (M16C/62P, M16C/62PT)
(
)
PIN CONFIGURATION (top view)
1. Overview
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P0_7/AN0_7
P2_0/AN2_0
P2_1/AN2_1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 1011121314151617181920
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_5/ANEX0/CLK4
P2_4/AN2_4
P2_2/AN2_2
P2_3/AN2_3
56
P2_7/AN2_7
P2_5/AN2_5
P2_6/AN2_6
P3_0
M16C/62P Group
M16C/62P, M16C/62PT
XOUT
RESET
P8_7/XCIN
P8_6/XCOUT
CNVSS(BYTE)
P9_0/TB0IN/CLK3
P9_2/TB2IN/SOUT3
P3_1
VSS
P3_2
XIN
P3_4
P3_3
VCC1
P8_5/NMI
P3_7
P3_6
P3_5
P8_3/INT1
P8_2/INT0
P8_4/INT2/ZP
P4_2
P4_0
P4_1
41424344454647484950515253545557585960
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P7_7/TA3IN
P8_1/TA4IN
P8_0/TA4OUT
P4_3
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT
P7_1/RXD2/SCL2/TA0IN/TB5IN
P7_6/TA3OUT
(1)
(1)
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
Figure 1.9 Pin Configuration (Top View)
page 16
Z0320-5810B90JER
Package: 80P6S-A
463fo4002,10peS03.2.veR
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