Renesas M16C/62P, M16C/62PT Hardware Manual

OCO

R

6C

6C/60 S

S

REJ09B0185-0230Z

M16C/62P Group

(M16C/62P, M16C/62PT)

16

Hardware Manual

RENESAS 16-BIT SINGLE-CHIP MICR

M1

FAMILY / M1

MPUTE

ERIE

Before using this material, please visit our website to verify that this is the most
updated document available.

Rev. 2.30
Revision date: Sep 01, 2004

www.renesas.com

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1.

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Remember to give due consideration to safety when making your circuit designs, with ap­propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non­flammable material or (iii) prevention against any malfunction or mishap.

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How to Use This Manual

1. Introduction

This hardware manual provides detailed information on the M16C/62P Group (M16C/62P, M16C/62PT) of
microcomputers.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.

2. Register Diagram

The symbols, and descriptions, used for bit function in each register are shown below.

XXX Register

b7 b6 b5 b4 b3 b2 b1 b0

0

0

Symbol Address After Reset
XXX XXX 00h

Bit Symbol

XXX0

XXX1

(b2)

(b4 - b3)

XXX5

XXX6

XXX7

*1

Bit Name

b1b0

0 0: XXX

XXX Bit

Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.

Reserved Bit

XXX Bit

XXX Bit

0 1: XXX
1 0: Do not set a value
1 1: XXX

Set to "0"

Function varies depending on mode
of operation

0: XXX
1: XXX

Function

*5

*1

Blank:Set to "0" or "1" according to the application
0: Set to "0"
1: Set to "1"
X: Nothing is assigned

*2

RW: Read and write
RO: Read only
WO: Write only
–: Nothing is assigned

*3

• Reserved bit
Reserved bit. Set to specified value.

*4

• Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to "0" when writing to this bit.

• Do not set to this value
The operation is not guaranteed when a value is set.

• Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.

*5

Follow the text in each manual for binary and hexadecimal notations.

RW

*2

RW

RW

*3

WO

*4

RW

RW

RO

3. M16C Family Documents

The following documents were prepared for the M16C family.

Document Contents
Short Sheet Hardware overview
Data Sheet Hardware overview and electrical characteristics
Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral

specifications, electrical characteristics, timing charts)

Software Manual Detailed description of assembly instructions and microcomputer per-

formance of each instruction

Application Note • Application examples of peripheral functions

• Sample programs

• Introduction to the basic functions in the M16C family

• Programming method with Assembly and C languages

RENESAS TECHNICAL UPDATE

Preliminary report about the specification of a product, a document,
etc.

NOTES :

1. Before using this material, please visit the our website to confirm that this is the most current document

available.

(1)

Table of Contents

1. Overview ___________________________________________________ 1

1.1 Applications .................................................................................................................1

1.2 Performance Outline....................................................................................................2

1.3 Block Diagram..............................................................................................................5

1.4 Product List ..................................................................................................................7

1.5 Pin Configuration.......................................................................................................13

1.6 Pin Description...........................................................................................................17

2. Central Processing Unit (CPU) ________________________________ 22

2.1 Data Registers (R0, R1, R2 and R3)..........................................................................22

2.2 Address Registers (A0 and A1) ................................................................................22

2.3 Frame Base Register (FB) .........................................................................................23

2.4 Interrupt Table Register (INTB)................................................................................. 23

2.5 Program Counter (PC) ...............................................................................................23

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)..................................23

2.7 Static Base Register (SB)..........................................................................................23

2.8 Flag Register (FLG)....................................................................................................23

2.8.1 Carry Flag (C Flag)..........................................................................................................................23

2.8.2 Debug Flag (D Flag) ........................................................................................................................ 23

2.8.3 Zero Flag (Z Flag)............................................................................................................................23

2.8.4 Sign Flag (S Flag)............................................................................................................................23

2.8.5 Register Bank Select Flag (B Flag) ............................................................................................... 23

2.8.6 Overflow Flag (O Flag)....................................................................................................................23

2.8.7 Interrupt Enable Flag (I Flag) .........................................................................................................23

2.8.8 Stack Pointer Select Flag (U Flag).................................................................................................23

2.8.9 Processor Interrupt Priority Level (IPL)........................................................................................23

2.8.10 Reserved Area...............................................................................................................................23

3. Memory ___________________________________________________ 24

4. Special Function Register (SFR) ______________________________ 25

5. Reset _____________________________________________________ 31

5.1 Hardware Reset 1.......................................................................................................31

5.1.1 Reset on a Stable Supply Voltage ..................................................................................................31

5.1.2 Power-on Reset................................................................................................................................31

5.2 Voltage Down Detection Reset (Hardware Reset 2)................................................ 31

5.3 Software Reset ...........................................................................................................32

5.4 Watchdog Timer Reset ..............................................................................................32

5.5 Oscillation Stop Detection Reset .............................................................................32

A-1

10.5 System Clock Protection Function ........................................................................85

10.6 Oscillation Stop and Re-oscillation Detect Function ...........................................85

10.6.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) ...........................................86

10.6.2 Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation Detect Interrupt) ............86

10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function............................................ 87

11. Protection ________________________________________________ 88

12. Interrupt _________________________________________________ 89

12.1 Type of Interrupts..................................................................................................... 89

12.2 Software Interrupts..................................................................................................90

12.2.1 Undefined Instruction Interrupt ................................................................................................... 90

12.2.2 Overflow Interrupt.........................................................................................................................90

12.2.3 BRK Interrupt ................................................................................................................................90

12.2.4 INT Instruction Interrupt...............................................................................................................90

12.3 Hardware Interrupts.................................................................................................91

12.3.1 Special Interrupts..........................................................................................................................91

12.3.2 Peripheral Function Interrupts .................................................................................................... 91

12.4 Interrupts and Interrupt Vector ...............................................................................92

12.4.1 Fixed Vector Tables ......................................................................................................................92

12.4.2 Relocatable Vector Tables............................................................................................................93

12.5 Interrupt Control ......................................................................................................94

12.5.1 I Flag...............................................................................................................................................96

12.5.2 IR Bit...............................................................................................................................................96

12.5.3 ILVL2 to ILVL0 Bits and IPL..........................................................................................................96

12.5.4 Interrupt Sequence .......................................................................................................................97

12.5.5 Interrupt Response Time..............................................................................................................98

12.5.6 Variation of IPL when Interrupt Request is Accepted................................................................98

12.5.7 Saving Registers........................................................................................................................... 99

12.5.8 Returning from an Interrupt Routine.........................................................................................101

12.5.9 Interrupt Priority..........................................................................................................................101

12.5.10 Interrupt Priority Resolution Circuit........................................................................................101

______

12.6 INT Interrupt ...........................................................................................................103

______

12.7 NMI Interrupt...........................................................................................................104

12.8 Key Input Interrupt.................................................................................................104

12.9 Address Match Interrupt .......................................................................................105

13. Watchdog Timer __________________________________________ 107

13.1 Count source protective mode .............................................................................108

13.2 Cold start / Warm start ...........................................................................................109

14. DMAC ___________________________________________________110

14.1 Transfer Cycles ......................................................................................................115

14.1.1 Effect of Source and Destination Addresses ...........................................................................115

14.1.2 Effect of BYTE Pin Level ...........................................................................................................115

A-3

14.1.3 Effect of Software Wait............................................................................................................... 115

14.1.4 Effect of RDY Signal ................................................................................................................... 115

_______

14.2 DMA Transfer Cycles ............................................................................................. 117

14.3 DMA Enable ............................................................................................................ 1 1 8

14.4 DMA Request.......................................................................................................... 118

14.5 Channel Priority and DMA Transfer Timing......................................................... 119

15. Timers __________________________________________________ 120

15.1 Timer A....................................................................................................................122

15.1.1 Timer Mode..................................................................................................................................126

15.1.2 Event Counter Mode ...................................................................................................................127

15.1.3 One-shot Timer Mode .................................................................................................................132

15.1.4 Pulse Width Modulation (PWM) Mode.......................................................................................134

15.2 Timer B....................................................................................................................137

15.2.1 Timer Mode..................................................................................................................................140

15.2.2 Event Counter Mode ..................................................................................................................141

15.2.3 Pulse Period and Pulse Width Measurement Mode.................................................................142

16. Three-Phase Motor Control Timer Function ___________________ 144

17. Serial I/O ________________________________________________ 154

17.1 UARTi (i=0 to 2) ......................................................................................................154

17.1.1 Clock Synchronous serial I/O Mode..........................................................................................164

17.1.2 Clock Asynchronous Serial I/O (UART) Mode..........................................................................172

17.1.3 Special Mode 1 (I2C mode) ........................................................................................................180

17.1.4 Special Mode 2 ............................................................................................................................190

17.1.5 Special Mode 3 (IE mode)...........................................................................................................195

17.1.6 Special Mode 4 (SIM Mode) (UART2) ........................................................................................197

17.2 SI/O3 and SI/O4 ......................................................................................................202

17.2.1 SI/Oi Operation Timing ...............................................................................................................205

17.2.2 CLK Polarity Selection ...............................................................................................................205

17.2.3 Functions for Setting an SOUTi Initial Value ............................................................................206

18. A/D Converter ____________________________________________ 207

18.1 Mode Description................................................................................................... 211

18.1.1 One-Shot Mode ............................................................................................................................211

18.1.2 Repeat mode ................................................................................................................................213

18.1.3 Single Sweep Mode ....................................................................................................................215

18.1.4 Repeat Sweep Mode 0 ................................................................................................................217

18.1.5 Repeat Sweep Mode 1 ................................................................................................................219

18.2 Function..................................................................................................................221

18.2.1 Resolution Select Function........................................................................................................221

18.2.2 Sample and Hold.........................................................................................................................221

18.2.3 Extended Analog Input Pins ......................................................................................................221

18.2.4 External Operation Amplifier (Op-Amp) Connection Mode ....................................................221

A-4

18.2.5 Current Consumption Reducing Function ...............................................................................222

18.2.6 Output Impedance of Sensor under A/D Conversion..............................................................222

19. D/A Converter ____________________________________________ 224

20. CRC Calculation __________________________________________ 226

21. Programmable I/O Ports ___________________________________ 228

21.1 Port Pi Direction Register (PDi Register, i = 0 to 13) ..........................................229

21.2 Port Pi Register (Pi Register, i = 0 to 13)..................................................................229

21.3

Pull-up Control Register 0 to Pull-up Control Register 3 (PUR0 to PUR3 Registers) ....

229

21.4 Port Control Register (PCR Register) ..................................................................229

22. Flash Memory Version _____________________________________ 242

22.1 Memory Map ...........................................................................................................244

22.1.1 Boot Mode ...................................................................................................................................245

22.2 Functions To Prevent Flash Memory from Rewriting......................................... 245

22.2.1 ROM Code Protect Function ...................................................................................................... 245

22.2.2 ID Code Check Function ............................................................................................................245

22.3 CPU Rewrite Mode .................................................................................................247

22.3.1 EW0 Mode....................................................................................................................................248

22.3.2 EW1 Mode....................................................................................................................................248

22.3.3 Flash memory Control Register (FIDR, FMR0 and FMR1 registers) ..................................... 248

22.3.4 Precautions on CPU Rewrite Mode ...........................................................................................254

22.3.5 Software Commands ..................................................................................................................256

22.3.6 Data Protect Function.................................................................................................................261

22.3.7 Status Register............................................................................................................................261

22.3.8 Full Status Check........................................................................................................................263

22.4 Standard Serial I/O Mode ......................................................................................265

22.4.1 ID Code Check Function ............................................................................................................265

22.4.2 Example of Circuit Application in the Standard Serial I/O Mode............................................271

22.5 Parallel I/O Mode ....................................................................................................273

22.5.1 User ROM and Boot ROM Areas................................................................................................273

22.5.2 ROM Code Protect Function ...................................................................................................... 273

23. Electrical Characteristics __________________________________ 274

23.1 Electrical Characteristics (M16C/62P)..................................................................274

23.2 Electrical Characteristics (M16C/62PT) ...............................................................313

24. Usage Precaution_________________________________________ 326

24.1 Reset .......................................................................................................................326

24.2 Bus ..........................................................................................................................327

24.3 PLL Frequency Synthesizer..................................................................................328

24.4 Power Control ........................................................................................................329

24.5 Protect.....................................................................................................................330

A-5

Appendix 1. Package Dimensions ______________________________ 359
Appendix 2. Differences Between M16C/62P and M16C/62A _________ 361

Register Index.......................................................... 364

A-7

SFR Page Reference

Address

0000h
0001h
0002h
0003h

Processor mode register 0 PM0

0004h

Processor mode register 1 PM1

0005h

System clock control register 0 CM0

0006h

System clock control register 1 CM1

0007h

Chip select control register CSR

0008h
0009h

Address match interrupt enable register AIER

000Ah

Protect register PRCR

000Bh

Data bank register DBR

000Ch

Oscillation stop detection register CM2

000Dh
000Eh

Watchdog timer start register WDTS

000Fh

Watchdog timer control register WDC

0010h

Address match interrupt register 0 RMAD0

0011h
0012h
0013h
0014h

Address match interrupt register 1 RMAD1

0015h
0016h
0017h
0018h
0019h

Voltage detection register 1 VCR1

001Ah

Voltage detection register 2 VCR2

001Bh

Chip select expansion control register CSE

001Ch

PLL control register 0 PLC0

001Dh
001Eh

Processor mode register 2 PM2

001Fh

Voltage down detection interrupt register D4INT

0020h
0021h

DMA0 source pointer SAR0

0022h
0023h
0024h

DMA0 destination pointer DAR0

0025h
0026h
0027h
0028h

DMA0 transfer counter TCR0

0029h
002Ah
002Bh
002Ch

DMA0 control register DM0CON

002Dh
002Eh
002Fh
0030h
0031h

DMA1 source pointer SAR1

0032h
0033h
0034h
0035h

DMA1 destination pointer DAR1

0036h
0037h
0038h

DMA1 transfer counter TCR1

0039h
003Ah
003Bh
003Ch

DMA1 control register DM1CON

003Dh
003Eh
003Fh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

Register Symbol Page

43
44

67
68
47

106

88
58
69

108
108

106

106

36
36
53
71

70
36

114

114

114

113

114

114

114

113

Address

0040h
0041h
0042h
0043h

INT3 interrupt control register INT3IC

0044h

Timer B5 interrupt control register TB5IC

0045h
0046h

Timer B4 interrupt control register, TB4IC,

UART1 BUS collision detection interrupt control register U1BCNIC

0047h

Timer B3 interrupt control register, TB3IC,
UART0 BUS collision detection interrupt control register U0BCNIC

0048h

SI/O4 interrupt control register S4IC,
INT5 interrupt control register INT5IC

0049h

SI/O3 interrupt control register, S3IC,

Register Symbol Page

INT4 interrupt control register INT4IC

004Ah

UART2 Bus collision detection interrupt control register BCNIC

004Bh

DMA0 interrupt control register DM0IC

004Ch

DMA1 interrupt control register DM1IC

004Dh

Key input interrupt control register KUPIC

004Eh

A/D conversion interrupt control register ADIC

004Fh

UART2 transmit interrupt control register

0050h

UART2 receive interrupt control register

0051h

UART0 transmit interrupt control register

0052h

UART0 receive interrupt control register
UART1 transmit interrupt control register

0053h

UART1 receive interrupt control register

0054h
0055h

Timer A0 interrupt control register TA0IC

0056h

Timer A1 interrupt control register TA1IC

0057h

Timer A2 interrupt control register TA2IC

0058h

Timer A3 interrupt control register TA3IC

0059h

Timer A4 interrupt control register TA4IC

005Ah

Timer B0 interrupt control register TB0IC

005Bh

Timer B1 interrupt control register TB1IC

005Ch

Timer B2 interrupt control register TB2IC

005Dh

INT0 interrupt control register INT0IC

005Eh

INT1 interrupt control register INT1IC

005Fh

INT2 interrupt control register INT2IC

0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh

S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC

95
95

95
95
95

95
95

95
95
95
95
95
95
95
95
95

95
95
95
95
95
95
95
95
95
95
95
95

B-1

SFR Page Reference

Address

0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h

to
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h

Flash identification register FIDR

01B5h

Flash memory control register 1 FMR1

01B6h
01B7h

Flash memory control register 0 FMR0

01B8h
01B9h

Address match interrupt register 2 RMAD2

01BAh
01BBh

Address match interrupt enable register 2

01BCh
01BDh

Address match interrupt register 3 RMAD3

01BEh
01BFh
01C0h

to
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh

Peripheral clock select register PCLKR

025Fh
0260h

to
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. This register is included in the flash memory version.

Register Symbol Page

(2)

(2)

(2)

AIER2

249
249

249

106
106

106

70

Address

0340h

Timer B3, 4, 5 count start flag TBSR

0341h
0342h

Timer A1-1 register TA11

0343h
0344h

Timer A2-1 register TA21

0345h
0346h

Timer A4-1 register TA41

0347h

Three-phase PWM control register 0 INVC0

0348h

Three-phase PWM control register 1 INVC1

0349h

Three-phase output buffer register 0 IDB0

034Ah

Three-phase output buffer register 1 IDB1

034Bh

Dead time timer DTT

034Ch

Timer B2 interrupt occurrence frequency set counter

034Dh
034Eh
034Fh
0350h

Timer B3 register TB3

0351h
0352h

Timer B4 register TB4

0353h
0354h

Timer B5 register TB5

0355h
0356h
0357h
0358h
0359h
035Ah
035Bh

Timer B3 mode register TB3MR

035Ch

Timer B4 mode register TB4MR

035Dh

Timer B5 mode register TB5MR
Interrupt cause select register 2 IFSR2A

035Eh

Interrupt cause select register IFSR

035Fh

SI/O3

0360h
0361h
0362h

SI/O3 control register S3C

0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh

bit rate generator

SI/O3

SI/O4

SI/O4 control register S4C
SI/O4

bit rate generator

UART0 special mode register 4 U0SMR4
UART0 special ode register 3 U0SMR3

UART0 special mode register 2 U0SMR2

UART0 special mode register U0SMR
UART1 special mode register 4 U1SMR4
UART1 special mode register 3 U1SMR3

UART1 special mode register 2 U1SMR2
UART1 special mode register U1SMR

UART2 special mode register 4 U2SMR4

UART2 special mode register 3 U2SMR3
UART2 special mode register 2 U2SMR2
UART2 special mode register U2SMR

UART2 transmit/receive mode register

UART2 bit rate generator

UART2 transmit buffer register

UART2 transmit/receive control register 0

UART2 transmit/receive control register 1
UART2 receive buffer register

Register Symbol Page

transmit/receive register

transmit/receive register

ICTB2

S3TRR

S3BRG
S4TRR

S4BRG

U2MR
U2BRG

U2TB
U2C0

U2C1
U2RB

139

149

149

149
146

147
148
148
148
149

139

139

139

138
138
138
103
103
203

203
203
203

203
203

163
162
162
161
163
162
162
161
163
162
162
161
159
158

158
159

160
158

B-2

SFR Page Reference

Address

Count start flag TABSR

0380h

Clock prescaler reset flag CPSRF

0381h

One-shot start flag ONSF

0382h

Trigger select register TRGSR

0383h

Up-down flag UDF

0384h
0385h
0386h

Timer A0 register TA0

0387h
0388h

Timer A1 register TA1

0389h
038Ah

Timer A2 register TA2

038Bh
038Ch

Timer A3 register TA3

038Dh
038Eh

Timer A4 register TA4

038Fh
0390h

Timer B0 register TB0

0391h
0392h

Timer B1 register TB1

0393h
0394h

Timer B2 register TB2

0395h
0396h

Timer A0 mode register TA0MR
Timer A1 mode register TA1MR

0397h

Timer A2 mode register TA2MR

0398h
0399h

Timer A3 mode register TA3MR

039Ah

Timer A4 mode register TA4MR
Timer B0 mode register TB0MR

039Bh
039Ch

Timer B1 mode register TB1MR

039Dh

Timer B2 mode register TB2MR

039Eh

Timer B2 special mode register TB2SC

039Fh
03A0h

UART0 transmit/receive mode register

03A1h

UART0 bit rate generator U0BRG

03A2h

UART0 transmit buffer register U0TB

03A3h
03A4h

UART0 transmit/receive control register 0

03A5h

UART0 transmit/receive control register 1

03A6h

UART0 receive buffer register U0RB

03A7h
03A8h

UART1 transmit/receive mode register

03A9h

UART1 bit rate generator U1BRG

03AAh

UART1 transmit buffer register U1TB

03ABh
03ACh

UART1 transmit/receive control register 0

03ADh

UART1 transmit/receive control register 1

03AEh

UART1 receive buffer register U1RB

03AFh
03B0h

UART transmit/receive control register 2

03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h

DMA0 request cause select register DM0SL

03B8h
03B9h
03BAh

DMA1 request cause select register DM1SL

03BBh
03BCh

CRC data register CRCD

03BDh
03BEh

CRC input register CRCIN

03BFh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. This register is included in the flash memory version.

Register Symbol Page

U0MR

U0C0
U0C1

U1MR

U1C0
U1C1

UCON

124, 139
150

125, 139

125

125, 150

124

124

124, 149

124, 149

124

124, 149

139

139

139, 150

123

123, 151
123, 151

123

123, 151

138
138

138. 151

149

159
158

158
159

160
158

159
158

158
159

160
158
161

112

113

226
226

Address

03C0h

A/D register 0 AD0

03C1h
03C2h

A/D register 1 AD1

03C3h
03C4h

A/D register 2 AD2

03C5h
03C6h

A/D register 3 AD3

03C7h
03C8h

A/D register 4 AD4

03C9h
03CAh

A/D register 5 AD5

03CBh
03CCh

A/D register 6 AD6

03CDh
03CEh

A/D register 7 AD7

03CFh
03D0h
03D1h
03D2h
03D3h

A/D control register 2 ADCON2

03D4h
03D5h
03D6h

A/D control register 0 ADCON0

03D7h

A/D control register 1 ADCON1
D/A register 0 DA0

03D8h
03D9h

D/A register 1 DA1

03DAh
03DBh
03DCh

D/A control register DACON

03DDh

Port P14 control register PC14

03DEh

Pull-up control register 3 PUR3

03DFh
03E0h

Port P0 register P0

03E1h

Port P1 register P1

03E2h

Port P0 direction register PD0

03E3h

Port P1 direction register PD1
Port P2 register P2

03E4h

Port P3 register P3

03E5h

Port P2 direction register PD2

03E6h
03E7h

Port P3 direction register PD3

03E8h

Port P4 register P4

03E9h

Port P5 register P5

03EAh

Port P4 direction register PD4

03EBh

Port P5 direction register PD5

03ECh

Port P6 register P6

03EDh

Port P7 register P7
Port P6 direction register PD6

03EEh

Port P7 direction register PD7

03EFh
03F0h

Port P8 register P8

03F1h

Port P9 register P9

03F2h

Port P8 direction register PD8

03F3h

Port P9 direction register PD9
Port P10 register P10

03F4h
03F5h

Port P11 register P11

03F6h

Port P10 direction register PD10

03F7h

Port P11 direction register PD11
Port P12 register P12

03F8h
03F9h

Port P13 register P13

03FAh

Port P12 direction register PD12
Port P13 direction register PD13

03FBh
03FCh

Pull-up control register 0 PUR0

03FDh

Pull-up control register 1 PUR1

03FEh

Pull-up control register 2 PUR2

03FFh

Port control register PCR

Register Symbol Page

210

210

210
210

210

210
210

210

210
209

209
225

225

225

237
237
236
236
235
235
236
236
235
235
236
236
235
235
236
236
235
235
236
236
235
235
236
236
235
235
236

236
235
235
238
238
238
239

B-3

M16C/62P Group (M16C/62P, M16C/62PT)

1.2 Performance Outline

Table 1.1 to table 1.3 list performance outline of M16C/62P group (M16C/62P, M16C/62PT).

Table 1.1 Performance Outline of M16C/62P group (M16C/62P) (128-pin version)

Item Performance

M16C/62P

CPU

Peripheral
Function

Electric
Characteris­tics

Flash Memory
Version

Operating Ambient Temperature –20 to 85oC

Package 128-pin plastic mold LQFP

NOTES:

1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Sep., 2004. Please inquire about a release schedule.

4. All options are on request basis.

Number of Basic Instructions 91 instructions
Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)

100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operation Mode Single-chip, memory expansion and microprocessor mode
Memory Space 1 Mbyte (Available to 4 Mbytes by memory space

expansion function)
Memory Capacity See Table 1.4 and 1.5 Product List
Port Input/Output : 113 pins, Input : 1 pin
Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels

Three phase motor control circuit
Serial I/O 3 channels

Clock synchronous, UART,

2

(1)

C bus

I

2 channels

Clock synchronous
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources,

Priority level: 7 levels

Clock Generation Circuit 4 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

On-chip oscillator, PLL synthesizer

(*)Equipped with a built-in feedback resistor.

Oscillation Stop Detection Function Stop detection of main clock oscillation

function
Voltage Detection Circuit Available (option
Supply Voltage VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=24MHz)

VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=10MHz)
Power Consumption 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)

8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)

1.8 µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)

0.7 µ A (VCC1=VCC2=3V, stop mode)
Program/Erase Supply Voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V
Program and Erase Endurance 100 times (all area)

or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)

–40 to 85oC

, IEBus

(3)

(4)

(2)

, re-oscillation detection

)

(3)

1. Overview

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M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.2 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (100-pin version)

Item Performance

M16C/62P M16C/62PT

CPU

Number of Basic Instructions 91 instructions
Minimum Instruction Execution Time

41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)

41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)

100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)

Operation Mode

Single-chip, memory expansion and

Single-chip mode

microprocessor mode

Memory Space 1 Mbyte (Available to 4 Mbytes by 1 Mbyte

memory space expansion function)

Memory Capacity See Table 1.4 to 1.7 Product List

Peripheral
function

Port Input/Output : 87 pins, Input : 1pin
Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels

Three phase motor control circuit

Serial I/O 3 channels

Clock synchronous, UART,

2

C bus

I

(1)

, IEBus

(2)

2 channels

Clock synchronous
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources,

Priority level: 7 levels

Clock Generation Circuit 4 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

On-chip oscillator, PLL synthesizer

(*)Equipped with a built-in feedback resistor.

Electric
characteris­tics

Oscillation Stop Detection Function
Voltage Detection Circuit Available (option
Supply Voltage

Power Consumption

Stop detection of main clock oscillation, re-oscillation detection function

(5)

) Absent

VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1

VCC1=VCC2=4.0V to 5.5 V
(f(BCLK)=24MHz) (f(BCLK)=24MHz)
VCC1=2.7 to 5.5V, V

(f(BCLK)=10MHz)

14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)

CC2

=2.7V to VCC1

14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0 µA (VCC1=VCC2=5V,

1.8 µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
f(XCIN)=32kHz, wait mode) 0.8 µ A (VCC1=VCC2=5V, stop mode)

0.7 µ A (VCC1=VCC2=3V, stop mode)

Flash memory
Version

Program/Erase Supply Voltage
Program and Erase Endurance

3.3 ± 0.3 V or 5.0 ± 0.5 V
100 times (all area)

5.0 ± 0.5 V

or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)

(3)

Operating Ambient Temperature –20 to 85oC T version : –40 to 85oC

–40 to 85oC

(3)

V version : –40 to 125oC

Package 100-pin plastic mold QFP, LQFP

NOTES:

2

C bus is a registered trademark of Koninklijke Philips Electronics N. V.

1. I

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Sep., 2004. Please inquire about a release schedule.

4. Use the M16C/62PT on VCC1 = VCC2.

5. All options are on request basis.

(Note 4)

1. Overview

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M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.3 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (80-pin version)

Item Performance

M16C/62P M16C/62PT

CPU

Peripheral
function

Electric
characteris­tics

Flash
memory
Version

Operating Ambient Temperature –20 to 85oC T version : –40 to 85oC

Package 80-pin plastic mold QFP

NOTES :

2

1. I

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Sep., 2004. Please inquire about a release schedule.

4. All options are on request basis.

Number of Basic Instructions 91 instructions
Minimum Instruction Execution Time

41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)

100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operation Mode Single-chip mode
Memory Space 1 Mbyte
Memory Capacity See Table 1.4 to 1.7 Product List
Port Input/Output : 70 pins, Input : 1pin
Multifunction Timer Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer)

Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial I/O 2 channels

Clock synchronous, UART,

2

C bus

I

(1)

, IEBus

(2)

1 channel

Clock synchronous,

2

C bus

I

(1)

, IEBus

(2)

2 channels

Clock synchronous (1 channel is only for transmission)
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 29 sources, External: 5 sources, Software: 4 sources,

Priority level: 7 levels

Clock Generating Circuit 4 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

On-chip oscillator, PLL synthesizer

(*)Equipped with a built-in feedback resistor.
Oscillation Stop Detection Function
Voltage Detection Circuit Available (option
Supply Voltage

Stop detection of main clock oscillation, re-oscillation detection function

(4)

) Absent
VCC1=3.0 to 5.5V, (f(BCLK)=24MHz) VCC1=4.0 to 5.5V, (f(BCLK)=24MHz)
VCC1=2.7 to 5.5V, (f(BCLK)=10MHz)

Power Consumption

14 mA (VCC1=5V, f(BCLK)=24MHz)

14 mA (VCC1=5V, f(BCLK)=24MHz)

8 mA (VCC1=3V, f(BCLK)=10MHz) 2.0 µA (VCC1=5V,

1.8 µA (VCC1=3V,

f(XCIN)=32kHz, wait mode) 0.8 µ A (VCC1=5V, stop mode)

f(XCIN)=32kHz, wait mode)

0.7 µ A (VCC1=3V, stop mode)

Program/Erase Supply Voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V
Program and Erase Endurance

100 times (all area)
or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)

(3)

–40 to 85oC(option) V version : –40 to 125oC

C bus is a registered trademark of Koninklijke Philips Electronics N. V.

1. Overview

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M16C/62P Group (M16C/62P, M16C/62PT)

A

1. Overview

1.3 Block Diagram

Figure 1.1 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin ver­sion, figure 1.2 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version.

8

Port P0

Internal peripheral functions

Port P18Port P2

Timer (16-bit)

Output (timer A): 5

Input (timer B): 6

Three-phase motor

control circuit

Watchdog timer

(15 bits)

DMAC

(2 channels)

D/A converter

(8 bits X 2 channels)

8 8 8 8

Port P4Port P3

<VCC2 ports>

Expandable up to 26 channels)

CRC arithmetic circuit (CCITT )

(4)

A/D converter

(10 bits X 8 channels

clock synchronous serial I/O

(Polynomial : X

UART or

(8 bits X 3 channels)

16+X12+X5

+1)

M16C/60 series16-bit CPU core

R0LR0H

R1H R1L

R2
R3

A0
A1
FB

INTB

PC

Port P5

System clock

generation circuit

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

On-chip oscillator

Clock synchronous serial I/O

(8 bits X 2 channels)

SB

USP

ISP

FLG

AAA

8

Port P6

<VCC1 ports>

Memory

(1)

ROM

(2)

RAM

Multiplier

(4)

<VCC1 ports>

(4)

Port P7

8

Port P8

7

Port P8_5

Port P9

8

Port P10

8

<VCC1 ports>

Port P11

(3)

(4)

Port P14

(3) (3)

<VCC2 ports>

Port P12

(4)

Port P13

(3)

8 8 82

NOTES :

1. ROM size depends on microcomputer type.

2. RAM size depends on microcomputer type.

3. Ports P11 to P14 exist only in 128-pin version.

4. Use M16C/62PT on VCC1= VCC2.

Figure 1.1 M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram

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M16C/62P Group (M16C/62P, M16C/62PT)

1. Overview

8

Port P0

Internal peripheral functions

Timer (16-bit)

Output (timer A): 5
Input (timer B): 6

Watchdog timer

(15 bits)

DMAC

(2 channels)

D/A converter

(8 bits X 2 channels)

8

Port P28Port P38Port P44Port P58Port P6

(4)

A/D converter

(10 bits X 8 channels

Expandable up to 26 channels)

UART or
clock synchronous serial I/O (2 channels)
UART (1 channel)

CRC arithmetic circuit (CCITT )

(Polynomial : X

16+X12+X5

(3)

+1)

M16C/60 series16-bit CPU core

R0LR0H

R1H R1L

R2
R3

A0
A1
FB

SB

USP

ISP

INTB

PC

FLG

System clock

generation circuit

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

On-chip oscillator

Clock synchronous serial I/O

(8 bits X 2 channels)

Memory

ROM

RAM

Multiplier

Port P7

4

Port P8

7

Port P8_5

(4)

(1)

(2)

Port P9

7

Port P10

8

NOTES :

1. ROM size depends on microcomputer type.

2. RAM size depends on microcomputer type.

3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).

4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.

Figure 1.2 M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram

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M16C/62P Group (M16C/62P, M16C/62PT)

1. Overview

1.4 Product List

Tables 1.4 to 1.7 list the product list, figure 1.3 shows the type numbers, memory sizes and packages, table

1.8 lists the product code of flash memory version and ROMless version for M16C/62P, and table 1.9 lists
the product code of flash memory version for M16C/62PT. Figure 1.4 shows the marking diagram of flash
memory version and ROMless version for M16C/62P, and figure 1.5 shows the marking diagram of flash
memory version for M16C/62PT. Please specify the mark of the mask ROM version at the time of ROM
order.

Table 1.4 Product List (1) (M16C/62P)

Type No.
M30622M6P-XXXFP
M30622M6P-XXXGP
M30623M6P-XXXGP

M30622M8P-XXXFP
M30622M8P-XXXGP
M30623M8P-XXXGP

M30622MAP-XXXFP
M30622MAP-XXXGP

M30623MAP-XXXGP
M30620MCP-XXXFP
M30620MCP-XXXGP

M30621MCP-XXXGP
M30622MEP-XXXFP
M30622MEP-XXXGP

M30623MEP-XXXGP
M30622MGP-XXXFP
M30622MGP-XXXGP
M30623MGP-XXXGP
M30624MGP-XXXFP

M30624MGP-XXXGP
M30625MGP-XXXGP
M30622MWP-XXXFP
M30622MWP-XXXGP
M30623MWP-XXXGP
M30624MWP-XXXFP
M30624MWP-XXXGP
M30625MWP-XXXGP

M30626MWP-XXXFP

M30626MWP-XXXGP

M30627MWP-XXXGP

(D): Under development

ROM Capacity Package Type

48 Kbytes

(D)

64 Kbytes

(D)

96 Kbytes

(D)

128 Kbytes

(D)

192 Kbytes

(D)

256 Kbytes

320 Kbytes

(D)
(D)
(D)
(D)

RAM Capacity

4 Kbytes

4 Kbytes

5 Kbytes

10 Kbytes

12 Kbytes

12 Kbytes

20 Kbytes

16 Kbytes

24 Kbytes

31 Kbytes

100P6S-A

100P6Q-A

80P6S-A

100P6S-A

100P6Q-A

80P6S-A

100P6S-A

100P6Q-A

80P6S-A

100P6S-A

100P6Q-A

80P6S-A

100P6S-A
100P6Q-A
128P6Q-A

100P6S-A
100P6Q-A
128P6Q-A

100P6S-A
100P6Q-A
128P6Q-A

100P6S-A
100P6Q-A
128P6Q-A

100P6S-A
100P6Q-A
128P6Q-A

100P6S-A
100P6Q-A
128P6Q-A

As of Sep. 2004

Remarks

Mask ROM version

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M16C/62P Group (M16C/62P, M16C/62PT)

1. Overview

Table 1.5 Product List (2) (M16C/62P)

ROM Capacity
M30622MHP-XXXFP
M30622MHP-XXXGP

M30623MHP-XXXGP
M30624MHP-XXXFP
M30624MHP-XXXGP

M30625MHP-XXXGP
M30626MHP-XXXFP

M30626MHP-XXXGP
M30627MHP-XXXGP

M30626MJP-XXXFP
M30626MJP-XXXGP

M30627MJP-XXXGP

M30622F8PFP
M30622F8PGP

M30623F8PGP
M30620FCPFP
M30620FCPGP
M30621FCPGP

M30624FGPFP
M30624FGPGP

M30625FGPGP
M30626FHPFP

M30626FHPGP
M30627FHPGP

(D)

384 Kbytes

(D)

(D)
(P)

512 Kbytes

(P)
(P)

64K+4 Kbytes

(D)

(D)

256K+4 Kbytes

ROM Capacity

16 Kbytes

24 Kbytes

31 Kbytes

31 Kbytes

4 Kbytes

10 Kbytes128K+4 Kbytes

20 Kbytes

Package Type

100P6S-A

100P6Q-A
128P6Q-A

100P6S-A
100P6Q-A
128P6Q-A

100P6S-A
100P6Q-A

128P6Q-A

100P6S-A
100P6Q-A

128P6Q-A

100P6S-A
100P6Q-A

80P6S-A

100P6S-A
100P6Q-A

80P6S-A

100P6S-A
100P6Q-A

128P6Q-A

100P6S-A
100P6Q-A31 Kbytes384K+4 Kbytes
128P6Q-A

As of Sep. 2004

RemarksType No.

Mask ROM version

Flash memory version

M30626FJPFP
M30626FJPGP
M30627FJPGP

M30622SPFP
M30622SPGP
M30620SPFP

M30620SPGP

(D): Under development
(P): Under planning

(P)
(P)

31 Kbytes512K+4 Kbytes

4 Kbytes

10 Kbytes

100P6S-A
100P6Q-A
128P6Q-A(P)

100P6S-A
100P6Q-A

100P6S-A
100P6Q-A

ROMless version

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M16C/62P Group (M16C/62P, M16C/62PT)

1. Overview

Table 1.6 Product List (3) (T version (M16C/62PT))

Type No.

M3062CM6T-XXXFP
M3062CM6T-XXXGP
M3062EM6T-XXXGP
M3062CM8T-XXXFP

M3062CM8T-XXXGP
M3062EM8T-XXXGP

M3062CMAT-XXXFP
M3062CMAT-XXXGP
M3062EMAT-XXXGP
M3062AMCT-XXXFP
M3062AMCT-XXXGP
M3062BMCT-XXXGP
M3062CF8TFP
M3062CF8TGP
M3062AFCTFP
M3062AFCTGP

M3062BFCTGP
M3062JFHTFP
M3062JFHTGP

(D): Under development
(P): Under planning

ROM Capacity
(D)
(D)

(P)
(D)

(D)

(P)
(D)

(D)

(P)
(D)
(D)

(P)

(D)
(D)
(D)

128K+4 Kbytes

(P)
(D)
(D)

RAM Capacity

4 Kbytes48 Kbytes

4 Kbytes64 Kbytes

5 Kbytes96 Kbytes

10 Kbytes128 Kbytes

4 Kbytes64 Kbytes

10 Kbytes

31 Kbytes384K+4 Kbytes

Package Type

100P6S-A
100P6Q-A

80P6S-A
100P6S-A
100P6Q-A

80P6S-A
100P6S-A

100P6Q-A

80P6S-A
100P6S-A

100P6Q-A

80P6S-A
100P6S-A(D)
100P6Q-A
100P6S-A

100P6Q-A

80P6S-A
100P6S-A

100P6Q-A

As of Sep. 2004

Remarks

Mask ROM
version

T Version
(High reliability
85 °C Version)

Flash memory
version

Table 1.7 Product List (4) (V version (M16C/62PT))

RAM CapacityROM Capacity
M3062CM6V-XXXFP
M3062CM6V-XXXGP
M3062EM6V-XXXGP
M3062CM8V-XXXFP
M3062CM8V-XXXGP
M3062EM8V-XXXGP
M3062CMAV-XXXFP
M3062CMAV-XXXGP
M3062EMAV-XXXGP
M3062AMCV-XXXFP
M3062AMCV-XXXGP
M3062BMCV-XXXGP
M3062AFCVFP
M3062AFCVGP
M3062BFCVGP
M3062JFHVFP
M3062JFHVGP

(D): Under development
(P): Under planning

(P)

(P)
(P)

(P)

(P)
(P)

(P)
(P)

(P)
(D)
(D)

(P)
(D)

(D)

(P)

(P)

(P)

4 Kbytes48 Kbytes

4 Kbytes64 Kbytes

5 Kbytes96 Kbytes

10 Kbytes128 Kbytes

31 Kbytes384K+4 Kbytes

Package Type

100P6S-A

100P6Q-A

80P6S-A

100P6S-A

100P6Q-A

80P6S-A

100P6S-A

100P6Q-A

80P6S-A

100P6S-A

100P6Q-A

80P6S-A

100P6S-A

100P6Q-A10 Kbytes128K+4 Kbytes

80P6S-A

100P6S-A

100P6Q-A

RemarksType No.

Mask ROM
version

Flash memory
version

As of Sep. 2004

V Version
(High reliability
125 °C Version)

page 9

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Z0320-5810B90JER

M16C/62P Group (M16C/62P, M16C/62PT)

Type No. M 3 0 6 2 6 M H P – X X X F P

1. Overview

Package type:
FP : Package 100P6S-A
GP : Package 80P6Q-A, 100P6Q-A, 128P6Q-A

ROM No.
Omitted for flash memory version and
ROMless version

Classification
P : M16C/62P
T : T version (M16C/62PT)
V : V version (M16C/62PT)

ROM capacity:
6: 48 Kbytes
8: 64 Kbytes
A: 96 Kbytes
C: 128 Kbytes
E: 192 Kbytes

Memory type:
M: Mask ROM version
F: Flash memory version
S: ROMless version

G: 256 Kbytes
W: 320 Kbytes
H: 384 Kbytes
J: 512 Kbytes

Figure 1.3 Type No., Memory Size, and Package

Shows RAM capacity, pin count, etc
Numeric : M16C/62P

Alphabet : M16C/62PT
M16C/62P Group
M16C Family

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Z0320-5810B90JER

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P

1. Overview

Flash Memory

Version

ROMless Version

Product

Code

D3
D5
D7
D9
U3
U5
U7
U9
D3
D5
U3
U5

Package

Lead-included

Lead-free

Lead-included

Lead-free

Internal ROM

(User ROM Area

Without Block 1)

Program

and Erase

Endurance

100

1,000

100

1,000

Temperature

Range

0°C to 60°C

Internal ROM

(Block A, Block 1)

Program

and Erase

Endurance

100

10,000

100

10,000

Temperature

Range

0°C to 60°C

-40°C to 85°C

-20°C to 85°C

0°C to 60°C

-40°C to 85°C

-20°C to 85°C

Operating

Ambient

Temperature

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

M16C

M30626FHPFP

BD5

XXXXXXX

The product without marking of chip version of the flash memory version and the ROMless version
corresponds to the chip version “A”.

Figure 1.4

Marking Diagram of Flash Memory version and ROMless version for M16C/62P (Top View)

Type No. (See Figure 1.3 Type No., Memory Size, and Package)

Chip version and product code

B : Shows chip version.

Henceforth, whenever it changes a version, it continues with B, C, and D.

D5 : Shows Product code. (See table 1.8 Product Code)

Date code seven digits

page 11

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Z0320-5810B90JER

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.9 Product Code of Flash Memory version for M16C/62PT

1. Overview

Flash

Memory

Version

T Version
V Version
T Version
V Version
T Version
V Version
T Version
V Version

Product

Code

B

B7

U

U7

Package

Lead-included

Lead-free

Internal ROM
(User ROM Area
Without Block 1)

Program

and Erase

Endurance

100

1,000

100

1,000

Temperature

Range

0°C to 60°C

Internal ROM

(Block A, Block 1)

Program

and Erase

Endurance

100

10,000

100

10,000

Temperature

Range

0°C to 60°C

-40°C to 85°C

-40°C to 125°C

0°C to 60°C

-40°C to 85°C

-40°C to 125°C

Operating

Ambient

Temperature

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

Figure 1.5

M1 6C

M3062JFHTFP

YYY XXXXXXX

Marking Diagram of Flash Memory version for M16C/62PT (Top View)

Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Date code seven digits

Product code. (See table 1.9 Product Code)

“ ” : Product code “B”
“ PBF” : Product code “U”
“ B7 ” : Product code “B7”

“ U7 ” : Product code “U7”

NOTES:

1. : Blank

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Z0320-5810B90JER

M16C/62P Group (M16C/62P, M16C/62PT)

1.5 Pin Configuration

Figures 1.6 to 1.9 show the pin configurations (top view).

PIN CONFIGURATION (top view)

P1_2/D10

P1_1/D9

101102

100

P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0

P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0

P10_3/AN3
P10_2/AN2
P10_1/AN1

AVSS

P10_0/AN0

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930

737475767778798081828384858687888990919293949596979899

31 32 33 34 35 36 37

P4_4/CS0

P4_5/CS1

P4_6/CS2

66676869707172

65

38

P4_7/CS3

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

1. Overview

P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK

P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT

P6_0/CTS0/RTS0
P6_1/CLK0

P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1

BYTE

CNVSS

P8_7/XCIN

P9_3/DA0/TB3IN

P9_4/DA1/TB4IN

P9_1/TB1IN/SIN3

P9_5/ANEX0/CLK4

P9_6/ANEX1/SOUT4

P9_0/TB0IN/CLK3

P9_2/TB2IN/SOUT3

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

2. Use the M16C/62PT on VCC1 = VCC2.

Figure 1.6 Pin Configuration (Top View)

page 13

Z0320-5810B90JER

463fo4002,10peS03.2.veR

VSS

XOUT

RESET

P8_6/XCOUT

XIN

VCC1

P8_5/NMI

P8_3/INT1

P8_2/INT0

P8_4/INT2/ZP

P8_1/TA4IN/U

P7_7/TA3IN

P7_6/TA3OUT

P7_5/TA2IN/W

P8_0/TA4OUT/U

P7_4/TA2OUT/W

(1)

(1)

P6_7/TXD1/SDA1

P6_6/RXD1/SCL1

P7_2/CLK2/TA1OUT/V

P7_3/CTS2/RTS2/TA1IN/V

P7_0/TXD2/SDA2/TA0OUT

P7_1/RXD2/SCL2/TA0IN/TB5IN

Package: 128P6Q-A

M16C/62P Group (M16C/62P, M16C/62PT)

(

)

PIN CONFIGURATION (top view)

1. Overview

P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0

P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3
P10_2/AN2
P10_1/AN1

AVSS

P10_0/AN0

VREF

P9_7/ADTRG/SIN4

AVCC

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

2. Use the M16C/62PT on VCC1 = VCC2.

P2_7/AN2_7/A7(/D7/D6)

P2_0/AN2_0/A0(/D0/-)

P1_7/D15/INT5

P1_0/D8

P1_1/D9

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
00

1

1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930

P9_5/ANEX0/CLK4

P9_6/ANEX1/SOUT4

P1_5/D13/INT3

P1_2/D10

P1_3/D11

P1_4/D12

P9_4/DA1/TB4IN

P9_3/DA0/TB3IN

P9_1/TB1IN/SIN3

P9_2/TB2IN/SOUT3

P2_1/AN2_1/A1(/D1/D0)

P1_6/D14/INT4

M16C/62P Group

M16C/62P, M16C/62PT

BYTE

CNVSS

P8_7/XCIN

P9_0/TB0IN/CLK3

P2_5/AN2_5/A5(/D5/D4)

P2_6/AN2_6/A6(/D6/D5)

P2_4/AN2_4/A4(/D4/D3)

P2_2/AN2_2/A2(/D2/D1)

P2_3/AN2_3/A3(/D3/D2)

<VCC2>

<VCC1>

VSS

XOUT

RESET

P8_6/XCOUT

XIN

(2)

(2)

VCC1

P3_0/A8(/-/D7)

VSS

P8_5/NMI

P8_4/INT2/ZP

VCC2

P3_1/A9

P3_2/A10

P8_3/INT1

P8_2/INT0

P8_1/TA4IN/U

P3_6/A14

P3_3/A11

P8_0/TA4OUT/U

P3_7/A15

P3_4/A12

P3_5/A13

P7_7/TA3IN

P7_6/TA3OUT

P7_5/TA2IN/W

P7_4/TA2OUT/W

P4_0/A16

P4_1/A17

P4_2/A18

P4_3/A19

515253545556575859606162636465666768697071727374757677787980

50

P4_4/CS0

49

P4_5/CS1

48

P4_6/CS2

47

P4_7/CS3

46

P5_0/WRL/WR

45

P5_1/WRH/BHE

44

P5_2/RD

43

P5_3/BCLK

42

P5_4/HLDA

41

P5_5/HOLD

40

P5_6/ALE

39

P5_7/RDY/CLKOUT

38

P6_0/CTS0/RTS0

37

P6_1/CLK0

36

P6_2/RXD0/SCL0

35

P6_3/TXD0/SDA0

34

P6_4/CTS1/RTS1/CTS0/CLKS1

33

P6_5/CLK1

32

P6_6/RXD1/SCL1

31

P6_7/TXD1/SDA1

(1)

(1)

P7_2/CLK2/TA1OUT/V

P7_3/CTS2/RTS2/TA1IN/V

P7_0/TXD2/SDA2/TA0OUT

P7_1/RXD2/SCL2/TA0IN/TB5IN

Package: 100P6S-A

Figure 1.7 Pin Configuration (Top View)

page 14

Z0320-5810B90JER

463fo4002,10peS03.2.veR

M16C/62P Group (M16C/62P, M16C/62PT)

(

)

PIN CONFIGURATION (top view)

1. Overview

P1_2/D10

P1_1/D9
P1_0/D8

P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3
P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

VREF

P9_7/ADTRG/SIN4

P9_6/ANEX1/SOUT4

P9_5/ANEX0/CLK4

AVCC

P2_3/AN2_3/A3(/D3/D2)

P2_4/AN2_4/A4(/D4/D3)

P2_5/AN2_5/A5(/D5/D4)

P1_3/D11

P1_4/D12

P1_5/D13/INT3

76
77
78
79
80

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

00

1

1 2 3 4 5 6 7 8 9 10111213141516171819202122232425

P2_1/AN2_1/A1(/D1/D0)

P2_0/AN2_0/A0(/D0/-)

P1_6/D14/INT4

P2_2/AN2_2/A2(/D2/D1)

P1_7/D15/INT5

M16C/62P Group

M16C/62P, M16C/62PT

P2_6/AN2_6/A6(/D6/D5)

P2_7/AN2_7/A7(/D7/D6)

<VCC2>

<VCC1>

P3_1/A9

VSS

VCC2

P3_0/A8(/-/D7)

(2)

(2)

P3_2/A10

P3_3/A11

P3_4/A12

57585960616263646566676869707172737475

P3_7/A15

P3_5/A13

P3_6/A14

P4_0/A16

P4_1/A17

515253545556

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

P4_2/A18
P4_3/A19

P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT

P7_1/RXD2/SCL2/TA0IN/TB5IN
P7_2/CLK2/TA1OUT/V

(1)

(1)

P9_4/DA1/TB4IN

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

2. Use the M16C/62PT on VCC1 = VCC2.

Figure 1.8 Pin Configuration (Top View)

page 15

Z0320-5810B90JER

BYTE

P9_3/DA0/TB3IN

P9_1/TB1IN/SIN3

P9_0/TB0IN/CLK3

P9_2/TB2IN/SOUT3

463fo4002,10peS03.2.veR

CNVSS

P8_7/XCIN

P8_6/XCOUT

XOUT

RESET

VSS

XIN

VCC1

P8_5/NMI

P8_2/INT0

P8_3/INT1

P8_4/INT2/ZP

P7_7/TA3IN

P8_1/TA4IN/U

P7_6/TA3OUT

P7_5/TA2IN/W

P8_0/TA4OUT/U

P7_4/TA2OUT/W

P7_3/CTS2/RTS2/TA1IN/V

Package: 100P6Q-A

M16C/62P Group (M16C/62P, M16C/62PT)

(

)

PIN CONFIGURATION (top view)

1. Overview

P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1

P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0

P10_3/AN3
P10_2/AN2
P10_1/AN1

AVSS

P10_0/AN0

VREF

AVCC

P9_7/ADTRG/SIN4

P9_6/ANEX1/SOUT4

P0_7/AN0_7

P2_0/AN2_0

P2_1/AN2_1

61
62
63
64
65
66
67
68
69
70
71
72
73
74

75
76

77
78
79
80

1 2 3 4 5 6 7 8 9 1011121314151617181920

P9_4/DA1/TB4IN

P9_3/DA0/TB3IN

P9_5/ANEX0/CLK4

P2_4/AN2_4

P2_2/AN2_2

P2_3/AN2_3

56

P2_7/AN2_7

P2_5/AN2_5

P2_6/AN2_6

P3_0

M16C/62P Group

M16C/62P, M16C/62PT

XOUT

RESET

P8_7/XCIN

P8_6/XCOUT

CNVSS(BYTE)

P9_0/TB0IN/CLK3

P9_2/TB2IN/SOUT3

P3_1

VSS

P3_2

XIN

P3_4

P3_3

VCC1

P8_5/NMI

P3_7

P3_6

P3_5

P8_3/INT1

P8_2/INT0

P8_4/INT2/ZP

P4_2

P4_0

P4_1

41424344454647484950515253545557585960

40
39
38
37

36
35
34

33
32
31
30
29
28
27
26
25
24
23
22
21

P7_7/TA3IN

P8_1/TA4IN

P8_0/TA4OUT

P4_3
P5_0
P5_1
P5_2
P5_3

P5_4
P5_5

P5_6
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT
P7_1/RXD2/SCL2/TA0IN/TB5IN
P7_6/TA3OUT

(1)

(1)

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

Figure 1.9 Pin Configuration (Top View)

page 16

Z0320-5810B90JER

Package: 80P6S-A

463fo4002,10peS03.2.veR

M16C/62P Group (M16C/62P, M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.11 Pin Description (100-pin and 128-pin Version) (2)

I

O

I

O

O
O

I
I
I

I

I/O

I

I
I

O

I

O

I/O

I
I

O

O
O

I/O

I/O

Power

Supply

VCC1
VCC1

VCC1
VCC1

VCC2
VCC2
VCC1
VCC2
VCC1

VCC1

VCC1

VCC1

VCC1
VCC1

VCC1

VCC1
VCC1
VCC1
VCC1
VCC1
VCC1

VCC1
VCC1
VCC1

VCC1

(1)

I/O pins for the main clock generation circuit. Connect a ceramic resonator or
crystal oscillator between XIN and XOUT
clock from XIN and leave XOUT open.
I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between
XCIN and XCOUT

(3)

. To use the external clock, input the clock from XCIN and
leave XCOUT open.
Outputs the BCLK signal.
The clock of the same cycle as fC, f8, or f32 is outputted.

______

Input pins for the INT interrupt

Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8

_______

register.
Input pins for the key input interrupt

These are timer A0 to timer A4 I/O pins. (except the output of TAOUT for the N­channel open drain output.)
These are timer A0 to timer A4 input pins.

Input pin for the Z-phase.
These are timer B0 to timer B5 input pins.

These are Three-phase motor control output pins.

These are send control input pins.
These are receive control output pins.
These are transfer clock I/O pins.
These are serial data input pins.
These are serial data input pins.
These are serial data output pins. (except TXD2 for the N-channel open drain
output.)
These are serial data output pins.
This is output pin for transfer clock output from multiple pins function.
These are serial data I/O pins. (except SDA2 for the N-channel open drain
output.)
These are transfer clock I/O pins. (except SCL2 for the N-channel open drain
output.)

Signal Name Pin Name I/O Type Description

(2)

XIN
XOUT

XCIN
XCOUT

BCLK
CLKOUT

________ ________

INT0 to INT2

________ ________

INT3 to INT5

_______

NMI

_____ ______

KI0 to KI3

Main clock input
Main clock output

Sub clock input
Sub clock output

BCLK output
Clock output

______

INT interrupt input

_______

NMI interrupt input

Key input interrupt
input
Timer A

TA0OUT to
TA4OUT
TA0IN to
TA4IN
ZP

Timer B

Three-phase motor
control output
Serial I/O

TB0IN to
TB5IN

__ __

U, U, V, V,

__

W, W

__________ ________

CTS0 to CTS2

________ ________

RTS0 to RTS2
CLK0 to CLK4
RXD0 to RXD2
SIN3, SIN4
TXD0 to
TXD2
SOUT3, SOUT4
CLKS1

I2C mode

SDA0 to SDA2

SCL0 to SCL2

I : Input O : Output I/O : Input and output

1. Overview

(3)

. To use the external clock, input the

NOTES:

1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.

2. This pin function in M16C/62PT cannot be used.

3. Ask the oscillator maker the oscillation characteristic.

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M16C/62P Group (M16C/62P, M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.13 Pin Description (80-pin Version) (1)

Signal Name Pin Name I/O Type Description

Power supply input

VCC1,

VSS
Analog power
supply input
Reset input
CNVSS

AVCC,

AVSS

____________

RESET

CNVSS

(BYTE)

Main clock input
Main clock output

Sub clock input
Sub clock output

Clock output

______

INT interrupt input

_______

NMI interrupt input
Key input interrupt

XIN

XOUT

XCIN

XCOUT

CLKOUT

________ ________

INT0 to INT2

_______

NMI

______ ______

KI0 to KI3
input
Timer A

TA0OUT,

I/O
TA3OUT,
TA4OUT
TA0IN,
TA3IN,
TA4IN
ZP

Timer B

Serial I/O

TB0IN,
TB2IN to TB5IN

_________ _________

CTS0, CTS2

_________ _________

RTS0, RTS2
CLK0, CLK1,

I/O
CLK3, CLK4
RXD0 to RXD2
SIN4
TXD0 to TXD4

SOUT3, SOUT4
CLKS1

I2C mode

SDA0 to SDA2

SCL0 to SCL2

I/O

I/O

I : Input O : Output I/O : Input and output

Power

Supply

I

I

-

VCC1

Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin.

Applies the power supply for the A/D converter. Connect the AVCC pin to
VCC1. Connect the AVSS pin to VSS.

I

VCC1

I

VCC1

The microcomputer is in a reset state when applying "L" to the this pin.
Switches processor mode. Connect this pin to V
start up in single-chip mode. Connect this pin to V
cessor mode. As for the BYTE pin of the 80-pin versions, pull-up processing
is performed within the microcomputer.

I

VCC1

O

VCC1

I/O pins for the main clock generation circuit. Connect a ceramic resonator or
crystal oscillator between XIN and XOUT
the clock from XIN and leave XOUT open.

I

VCC1

O

VCC1

I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between
XCIN and XCOUT

(3)

. To use the external clock, input the clock from XCIN

and leave XCOUT open.

O

VCC2

I

VCC1

I

VCC1

I

VCC1

VCC1

The clock of the same cycle as fC, f8, or f32 is outputted.
Input pins for the INT interrupt

______

_______

Input pin for the NMI interrupt.
Input pins for the key input interrupt

These are timer A0, timer A3 and Timer A4 I/O pins. (except the output of
TAOUT for the N-channel open drain output.)

I

VCC1

I

VCC1

I

VCC1

I

VCC1

O

VCC1
VCC1

I

VCC1

I

VCC1

O

VCC1

These are timer A0, timer A3 and Timer A4 input pins.

Input pin for the Z-phase.
These are timer B0, timer B2 to timer B5 input pins.

These are send control input pins.
These are receive control output pins.
These are transfer clock I/O pins.

These are serial data input pins.
These are serial data input pins.
These are serial data output pins. (except TXD2 for the N-channel open drain
output.)

O

VCC1

O

VCC1
VCC1

These are serial data output pins.
This is output pin for transfer clock output from multiple pins function.
These are serial data I/O pins. (except SDA2 for the N-channel open drain
output.)

VCC1

These are transfer clock I/O pins. (except SCL2 for the N-channel open drain
output.)

1. Overview

(2)

SS

to when after a reset to

CC1

to start up in micropro-

(3)

. To use the external clock, input

NOTES:

1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin.

3. Ask the oscillator maker the oscillation characteristic.

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M16C/62P Group (M16C/62P, M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

2. Central Processing Unit (CPU)

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.

Figure 2.1 Central Processing Unit Register

2.1 Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R37Tj 0 0 12 53f 16 bits, and is used ma1ic/logic 19

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M16C/62P Group (M16C/62P, M16C/62PT)

2. Central Processing Unit (CPU)

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3 Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4 Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5 Register Bank Select Flag (B Flag)

Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.

2.8.6 Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.

2.8.10 Reserved Area

When write to this bit, write “0”. When read, its content is indeterminate.

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M16C/62P Group (M16C/62P, M16C/62PT)

A

A

A

A

3. Memory

Figure 3.1 is a memory map of the M16C/62P group. The address space extends the 1M bytes from
address 00000h to FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a
64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is
mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the
start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example,
a 10-Kbyte internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data,
the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SRF is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by
the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users. Use M16C/62P (80-pin version) and M16C/62PT in single-chip mode. The memory expan­sion and microprocessor modes cannot be used.

3. Memory

00000h

SFR

00400h

Internal RAM

Internal RAM

Size

Address XXXXXh

4K bytes 013FFh

5K bytes

10K bytes
12K bytes

20K bytes
24K bytes

31K bytes

017FFh
02BFFh

033FFh
043FFh16K bytes

053FFh
063FFh

07FFFh

Internal ROM

48K bytes
64K bytes

96K bytes
128K bytes
192K bytes

256K bytes
320K bytes
384K bytes
512K bytes

Address YYYYYhSize

(3)

F4000h
F0000h

E8000h
E0000h
D0000h
C0000h
B0000h
A0000h
80000h

XXXXXh

0F000h

0FFFFh

10000h

27000h

28000h

80000h

YYYYYh

FFFFFh

Reserved area

Internal ROM
(data area)

External area

AAAA
AAAA

Reserved area

AAAA

External area

AAAA

Reserved area

Internal ROM

(program area)

(1)

(3)

(2)

(5)

NOTES:

1. During memory expansion and microprocessor modes, can not be used.

2. In memory expansion mode, can not be used.

3. As for the flash memory version, 4-Kbyte space (block A) exists.

4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1”
and the PM13 bit in the PM1 register is “1”.

5. When using the masked ROM version, write nothing to internal ROM area.

FFE00h

FFFDCh

FFFFFh

Special page

vector table

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer

DBC

NMI

Reset

Figure 3.1 Memory Map

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M16C/62P Group (M16C/62P, M16C/62PT)

e

4. Special Function Register (SFR)

4. Special Function Register (SFR)

SFR(Special Function Register) is the control register of peripheral functions. Table 4.1 to 4.6 list the SFR
information.

Table 4.1 SFR information (1)

Address

0000h
0001h
0002h
0003h
0004h

Processor Mode Register 0
Processor Mode Register 1 PM1 00001000b

0005h

System Clock Control Register 0 CM0 01001000b

0006h

System Clock Control Register 1 CM1 00100000b

0007h
0008h

Chip Select Control Register
Address Match Interrupt Enable Register AIER XXXXXX00b

0009h

Protect Register PRCR XX000000b

000Ah
000Bh

Data Bank Register

000Ch

Oscillation Stop Detection Register

000Dh

Watchdog Timer Start Register WDTS XXh

000Eh
000Fh

Watchdog Timer Control Register WDC 00XXXXXXb

0010h

Address Match Interrupt Register 0 RMAD0 00h

0011h
0012h
0013h
0014h

Address Match Interrupt Register 1 RMAD1 00h

0015h
0016h
0017h
0018h
0019h

Voltage Detection Register 1
Voltage Detection Register 2

001Ah

Chip Select Expansion Control Register

001Bh

PLL Control Register 0 PLC0 0001X010b

001Ch
001Dh

Processor Mode Register 2 PM2 XXX00000b

001Eh

Voltage Down Detection Interrupt Register

001Fh
0020h

DMA0 Source Pointer SAR0 XXh

0021h
0022h
0023h
0024h

DMA0 Destination Pointer DAR0 XXh

0025h
0026h
0027h
0028h

DMA0 Transfer Counter TCR0 XXh

0029h
002Ah
002Bh
002Ch

DMA0 Control Register DM0CON 00000X00b

002Dh
002Eh
002Fh
0030h

DMA1 Source Pointer SAR1 XXh

0031h
0032h
0033h
0034h

DMA1 Destination Pointer DAR1 XXh

0035h
0036h
0037h
0038h

DMA1 Transfer Counter TCR1 XXh

0039h
003Ah
003Bh
003Ch

DMA1 Control Register DM1CON 00000X00b

003Dh
003Eh
003Fh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.

3. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.

4. The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input voltage

5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.

6. This register in M16C/62PT cannot be used.

X : Nothing is mapped to this bit

CC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit enabl

at the V

(6)

(1)

Register Symbol After Reset

(2)

(6)

(5, 6)
(5, 6)

(3)

(6)

(6)

PM0 00000000b(CNVSS pin is “L”)

00000011b(CNVSS pin is “H”)

CSR 00000001b

DBR 00h
CM2 0X000000b

00h
X0h

00h
X0h

VCR1 00001000b
VCR2 00h
CSE 00h

D4INT 00h

XXh
XXh

XXh
XXh

XXh

XXh
XXh

XXh
XXh

XXh

(4)

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

Table 4.2 SFR information (2)

A d d r e s s

0 0 4 0 h
0 0 4 1 h
0 0 4 2 h
0 0 4 3 h

N T 3 I

X 0 0 X 0 0 0

0 0 4 4 h

I N T 3 I n t e r r u p t C o n t r o l R e g i s t e rI

0 0 4 5 h

Timer B5 Interrupt Contr ol Re gis ter TB5IC XXXXX000b

0 0 4 6 h

T i m e r B 4 I n t e r r u p t C o n t r o l R e g i s t e r , U A R T 1 B U S C o l l i s i o n D e t e c t i o n I n t e r r u p t C o n t r o l R e g i s t e rT B 4 I C , U 1 B C N I C

0 0 4 7 h

T i m e r B 3 I n t e r r u p t C o n t r o l R e g i s t e r , U A R T 0 B U S C o l l i s i o n D e t e c t i o n I n t e r r u p t C o n t r o l R e g i s t e rT B 3 I C , U 0 B C N I C

X 0 0 X 0 0 0

0 0 4 8 h

S I / O 4 I n t e r r u p t C o n t r o l R e g i s t e r ( S 4 I C ) , I N T 5 I n t e r r u p t C o n t r o l R e g i s t e rS 4 I C
3 I

X 0 0 X 0 0 0

0 0 4 9 h

S I / O 3 I n t e r r u p t C o n t r o l R e g i s t e r , I N T 4 I n t e r r u p t C o n t r o l R e g i s t e rS

C N I

0 0 4 A h
0 0 4 B h
0 0 4 C h
0 0 4 D h
0 0 4 E h
0 0 4 F h
0 0 5 0 h
0 0 5 1 h
0 0 5 2 h
0 0 5 3 h
0 0 5 4 h
0 0 5 5 h
0 0 5 6 h
0 0 5 7 h
0 0 5 8 h
0 0 5 9 h
0 0 5 A h
0 0 5 B h
0 0 5 C h
0 0 5 D h
0 0 5 E h
0 0 5 F h

0 0 6 0 h
0 0 6 1 h
0 0 6 2 h
0 0 6 3 h
0 0 6 4 h
0 0 6 5 h
0 0 6 6 h
0 0 6 7 h
0 0 6 8 h
0 0 6 9 h
0 0 6 A h
0 0 6 B h
0 0 6 C h
0 0 6 D h
0 0 6 E h
0 0 6 F h
0 0 7 0 h
0 0 7 1 h
0 0 7 2 h
0 0 7 3 h
0 0 7 4 h
0 0 7 5 h
0 0 7 6 h
0 0 7 7 h
0 0 7 8 h
0 0 7 9 h
0 0 7 A h
0 0 7 B h
0 0 7 C h
0 0 7 D h
0 0 7 E h
0 0 7 F h

NO T E S :

X : N o t h i n g i s m a p p e d t o t h i s b i t

X X X X 0 0 0
U A R T 2 B u s C o l l i s i o n D e t e c t i o n I n t e r r u p t C o n t r o l R e g i s t e rB

M 0 I

X X X X 0 0 0
D M A 0 I n t e r r u p t C o n t r o l R e g i s t e rD

M 1 I

X X X X 0 0 0
D M A 1 I n t e r r u p t C o n t r o l R e g i s t e rD

U P I

X X X X 0 0 0
K e y I n p u t I n t e r r u p t C o n t r o l R e g i s t e rK

A/D Conversion Interrupt Control Register ADIC XXXXX000b

UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register

X X X X 0 0 0

U A R T 0 T r a n s m i t I n t e r r u p t C o n t r o l R e g i s t e r

X X X X 0 0 0

U A R T 0 R e c e i v e I n t e r r u p t C o n t r o l R e g i s t e r

X X X X 0 0 0

U A R T 1 T r a n s m i t I n t e r r u p t C o n t r o l R e g i s t e r

X X X X 0 0 0

U A R T 1 R e c e i v e I n t e r r u p t C o n t r o l R e g i s t e r

Timer A0 Interrupt Contr ol Re gis ter TA0IC XXXXX000b

A 1 I

X X X X 0 0 0
T i m e r A 1 I n t e r r u p t C o n t r o l R e g i s t e rT

A 2 I

X X X X 0 0 0
T i m e r A 2 I n t e r r u p t C o n t r o l R e g i s t e rT

Timer A3 Interrupt Contr ol Re gis ter TA3IC XXXXX000b

A 4 I

X X X X 0 0 0
T i m e r A 4 I n t e r r u p t C o n t r o l R e g i s t e rT

B 0 I

X X X X 0 0 0
T i m e r B 0 I n t e r r u p t C o n t r o l R e g i s t e r T

Timer B1 Interrupt Contr ol Re gis ter TB1IC XXXXX000b

B 2 I

X X X X 0 0 0
T i m e r B 2 I n t e r r u p t C o n t r o l R e g i s t e rT

INT0 Interrupt Control Register INT0IC XX00X000b

N T 1 I

X 0 0 X 0 0 0
I N T 1 I n t e r r u p t C o n t r o l R e g i s t e rI

N T 2 I

X 0 0 X 0 0 0
I N T 2 I n t e r r u p t C o n t r o l R e g i s t e rI

1 . T h e b l a n k a r e a s a r e r e s e r v e d a n d c a n n o t b e a c c e s s e d b y u s e r s .

(1)

R e g i s t e rS

y m b o

f t e r R e s e

lA

CX

X X X X X 0 0 0 b
X X X X X 0 0 0 b

,

I N T 5 I CX

C

,

I N T 4 I CX

CX
CX
CX

CX

S2TIC XXXXX000b
S2RIC XXXXX000b

S 0 T I CX
S 0 R I CX

S 1 T I CX
S 1 R I CX

CX
CX

CX
CX

CX

CX

CX

t

b

b

b

b

b
b
b

b
b

b
b

b
b

b
b

b

b

b

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

Table 4.3 SFR information (3)

Address

0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h

to
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
00C0h

02AFh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h

032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh

Flash Identification Register
Flash Memory Control Register 1

Flash Memory Control Register 0

Address Match Interrupt Register 2 RMAD2 00h

Address Match Interrupt Enable Register 2

Address Match Interrupt Register 3 RMAD3 00h

to

Peripheral Clock Select Register PCLKR 00000011b

to

(1)

Register

(2)

(2)

(2)

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. This register is included in the flash memory version.

Symbol

After Reset

FIDR XXXXXX00b
FMR1 0X00XX0Xb

FMR0 00000001b

00h
X0h

AIER2 XXXXXX00b

00h
X0h

X : Nothing is mapped to this bit

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

Table 4.4 SFR information (4)

Address

0340h

Timer B3, 4, 5 Count Start Flag TBSR 000XXXXXb

0341h

0342h

Timer A1-1 Register TA11 XXh

0343h

0344h

Timer A2-1 Register TA21 XXh

0345h

0346h

Timer A4-1 Register TA41 XXh

0347h

0348h

Three-Phase PWM Control Register 0 INVC0 00h

0349h

Three-Phase PWM Control Register 1 INVC1 00h

034Ah

Three-Phase Output Buffer Register 0 IDB0 00h

034Bh

Three-Phase Output Buffer Register 1 IDB1 00h

034Ch

Dead Time Timer DTT XXh

034Dh

Timer B2 Interrupt Occurrence Frequency Set Counter ICTB2 XXh

034Eh

034Fh

0350h

Timer B3 Register TB3 XXh

0351h

0352h

Timer B4 Register TB4 XXh

0353h

0354h

Timer B5 Register TB5 XXh

0355h

0356h

0357h

0358h

0359h

035Ah

035Bh

Timer B3 Mode Register TB3MR 00XX0000b

035Ch

Timer B4 Mode Register TB4MR 00XX0000b

035Dh

Timer B5 Mode Register TB5MR 00XX0000b

035Eh

Interrupt Cause Select Register 2 IFSR2A 00XXXXXXb

035Fh

Interrupt Cause Select Register IFSR 00h

0360h

SI/O3

0361h

0362h

0363h

0364h

0365h

0366h

0367h

0368h

0369h

036Ah

036Bh

036Ch

036Dh

036Eh

036Fh

0370h

0371h

0372h

0373h

0374h

0375h

0376h

0377h

0378h

0379h

037Ah

037Bh

037Ch

037Dh

037Eh

037Fh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

Transmit/Receive Register

SI/O3 Control Register S3C 01000000b
SI/O3

Bit Rate Generator

SI/O4

Transmit/Receive Register

SI/O4 Control Register S4C 01000000b
SI/O4

Bit Rate Generator

UART0 Special Mode Register 4 U0SMR4 00h
UART0 Special Mode Register 3 U0SMR3 000X0X0Xb
UART0 Special Mode Register 2 U0SMR2 X0000000b

UART0 Special Mode Register U0SMR X0000000b
UART1 Special Mode Register 4 U1SMR4 00h
UART1 Special Mode Register 3 U1SMR3 000X0X0Xb
UART1 Special Mode Register 2 U1SMR2 X0000000b

UART1 Special Mode Register U1SMR X0000000b
UART2 Special Mode Register 4 U2SMR4 00h
UART2 Special Mode Register 3 U2SMR3 000X0X0Xb
UART2 Special Mode Register 2 U2SMR2 X0000000b
UART2 Special Mode Register U2SMR X0000000b

UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator

UART2 Transmit Buffer Register
UART2 Transmit/Receive Control Register 0

UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register

(1)

Register Symbol After Reset

XXh

XXh

XXh

XXh
XXh
XXh

S3TRR XXh

S3BRG XXh
S4TRR XXh

S4BRG XXh

U2MR 00h
U2BRG XXh

U2TB XXh

XXh

U2C0 00001000b

U2C1 00000010b
U2RB XXh

XXh

X : Nothing is mapped to this bit

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

Table 4.5 SFR information (5)

Address

0380h

Count Start Flag TABSR 00h

0381h

Clock Prescaler Reset Fag CPSRF 0XXXXXXXb

0382h

One-Shot Start Flag ONSF 00h

0383h

Trigger Select Register TRGSR 00h

0384h

Up-Down Flag UDF 00h

0385h

0386h

Timer A0 Register TA0 XXh

0387h

0388h

Timer A1 Register TA1 XXh

0389h

038Ah

Timer A2 Register TA2 XXh

038Bh

038Ch

Timer A3 Register TA3 XXh

038Dh

038Eh

Timer A4 Register TA4 XXh

038Fh

0390h

Timer B0 Register TB0 XXh

0391h

0392h

Timer B1 Register TB1 XXh

0393h

0394h

Timer B2 Register TB2 XXh

0395h

0396h

Timer A0 Mode Register TA0MR 00h

0397h

Timer A1 Mode Register TA1MR 00h

0398h

Timer A2 Mode Register TA2MR 00h

0399h

Timer A3 Mode Register TA3MR 00h

039Ah

Timer A4 Mode Register TA4MR 00h

039Bh

Timer B0 Mode Register TB0MR 00XX0000b

039Ch

Timer B1 Mode Register TB1MR 00XX0000b

039Dh

Timer B2 Mode Register TB2MR 00XX0000b

039Eh

Timer B2 Special Mode Register TB2SC XXXXXX00b

039Fh

03A0h

UART0 Transmit/Receive Mode Register

03A1h

UART0 Bit Rate Generator U0BRG XXh

03A2h

UART0 Transmit Buffer Register U0TB XXh

03A3h

03A4h

UART0 Transmit/Receive Control Register 0

03A5h

UART0 Transmit/Receive Control Register 1

03A6h

UART0 Receive Buffer Register U0RB XXh

03A7h

03A8h

UART1 Transmit/Receive Mode Register

03A9h

UART1 Bit Rate Generator U1BRG XXh

03AAh

UART1 Transmit Buffer Register U1TB XXh

03ABh

UART1 Transmit/Receive Control Register 0

03ACh

03ADh

UART1 Transmit/Receive Control Register 1

03AEh

UART1 Receive Buffer Register U1RB XXh

03AFh

03B0h

UART Transmit/Receive Control Register 2

03B1h

03B2h

03B3h

03B4h

03B5h

03B6h

03B7h

03B8h

DMA0 Request Cause Select Register DM0SL 00h

03B9h

DMA1 Request Cause Select Register DM1SL 00h

03BAh

03BBh

03BCh

CRC Data Register CRCD XXh

03BDh

03BEh

CRC Input Register CRCIN XXh

03BFh

NOTES :

1.The blank areas are reserved and cannot be accessed by users.

2. Bits 7 to 5 in the Up-down flag are “

(1)

Register Symbol

0” by reset. However, The values in these bits when read are indeterminate.

After Reset

(2)

XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh

U0MR 00h

XXh
U0C0 00001000b
U0C1 00XX0010b

XXh
U1MR 00h

XXh

U1C0 00001000b
U1C1 00XX0010b

XXh
UCON X0000000b

XXh

X : Nothing is mapped to this bit

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

Table 4.6 SFR information (6)

Address

03C0h

A/D Register 0 AD0 XXh

03C1h
03C2h

A/D Register 1 AD1 XXh

03C3h
03C4h

A/D Register 2 AD2 XXh

03C5h
03C6h

A/D Register 3 AD3 XXh

03C7h
03C8h

A/D Register 4 AD4 XXh

03C9h
03CAh

A/D Register 5 AD5 XXh

03CBh
03CCh

A/D Register 6 AD6 XXh

03CDh
03CEh

A/D Register 7 AD7 XXh

03CFh
03D0h
03D1h
03D2h
03D3h
03D4h

A/D Control Register 2 ADCON2 00h

03D5h

A/D Control Register 0 ADCON0 00000XXXb

03D6h

A/D Control Register 1 ADCON1 00h

03D7h
03D8h

D/A Register 0 DA0 00h

03D9h
03DAh

D/A Register 1 DA1 00h

03DBh
03DCh

D/A Control Register DACON 00h

03DDh

Port P14 Control Register PC14 XX00XXXXb

03DEh

Pull-Up Control Register 3 PUR3 00h

03DFh
03E0h

Port P0 Register P0 XXh
Port P1 Register P1 XXh

03E1h
03E2h

Port P0 Direction Register PD0 00h

03E3h

Port P1 Direction Register PD1 00h
Port P2 Register P2 XXh

03E4h
03E5h

Port P3 Register P3 XXh
Port P2 Direction Register PD2 00h

03E6h
03E7h

Port P3 Direction Register PD3 00h
Port P4 Register P4 XXh

03E8h
03E9h

Port P5 Register P5 XXh

03EAh

Port P4 Direction Register PD4 00h
Port P5 Direction Register PD5 00h

03EBh
03ECh

Port P6 Register P6 XXh
Port P7 Register P7 XXh

03EDh

Port P6 Direction Register PD6 00h

03EEh
03EFh

Port P7 Direction Register PD7 00h
Port P8 Register P8 XXh

03F0h

Port P9 Register P9 XXh

03F1h

Port P8 Direction Register PD8 00X00000b

03F2h

Port P9 Direction Register PD9 00h

03F3h

Port P10 Register P10 XXh

03F4h

Port P11 Register P11 XXh

03F5h

Port P10 Direction Register PD10 00h

03F6h

Port P11 Direction Register PD11 00h

03F7h
03F8h

Port P12 Register P12 XXh

03F9h

Port P13 Register P13 XXh
Port P12 Direction Register PD12 00h

03FAh

Port P13 Direction Register PD13 00h

03FBh

Pull-Up Control Register 0 PUR0 00h

03FCh

Pull-Up Control Register 1 PUR1 00000000b

03FDh

Pull-Up Control Register 2 PUR2 00h

03FEh
03FFh

Port Control Register PCR 00h

(1)

Register

(3)
(3)

(3)

(3)
(3)

(3)
(3)
(3)

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. At hardware reset 1 or hardware reset 2, the register is as follows:

SS

• “00000000b” where “L” is inputted to the CNV

• “00000010b” where “H” is inputted to the CNV

pin

SS

pin

At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:

• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode)

• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or

“11b” (microprocessor mode)

3. These registers do not exist in M16C/62P (80-pin version), and M16C/62PT (80-pin version).

X : Nothing is mapped to this bit

Symbol After Reset

XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh

(2)

00000010b

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M16C/62P Group (M16C/62P, M16C/62PT)

5. Reset

Hardware reset 1, voltage down detection reset (hardware reset 2), software reset, watchdog timer reset
and oscillation stop detection reset are available to reset the microcomputer.

5. Reset

5.1 Hardware Reset 1

____________

The microcomputer resets pins, the CPU and SFR by setting the RESET pin. If the supply voltage meets
the recommended operating conditions, the microcomputer resets all pins when an “L” signal is applied to

___________ ____________

the RESET pin (see Table 5.1 Pin Status When RESET Pin Level is “L”). The oscillation circuit is also
reset and the main clock starts oscillation. The microcomputer resets the CPU and SFR when the signal

____________

applied to the RESET pin changes low (“L”) to high (“H”). The microcomputer executes the program in an
address indicated by the reset vector. The internal RAM is not reset. When an “L” signal is applied to the

____________

RESET pin while writing data to the internal RAM, the internal RAM is in an indeterminate state.
Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows a reset sequence. Table 5.1 lists pin

____________

states while the RESET pin is held low (“L”). Figure 5.3 shows CPU register states after reset. Refer to 4.

SFR for SFR states after reset.

5.1.1 Reset on a Stable Supply Voltage

(1) Apply “L” to the RESET pin
(2) Apply 20 or more clock cycles to the XIN pin
(3) Apply an “H” signal to the RESET pin

5.1.2 Power-on Reset

(1) Apply “L” to the RESET pin
(2) Raise the supply voltage to the recommended operating level
(3) Insert td(P-R) ms as wait time for the internal voltage to stabilize
(4) Apply 20 or more clock cycles to the XIN pin
(5) Apply “H” to the RESET pin

____________

____________

____________

____________

5.2 Voltage Down Detection Reset (Hardware Reset 2)

The microcomputer resets pins, the CPU or SFR by setting the built-in voltage detect circuit. The voltage
detect circuit monitors the voltage applied to the VCC1 pin.
When the VC26 bit in the VCR2 register is set to “1” (reset level detect circuit enabled), the microcomputer
resets pins, the CPU and SFR as soon as the voltage that is applied to the VCC1 pin drops to Vdet3 or
below.
Then, the microcomputer initializes pins, the CPU and SFR as soon as the voltage to the VCC1 pin reaches
Vdet3r or above. The microcomputer executes the program in an address determined by the reset vector.
The microcomputer executes the program td(S-R) ms after detecting Vdet3r. The same pins and registers
are reset by the hardware reset 1 and voltage down detection reset (hardware reset 2) , and are also placed
in the same reset state.
The microcomputer cannot exit stop mode by voltage down detection reset (hardware reset 2) .

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M16C/62P Group (M16C/62P, M16C/62PT)

VCC1

RESET

VCC1

5. Reset

Recommended
operation voltage

0V

RESET

0V

NOTES:

1. If VCC1>VCC2, the VCC2 voltage must be lower than that of VCC1 when the power
is being turned on or off.

0.2VCC1
or below

0.2VCC1 or below

Supply a clock with td(P-R) + 2
0 or more cycles to the XIN pin

Figure 5.1 Example Reset Circuit

5.3 Software Reset

The microcomputer resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to “1”
(microcomputer reset). Then the microcomputer executes the program in an address determined by the
reset vector.
Set the PM03 bit to “1” while the main clock is selected as the CPU clock and the main clock oscillation is
stable.
In the software reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for details.
Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not reset.
Figure 5.2 shows the reset sequence.

5.4 Watchdog Timer Reset

The microcomputer resets pins, the CPU and SFR when the CM06 bit in the CM0 register is set to “1”
(reset) and the watchdog timer underflows. Then the microcomputer executes the program in an address
determined by the reset vector.
In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for
details. Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not
reset.

5.5 Oscillation Stop Detection Reset

The microcomputer resets and stops pins, the CPU and SFR when the CM27 bit in the CM2 register is 0, if
it detects main clock oscillation circuit stop. Refer to 10.6 Oscillation Stop, Re-Oscillation Detection
Function for details.
In the oscillation stop detection reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR
for details. Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not
reset.

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M16C/62P Group (M16C/62P, M16C/62PT)

VCC1, VCC2

XIN

t

Microprocessor

mode BYTE = H

RESET

d(P-R)

More than
20 cycles
are needed

BCLK 28cycles

5. Reset

BCLK

Address

RD

WR

CS0

Microprocessor

mode BYTE = L

Address

RD

WR

CS0

Single chip

mode

Address

Figure 5.2 Reset Sequence

FFFFCh

FFFFCh FFFFEh

FFFFCh

FFFFDh

Content of reset vector

FFFFEh

Content of reset vector

FFFFEh

Content of reset vector

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M16C/62P Group (M16C/62P, M16C/62PT)

A

5. Reset

Table 5.1 Pin Status When RESET Pin Level is “L”

____________

Pin Name

P0
P1
P2, P3, P4_0 to P4_3

P4_4

P4_5 to P4_7
P5_0

P5_1
P5_2
P5_3

P5_4

P5_5

CNVSS = VSS

Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port

Input port

Input port

Data input
Data input
Address output (undefined)
CS0 output (“H” is output)
Input port (
WR output (“H” is output)
BHE output (undefined)
RD output (“H” is output)
BCLK output

HLDA output (The output value
depends on the input to the
HOLD pin)

HOLD input

Status

CNVSS = VCC1

BYTE = VSS BYTE = VCC

Pulled high

)

(1)

Data input
Input port
Address output (undefined)
CS0 output (“H” is output)
Input port (

Pulled high

WR output (“H” is output)
BHE output (undefined)
RD output (“H” is output)
BCLK output

HLDA output (The output value
depends on the input to the
HOLD pin)

HOLD input

)

P5_6
P5_7

P6, P7, P8_0 to P8_4,
P8_6, P8_7, P9, P10

P11, P12, P13,
P14_0, P14_1

(2)

Input port
Input port

Input port

Input port

ALE output (“L” is output)
RDY input

ALE output (“L” is output)
RDY input

Input port Input port

Input port

Input port

NOTES :

1. Shown here is the valid pin state when the internal power supply voltage has stabilized after power-on.
When CNVSS = VCC1, the pin state is indeterminate until the internal power supply voltage stabilizes.

2. P11, P12, P13, P14_0, P14_1 pins exist in 128-pin version.

b15

0000h

0000h
0000h
0000h
0000h
0000h
0000h

b19

00000h

Content of addresses FFFFEh to FFFFCh

b15

0000h
0000h

0000h

b0

Data Register(R0)
Data Register(R1)
Data Register(R2)

Data Register(R3)
Address Register(A0)

Address Register(A1)
Frame Base Register(FB)

b0

Interrupt Table Register(INTB)
Program Counter(PC)

b0

User Stack Pointer(USP)
Interrupt Stack Pointer(ISP)
Static Base Register(SB)

b15

b15

IPL

0000h

b7 b8

Figure 5.3 CPU Register Status After Reset

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b0

Flag Register(FLG)

b0

CDZSBOIU

M16C/62P Group (M16C/62P, M16C/62PT)

6. Voltage Detection Circuit

6. Voltage Detection Circuit

Note

6. Voltage Detection Circuit is described in the M16C/62P only as an example.

The M16C/62PT do not use this function.

The voltage detection circuit monitors the voltage applied to the VCC1 pin in Vdet3 and Vdet 4. The VC26
to VC27 bits in the VCR2 register determine whether this circuit is enabled or disabled.
The reset level detect circuit is required for the voltage down detection reset (hardware reset 2) .
The voltage down detection circuit detects whether VCC1 is more than or less than Vdet4. The VC13 bit in
the VCR1 register determines the detection result. The voltage detect interrupt is available.
Figure 6.1 shows a voltage detection circuit Block

R E S E T

V C C 1

CM10 Bit=1
(Stop Mode)

V C R 2 R e g i s t e r
b7 b6

Figure 6.1 Voltage Detection Circuit Block

Write to WDC register

Internal power on reset

+

≥Vdet3

E

+
≥Vdet4

E

Noise Rejection

WDC5 Bit

SRQ

1 shot

>T

V C R 1 R e g i s t e r

WARM/COLD

(Cold start, warm start)

Voltage Down Detect Reset
(Hardware Reset 2

Release Wait Time)

t d ( S - R )

Q

I n t e r n a l R e s e t S i g n a l
( “ L ” a c t i v e )

V o l t a g e D o w n
D e t e c t S i g n a l

b 3

VC13 Bit

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M16C/62P Group (M16C/62P, M16C/62PT)

6. Voltage Detection Circuit

V o l t a g e D o w n D e t e c t i o n I n t e r r u p t R e g i s t e r

d d r e s

f t e r R e s e

0 1 F

b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0

N O T E S :

1 . W r i t e t o t h i s r e g i s t e r a f t e r s e t t i n g t h e P R C 3 b i t i n t h e P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) .
2 . U s e f u l w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o “ 1 ” ( v o l t a g e d o w n d e t e c t i o n c i r c u i t e n a b l e d ) . I f t h e

V C 2 7 b i t i s s e t t o “ 0 ” ( v o l t a g e d o w n d e t e c t i o n c i r c u i t d i s a b l e ) , t h e D 4 2 b i t i s s e t t o “ 0 ” ( N o t d e t e c t ) .
3 . T h i s b i t i s s e t t o “ 0 ” b y w r i t i n g a “ 0 ” i n a p r o g r a m . ( W r i t i n g a “ 1 ” h a s n o e f f e c t . )
4 . I f t h e v o l t a g e d o w n d e t e c t i o n i n t e r r u p t n e e d s t o b e u s e d t o g e t o u t o f s t o p m o d e a g a i n a f t e r o n c e u s e d f o r t h a t

p u r p o s e , r e s e t t h e D 4 1 b i t b y w r i t i n g a “ 0 ” a n d t h e n a “ 1 ” .
5 . T h e D 4 0 b i t i s e f f e c t i v e w h e n t h e V C 2 7 b i t = 1 . T o s e t t h e D 4 0 b i t t o “ 1 , ” s e t b i t s i n t h e f o l l o w i n g o r d e r .

( a ) S e t t h e V C 2 7 b i t t o “ 1 ” .
( b ) W a i t f o r t d ( E – A ) u n t i l t h e d e t e c t i o n c i r c u i t i s a c t u a t e d .
( c7222 -10.7778f9.3889 10.7778 TD( 0.7778 (c72223s)Tj-24.8889 10.7778 TD( )Tj25.3889 -10. TD( )Tj13.666778 TD( .8889 10D( )Tj.)Tj-24.7222 -1.11 -10.7778 TD(i)Tj8 TD( )Tj28.944.7778 TD( )Tj20.8 TD( 5889 -109r )Tj13.58 TD( 5889 -109r )-10.77j13.58 b8 TD( )Tj277737lD( )Tj 10.7778 .277737l 10.77.20.8 TD( )Tj277737lD( )Tj 10.77737lD(7l 10.77.20.8 TD( )0.77j13.58 b8 7lD(7l)Tj 10.77737lD(7ld 7lD(7l)Tj 10.77737lD.7778 TD( )Tj20.8 TD( 7l)Tj 1)Tj-25.3889 10.77778 TD22 -10.7778 TD( )T.3889 10 10.77926.7222 -10.7778 TD(t TD( )Tj28.3889 4667 -9.6667 TD(o)Tj )Tj5.1-10.772TD( )Tj( )Tj3)Tj.)Tj-24.7222 -1.1101

0
S y m b o lA

D 4 I N T0

B i t S y m b o l

Voltage Down Detection

D 4 0

Interrupt Enable Bit
STOP Mode Deactivation

D 4 1

Control Bit

Voltage Change Detection

D 4 2

Flag
WDT Overflow Detect Flag

D 4 3

Sampling Clock Select Bit

D F 0

D F 1

( 1 )

sA

h0

B i t N a m e

(5)

0 : D i s a b l e ( d o n o t u s e t h e p o w e r

(4)

(2)

s u p p l y d o w n d e t e c t i o n
i n t e r r u p t t o g e t o u t o f s t o p m o d e )
1 : E n a b l e ( u s e t h e v o l t a g e
d o w n d e t e c t i o n i n t e r r u p t t o g e t
o u t o f s t o p m o d e )

t

h

0 : D i s a b l e
1 : E n a b l e

0 : N o t d e t e c t e d
1 : V d e t 4 p a s s i n g d e t e c t i o n

0 : N o t d e t e c t e d
1 : D e t e c t e d

0 0 : C P U c l o c k d i v i d e d b y 8
0 1 : C P U c l o c k d i v i d e d b y 1 6
1 0 : C P U c l o c k d i v i d e d b y 3 2
1 1 : C P U c l o c k d i v i d e d b y 6 4

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M16C/62P Group (M16C/62P, M16C/62PT)

6. Voltage Detection Circuit

VCC1

RESET

Internal Reset Signal

VC13 bit in
VCR1 register

VC26 bit in
VCR2 register

VC27 bit in
VCR2 register

(1)

NOTES :

1. VC26 bit is invalid (the microcomputer is not reset even if input voltage of VCC1 pin
becomes lower than Vdet3).

Vdet4

Vdet3r

Vdet3

Vdet3s

VSS

Indefinite

Indefinite

Indefinite

5.0V

5.0V

Set to “1” by program (reset level detect circuit enable)

Set to “1” by program
(voltage down detect circuit enable)

Figure 6.3 Typical Operation of Voltage Down Detection Reset (Hardware Reset 2)

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M16C/62P Group (M16C/62P, M16C/62PT)

6. Voltage Detection Circuit

6.1 Voltage Down Detection Interrupt

If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage down
detection interrupt request is generated when the voltage applied to the VCC1 pin is above or below Vdet4.
The voltage down detection interrupt shares the same interrupt vector with the watchdog timer interrupt and
oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to “1” (enabled) to use the voltage down detection interrupt to exit stop
mode.
The D42 bit in the D4INT register is set to “1” as soon as the voltage applied to the VCC1 pin reaches Vdet4
due to the voltage rise and voltage drop. When the D42 bit changes “0” to “1”, the voltage down detection
interrupt request is generated. Set the D42 bit to “0” by program. However, when the D41 bit is set to “1”
and the microcomputer is in stop mode, the voltage down detection interrupt request is generated regard­less of the D42 bit state if the voltage applied to the VCC1 pin is detected to be above Vdet4. The micro­computer then exits stop mode.
Table 6.1 shows how the voltage down detection interrupt request is generated.
The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage applied to
the VCC1 pin reaches Vdet4. Table 6.2 shows the sampling periods.

Table 6.1 Voltage Down Detection Interrupt Request Generation Conditions

D41 BitVC27 BitOperation Mode D40 Bit D42 Bit CM02 Bit VC13 Bit

Normal

Operation

(1)

Mode

Wait Mode

Stop Mode

NOTES:

1. The status except the wait mode and stop mode is handled as the normal mode.(Refer to 10. Clock generating circuit)

2. Refer to 6.2 Limitations on stop mode, 6.3 Limitations on wait mode.

3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.

(2)

(2)

See the Figure 6.5 Voltage Down Detection Interrupt Generation Circuit Operation Example for details.

1

1

1

0 to 1

0 to 1

0

1
0

(3)

0 to 1

(3)

1 to 0

(3)

0 to 1

(3)

1 to 0

0 to 1
0 to 1

– : “0”or “1”

Table 6.2 Sampling Periods

CPU
Clock
(MHz)

DF1 to DF0=00

(CPU clock divided by 8)

(CPU clock divided by 16)

Sampling Period (µs)

DF1 to DF0=01

DF1 to DF0=10

(CPU clock divided by 32)

DF1 to DF0=11

(CPU clock divided by 64)

16 3.0 6.0 12.0 24.0

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Voltage down detection interrupt generation circuit

Voltage Down Detection Circuit

D4INT clock(the

VC27

VCC1

+

Noise

VREF

Watchdog Timer Block

Rejection

­(Rejection Range:200 ns)

WAIT instruction(wait mode)

clock with which it
operates also in
wait mode)

VC13

Voltage down
detection signal

The Voltage down detection
signal becomes “H” when the
VC27 bit is set to “0” (disabled)

Watchdog timer
underflow signal

CM10

CM02

DF1, DF0

00b
01b
10b
11b

1/2

Noise Rejection
Circuit

1/2

1/21/8

D41

D43

This bit is set to “0”(not detected) by program.

The D42 bit is set to “0” (not detected)
by program. the VC27 bit is set to “0”
(voltage down detect circuit disabled),
the D42 bit is set to “0”.

D42

Digital
Filter

D40

6. Voltage Detection Circuit

Watchdog
timer interrupt
signal

Voltage down
detection

interrupt signal

Oscillation stop,
re-oscillation
detection
interrupt signal

Non-maskable
interrupt signal

Figure 6.4 Power Supply Down Detection Interrupt Generation Block

VCC1

VC13 bit in VCR1 register

Output of the digital filter

D42 bit in D4INT register

Voltage down detection
interrupt signal

sampling

(2)

sampling sampling sampling

No voltage down detection interrupt signals are
generated when the D42 bit is “H”.

Set to “0” by program (not detected)

NOTES :

1. D40 bit in the D4INT register is set to “1” (voltage down

detection interrupt enabled).

2. Output of the digital filter is shown in Figure 6.5.

Figure 6.5 Power Supply Down Detection Interrupt Generation Circuit Operation Example

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6. Voltage Detection Circuit

6.2 Limitations on Exiting Stop Mode

The voltage down detection interrupt is immediately generated and the microcomputer exits stop mode if
the CM10 bit in the CM1 register is set to “1” under the conditions below.

• the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled),

• the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled),

•

the D41 bit in the D4INT register is set to “1” (voltage down detection interrupt is used to exit stop mode), and

• the voltage applied to the VCC1 pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)

If the microcomputer is set to enter stop mode when the voltage applied to the VCC1 pin drops below Vdet4
and to exit stop mode when the voltage applied rises to Vdet4 or above, set the CM10 bit to “1” when VC13
bit is “0” (VCC1 < Vdet4).

6.3 Limitations on Exiting Wait Mode

The voltage down detection interrupt is immediately generated and the microcomputer exits wait mode If
WAIT instruction is executed under the conditions below.

• the CM02 bit in the CM0 register is set to “1” (stop peripheral function clock),

• the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled),

• the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled),

•

the D41 bit in the D4INT register is set to “1” (voltage down detection interrupt is used to exit wait mode), and

• the voltage applied to the VCC1 pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)

If the microcomputer is set to enter wait mode when the voltage applied to the VCC1 pin drops below Vdet4
and to exit wait mode when the voltage applied rises to Vdet4 or above, perform WAIT instruction when
VC13 bit is “0” (VCC1 < Vdet4).

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7. Processor Mode

7. Processor Mode

Note

7. Processor Mode is described in the M16C/62P (128-pin version and 100-pin version)

only as an example.
The M16C/62P (80-pin version) and M16C/62PT do not use memory expansion mode,
and microprocessor mode.

7.1 Types of Processor Mode

Three processor modes are available to choose from: single-chip mode, memory expansion mode, and
microprocessor mode. Table 7.1 shows the features of these processor modes.

Table 7.1 Features of Processor Modes

Processor Modes

Single-Chip Mode SFR, Internal RAM, Internal ROM

Memory Expansion Mode

Microprocessor Mode

NOTES :

1. Refer to 8. Bus.

SFR, Internal RAM, Internal ROM,
External Area
SFR, Internal RAM, External Area

Access Space Pins which are Assigned I/O Ports

(1)

All pins are I/O ports or peripheral
function I/O pins

Some pins serve as bus control pins

(1)

Some pins serve as bus control pins

(1)

(1)

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7. Processor Mode

7.2 Setting Processor Modes

Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Table 7.2 shows the processor mode after hardware reset. Table 7.3 shows the PM01 to PM00 bit set
values and processor modes.

Table 7.2 Processor Mode After Hardware Reset

CNVSS Pin Input Level Processor Mode

VSS Single-Chip Mode

(1, 2)

VCC1

NOTES :

1. If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1
or hardware reset 2), the internal ROM cannot be accessed regardless of PM10 to PM00 bits.

2. The multiplexed bus cannot be assigned to the entire CS space.

Table 7.3 PM01 to PM00 Bits Set Values and Processor Modes

Microprocessor Mode

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7. Processor Mode

Processor Mode Register 0

b7 b6 b5 b4 b3 b2 b1 b0

(1)

Symbol Address After Reset

(4)

PM0 0004h 00000000b (CNVSS pin = L)

00000011b (CNVSS pin = H)

Bit Name FunctionBit symbol

PM00

Processor Mode Bit

(4)

PM01

PM02

PM03

PM04

R/W Mode Select Bit

Software Reset Bit

Multiplexed Bus Space
Select Bit

(2)

PM05

PM06

PM07

Port P4_0 to P4_3
Function Select Bit

BCLK Output
Disable Bit

(2)

(2)

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).

2. Effective when the PM01 to PM00 bits are set to “01b” (memory expansion mode) or “11b” (microprocessor
mode).

3. To set the PM01 to PM00 bits are “01b” and the PM05 to PM04 bits are “11b” (multiplexed bus assigned to
the entire CS space), apply an “H” signal to the BYTE pin (external data bus is 8 bits wide). While the CNVSS
pin is held “H” (= VCC1), do not rewrite the PM05 to PM04 bits to “11b” after reset.
If the PM05 to PM04 bits are set to “11b” during memory expansion mode, P3_1 to P3_7 and P4_0 to P4_3
become I/O ports, in which case the accessible area for each CS is 256 bytes.

4. The PM01 to PM00 bits do not change at software reset, watchdog timer reset and oscillation stop detection
reset.

b1 b0

0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Do not set
1 1: Microprocessor mode

(2)

0 : RD,BHE,WR
1 : RD,WRH,WRL

Setting this bit to “1” resets the
microcomputer. When read, its content
is “0”.

b5 b4

0 0 : Multiplexed bus is unused
(Separate bus in the entire CS
space)
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to the entire CS space

0 : Address output
1 : Port function
(Address is not output)

0 : BCLK is output
1 : BCLK is not output
(Pin is left high-impedance)

RW
RW

RW

RW

RW

RW

RW

(3)

RW

RW

Figure 7.1 PM0 Register

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7. Processor Mode

Processor Mode Register 1

b7 b6 b5 b4 b3 b2 b1 b0

0

(1)

Symbol Address After Reset
PM1 0005h 0X001000b

Bit Name FunctionBit Symbol

PM10

PM11

PM12

PM13

PM14

PM15

(b6)

PM17

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).

2. Set the PM10 bit to “0” for Mask ROM version. For flash memory version, the PM10 bit controls whether
Block A is enabled or disabled. When the PM10 bit is set to “1”, 0F000h to 0FFFFh can be used as internal
ROM area. In addition, the PM10 bit is automatically set to “1” while the FMR01 bit in the FMR0 register is set
to “1” (CPU rewrite mode).

3. Effective when the PM01 to PM00 bits are set to “01b” (memory expansion mode) or “11b” (microprocessor
mode).

4. PM12 bit is set to “1” by writing a “1” in a program (writing a “0” has no effect).

5. When PM17 bit is set to “1” (with wait state), one wait state is inserted when accessing the internal RAM, or
internal ROM.
When PM17 bit is set to “1” and accesses an external area, set the CSiW bit in the CSR register (i=0 to 3) to “0”
(with wait state).

6. The PM13 bit is automatically set to “1” when the FMR01 bit in the FMR0 register is “1” (CPU rewrite mode).

7. The access area is changed by the PM13 bit as listed in the table below.

Access Area

Internal

External

RAM

Up to Addresses 00400h to 03FFFh (15 Kbytes)

ROM

Up to Addresses D0000h to FFFFFh (192 Kbytes)
Addresses 04000h to 07FFFh are usable

Addresses 80000h to CFFFFh are usable

PM13=0 PM13=1

CS2 Area Switch Bit
(Data Block Enable Bit)

Port P3_7 to P3_4
Function Select Bit

Watchdog Timer Function
Select Bit

Internal Reserved Area
Expansion Bit

Memory Area
Expansion Bit

Reserved Bit

(5)

Wait Bit

(6)

(3)

(3)

0: 08000h to 26FFFh

(2)

(Block A disable)
1: 10000h to 26FFFh
(Block A enable)

0 : Address output
1 : Port function

0 : Watchdog timer interrupt
1 : Watchdog timer reset

(NOTE 7)

b5 b4

0 0 : 1-Mbyte mode

(Do not expand)
0 1 : Do not be set
1 0 : Do not be set
1 1 : 4-Mbyte mode

Set to “0”.

0 : No wait state
1 : With wait state (1 wait)

The entire area is usable

The entire area is usable

Addresses 04000h to 07FFFh are reserved

Addresses 80000h to CFFFFh are reserved

(4)

RW
RW

RW

RW
RW

RW

RW

RW
RW

Figure 7.2 PM1 Register

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7. Processor Mode

Single-Chip Mode

00000h

00400h

Internal RAM

XXXXXh

Can not use

YYYYYh

Internal ROM

FFFFFh

SFR

PM13=0

Capacity

4 Kbytes
5 Kbytes

10 Kbytes
12 Kbytes

16 Kbytes
20 Kbytes

24 Kbytes
31 Kbytes

PM13=1

Capacity

4 Kbytes
5 Kbytes

10 Kbytes
12 Kbytes

16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes

Internal RAM Internal ROM

Address XXXXXh

013FFh
017FFh
02BFFh
033FFh

03FFFh

03FFFh

03FFFh
03FFFh

Internal RAM

Address XXXXXh

013FFh
017FFh

02BFFh
033FFh
043FFh
053FFh
063FFh
07FFFh

(2)
(2)

(2)

(2)

Capacity
48 Kbytes
64 Kbytes

96 Kbytes
128 Kbytes
192 Kbytes
256 Kbytes

320 Kbytes
384 Kbytes
512 Kbytes

Internal ROM

Capacity
48 Kbytes
64 Kbytes

96 Kbytes

128 Kbytes
192 Kbytes

256 Kbytes
320 Kbytes

384 Kbytes
512 Kbytes

Address YYYYYh
F4000h
F0000h

E8000h
E0000h
D0000h

D0000h

D0000h
D0000h
D0000h

Address YYYYYh

F4000h
F0000h
E8000h
E0000h
D0000h

C0000h
B0000h

A0000h
80000h

(2)
(2)

(2)
(2)

NOTES :

1. For the mask ROM version, set the PM10 bit to “0” (08000h to 26FFFh for CS2 area).

2. If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.

Figure 7.3 Memory Map in Single Chip Mode

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8. Bus

Note

8. Bus is described in the M16C/62P (128-pin version and 100-pin version)

only as an example.
The M16C/62P (80-pin version) and M16C/62PT do not use memory expansion mode,
and microprocessor mode.

8. Bus

During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform
data input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0

_______ _____ ________ ______ ________ ________ ________ __________ _________

to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.

8.1 Bus Mode

The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits in the PM0
register. Table 8.1 shows the difference between a separate bus and multiplexed bus.

8.1.1 Separate Bus

In this bus mode, data and address are separate.

8.1.2 Multiplexed Bus

In this bus mode, data and address are multiplexed.

8.1.2.1 When the input level on BYTE pin is high (8-bit data bus)

D0 to D7 and A0 to A7 are multiplexed.

8.1.2.2 When the input level on BYTE pin is low (16-bit data bus)

D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15. External
devices connecting to a multiplexed bus are allocated to only the even addresses of the microcom­puter. Odd addresses cannot be accessed.

_______

Table 8.1 Difference between a separate bus and multiplexed bus

Pin Name

P0_0 to P0_7/D0 to D7

P1_0 to P1_7/D8 to D15

P2_0/A0 (/D0/-)

P2_1 to P2_7/A1 to A7
(/D1 to D7/D0 to D6)

P3_0/A8 (/-/D7)

NOTES :

1. See Table 8.6 Pin Functions for Each Processor Mode for bus control signals other than the above.

2. It changes with a setup of PM05 to PM04, and area to access.
See Table 8.6 Pin Functions for Each Processor Mode for details.

(1)

Separate Bus

D0 to D7

D8 to D15

A0

A1 to A7

A8

BYTE = H

(NOTE 2) (NOTE 2)

I/O Port

P1_0 to P1_7

A0 D0

A1 to A7

A8

Multiplex Bus

D1 to D7

BYTE = L

(NOTE 2)

A0

A1 to A7 D0 to D6

A8 D7

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8.2 Bus Control

The following describes the signals needed for accessing external devices and the functionality of software wait.

8.2.1 Address Bus

The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20
bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 8.2 shows the
PM06 and PM11 bit set values and address bus widths.

Table 8.2 PM06 and PM11 Bits Set Value and Address Bus Width

Set Value
PM11=1 P3_4 to P3_7
PM06=1 P4_0 to P4_3

PM11=0 A12 to A15
PM06=1 P4_0 to P4_3
PM11=0 A12 to A15
PM06=0 A16 to A19

NOTES :

1. No values other than those shown above can be set.

When processor mode is changed from single-chip mode to memory extension mode, the address bus is
indeterminate until any external area is accessed.

(1)

Pin Function

Address Bus Width

12 bits

16 bits

20 bits

8. Bus

8.2.2 Data Bus

When input on the BYTE pin is high(data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus; when
input on the BYTE pin is low(data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.

8.2.3 Chip Select Signal

The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins. These
pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 8.1 shows the CSR register.
During 1-Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
from the CSi pin. During 4-Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to 9.
Memory space expansion function. Figure 8.2 shows the example of address bus and CSi signal
output in 1-Mbyte mode.

______ ______ ______

Chip Select Control Register

b7 b6 b5 b4 b3 b2 b1 b0

NOTES :

1. Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set the
CSiW bit to “0” (with wait state).

2. If the PM17 bit in the PM1 register is set to “1” (with wait state), set the CSiW bit to “0” (with wait state).

3. When the CSiW bit = 0 (with wait state), the number of wait states (interms of clock cycles) can be selected
using the CSEi1W to CSEi0W bits in the CSE register.

Symbol Address After Reset
CSR 0008h 00000001b

Bit Symbol

CS0
CS1
CS2

CS3
CS0W
CS1W
CS2W
CS3W

______ ______

_____

Bit Name

CS0 Output Enable Bit
CS1 Output Enable Bit
CS2 Output Enable Bit
CS3 Output Enable Bit

CS0 Wait Bit
CS1 Wait Bit
CS2 Wait Bit
CS3 Wait Bit

0 : Chip select output disabled
1 : Chip select output enabled

0 : With wait state
1 : Without wait state

Function

(functions as I/O port)

(1, 2, 3)

______

______

RW
RW

RW
RW
RW
RW
RW

RW
RW

Figure 8.1 CSR Register

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8. Bus

Example 1

To access the external area indicated by CSj in the next cycle after
accessing the external area indicated by CSi

The address bus and the chip select signal both change state between
these two cycles.

Access to the external

area indicated by CSi

BCLK

Read signal

Data bus

Address bus

CSi

CSj

Example 3

To access the external area indicated by CSi in the next cycle after
accessing the external area indicated by the same CSi

Address

Access to the external
area indicated by CSj

Data

Data

Address

Example 2

To access the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi

The chip select signal changes state but the address bus does not
change state

Access to the external

area indicated by CSi

BCLK

Read signal

Data bus

Address bus

CSi

Example 4

Not to access any area (nor instruction prefetch generated) in the next cycle after
accessing the external area indicated by CSi

Address

Access to the internal
ROM or internal RAM

Data

The address bus changes state but the chip select signal does not
change state

Access to the external

area indicated by CSi

BCLK

Read signal

Data bus

Address bus

CSi

NOTES :

1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
may be extended more than two cycles depending on a combination of these examples.

Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3
(not including i, however)

Address

Access to the same
external area

Data Data

Address

______

Neither the address bus nor the chip select signal changes state between
these two cycles

Access to the external

area indicated by CSi

BCLK

Read signal

Data bus

Address bus

CSi

Data

Address

Figure 8.2 Example of Address Bus and CSi Signal Output in 1-Mbyte mode

No access

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8. Bus

8.2.4 Read and Write Signals

When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD,

________ ______ _____ ________ ________

BHE and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When
the data bus is 8 bits wide, use a combination of RD, WR and BHE.
Table 8.3 shows the operation of RD, WRL, and WRH signals. Table 8.4 shows the operation of opera-

_____ ______ ________

_____ ________ _________

tion of RD, WR, and BHE signals.

Table 8.3 Operation of RD, WRL and WRH Signals

_____ ________ _________

Data Bus Width

16-bit

( BYTE pin

input = L)

L
H
H
H

_____ ______ ________

H

L

H

L

Table 8.4 Operation of RD, WR and BHE Signals

Data Bus Width A0

16-bit

(BYTE pin

input = L)

8-bit (BYTE pin

input = H)

RD

HLL
LHL
HLH
LHH
HLLL
LHLL
HL H or L
LH H or L

BHEWR

Not used
Not used

_____ ______ ________

WRHWRLRD

H
H

L
L

Read data
Write 1 byte of data to an even address

Write 1 byte of data to an odd address

Write data to both even and odd addresses

H
H

L
L

Status of External Data Bus

Status of External Data Bus
Write 1 byte of data to an odd address
Read 1 byte of data from an odd address
Write 1 byte of data to an even address
Read 1 byte of data from an even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data

_____

8.2.5 ALE Signal

The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.

When BYTE Pin Input = H When BYTE Pin Input = L

ALE

A0/D0 to A7/D7

A8 to A19

NOTES :

1. If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.

Address Data

Address

(1)

Figure 8.3 ALE Signal, Address Bus, Data Bus

A1/D0 to A8/D7

ALE

A0

A9 to A19

Address

Address Data

Address

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________

8.2.6 The RDY Signal

This signal is provided for accessing external devices which need to be accessed at low speed. If input

________

on the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted
in the bus cycle. While in a wait state, the following signals retain the state in which they were when the

________

RDY signal was acknowledged.

8. Bus

A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA

______ ______ ______ ________ ________ ______ ________ __________

Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle

________

is executed. Figure 8.4 shows example in which the wait state was inserted into the read cycle by the

________ ________

RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register

________ ________

to “0” (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.

In an instance of separate bus

BCLK

RD

CSi

(i=0 to 3)

RDY

tsu(RDY - BCLK)

Accept timing of RDY signal

In an instance of multiplexed bus

BCLK

RD

CSi

(i=0 to 3)

RDY

tsu(RDY - BCLK)

: Wait using RDY signal
: Wait using software

Shown above is the case where CSEi1W to CSEi0W (i = 0 to 3) bits in the CSE register are “00b” (one wait state).

Accept timing of RDY signal

________

Figure 8.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal

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__________

8.2.7 HOLD Signal

This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the
input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in
process finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during
which time the HLDA pin outputs a low-level signal.
Table 8.5 shows the microcomputer status in the hold state.
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However,
if the CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two
separate accesses.

__________

__________

__________

__________

__________

HOLD > DMAC > CPU

Figure 8.5 Bus-Using Priorities
Table 8.5 Microcomputer Status in Hold State

8. Bus

Item

BCLK
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,

_________ _______ _______

_______ _______ _____ ________

Output
High-impedance

Status

WRH, WR, BHE
I/O ports P0, P1, P3, P4

(1)

__________

P6 to P14

HLDA
Internal Peripheral Circuits
ALE Signal

(2)

High-impedance

__________

Maintains status when HOLD signal is received
Output “L”

ON (but watchdog timer stops)
Undefined

NOTES:

1. P11 to P14 are included in the 128-pin version.

2. When I/O port function is selected.

3. The watchdog timer dose not stop when the PM22 bit in the PM2 register is set to “1” (the count
source for the watchdog timer is the on-chip oscillator clock).

8.2.8 BCLK Output

If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that of
the CPU clock is output as BCLK from the BCLK pin. Refer to 10.2 CPU clock and pheripheral clock.

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Table 8.6 Pin Functions for Each Processor Mode

Processor Mode Memory Expansion Mode or Microprocessor Mode

00b(separate bus)

PM05 to PM04 Bits

01b(CS2 is for multiplexed bus and
others are for separate bus)
10b(CS1 is for multiplexed bus and
others are for separate bus)

8. Bus

Memory Expansion
Mode

11b (multiplexed
bus for the entire

(1)

space)

Data Bus Width

BYTE Pin

8 bits

“H”

P0_0 to P0_7 D0 to D7 D0 to D7
P1_0 to P1_7 I/O ports D8 to D15 I/O ports
P2_0 A0 A0
P2_1 to P2_7 A1 to A7 A1 to A7

P3_0 A8 A8 A8

16 bits

“L”

8 bits

“H”

D0 to D7

(2)

A0/D0

A1 to A7
/D1 to D7

(4)

(2)

16 bits

“L”

D0 to D7
D8 to D15

(4)

(4)

I/O ports

I/O ports
A0 A0/D0
A1 to A7

/D0 to D6

(2)

A8/D7

(2)

A1 to A7/D1 to D7

A8

8 bits

“H”

P3_1 to P3_3 A9 to A11 I/O ports
P3_4 to

P3_7
P4_0 to

P4_3
P4_4

PM11=0
PM11=1

PM06=0
PM06=1

CS0=0
CS0=1

P4_5

CS1=0
CS1=1

P4_6

CS2=0
CS2=1

P4_7

CS3=0
CS3=1

P5_0

PM02=0
PM02=1

P5_1 BHE

PM02=0

PM02=1 WRH
P5_2
P5_3
P5_4
P5_5

A12 to A15

I/O ports
A16 to A19

I/O ports
I/O ports

CS0
I/O ports
CS1
I/O ports

CS2
I/O ports
CS3

WR

RD
BCLK

HLDA
HOLD

(3)

(3)

WRL

WRH

(3)

(3)

WRL

I/O ports

I/O ports

(3)

(3)

P5_6 ALE
P5_7

RDY

I/O ports: Function as I/O ports or peripheral function I/O pins.

NOTES :

1. To set the PM01 to PM00 bits are set to “01b” and the PM05 to PM04 bits are set to “11b” (multiplexed bus assigned to the entire CS
space), apply “H” to the BYTE pin (external data bus 8 bits wide). While the CNVSS pin is held “H” (= VCC1), do not rewrite the PM05 to
PM04 bits to “11b” after reset. If the PM05 to PM04 bits are set to “11b” during memory expansion mode, P3_1 to P3_7 and P4_0 to
P4_3 become I/O ports, in which case the accessible area for each CS is 256 bytes.

2. In separate bus mode, these pins serve as the address bus.

3. If the data bus is 8 bits wide, make sure the PM02 bit is set to “0” (RD, BHE, WR).

4. When accessing the area that uses a multiplexed bus, these pins output an indeterminate value during a write.

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8.2.9 External Bus Status When Internal Area Accessed

Table 8.7 shows the external bus status when the internal area is accessed.

Table 8.7 External Bus Status When Internal Area Accessed

Item SFR Accessed Internal ROM, RAM Accessed
A0 to A19 Address output Maintain status before accessed

address of external area or SFR

D0 to D15 When Read High-impedance High-impedance

When Write Output data Undefined
RD, WR, WRL, WRH RD, WR, WRL, WRH output Output “H”
BHE BHE output Maintain status before accessed

status of external area or SFR
CS0 to CS3 Output “H” Output “H”
ALE Output “L” Output “L”

8.2.10 Software Wait

Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See
Table 8.8 Bit and Bus Cycle Related to Software Wait for details.
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0” (with wait state). Figure 8.6
shows the CSE register. Table 8.8 shows the software wait related bits and bus cycles. Figure 8.7 and

8.8 show the typical bus timings using software wait.

________

8. Bus

Chip Select Expansion Control Register

b7 b6 b5 b4 b3 b2 b1 b0

NOTES :

1. Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (with wait state) before writing to the CSEi1W to
CSEi0W bits. If the CSiW bit needs to be set to “1” (without wait state), set the CSEi1W to CSEi0W bits to
“00b” before setting it.

Symbol Address After Reset
CSE 001Bh 00h

Bit Symbol

CSE00W

CSE01W

CSE10W

CSE11W

CSE20W

CSE21W

CSE30W

CSE31W

Bit Name

CS0 Wait Expansion Bit

CS1 Wait Expansion Bit

CS2 Wait Expansion Bit

CS3 Wait Expansion Bit

b1 b0

(1)

0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Do not set

b3 b2

(1)

0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Do not set

b5 b4

(1)

0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Do not set

b7 b6

(1)

0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Do not set

Function

RW

RW

RW

RW

RW

RW

RW

RW

RW

Figure 8.6 CSE Register

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M16C/62P Group (M16C/62P, M16C/62PT)

Table 8.8 Bit and Bus Cycle Related to Software Wait

CSR Register

0
1

PM1 Register

(5)

PM17 Bit

0
1

0

1

1

(2)

PM2 Register

PM20 Bit

Area

SFR

Internal

RAM, ROM

External

Area

NOTES :

1. To use the RDY signal, set this bit to “0”.

2. To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait state).

3. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by the PM20 bit in the PM2 register. When using a
16 MHz or higher PLL clock, be sure to set the PM20 bit to “0” (2 wait cycles).

4. After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0” (with wait state), and the CSE register is set to
“00h” (one wait state for CS0 to CS3). Therefore, the internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.

5. When PM17 bit is set to “1” and accesses an external area, set the CSiW (i=0 to 3) bits to “0” (with wait state).

Bus Mode

Separate Bus

Multiplexed

Bus

CS3W Bit
CS2W Bit
CS1W Bit
CS0W Bit

1

0
0
0
0
0
0
0
0

(1)
(1)
(1)
(1)

CSE Register
CSE31W to CSE30W Bit
CSE21W to CSE20W Bit
CSE11W to CSE10W Bit
CSE01W to CSE00W Bit

00b

00b
01b
10b
00b
00b
01b
10b
00b

Software Wait

No wait

1 wait

No wait

1 wait
2 waits
3 waits

1 wait

1 wait
2 waits
3 waits

1 wait

2 BCLK cycle
3 BCLK cycle

1 BCLK cycle
2 BCLK cycles

1 BCLK cycle (read)

2 BCLK cycles (write)
2 BCLK cycles

3 BCLK cycles
4 BCLK cycles

2 BCLK cycles

3 BCLK cycles
3 BCLK cycles
4 BCLK cycles
3 BCLK cycles

8. Bus

Bus Cycle

(3)
(3)

(4)

(4)

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8. Bus

Figure 8.7 Typical Bus Timings Using Software Wait (1)

-

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M16C/62P Group (M16C/62P, M16C/62PT)

(1) Separate Bus, 3-Wait Setting

BCLK

Write signal

Read signal

Bus cycle

(1)

Bus cycle

8. Bus

(1)

Data bus

Address bus

CS

(2) Multiplexed Bus, 1- or 2-Wait Setting

BCLK

Write signal

Read signal

ALE

Address bus
Address bus/

Data bus

CS

(3) Multiplexed Bus, 3-Wait Setting

Address

Bus cycle

Address

Bus cycle

Output

Address

(1)

Data output

(1)

Address

Bus cycle

Address

(1)

Bus cycle

Input

Address

Input

(1)

BCLK

Write signal

Read signal

ALE

Address bus

Address bus/

Data bus

NOTES :

1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.

Address

CS

Address

Data output

Address

Figure 8.8 Typical Bus Timings Using Software Wait (2)

Address

Input

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M16C/62P Group (M16C/62P, M16C/62PT)

9. Memory Space Expansion Function

9. Memory Space Expansion Function

Note

9. Memory Space Expansion Function is described in the M16C/62P (128-pin version and

100-pin version) only as an example.
The M16C/62P (80-pin version) and M16C/62PT do not use this function.

The following describes a memory space extension function.
During memory expansion or microprocessor mode, the memory space expansion function allows the
access space to be expanded using the appropriate register bits.
Table 9.1 shows the way of setting memory space expansion function, memory spaces.

Table 9.1 The Way of Setting Memory Space Expansion Function, Memory Space

Memory Space Expansion Function How to Set (PM15 to PM14) Memory Space
1-Mbyte Mode 00b 1 Mbyte (no expansion)
4-Mbyte Mode 11b 4 Mbytes

9.1 1-Mbyte Mode

In this mode, the memory space is 1 Mbytes. In 1-Mbyte mode, the external area to be accessed is
specified using the CSi (i = 0 to 3) signals (hereafter referred to as the CSi area). Figures 9.2 to 9.3 show
the memory mapping and CS area in 1-Mbyte mode.

______ ______

_____

9.2 4-Mbyte Mode

In this mode, the memory space is 4 Mbytes. Figure 9.1 shows the DBR register. The BSR2 to BSR0 bits
in the DBR register select a bank number which is to be accessed to read or write data. Setting the OFS bit
to “1” (with offset) allows the accessed address to be offset by 40000h.

In 4-Mbyte mode, the CSi (i=0 to 3) pin functions differently for each area to be accessed.

9.2.1 Addresses 04000h to 3FFFFh, C0000h to FFFFFh

______ ______

• The CSi signal is output from the CSi pin (same operation as 1-Mbyte mode. However the last
address of CS1 area is 3FFFFh)

9.2.2 Addresses 40000h to BFFFFh

______

• The CS0 pin outputs “L”

______ ______

• The CS1 to CS3 pins output the value of setting as the BSR2 to BSR0 bits (bank number)

Figures 9.4 to 9.5 show the memory mapping and CS area in 4-Mbyte mode. Note that banks 0 to 6 are
data-only areas. Locate the program in bank 7 or the CSi area.

______

_______

______

______

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9. Memory Space Expansion Function

Data Bank Register

b7 b6 b5 b4 b3 b2 b1 b0

NOTES:

1. Effective when the PM01 to PM00 bits in the PM0 register are set to “01b” (memory expansion mode) or
“11b” (microprocessor mode).

Figure 9.1 DBR Register

(1)

Symbol Address After Reset

DBR 000Bh 00h

Bit Symbol

(b1-b0)

OFS

BSR0

BSR1

BSR2

(b7-b6)

Bit Name Function

Nothing is assigned. When write, set to “0”. When read, its content is
“0”.

Offset Bit

Bank Selection Bits

Nothing is assigned. When write, set to “0”. When read, its content is
“0”.

0: Not offset
1: Offset

b5 b4 b3 b5 b4 b3

0 0 0: Bank 0 0 0 1: Bank 1
0 1 0: Bank 2 0 1 1: Bank 3
1 0 0: Bank 4 1 0 1: Bank 5
1 1 0: Bank 6 1 1 1: Bank 7

RW

RW
RW

RW
RW

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M16C/62P Group (M16C/62P, M16C/62PT)

9. Memory Space Expansion Function

Memory expansion mode

00000h
00400h

XXXXXh

08000h

Reserved, external area

10000h
27000h

28000h
30000h

80000h

YYYYYh

FFFFFh

PM13=1

Capacity

10 Kbytes
12 Kbytes

20 Kbytes
24 Kbytes

Address XXXXXh

SFR

Internal RAM

Reserved area

External area

Reserved area

Internal ROM

02BFFh

033FFh

053FFh
063FFh

(1)

Capacity

128 Kbytes

256 Kbytes

384 Kbytes
512 Kbytes

Microprocessor mode

Address YYYYYh

E0000h

C0000h

A0000h

80000h

(PM10=0: 124 Kbytes)

CS2

(32 Kbytes)

CS1

CS0

(Microprocessor mode:832 Kbytes)

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M16C/62P Group (M16C/62P, M16C/62PT)

9. Memory Space Expansion Function

Memory expansion mode

00000h
00400h

h

XXXXX

04000h
08000h

Reserved, external area

10000h
27000h

28000h
40000h

C0000h
D0000h

YYYYYh

FFFFFh

SFR

Internal RAM

Reserved area

(3)

Reserved area

External area

Reserved area

Internal ROM

Microprocessor mode

SFR

Internal RAM

Reserved area

Reserved, external area

Reserved area

External area

(3)

(16 Kbytes)

CS3

(PM10=0: 124 Kbytes)

CS2

(PM10=1: 92 Kbytes)

CS2

(96 Kbytes)

CS1

Other than the CS area

CS0

(512 Kbytes X 8 banks)

CS0

(Memory expansion mode:64 Kbytes )

(Microprocessor mode:256 Kbytes)

PM13=0

Internal RAM Internal ROM

Capacity

10 Kbytes
12 Kbytes

16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes

NOTES :

Address XXXXXh

4 Kbytes

013FFh

5 Kbytes

017FFh
02BFFh
033FFh
03FFFh
03FFFh

03FFFh
03FFFh

1. The CS0 pin outputs a low signal, and the CS1–CS3 pins output a bank number.

2. If PM13 bit in the PM1 register is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.

3. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.

Capacity

48 Kbytes
64 Kbytes

96 Kbytes
128 Kbytes
192 Kbytes

(2)
(2)

256 Kbytes

(2)

320 Kbytes

(2)

384 Kbytes

512 Kbytes

Address YYYYYh

F4000h
F0000h
E8000h
E0000h
D0000h

(2)

D0000h

(2)

D0000h

(2)

D0000h

(2)

D0000h

CS0

Memory expansion mode
C0000h–CFFFFh

Microprocessor mode
C0000h–FFFFFh

______

External area

CS1

28000h–
3FFFFh

CS2

When PM10=0
08000h–26FFFh

When PM10=1
10000h–26FFFh

Figure 9.4 Memory Mapping and CS Area in 4-Mbyte mode (PM13=0)

CS3

04000h–
07FFFh

Other than the CS area

40000h–BFFFFh

(1)

Memory expansion mode

00000h
00400h

h

XXXXX

08000h

Reserved, external area
10000h
27000h
28000h

40000h

80000h

C0000h

YYYYYh

FFFFFh

SFR

Internal RAM

Reserved area

(2)

Reserved area

External area

Reserved area

Internal ROM

Microprocessor mode

SFR

Internal RAM

Reserved area

Reserved, external area

Reserved area

External area

(2)

(PM10=0: 124 Kbytes)

CS2

(PM10=1: 92 Kbytes)

CS2

(96 Kbytes)

CS1

Other than the CS area

*Two 256 Kbytes X 8 banks can be used by changing the offset.

Other than the CS area

CS0

(Microprocessor mode:256 Kbytes)

(Memory expansion mode:256 Kbytes X 8 banks)*

(Microprocessor mode:512 Kbytes X 8 banks)

PM13=1

Internal RAM

Capacity

Address XXXXXh

4 Kbytes 013FFh

5 Kbytes 017FFh
10 Kbytes 02BFFh
12 Kbytes 033FFh
16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes

NOTES :

1. The CS0 pin outputs a low signal, and the CS1–CS3 pins output a bank number.

2. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.

043FFh
053FFh
063FFh
07FFFh

Internal ROM

Capacity

48 Kbytes
64 Kbytes

96 Kbytes
128 Kbytes
192 Kbytes
256 Kbytes

320 Kbytes
384 Kbytes
512 Kbytes

Address YYYYYh

F4000h

F0000h
E8000h
E0000h
D0000h
C0000h

B0000h
A0000h

80000h

CS0

Microprocessor mode
C0000h–FFFFFh

______

External area

CS1

28000h–
3FFFFh

CS2

When PM10=0
08000h–26FFFh

When PM10=1
10000h–26FFFh

Figure 9.5 Memory Mapping and CS Area in 4-Mbyte mode (PM13=1)

CS3

No area

Other than the CS area

Memory expansion mode
40000h–7FFFFh

Microprocessor mode
40000h–BFFFFh

(1)

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M16C/62P Group (M16C/62P, M16C/62PT)

9. Memory Space Expansion Function

Figure 9.6 shows the external memory connect example in 4-Mbyte mode.
In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The 4 Mbyte

_____ _______

_______ _______ _______

ROM address input AD21, AD20 and AD19 pins are connected to the CS3, CS2 and CS1 pins of micro­computer, respectively. The address input AD18 pin is connected to the A19 pin of microcomputer. Fig­ures 9.7 to 9.9 show the relationship of addresses between the 4-Mbyte ROM and the microcomputer for
the case of a connection example in Figure 9.6.
In microprocessor mode, or in memory expansion mode where the PM13 bit in the PM1 register is “0”,
banks are located every 512 Kbytes. Setting the OFS bit in the DBR register to “1” (offset) allows the
accessed address to be offset by 40000h, so that even the data overlapping a bank boundary can be
accessed in succession.
In memory expansion mode where the PM13 bit is “1,” each 512-Kbyte bank can be accessed in 256 Kbyte
units by switching them over with the OFS bit.
Because the SRAM can be accessed on condition that the chip select signals S2 = H and S1 =L, CS0 and

_______ _____ ____

CS2 can be connected to S2 and S1, respectively. If the SRAM does not have the input pins to accept “H”

____ _______ _______

____ _______

active and “L” active chip select signals(S1, S2), CS0 and CS2 should be decoded external to the chip.

D0 to D7

A0 to A16

A17

A19

8

17

DQ0 to DQ7
AD0 to AD16

AD17

AD18

CS1
CS2
CS3

Microcomputer

RD

CS0

WR

AD19
AD20
AD21

OE
CS

DQ0 to DQ7

AD0 to AD16

OE
S2

(1)

S1
W

4M bytes ROM

128K bytes SRAM

NOTES:

1. If only one chip select pin (S1 or S2) is present,
decoding by use of an external circuit is required.

Figure 9.6 External Memory Connect Example in 4-Mbyte Mode

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M16C/62P Group (M16C/62P, M16C/62PT)

Memory expansion mode where PM13 =0

9. Memory Space Expansion Function

ROM address Microcomputer address

OFS bit in DBR
register = 0

000000h

bank 0

040000h

(512 Kbytes)

080000h

bank 1

0C0000h

(512 Kbytes)

100000h

bank 2

140000h

(512 Kbytes)

180000h

Data

1C0000h

bank 3
(512 Kbytes)

200000h

bank 4

240000h

(512 Kbytes)

280000h

bank 5

2C0000h

(512 Kbytes)

300000h

bank 6
(512 Kbytes)

bank 7
(512 Kbytes)

Program

or data

Program

or data

340000h

380000h

3C0000h

3FFFFFh

40000h

BFFFFh
40000h

BFFFFh

40000h

BFFFFh
40000h

BFFFFh
40000h

BFFFFh
40000h

BFFFFh

40000h

BFFFFh

40000h

BFFFFh

OFS bit in DBR
register = 1

40000h

bank 0
(512 Kbytes)

BFFFFh
40000h

bank 1
(512 Kbytes)

BFFFFh
40000h

bank 2
(512 Kbytes)

BFFFFh
40000h

bank 3
(512 Kbytes)

BFFFFh
40000h

bank 4
(512 Kbytes)

BFFFFh
40000h

bank 5
(512 Kbytes)

BFFFFh
40000h

bank 6
(512 Kbytes)

BFFFFh

Bank

Number

0

OFS

Access

40000h

0

BFFFFh

40000h

1

BFFFFh

40000h

0

1

BFFFFh

40000h

1

BFFFFh

40000h

0

2

BFFFFh

40000h

1

BFFFFh

40000h

0

3

4

5

6

BFFFFh

40000h

1

BFFFFh

40000h

0

BFFFFh

40000h

1

BFFFFh

40000h

0

BFFFFh

40000h

1

BFFFFh

40000h

0

BFFFFh

40000h

1

BFFFFh

40000h 380000h

7FFFFh

80000h 3C0000h

7 0

BFFFFh
C0000h 3C0000h

CFFFFh

D0000h

DFFFFh

D0000h

DFFFFh

N.C.: No connected

Output from the Microcomputer Pins

Area

CS Output Address Output

CS3 CS2 CS1 A19 A17 A16

0

000100

0001011

0001000

0010111

0010100

0011011
0011000

0100111

0100100

0101011

0101000

0110111

0110100

0111011

0111000

1000111

1000100

1001011

1001000
1010111

1010100

1011011

1011000

1100111

1100100
1101011

1101000

1110111

1 1 1 0 1 0 0 0000h

1110111

1 1 1 1 0 0 0 0000h

1111011

1 1 1 1 1 0 0 0000h
1111100

A20 A19 A18

A21

Address Input for 4-Mbyte ROM

A18

N.C.

A17 A16

A15 to A0

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

FFFFh

FFFFh

FFFFh

A15 to A0

000000h
07FFFFh
040000h
0BFFFFh
080000h

0FFFFFh

0C0000h
13FFFFh
100000h
17FFFFh
140000h

1BFFFFh

180000h

1FFFFFh

1C0000h
23FFFFh
200000h
27FFFFh
240000h

2BFFFFh

280000h

2FFFFFh

2C0000h
33FFFFh

300000h
37FFFFh
340000h

3BFFFFh

3BFFFFh

3FFFFFh

3CFFFFh

Internal ROM access

Internal ROM access

Internal ROM access

Internal ROM access

Address input for

4-Mbyte ROM

Figure 9.7 Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (1)

page 62

Z0320-5810B90JER

463fo4002,10peS03.2.veR

M16C/62P Group (M16C/62P, M16C/62PT)

Memory expansion mode where PM13 =1

9. Memory Space Expansion Function

ROM address Microcomputer address

OFS bit in DBR
register = 0

000000h

bank 0
(256 Kbytes)

040000h

080000h

bank 1
(256 Kbytes)

0C0000h

100000h

bank 2
(256 Kbytes)

140000h

180000h

bank 3
(256 Kbytes)

Data

1C0000h

Program

or data

200000h

240000h

280000h

2C0000h

300000h

340000h

380000h

3C0000h

3FFFFFh

bank 4
(256 Kbytes)

bank 5
(256 Kbytes)

bank 6
(256 Kbytes)

bank 7
(256 Kbytes)

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

40000h

7FFFFh

OFS bit in DBR
register = 1

40000h

bank 0
(256 Kbytes)

7FFFFh

40000h

bank 1
(256 Kbytes)

7FFFFh

40000h

bank 2
(256 Kbytes)

7FFFFh

40000h

bank 3
(256 Kbytes)

7FFFFh

40000h

bank 4
(256 Kbytes)

7FFFFh

40000h

bank 5
(256 Kbytes)

7FFFFh

40000h

bank 6
(256 Kbytes)

7FFFFh

40000h

bank 7
(256 Kbytes)

7FFFFh

Bank

Number

0

OFS

Access

40000h

0

7FFFFh
40000h

1

7FFFFh
40000h

0

1

7FFFFh
40000h

1

7FFFFh
40000h

0

2

7FFFFh
40000h

1

7FFFFh
40000h

0

3

4

7FFFFh

40000h

1

7FFFFh
40000h

0

7FFFFh
40000h

1

7FFFFh
40000h

0

7FFFFh

5

6

40000h

1

7FFFFh

40000h

0

7FFFFh
40000h

1

7FFFFh

40000h 380000h

7FFFFh

0

7

80000h
FFFFFh
40000h

7FFFFh

1

7

80000h
FFFFFh

N.C.: No connected

Output from the Microcomputer Pins

Area

CS Output Address Output

CS3 CS2 CS1 A19 A17 A16

000100

0

0000111

0001000

0001011

0010100

0010111
0011000

0011011

0100100

0100111

0101000

0101011

0110100

0110111

0111000

0111011

1000100

1000111

1001000
1001011

1010100

1010111

1011000

1011011

1100100
1100111

1101000

1101011

11101000000h

1110111

11110000000h

1111011FFFFh

A20 A19 A18

A21

A18

N.C.

Address Input for 4-Mbyte ROM

A17 A16

A15 to A0

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

0000h

FFFFh

FFFFh

A15 to A0

000000h

03FFFFh

040000h

07FFFFh

080000h

0BFFFFh

0C0000h

0FFFFFh

100000h

13FFFFh

140000h
17FFFFh
180000h

1BFFFFh

1C0000h

1FFFFFh

200000h

23FFFFh

240000h
27FFFFh
280000h

2BFFFFh

2C0000h

2FFFFFh

300000h

33FFFFh

340000h
37FFFFh

3BFFFFh

Internal ROM access

Internal ROM access

3C0000h

3FFFFFh

Internal ROM access

Internal ROM access

Address input for

4-Mbyte ROM

Figure 9.8 Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (2)

page 63

Z0320-5810B90JER

463fo4002,10peS03.2.veR

M16C/62P Group (M16C/62P, M16C/62PT)

Microprocessor mode

9. Memory Space Expansion Function

ROM address Microcomputer address

OFS bit in DBR
register = 0

000000h

bank 0

040000h

(512 Kbytes)

080000h

bank 1

0C0000h

(512 Kbytes)

100000h

bank 2

140000h

(512 Kbytes)

180000h

Data

1C0000h

bank 3
(512 Kbytes)

200000h

bank 4

240000h

(512 Kbytes)

280000h

bank 5

2C0000h

(512 Kbytes)

300000h

bank 6
(512 Kbytes)

bank 7
(512 Kbytes)

Program

or data

Program

or data

340000h

380000h

3C0000h

3FFFFFh

40000h

BFFFFh
40000h

BFFFFh
40000h

BFFFFh
40000h

BFFFFh
40000h

BFFFFh
40000h

BFFFFh
40000h

BFFFFh
40000h

7FFFFh
C0000h

FFFFFh

OFS bit in DBR
register = 1

40000h

bank 0
(512 Kbytes)

BFFFFh

40000h

bank 1
(512 Kbytes)

BFFFFh
40000h

bank 2
(512 Kbytes)

BFFFFh
40000h

bank 3
(512 Kbytes)

BFFFFh
40000h

bank 4
(512 Kbytes)

BFFFFh
40000h

bank 5
(512 Kbytes)

BFFFFh

40000h

bank 6
(512 Kbytes)

BFFFFh

Bank

OFS

Number

40000h

0

0

1

BFFFFh
40000h

1

BFFFFh
40000h

0

40000h

1

BFFFFh
40000h

0

2

3

4

5

6

BFFFFh

1

BFFFFh

0

BFFFFh

40000h

1

0

BFFFFh

1

BFFFFh

0

BFFFFh
40000h

1

BFFFFh

0

BFFFFh

1

40000h 380000h
7FFFFh

7 0

80000h 3C0000h
BFFFFh

C0000h 3C0000h111

FFFFFh

N.C.: No connected

Access

Area

Output from the Microcomputer Pins

CS Output Address Output

CS3 CS2 CS1 A19 A17 A16 A15 to A0

0

000100

000 1011

0001000

0010111

001 0100

0011011BFFFFh FFFFh 0FFFFFh
001 1000

010 0111

010 0100

0101011

011 0111

011101

011 1000

1000111BFFFFh FFFFh 23FFFFh

1001011

1010111

101 1011

101 1000

110 0111

110 1011

1110111BFFFFh FFFFh 3BFFFFh

1 1 1 0 1 0 0 0000h

1110111

11110 0 0 0000h

1111011

1111111

A20 A19 A18 N.C. A17 A16

A21

A18

1

00040000h 0000h

0

10040000h 0000h

0

10040000h 0000h

1

00040000h 0000h

0

10040000h 0000h

0

10040000h 0000h

1

00040000h 0000h

1

1 0 0 0000h

Address Input for 4-Mbyte ROM

1

0000h

FFFFh

0000h

FFFFh

0000h

0000h

FFFFh

0000h

FFFFh

FFFFh

FFFFh

0000h

FFFFh

FFFFh

FFFFh

0000h

FFFFh

FFFFh

FFFFh

FFFFh

FFFFh

A15 to A0

000000h

07FFFFh

040000h
0BFFFFh
080000h

0C0000h

13FFFFh

100000h

17FFFFh

140000h010
1BFFFFh
180000h011

1FFFFFh
1C0000h

200000h100

27FFFFh

240000h100
2BFFFFh
280000h101
2FFFFFh

2C0000h

33FFFFh

300000h110

37FFFFh

340000h110

3BFFFFh

3FFFFFh

3FFFFFh

Address Input for

4-Mbyte ROM

Figure 9.9 Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (3)

page 64

Z0320-5810B90JER

463fo4002,10peS03.2.veR

M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

10. Clock Generating Circuit

10.1 Types of the Clock Generating Circuit

Four circuits are incorporated to generate the system clock signal :

• Main clock oscillation circuit

• Sub clock oscillation circuit

• On-chip oscillator

• PLL frequency synthesizer

Table 10.1 lists the clock generation circuit specifications. Figure 10.1 shows the clock generation circuit.
Figures 10.2 to 10.6 show the clock-related registers.

Table 10.1 Clock Generation Circuit Specifications

Item

Use of Clock

Clock Frequency 0 to 16 MHz 32.768 kHz

Usable Oscillator

Pins to Connect
Oscillator

Oscillation Stop,
Restart Function

Oscillator Status
After Reset

Other

Main Clock

Oscillation Circuit

• CPU clock source

• Peripheral function

clock source

• Ceramic oscillator

• Crystal oscillator

XIN, XOUT

Presence

Oscillating

Externally derived clock can be input

Sub Clock

Oscillation Circuit

•CPU clock source

• Clock source of

Timer A, B

• Crystal oscillator

XCIN, XCOUT

Presence

Stopped

On-chip Oscillator

• CPU clock source

• Peripheral function clock source

• CPU and peripheral function

clock sources when the main
clock stops oscillating

About 1 MHz

Presence

Stopped

PLL Frequency

Synthesizer

• CPU clock source

• Peripheral function clock

source

10 to 24 MHz

Presence

Stopped

Z0320-5810B90JER

page 65

463fo4002,10peS03.2.veR

M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

CM04

CM10=1(stop mode)

WAIT instruction

RESET

Software reset

NMI

Interrupt request level judgment output

CM02, CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
PCLK0, PCLK1: Bits in PCLKR register
CM21, CM27 : Bits in CM2 register

Q

S

R

CM05

QS

R

Sub-clock

generating circuit

XCIN

CM21

XOUTXIN

Main clock

generating circuit

XCOUT

Main
clock

Sub-clock

On-chip
oscillator

Oscillation
stop, re­oscillation
detection
circuit

PLL
frequency
synthesizer

PLL
clock

1

0

CM11

CM02

a

I/O ports

PM01–PM00=00b, CM01–CM00=01b
PM01–PM00=00b, CM01–CM00=10b

fC32

1/32

f1
f2

On-chip
oscillator
clock

CM21=1

CM21=0

fC

c

b

e

a

Divider

e

b

1/2 1/2 1/2 1/2

1/2 1/4 1/8 1/16

CM06=1

CM06=0
CM17–CM16=00b

CM06=0
CM17–CM16=10b

CM06=0
CM17–CM16=01b

CM01–CM00=00b

PCLK0=1
PCLK0=0

f8

f32

f1SIO

PCLK1=1

f2SIO

PCLK1=0

CM07=0

d

fC

CM07=1

Details of divider

PM01–PM00=00b,
CM01–CM00=11b

fAD

f8SIO

f32SIO

1/2

CM06=0
CM17–CM16=11b

CLKOUT

D4INT clock

CPU clock

BCLK

c

1/32

d

Main
clock

Main clock

Oscillation Stop, Re-Oscillation Detection Circuit

Pulse generation
circuit for clock
edge detection
and charge,
discharge control

Charge,
discharge
circuit

CM27=0

CM27=1

PLL Frequency Synthesizer

Programmable

counter

Phase

comparator

Reset
generating
circuit

Oscillation stop,
re-oscillation
detection interrupt
generating circuit

Charge

pump

Oscillation stop
detection reset

Oscillation stop,
re-oscillation
detection signal

CM21 switch signal

Voltage

control

oscillator

(VCO)

Internal low-

pass filter

1/2

PLL clock

Figure 10.1 Clock Generation Circuit

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M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

System Clock Control Register 0

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address After Reset

(1)

CM0 0006h 01001000b

Bit

CM00

CM01

CM02

CM03

CM04
CM05

CM06

CM07

NOTES :

1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).

2. The CM03 bit is set to “1” (high) while the CM04 bit is set to “0,” or when entered to stop mode.

3. This bit is provided to stop the main clock when the low power dissipation mode or on-chip oscillator low power dissipation
mode is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock,
set bits in the following order.

(a) Set the CM07 bit to “1” (Sub-clock select) or the CM21 bit of CM2 register to “1” (On-chip oscillator select) with the

sub-clock stably oscillating.
(b) Set the CM20 bit of CM2 register to “0” (Oscillation stop, re-oscillation detection function disabled).
(c) Set the CM05 bit to “1” (Stop).

4. During external clock input, Set the CM05 bit to “0” (oscillate).

5. When CM05 bit is set to “1”, the XOUT pin goes “H”. Furthermore, because the internal feedback resistor remains connected,
the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.

6. After setting the CM04 bit to “1” (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from “0” to “1” (sub-clock).

7. When entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip oscillator low power mode,
the CM06 bit is set to “1” (divide-by-8 mode).

8. The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to “1” (peripheral clock
turned off when in wait mode).

9. To use a sub-clock, set this bit to “1”. Also make sure ports P8_6 and P8_7 are directed for input, with no pull-ups.

10. When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM02, CM05, and CM07 bits has

no effect.

11. If the PM21 bit needs to be set to “1,” set the CM07 bit to “0” (main clock) before setting it.

12. To use the main clock as the clock source for the CPU clock, set bits in the following order.

(a) Set the CM05 bit to “0” (oscillate).
(b) Wait the main clock oscillation stabilizes.
(c) Set the CM11, CM21 and CM07 bits all to “0”.

13. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to “1”
(divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).

14. To return from on-chip oscillator mode to high-speed or middle-speed mode, set the CM06 and CM15 bits both to “1”.

Clock Output Function
Select Bit
(Valid only in single-chip
mode)

WAIT Mode Peripheral
Function Clock Stop Bit

XCIN-XCOUT Drive
Capacity Select Bit

Port XC Select Bit

Main Clock Stop Bit

(3, 10, 12, 13)

Main Clock Division
Select Bit 0

System Clock Select Bit

(6, 10, 11, 12)

Name

(2)

(2)

(7, 13, 14)

b1 b0

0 0 : I/O port P5_7
0 1 : fC output
1 0 : f8 output
1 1 : f32 output

0 : Do not stop peripheral function clock in wait mode

(10)

1 : Stop peripheral function clock in wait mode
0 : LOW

1 : HIGH
0 : I/O port P8_6, P8_7

1 : XCIN-XCOUT generation function
0 : On

(4, 5)

1 : Off
0 : CM16 and CM17 valid

1 : Division by 8 mode
0 : Main clock, PLL clock, or on-chip oscillator clock

1 : Sub-clock

FunctionBit Symbol

(8)

(9)

RW
RW

RW

RW
RW
RW
RW

RW

RW

Figure 10.2 CM0 Register

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Z0320-5810B90JER

463fo4002,10peS03.2.veR

M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

System Clock Control Register 1

b7 b6 b5 b4 b3 b2 b1 b0

000

NOTES:

1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).

2. When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).

3. Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).

4. If the CM10 bit is “1” (stop mode), XOUT goes “H” and the internal feedback resistor is disconnected. The XCIN and XCOUT
pins are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the CM2 register is
set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.

5. After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), wait until Tsu (PLL) elapses before setting the CM11 bit to
“1” (PLL clock).

6. When the PM21 bit in the PM2 register is set to “1” (clock modification disable), writing to the CM10, CM11 bits has no effect.
When the PM22 bit in the PM2 register is set to “1” (watchdog timer count source is on-chip oscillator clock), writing to the CM10
bit has no effect.

7. Effective when CM07 bit is “0” and CM21 bit is “0” .

Symbol Address After Reset
CM1 0007h 00100000b

CM10

CM11

(b4-b2)

CM15

CM16
CM17

(1)

Bit

All Clock Stop Control Bit

(4, 6)

System Clock Select Bit 1

(6, 7)

Reserved Bit

XIN-XOUT Drive Capacity
Select Bit

Main Clock Division
Select Bit 1

Name

(2)

(3)

FunctionBit Symbol

0 : Clock on
1 : All clocks off (stop mode)

0 : Main clock
1 : PLL clock

Set to
0 : LOW

1 : HIGH

b7 b6

0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode

(5)

“0”

RW
RW

RW

RW
RW

RW

RW

Figure 10.3 CM1 Register

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Z0320-5810B90JER

M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

Oscillation Stop Detection Register

b7 b6 b5 b4 b3 b2 b1 b0

00

NOTES:

1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).

2. When the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the
CM21 bit is set to “1” (on-chip oscillator clock) if the main clock stop is detected.

3. If the CM20 bit is “1” and the CM23 bit is “1” (main clock turned off), do not set the CM21 bit to “0”.

4. This flag is set to “1” when the main clock is detected to have stopped and when the main clock is
detected to have restarted oscillating. When this flag changes state from “0” to “1,” an oscillation stop or
an oscillation restart detection interrupt is generated. Use this flag in an interrupt routine to discriminate
the causes of interrupts between the oscillation stop and oscillation restart detection interrupts and the
watchdog timer interrupt. The flag is cleared to “0” by writing a “0” in a program. (Writing a “1” has no
effect. Nor is it cleared to “0” by an oscillation stop or an oscillation restart detection interrupt request
acknowledged.)
If when the CM22 bit = 1 an oscillation stoppage or an oscillation restart is detected, no oscillation
stop and oscillation restart detection interrupts are generated.

5. Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine
the main clock status.

6. Effective when the CM07 bit in the CM0 register is “0”.

7. When the PM21 bit in the PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no
effect.

8. Where the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is “1” (the CPU clock source is PLL
clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is “0”
under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop
detection; it is, therefore, necessary to set the CM21 bit to “1” (on-chip oscillator clock) inside the interrupt
routine.

9. Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit
back to “1” (enable).

10.Set the CM20 bit to “0” (disable) before setting the CM05 bit in the CM0 register.

11.The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.

12.When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the
CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).

Symbol Address After Reset

CM2 000Ch

Bit Symbol

CM20

CM21

CM22

CM23

(b5-b4)

(b6)
CM27

(1)

0X000000b

Bit Name

Oscillation Stop,
Re-Oscillation Detection

(7, 9, 10, 11)

Bit

System Clock
Select Bit 2

(2, 3, 6, 8, 11, 12)

Oscillation Stop,
Re-Oscillation Detection

(4)

Flag

XIN Monitor Flag

Reserved Bit

Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.

Operation Select Bit
(when an oscillation stop,
re-oscillation is detected)

(11)

(5)

0: Oscillation stop, re-oscillation
detection function disabled
1: Oscillation stop, re-oscillation
detection function enabled

0: Main clock or PLL clock
1: On-chip oscillator clock
(On-chip oscillator oscillating)

0: Main clock stop, re-oscillation
not detected
1: Main clock stop, re-oscillation
detected

0: Main clock oscillating
1: Main clock turned off

Set to “0”

0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
detection interrupt

(11)

Function

RW

RW

RW

RW

RO

RW

RW

Figure 10.4 CM2 Register

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M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

Peripheral Clock Select Register

b7 b6 b5 b4 b3 b2 b1 b0

000

NOTES:

000

Bit Symbol

PCLK0

PCLK1

(b7-b2)

1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).

Processor Mode Register 2

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol

(1)

Symbol Address When Reset
PCLKR 025Eh 00000011b

Bit Name

Timers A, B Clock Select
Bit (Clock source for
Timers A, B, and the dead
timer)

SI/O Clock Select Bit
(Clock source for UART0
to UART2, SI/O3, SI/O4)

Reserved bit Set to

(1)

Symbol Address After Reset
PM2 001Eh XXX00000b

Bit Name

0 : f2
1 : f1

0 : f2SIO
1 : f1SIO

“0”

Function

Function

RW

RW

RW

RW

RW

Figure 10.5 PCLKR Register and PM2 Register

page 70

Z0320-5810B90JER

463fo4002,10peS03.2.veR

M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

PLL Control Register 0

b7 b6 b5 b4 b3 b2 b1 b0

0 10

NOTES:

1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).

2. When the PM21 bit in the PM2 register is “1” (clock modification disable), writing to this register has no effect.

3.

These three bits can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to this bit

cannot be modified.

4. Before setting this bit to “1,” set the CM07 bit in the CM0 register to “0” (main clock), set the CM17 to CM16
bits in the CM1 register to “00b” (main clock undivided mode), and set the CM06 bit in the CM0 register to
“0” (CM16 and CM17 bits enable).

(1, 2)

Symbol Address After Reset
PLC0 001Ch 0001X010b

Bit

Symbol

PLC00

PLC01

PLC02

(b3)

(b4)

(b6-b5)

PLC07

Bit Name

PLL Multiplying Factor
Select Bit

Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.

Reserved Bit

Reserved Bit Set to “0”

Operation Enable Bit

(3)

b1b0b2

0 0 0:
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1: Multiply by 6
1 0 0: Multiply by 8
1 0 1:
1 1 0:
1 1 1:

Set to “1”

(4)

0: PLL Off
1: PLL On

Do not set

Function

Do not set

RW

RW

RW

RW

RW

RW

RW

Figure 10.6 PLC0 Register

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10. Clock Generating Circuit

The following describes the clocks generated by the clock generation circuit.

10.1.1 Main Clock

This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as
the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is config­ured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit con­tains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to
reduce the amount of power consumed in the chip. The main clock oscillator circuit may also be config­ured by feeding an externally generated clock to the XIN pin. Figure 10.7 shows the examples of main
clock connection circuit.
After reset, the main clock divided by 8 is selected for the CPU clock.
The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to “1”
(main clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or
on-chip oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback
resistor remains on, XIN is pulled “H” to XOUT via the feedback resistor. Note that if an externally
generated clock is fed into the XIN pin, the main clock cannot be turned off by setting the CM05 bit to “1,”
unless the sub clock is chosen as a CPU clock. If necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to 10.4 Power Control.

Microcomputer

(Built-in feedback resistor)
XIN XOUT

(1)

Rd

CIN

NOTES:

1. Place a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by each oscillator the oscillator manufacturer.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, place a feedback resistor
between XIN and XOUT if the oscillator manufacturer recommends placing the resistor externally.

COUT

Figure 10.7 Examples of Main Clock Connection Circuit

Microcomputer

(Built-in feedback resistor)

XIN XOUT

Open

Externally derived clock

VCC1
VSS

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10. Clock Generating Circuit

10.1.2 Sub Clock

The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same
frequency as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and
XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the
oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub
clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 10.8 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the
oscillator circuit.
To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to “1 ” (sub clock) after the
sub clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to 10.4 Power Control.

Microcomputer

(Built-in feedback resistor)

XCIN XCOUT

CCIN CCOUT

NOTES:

1. Place a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by each oscillator the oscillator manufacturer.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, place a feedback resistor
between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally.

(1)

RCd

Figure 10.8 Examples of Sub Clock Connection Circuit

Microcomputer

(Built-in feedback resistor)

XCIN XCOUT

Externally derived clock

VCC1

VSS

Open

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10. Clock Generating Circuit

10.1.3 On-chip Oscillator Clock

This clock, approximately 1MHz, is supplied by a on-chip oscillator. This clock is used as the clock
source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1”
(on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for
the watchdog timer (Refer to 13.1 Count Source Protective Mode).
After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register
to “1” (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function
clocks, in place of the main clock. If the main clock stops oscillating when the CM20 bit in the CM2
register is “1” (oscillation stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscilla­tion stop, re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying
the necessary clock for the microcomputer.

10.1.4 PLL Clock

The PLL clock is generated PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthe­sizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is used as the clock
source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the
CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”
(PLL stops). Figure 10.9 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.

PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register

(However, 10 MHz ≤ PLL clock frequency ≤ 24 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 10.2 shows the example for setting PLL
clock frequencies.

Table 10.2 Example for Setting PLL Clock Frequencies

XIN

PLC02 PLC01 PLC00 Multiplying Factor PLL Clock

(MHz)

10001 2

5010 4

3.33 0 1 1 6

2.5 1 0 0 8
12

6
4
3

001 2
010 4
011 6
100 8

NOTES :

1. 10MHz ≤ PLL clock frequency ≤ 24MHz.

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(MHz)

20

24

(1)

M16C/62P Group (M16C/62P, M16C/62PT)

Using the PLL clock as the clock source for the CPU

Set the CM07 bit to “0” (main clock), the CM17 to CM16
bits to “00b”(main clock undivided), and the CM06 bit to “0”

(CM16 and CM17 bits enabled).

Set the PLC02 to PLC00 bits (multiplying factor).

(When PLL clock > 16MHz)
Set the PM20 bit to “0” (2 wait states).

Set the PLC07 bit to “1” (PLL operation).

10. Clock Generating Circuit

(1)

Wait until the PLL clock becomes stable (tsu(PLL)).

Set the CM11 bit to “1” (PLL clock for the CPU clock source).

END

NOTES :

1. PLL operation mode can be entered from high speed mode.

Figure 10.9 Procedure to Use PLL Clock as CPU Clock Source

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10. Clock Generating Circuit

10.2 CPU Clock and Peripheral Function Clock

Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral
functions.

10.2.1 CPU Clock and BCLK

These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock
or the PLL clock.
If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit
in CM0 register and the CM17 to CM16 bits in the CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”
and the CM17 to CM16 bits to “00b” (undivided).
After reset, the main clock divided by 8 provides the CPU clock.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU
clock can be output from the BCLK pin by setting the PM07 bit in the PM0 register to “0” (output enabled).
Note that when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip
oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to “1” (main clock
turned off) in low-speed mode, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode).

10.2.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)

These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator clock
by dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O. The f8 and
f32 clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the
A/D converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used
when the sub clock is on.

10.3 Clock Output Function

During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to
CM00 bits in the CM0 register to select.

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10. Clock Generating Circuit

10.4 Power Control

Normal operation mode, wait mode and stop mode are provided as the power consumption control. All
mode states, except wait mode and stop mode, are called normal operation mode in this document.

10.4.1 Normal Operation Mode

Normal operation mode is further classified into seven modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the
CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator cir­cuits are turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a
sufficient wait time in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low speed or low power dissipation mode to
on-chip oscillator or on-chip oscillator low power dissipation mode. Nor can operation modes be changed
directly from on-chip oscillator or on-chip oscillator low power dissipation mode to low speed or low power
dissipation mode. Where the CPU clock source is changed from the on-chip oscillator to the main clock,
change the operation mode to the medium speed mode (divided by 8 mode) after the clock was divided
by 8 (the CM06 bit in the CM0 register was set to “1”) in the on-chip oscillator mode.

10.4.1.1 High-speed Mode

The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.

10.4.1.2 PLL Operation Mode

The main clock multiplied by 2, 4, 6 or 8 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. PLL operation
mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop
mode, first go to high speed mode before changing.

10.4.1.3 Medium-Speed Mode

The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be
used as the count source for timers A and B.

10.4.1.4 Low-Speed Mode

The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit in the CM2 register is set to “0” (on-chip oscillator turned off), and the
on-chip oscillator clock is used when the CM21 bit is set to “1” (on-chip oscillator oscillating).
The fC32 clock can be used as the count source for timers A and B.

10.4.1.5 Low Power Dissipation Mode

In this mode, the main clock is turned off after being placed in low speed mode. The sub clock
provides the CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit becomes “1” (divided by 8 mode). In the low
power dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divided by

8) mode is to be selected when the main clock is operated next.

10.4.1.6 On-chip Oscillator Mode

The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on­chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on,
fC32 can be used as the count source for timers A and B.

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10.4.1.7 On-chip Oscillator Low Power Dissipation Mode

The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be
selected as in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the
peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for timers A
and B. When the operation mode is returned to the high and medium speed modes, set the CM06 bit
in the CM0 register to “1” (divided by 8 mode).

Table 10.3 Setting Clock Related Bit and Modes

Modes
PLL Operation Mode 0 100b 00

High-Speed Mode 0 0 00b
Medium-

Speed
Mode

Low-Speed Mode 1 0 1

Low Power Dissipation Mode

On-chip
Oscillator
Mode

On-chip Oscillator Low Power
Dissipation Mode

NOTES :

divided by 2
divided by 4
divided by 8
divided by 16

divided by 1
divided by 2
divided by 4
divided by 8
divided by 16

1. When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low power
dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.

2. The divide-by-n value can be selected the same way as in on-chip oscillator mode.

CM2 Register

CM21

0001b
0010b 000
00 010
0011b 000

0
100b
101b
1 10b 0 0 0
1010
111b

1

CM1 Register

CM11 CM17, CM16

0
0
0
0
0
0
0

0

(NOTE 2)

CM07 CM06 CM05 CM04

CM0 Register

0
000
000

1
000
000

000
0

(1)

1

(NOTE 2) 1

1

(1)

10. Clock Generating Circuit

1

: “0” or “1”

10.4.2 Wait Mode

In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the
watchdog timer count source), the watchdog timer remains active. Because the main clock, sub clock
and on-chip oscillator clock all are on, the peripheral functions using these clocks keep operating.

10.4.2.1 Peripheral Function Clock Stop Function

If the CM02 bit in the CM0 register is “1” (peripheral function clocks turned off during wait mode), the
f1, f2, f8, f32, f1SIO, f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power
consumption reduced that much. However, fC32 remains on.

10.4.2.2 Entering Wait Mode

The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit = 1 (CPU clock source is the PLL clock), be sure to clear the CM11 bit in the CM1
register to “0” (CPU clock source is the main clock) before going to wait mode. The power consump­tion of the chip can be reduced by clearing the PLC07 bit in the PLC0 register to “0” (PLL stops).

10.4.2.3 Pin Status During Wait Mode

Table 10.4 lists pin status during wait mode

10.4.2.4 Exiting Wait Mode

The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral func­tion interrupt.
If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “000b” (interrupts disabled) before execut­ing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), peripheral function interrupts can be used to exit wait mode. If
CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral functions using
the peripheral function clocks stop operating, so that only the peripheral functions clocked by external
signals can be used to exit wait mode.

______

______

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10. Clock Generating Circuit

Table 10.4 Pin Status During Wait Mode

Pin Memory Expansion Mode Single-Chip Mode

Microprocessor Mode

A0 to A19, D0 to D15, CS0 to CS3,

_______ _______

________

BHE

_____ ______ ________ _________

Retains status before wait mode

Does not become a bus
control pin.

RD, WR, WRL, WRH “H”
HLDA, BCLK “H”

ALE “L”
I/O ports
CLKOUT When fC selected Does not stop

When f8, f32 selected

Retains status before wait mode Retains status before wait mode

Does not become a CLKOUT
pin.

Does not stop when the CM02
bit is “0”.
When the CM02 bit is “1”, the
status immediately prior to
entering wait mode is main­tained.

Table 10.5 Interrupts to Exit Wait Mode

Interrupt CM02=0 CM02=1
NMI Interrupt Can be used
Serial I/O Interrupt

Key Input Interrupt Can be used Can be used

A/D Conversion
Interrupt

Timer A Interrupt Can be used in all modes Can be used in event counter
Timer B Interrupt

INT Interrupt

Can be used when operating
with internal or external clock

Can be used in one-shot mode
or single sweep mode

Can be used

Can be used

Can be used when operating
with external clock

(Do not use)

mode or when the count
source is fC32

Can be used

Table 10.5 lists the interrupts to exit wait mode.
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.

(1) Set the ILVL2 to ILVL0 bits in the interrupt control register, for peripheral function interrupts used

to exit wait mode,
The ILVL2 to ILVL0 bits in all other interrupt control registers, for peripheral function interrupts not

used to exit wait mode, are set to “000b” (interrupt disable).
(2) Set the I flag to “1”.
(3) Start operating the peripheral functions used to exit wait mode.

When the peripheral function interrupt is used, an interrupt routine is performed as soon as an

interrupt request is acknowledged and the CPU clock is supplied again.

When the microcomputer exits wait mode by the peripheral function interrupt, the CPU clock is the
same clock as the CPU clock executing the WAIT instruction.

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10. Clock Generating Circuit

10.4.3 Stop Mode

In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to VCC1 and VCC2 pins is VRAM or
more, the internal RAM is retained. When applying 2.7 or less voltage to VCC1 and VCC2 pins, make
sure VCC1 ≥ VCC2 ≥ VRAM.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.

______

• NMI interrupt

• Key interrupt

______

• INT interrupt

• Timer A, Timer B interrupt (when counting external pulses in event counter mode)

• Serial I/O interrupt (when external clock is selected)

• Voltage down detection interrupt (Refer to 6.1 Voltage Down Detection Interrupt for an Oper-

ating Condition)

10.4.3.1 Entering Stop Mode

The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to “1” (all
clocks turned off). At the same time, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode)
and the CM15 bit in the CM1 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit in the CM2 register to “0” (oscillation stop, re-oscillation
detection function disable).
Also, if the CM11 bit in the CM1 register is “1” (PLL clock for the CPU clock source), set the CM11 bit
to “0” (main clock for the CPU clock source) and the PLC07 bit in the PLC0 register to “0” (PLL turned
off) before entering stop mode.

10.4.3.2 Pin Status in Stop Mode

Table 10.6 lists pin status during stop mode.

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10.4.3.3 Exiting Stop Mode

10. Clock Generating Circuit

Table 10.6 Pin Status in Stop Mode

Pin Memory Expansion Mode Single-Chip Mode

Microprocessor Mode

A0 to A19, D0 to D15, CS0 to CS3,

________

_______ _______

Retains status before stop mode

BHE

_____ ______ ________ _________

RD, WR, WRL, WRH “H”

__________

HLDA, BCLK “H”
ALE indeterminate
I/O ports

Retains status before stop mode

CLKOUT When fC selected “H”

When f8, f32 selected

Retains status before stop mode

Retains status before stop mode

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10. Clock Generating Circuit

Figure 10.10 shows the state transition from normal operation mode to stop mode and wait mode. Figure

10.11 shows the state transition in normal operation mode.
Table 10.7 shows a state transition matrix describing allowed transition and setting. The vertical line
shows current state and horizontal line shows state after transition.

Reset

All oscillators stopped

CM07=0
CM06=1
CM05=0
CM11=0

(5)

CM10=1

Stop mode

Stop mode

Stop mode

Stop mode

CM10=1

Interrupt

CM10=1

CM10=1

CM10=1

Interrupt

Interrupt

Interrupt

(6)

Medium-speed mode

(divided-by-8 mode)

High-speed, medium-

(6)

When
low power
dissipation
mode

(6)

(6)

(4)

speed mode

When
low­speed
mode

Low-speed, low power
dissipation mode

On-chip oscillator, On-chip
oscillator dissipation mode

PLL operation
mode

(NOTES 1, 2)

WAIT
instruction

Interrupt

WAIT
instruction

Interrupt

WAIT
instruction

Interrupt

WAIT
instruction

Interrupt

CPU operation stopped

Wait mode

Wait mode

Wait mode

Wait mode

Normal mode

NOTES :

1. Do not go directly from PLL operation mode to wait or stop mode.

2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.

3. Shown above is the case where the PM21 bit in the PM2 register = 0 (system clock protective function unused).

4. The on-chip oscillator clock divided by 8 provides the CPU clock.

5. Write to the CM0 and CM1 registers per 16 bit with CM21=0 (on-chip oscillator stops).
Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.

6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to “0” (oscillation stop and oscillation restart detection function disabled).

Figure 10.10 State Transition to Stop Mode and Wait Mode

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CM05=0

0

10. Clock Generating Circuit

Main clock oscillation

PLL operation mode

CPU clock: f(PLL)

CM07=0
CM06=0
CM17=0
CM16=0

PLL operation
mode

CPU clock: f(PLL)

CM07=0
CM06=0
CM17=0
CM16=0

CM04=0

PLC07=1

CM11=1

PLC07=0
CM11=0

PLC07=1
CM11=1

PLC07=0

CM11=0

(6)

(7)

(6)

(7)

High-speed mode

CPU clock: f(XIN)

CM07=0
CM06=0
CM17=0
CM16=0

High-speed mode

CPU clock: f(XIN)

CM07=0
CM06=0
CM17=0
CM16=0

Middle-speed mode
(divide by 2)

CPU clock: f(XIN)/2

CM07=0
CM06=0
CM17=0
CM16=1

Middle-speed mode
(divide by 2)

CPU clock: f(XIN)/2

CM07=0
CM06=0
CM17=0
CM16=1

CM07=1

CM05=1

Middle-speed mode
(divide by 4)

CPU clock: f(XIN)/4

Middle-speed mode
(divide by 4)

CPU clock: f(XIN)/4 CPU clock: f(XIN)/8 CPU clock: f(XIN)/16

(3)

Low-speed mode

CPU clock: f(XCIN)

(1, 9)

Low power dissipation mode

CPU clock: f(XCIN)

CM07=0
CM06=0
CM17=1
CM16=0

CM07=0
CM06=0
CM17=1
CM16=0

CM07=0

CM07=0
CM06=1
CM15=1

Middle-speed mode
(divide by 8)

CPU clock: f(XIN)/8 CPU clock: f(XIN)/16

Middle-speed mode
(divide by 8)

Middle-speed mode
(divide by 16)

CM07=0

CM06=1

CM07=0

CM06=1

CM07=0
CM06=0
CM17=1
CM16=1

CM04=0CM04=1CM04=1 CM04=1 CM04=0CM04=1

Middle-speed mode
(divide by 16)

CM07=0
CM06=0
CM17=1
CM16=1

(2, 4)

CM07=0

CM05=0

CM21=0

CM21=1

CM21=0

CM21=1

CM21=0

CM21=1

On-chip oscillator mode

CPU clock

(8)

f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16

On-chip oscillator
mode

(8)

CPU clock

f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16

Low-speed mode

CPU clock: f(XCIN)

CM07=0

CM05=1

CM04=0

CM05=0

(1)

CM05=1

On-chip oscillator clock
oscillation

On-chip oscillator low power
dissipation mode

CPU clock

f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16

On-chip oscillator
low power
dissipation mode

CPU clock

f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16

(1)

Sub clock oscillation

NOTES:

1. Avoid making a transition when the CM20 bit in the CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.

2. Wait the main clock oscillation stabilizes.

3. Switch clock after oscillation of sub-clock is sufficiently stable.

4. Change CM17 and CM16 bits in the CM1 register before changing CM06 bit in the CM0 register.

5. Transit in accordance with arrow.

6. The PM20 bit in the PM2 register become effective when the PLC07 bit in the PLC0 register is set to “1” (PLL on). Change the PM20 bit when the PLC07 bit is set to “0” (PLL off).
Set the PM20 bit to “0” (2 waits) when PLL clock >16MHz.

7. PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 bit to “0” (PLL off) before setting the PM20 bit to “1”
(SFR accessed with one wait state).

8. Set the CM06 bit to “1” (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.

9. When the CM21 bit in the CM2 register = 0 (on-chip oscillator turned off) and the CM05 bit in the CM0 register = 1 (main clock turned off), the CM06 bit is fixed to “1” (divide-by-8 mode) and
the CM15 bit in the CM1 register is fixed to “1” (drive capability High).

Figure 10.11 State Transition in Normal Mode

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M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

Table 10.7 Allowed Transition and Setting

State after transition

High-Speed Mode,
Middle-Speed Mode

High-Speed Mode,
Middle-Speed Mode

Low-Speed Mode

Low Power Dissipation
Mode

PLL Operation Mode

On-chip Oscillator Mode

Current state

On-chip Oscillator
Low Power Dissipation
Mode

Stop Mode

Wait Mode

NOTES :

1. Avoid making a transition when the CM21 bit is set in to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM21 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.

2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function clock.

3. PLL operation mode can only be entered from and changed to high-speed mode.

4. Set the CM06 bit to “1” (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.

5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).

6. If the CM05 bit set to “1” (main clock stop), then the CM06 bit is set to “1” (division by 8 mode).

7. A transition can be made only when sub clock is oscillating.

8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.

No

No Division

Divided by 2
Divided by 4
Divided by 8

Sub clock

Oscillating

Divided by 16

No division

Divided by 2
Divided by 4
Divided by 8

Sub clock

Turned Off

Divided by 16

9. ( ) : setting method. See the following table.

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)

(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)

Division

(3)
(3)
(3)
(3)
(2)

--

-- --

--

--

Setting Operation
CM04 = 0 Sub clock turned off
CM04 = 1 Sub clock oscillating

CM06 = 0,

CM17 = 0 , CM16 = 0

CM06 = 0,

CM17 = 0 , CM16 = 1

CM06 = 0,

CM17 = 1 , CM16 = 0

CM06 = 0,

CM17 = 1 , CM16 = 1

CM06 = 1
CM07 = 0
CM07 = 1 Sub clock selected
CM05 = 0 Main clock oscillating
CM05 = 1 Main clock turned off

PLC07 = 0,

CM11 = 0

PLC07 = 1,

CM11 = 1
CM21 = 0

CM21 = 1 On-chip oscillator clock selected
CM10 = 1 Transition to stop mode

Wait Instruction Transition to wait mode

Hardware Interrupt

(NOTE 8)

(2)

(8)

--

(2)

(12)
(14)

(18)

Sub Clock Oscillating Sub Clock Turned Off

Divided

Divided

by 4

by 2

(4)

(5)

(5)
(4)
(4)

(5)
(4)

(5)

--

-- -- --

(2)

--

(2)

--

--

----

CPU clock no division mode
CPU clock division by 2 mode

CPU clock division by 4 mode
CPU clock division by 16 mode
CPU clock division by 8 mode

Main clock, PLL clock,
or on-chip oscillator clock selected

Main clock selected
PLL clock selected
Main clock or PLL clock selected

Exit stop mode or wait mode

(NOTE 3)

(NOTE 4)

--

(NOTE 5)

Divided
by 8

Low-Speed Mode

(10)

Divided
by 16

(7)
(7)
(7)

(7)

-- --

--

(2)

--

(9)

(6)
(6)
(6)
(6)

--

--

(2)

(NOTE 7)

Low Power

(2)

Dissipation Mode

--

(NOTE 1,6)

(11)

--

--

--

--

-- -- -­(18)(18) --

No

Divided

Division

by 2

(1)

--

(1)

--

--

--

--

--

--

--

(4)
(3)
(3)

(4)
(3)

(4)
(3)

(4)

PLL Operation

(2)

Mode

(13)

--

--

(NOTE 3)

On-chip Oscillator
Mode

(15) --

--

--

--

--

(NOTE 8)

(10)

--

(18)

--

Divided

Divided

by 4

--

-- --

(1)

--

-­(5)
(5) (7)

(5)
(5)

CM04, CM05, CM06, CM07 : Bits in CM0 register
CM10, CM11, CM16, CM17 : Bits in CM1 register
CM20, CM21 : Bits in CM2 register
PLC07 : Bit in PLC0 register

Divided

by 8

by 16

--

--

------

(1)

--

(1)

-­(6)

(7)

(6)
(6)

(7)

(6)

(7)

--: Cannot transit

(NOTE 5)

On-chip Oscillator
Low Power
Dissipation Mode

--

--

--

(NOTE 1)

(11)

(NOTE 8)

(NOTE 5)

(18)

(18)(18)(18)(18)(18)

Stop Mode Wait Mode

(NOTE 1)

(16)
(16)
(16)

(NOTE 1)

(NOTE 1)

(17)
(17)
(17)

--

(NOTE 1)

(16)
(16)

(NOTE 1)

(17)
(17)

--

--: Cannot transit

--

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M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

10.5 System Clock Protection Function

The system clock protection function prohibits the CPU clock from changing clock sources when the main
clock is selected the CPU clock source. This prevents the CPU clock from stopping should the program
crash. This function is available when the main clock is selected as the CPU clock source.
When the PM21 bit in the PM2 register is set to “1” (clock change disabled), the following bits cannot be
written to:

• The CM02 bit, CM05 bit and CM07 bit in the CM0 register

• The CM10 bit and CM11 bit in the CM1 register

• The CM20 bit in the CM2 register

• All bits in the PLC0 register

When using the system clock protection function, set the CM05 bit in the CM0 register to “0” (main clock
oscillation) and CM07 bit to “0” (main clock as BCLK clock source) and follow the procedure below.

(1) Set the PRC1 bit in the PRCR register to “1” (write enable).
(2) Set the PM21 bit in the PM2 register to “1” (protects the clock).
(3) Set the PRC1 bit in the PRCR register to “0” (write disable).

When the PM21 bit is set to “1,” do not execute the WAIT instruction.

10.6 Oscillation Stop and Re-oscillation Detect Function

The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and re­oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation
detection interrupt are generated. Which is to be generated can be selected using the CM27 bit in the CM2
register. The oscillation stop detection function can be enabled and disabled by the CM20 bit in the CM2
register. Table 10.8 lists an specification overview of the oscillation stop and re-oscillation detect function.

Table 10.8 Specification Overview of Oscillation Stop and Re-Oscillation Detect Function

Item Specification
Oscillation Stop Detectable Clock and f(XIN) ≥ 2 MHz
Frequency Bandwidth
Enabling Condition for Oscillation Stop, Set CM20 bit to “1”(enable)
Re-Oscillation Detection Function
Operation at Oscillation Stop, •Reset occurs (when CM27 bit =0)
Re-Oscillation Detection •

Oscillation stop, re-oscillation detection interrupt occurs (when CM27 bit =1)

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M16C/62P Group (M16C/62P, M16C/62PT)

10. Clock Generating Circuit

10.6.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)

Where main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4.
SFR, 5. Reset).
This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected,
the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage (During
main clock stop, do not set the CM20 bit to “1” and the CM27 bit to “0”).

10.6.2

Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation Detect Interrupt)

Where the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop and
re-oscillation detect function enabled), the system is placed in the following state if the main clock comes
to a halt:

• Oscillation stop and re-oscillation detect interrupt request occurs.

• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the clock source

for CPU clock and peripheral functions in place of the main clock.

• CM21 bit = 1 (on-chip oscillator clock for CPU clock source)

• CM22 bit = 1 (main clock stop detected)

• CM23 bit = 1 (main clock stopped)

Where the PLL clock corresponds to the CPU clock source and the CM20 bit is “1,” the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”
(on-chip oscillator clock) inside the interrupt routine.

• Oscillation stop and re-oscillation detect interrupt request occurs.

• CM22 bit = 1 (main clock stop detected)

• CM23 bit = 1 (main clock stopped)

• CM21 bit remains unchanged

Where the CM20 bit is “1,” the system is placed in the following state if the main clock re-oscillates from
the stop condition:

• Oscillation stop and re-oscillation detect interrupt request occurs.

• CM22 bit = 1 (main clock re-oscillation detected)

• CM23 bit = 0 (main clock oscillation)

• CM21 bit remains unchanged

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