
HD74LS221
Dual Monostable Multivibrators
REJ03D0458–0300
Rev.3.00
Jul.15.2005
This multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either of which
can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the
transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free
triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity of
typically 1.2 V. A high immunity to V
fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses may be of any duration
relative to the output pulse. Output rise and fall times are TTL compatible and independent of pulse length.
Typical triggering and clearing sequence are illustrated as a part of the switching characteristics waveforms. Pulse
width stability is achieved through internal compensation and is virtually independent of V
In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free
operation is maintained over the full temperature and V
to 10 µF) and more than one decade of timing resistance (2 kΩ to 100 kΩ).
noise of typically 1.5 V is also provided by internal latching circuitry. Once
CC
and temperature.
CC
range for more than six decades of timing capacitance (10 pF
CC
Throughout these ranges, pulse width is defined by the relationship: t
w (out)
Features
• Ordering Information
Part Name Package Type
HD74LS221P DILP-16 pin
HD74LS221RPEL SOP-16 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DG-A
(FP-16DNV)
= Cext • Rext • 1n 2.
Package
Abbreviation
P —
RP EL (2,500 pcs/reel)
Taping Abbreviation
(Quantity)
Rev.3.00, Jul.15.2005, page 1 of 8

HD74LS221
Absolute Maximum Ratings
Item Symbol Ratings Unit
V
Supply voltage
Input voltage
Power dissipation
Storage temperature
CC
V
IN
P
T
Tstg
7 V
7 V
400 mW
–65 to +150 °C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
V
Supply voltage
Output current
Operating temperature
Rate of rise or fall of
input pulse
Input pulse width
Schmitt input, B 1 — — V/s
Logic Input, A
A or B
Clear
Setup time
External timing resistance R
External timing capacitance C
Duty cycle
RT = 2 kΩ — — 50
= 100 kΩ
R
T
CC
IOH
I
OL
T
opr
dV/dt
t
w (in)
t
w (clear)
t
su
1.4 — 100 kΩ
ext
0 — 1000 µF
ext
4.75 5.00 5.25 V
— — –400 µA
— — 8 mA
–20 25 75 °C
1 — — V/µs
40 — —
40 — —
15 — — ns
— — 90
ns
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
Threshold
voltage
A
B
Output voltage
I
A — — –0.4
B, Clear
I
Short-circuit output
current
Supply current ICC
Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Note: * VCC = 5 V, Ta = 25°C
+
V
— 1.0 2.0 V VCC = 4.75 V
T
–
V
0.8 1.0 — V VCC = 4.75 V
T
+
V
— 1.0 2.0 V VCC = 4.75 V
T
–
0.8 0.9 — V VCC = 4.75 V
V
T
VOH 2.7 — — V VCC = 4.75 V, IOH = –400 µA
V
OL
— — 20 µA VCC = 5.25 V, VI = 2.7 V
IH
I
IL
— — 0.1 mA VCC = 5.25 V, VI = 7 V
I
–20 — –100 mA VCC = 5.25 V
I
OS
— — 0.4 IOL = 4 mA
— — 0.5
— — –0.8
— 4.7 11 Ouiescent
— 19 27
V
mA VCC = 5.25 V, VI = 0.4 V Input current
mA
= 8 mA
I
OL
Triggered
V
= 4.75 V
CC
VCC = 5.25 V
Rev.3.00, Jul.15.2005, page 3 of 8

HD74LS221
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol Inputs Outputs min. typ. max. Unit Condition
A Q — 45 70
B Q — 35 55
A Q — 50 80
B Q — 40 65
ns
ns
70 120 150
20 47 70
ns
600 670 750
6 6.7 7.5 ms
C
= 80 pF,
ext
= 2 kΩ
R
ext
C
= 80 pF,
ext
= 2 kΩ
R
ext
C
= 0 pF,
ext
= 2 kΩ
R
ext
C
= 100 pF,
ext
= 10 kΩ
R
ext
C
= 1 µF,
ext
= 10 kΩ
R
ext
Propagation
delay time
Output pulse
width
t
PLH
t
PHL
t
Clear Q — 35 55 ns
PHL
t
Clear Q — 44 65 ns
PLH
t
A or B Q or Q
w (out)
Caution in use
C
= 15 pF,
L
= 2 kΩ
R
L
In order to prevent any malfunctions due to noise, connect a high frequency performance capacitor between Vcc and
GND, and keep the wiring between the External components and Cext, Rext/Cext pins as short as possible.
Testing Method
Test Circuit
V
CC
Cext
B
+–
Cext
Rext
Rext
/Cext
CLR
Load circuit 1
R
L
Q
C
L
Q
Same as Load Circuit 1.
A Input
Z
out
P.G.
= 50Ω
A
B Input
P.G.
Z
out
= 50Ω
CLR Input
P.G.
out
= 50Ω
Z
Notes: 1. CL includes probe and jig capacitance.
2. All diodes are 1S2074(H).
Rev.3.00, Jul.15.2005, page 4 of 8

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