Renesas ISL78010EVAL1Z User Manual

USER’S MANUAL
FIGURE 1. TOP VIEW OF ISL78010EVAL1Z
FIGURE 2. BOTTOM VIEW OF ISL78010EVAL1Z
ISL78010EVAL1Z
Evaluation Board
The top side and the bottom side of ISL78010EVAL1Z are shown in Figures 1 and 2, respectively. This board consists of power and load connectors for source and load side, external passive components, and the place holders reserved for the following ap plications:
1. Place holder for second stage positive charge pump for high voltage application at V
2. Place holder for additional external compensation.
3. Place holder for snubber circuits to improve EMI performance.
ON
rail.
AN1523
Rev 0.00
January 14, 2010
Reference Documents
• ISL 78010 Data Sheet (FN6501)
Key Features
• 2A current FET
•3V to 5V input
• Up to 20V boost output
• 1% regulation on boost output
•V
LOGIC-VBOOST-VOFF-VON
V
LOGIC-VOFF-VBOOST-VON
• Programmable sequence delay
• Fully fault protected
• Thermal shutdown
• Internal soft-start
• 32 Ld 5x5 TQFP packages
• Pb-free plus anneal available (RoHS compliant)
or sequence control
Recommended Equipment
The following materials are recommended to perform testing:
• 0V to 10V Power Supply with at least 5A source current capability
• Electronic Loads capable of sinking curr ent u p to 5A
• Digital Multimeters (DMMs)
• 100MHz quad-trace oscilloscope
The input voltage range is from 3V to 5V, and the maximum output voltage on main boost rail is 20V.
Quick Setup Guide
1. Set power source to be 5V and with 0.5A current limiting.
2. Apply 5V to the input: J1 (V is input-. Check the power source to make sure that no current limiting occurs.
3. Release the input power source’ s current limiting to 5A.
4. Turn off the input power source. Set the electronic load to constant current load of 100mA, connect the electronic load to the V output+, J8 (PGND) is output-.
5. Turn on the input power source, verify the output voltage is around 12V for V
6. Verify that the ripple voltage (about 1MHz frequency) for the V
7. Verify the v oltage at V 20V.
8. Verify the voltage at V is 2.5V.
9. Verify the voltage at V is -8V.
BST
voltage is around 50mV.
BST
ON
LOGIC
OFF
) is input+, J2 (V
IN+
output: J6 (V
(J6, J8).
BST
rail (between J3 and J7) is
rail (between J4 and J7)
rail (between J5 and J7),
BST
IN-
) is
)
AN1523 Rev 0.00 Page 1 of 8 January 14, 2010
ISL78010EVAL1Z
FIGURE 3. QUICK SET UP TO MEASURE THE V
BST
VOLTAGE
Efficiency
Output Power
In p u t Power
------------------------------------
P
OUT
P
IN
----------------
V
OUTIOUT

V
INIIN

----------------------------------------
===
(EQ. 1)
FIGURE 4. EFFICIENCY MEASUREMENT SET UP
FIGURE 5. OUTPUT RIPPLE/NOISE MEASUREMENT
Quick Start to Measure the Boost Output Voltage
The evaluation board can be evaluated simply . Figure 3 shows the quick configuration to measure the boost rail output voltage. After powering on the input power supply, the oscilloscope probes can be placed at V
BST
pin to check the output voltage, and at LX pin to check the phase node voltage.
Efficiency Measurement
Figure 4 shows the efficiency measurement set up for the ISL78010EVAL1Z Eval Board. The voltage and current meter can be used to measure input/output voltage and current. In order to obtain an accurate measurement and prevent the voltage drop of PCB or wire trace, the voltage meter must be close to the input/output terminals.
Output Ripple/Noise Measurement
The total noise is equal to the sum of the ripple and noise components. Simple steps should be taken to assure that there is minimum pickup noise due to the high frequency events, which can be magnified by the large ground loop formed by the oscilloscope probe ground. This means that even a few inches of ground wire on the oscilloscope probe may result in hundreds of millivolts of noise spikes when improperly routed or terminated. This effect can be overcome by using the short loop measurement method to minimize the measurement loop area for reducing the pickup noise. The short loop measurement method is shown in Figure 5. For ISL78010EVAL1Z evaluation board, the output ripple/noise measurement point is located at
terminal.
the C
9
The efficiency equation is shown in Equation 1:
As shown in Figure 4, the measuring point for the input voltage meter is at the C
terminal, and the measuring
10
point for the output voltage meter is at the C9 terminal.
AN1523 Rev 0.00 Page 2 of 8 January 14, 2010
AN1523 Rev 0.00 Page 3 of 8
January 14, 2010
ISL78010EVAL1Z
ISL78010EVAL1Z Eval Board Application Diagram
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