Renesas ISL73040SEHEV4Z User Manual
USER MANUAL
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ISL73040SEHEV4Z
Evaluation Board
The ISL73040SEHEV4Z evaluation board demonstrates how to build a half bridge power stage with the ISL73040SEH low
side GaN driver and the ISL73024SEH
200V GaN FET. The ISL73040SEH has a 4.5V gate drive voltage (VDRV)
generated using an internal regulator that prevents the gate voltage from exceeding the maximum gate-source rating of the
ISL73024SEH GaN FET. The ISL73024SEH is a 200V GaN FET capable of 7.5A drain current.
Key Features
• Single PWM input to drive a half bridge configuration
• Adjustable dead time control
• Wide openings to support various inductor footprints
• >95% peak efficiency with high switching frequencies
• Enable/disable functions
Specifications
•VDD = 4.5V to 13.2V
•V
= up to 100V (limited by VDS of the GaN FET)
BUS
• PWM input: 40kHz to 1MHz, duty cycle = 2% to 97%
Ordering Information
Mar 24, 2021
UG186
Rev.2.0
Part Number Description
ISL73040SEHEV4Z 100V half bridge power stage evaluation board
Related Literature
For a full list of related documents, visit our website:
• ISL73040SEH
and ISL73024SEH device pages
Figure 1. ISL73040SEHEV4Z Block Diagram
UG186 Rev.2.0 Page 1 of 14
Mar 24, 2021 © 2021 Renesas Electronics
ISL73040SEHEV4Z
Contents
1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 PWM Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Dead Time Control Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Quick Start Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Single Events Effects Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
UG186 Rev.2.0 Page 2 of 14
Mar 24, 2021
ISL73040SEHEV4Z 1. Functional Description
0
20
40
60
80
100
012345
% of Capacitor Voltage
Time Constant (τ)
0
20
40
60
80
100
012345
% of Capacitor Voltage
Time Constant (τ)
R
6
t
don
1.1668
100
12–
10 F
--------------------------------------=
(EQ. 1)
1. Functional Description
The ISL73040SEHEV4Z demonstrates how to use the ISL73040SEH and ISL73024SEH in a half bridge
configuration. The following sections describe how to tune the evaluation board for a given application.
1.1 PWM Input
The input signal frequency is limited to 40kHz to 1MHz with a duty cycle between 2% and 97%, and is fed into J7.
The input is designed to accommodate voltages between 3.3V and 10V to be compatible with readily available
PWM controllers on the market. The input signal is fed into two ISL71610M front ends in series, which can be
simplified into coils with a coil resistance of 128Ω each. R
of the ISL71610M. Assuming the input voltage is 3.3V, R
ISL71610M front end to 8mA (steady state), and C
times. R
(1MΩ) and C56 (100pF) are optional, but provide the ability to isolate the incoming signal from power
22
provides the instantaneous current for quicker rise and fall
55
ground.
1.2 Dead Time Control Adjustment
The dead time control is adjusted based on the RC charge and discharge times of R6/C54 and R5/C22. The
ISL73040SEH has inverting and non-inverting inputs that provide complimentary drive for the upper and lower
GaN FETs. D
lower resistance path during turn-off.
Dead time is controlled by turning off the active GaN FET quickly and delaying the turn-on of the inactive FET.
Select the R and C values so that the charge and discharge times to the logic thresholds of the ISL73040SEH are
equal to the desired dead time. The ideal RC charge and discharge profiles are shown in Figures 2
respectively:
and D4 ensure that the turn-on time is delayed only for the high-side and low-side by providing a
3
and C55 control the current going into the input coils
20
is set to 150Ω, which limits the current into the
20
and 3,
Figure 2. RC Charge Profile Figure 3. RC Discharge Profile
The final capacitor voltage is 4.5V because the V
of the ISL71610M is tied to the VDRV of its respective gate
DD
driver. As the high side GaN FET is driven with an inverted logic signal, the dead time for turning on the high-side
is determined by how long the RC filter takes to discharge from 4.5V down to the V
is 31.1% of 4.5V (V
up to the V
of the ISL73040SEH, which is 37.8% of 4.5V (VIH =1.7V). These percentages yield time constant
IH
= 1.4V). The dead time for turning on the low-side is gated by the RC filter’s charging time
IL
of the ISL73040SEH, which
IL
multiples of 1.1668τ for the high-side dead time, and 0.4721τ for the low-side dead time (where τ is the time
constant). The dead time can be calculated using Equations 1
and 2 by choosing a capacitor value (100pF is used in
this design) and calculating the needed resistance.
where t
UG186 Rev.2.0 Page 3 of 14
Mar 24, 2021
is the high-side dead time, in seconds.
don
ISL73040SEHEV4Z 1. Functional Description
(EQ. 2)
R
5
t
doff
0.4721
100
12–
10 F
---------------------------------------=
where t
For example, a t
R
6
propagation delay mismatches between the high-side and low-side drivers (U
isolators (U
is the low-side dead time, in seconds.
doff
(high side dead time) of 16ns and a t
don
(low side dead time) of 30ns yields R5 = 635Ω and
doff
= 137Ω. Use common resistor values to round R5 = 620Ω and R6 = 140Ω. These calculations do not account for
) and the high-side and low-side
), so the final value on the board may need to be adjusted to achieve the desired results. Figure 15
3/U4
1/U2
on page 13 shows the actual dead times that result from using R5 = 620Ω and R6 = 140Ω.
1.3 Quick Start Guide
The following equipment is needed to evaluate the board:
• Bus power supply: a power supply capable of 100V with 5A current capability
• Bias power supply: a power supply capable of 5V to 12V with 1A current capability
• Function generator capable of producing a square wave up to 1MHz with duty cycle control
• Electronic load capable of 7A
• Digital multimeter to measure V
OUT
1.3.1 Operation Procedure
(1) Connect the bus power supply between VBUS and GND (J3/J4).
(2) Connect the bias power supply between J
(3) Connect the function generator the BNC jack (J
(4) Connect the electronic load to VOUT and GND (J
(5) Connect the digital multimeter between VOUT and GND (J
(6) Set the bias power supply to any voltage between 5V and 12V. In this example it is set to 5V.
(7) Set the bus power supply to 100V.
(8) Set the electronic load anywhere up to 7A. The inductor on the evaluation platform is rated for 10.5A with
a 20°C rise in temperature, so 7A provides enough margin.
(9) Set the function generator to output a square wave with 28% duty cycle at 500kHz.
(10) Set the function generator output voltage levels to V
limited 10V, because of a 25mA coil rating. The input coils of U
(11) Turn on the bias power supply.
(12) Turn on the bus power supply.
(13) Turn on the function generator output.
(14) V
should be roughly 28% of the bus supply voltage (100V in this example).
OUT
(15) Turn on the electronic load.
(16) V
drops below 28V. The duty cycle of the function generator can be modified to return V
OUT
and J2.
1
) on the board.
7
).
5/J6
).
5/J6
= 0.0V and VOH = 3.3V. The PWM voltage is
OL
and U4 are specified at 128Ω (max) each.
3
OUT
to 28V.
UG186 Rev.2.0 Page 4 of 14
Mar 24, 2021
ISL73040SEHEV4Z 2. Single Events Effects Testing
2. Single Events Effects Testing
The ISL73040SEHEV4Z, which uses the ISL71610M isolators and the ISL73040SEH drivers was evaluated for
shoot-through under heavy ions. The following is the test setup:
• VDD = 12V
• VBUS = 28V
• L1 was depopulated
•A 1Ω current-sense resistor was placed in line with the drain of Q1
• A 1MHz, 0V-5V signal was provided to J7
•LET = 86MeV•cm
• Fluence = 1x10
The voltage at the drain of Q1 was monitored on an oscilloscope for events with a trigger window of ±50mV around
the nominal voltage at the drain. A shoot-through event under heavy ions turned on Q1 and Q2, pulling the Q1 drain
significantly below VBUS. A 50mV trigger window across 1Ω represents 50mA of shoot-through current. For the
first test, both isolators (ISL71610M) were simultaneously exposed to heavy ions, no events were captured. For the
second test, both drivers (ISL73040SEH) were simultaneously exposed to heavy ions with no events captures. In
conclusion, there were no shoot-through events recorded for the half-bridge configuration used in the
ISL73040SEHEV4Z evaluation board up to an LET of 86 MeV•cm
2
/mg
7
ions/cm
2
2
/mg.
UG186 Rev.2.0 Page 5 of 14
Mar 24, 2021
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