Renesas ISL71043MEVAL1Z User Manual

User’s Manual

ISL71043MEVAL1Z

Evaluation Board

The ISL71043MEVAL1Z evaluation platform is designed to evaluate the ISL71043M and ISL71040M in a flyback
power supply configuration.

The ISL71043M is a radiation tolerant drop-in replacement for the popular 28C4x and 18C4x PWM controllers
suitable for a wide range of power conversion applications including boost, flyback, and isolated output
configurations. This evaluation board is a flyback power supply. The board features up to 13.2V V
low operating current, 90μA typical start-up current, adjustable operating frequency to 1MHz, and high peak
current drive capability with 50ns rise and fall times.

The ISL71040M is a low-side driver designed to drive enhancement mode Gallium Nitride (GaN) FETs in isolated
topologies and boost type configurations. The ISL71040M operates with a supply voltage from 4.5V to 13.2V and
has inverting (INB) and non-inverting (IN) inputs to satisfy requirements for both inverting and non-inverting gate
drives with a single device. The ISL71040M has a 4.5V gate drive voltage (V
internal regulator, which prevents the gate voltage from exceeding the maximum gate-source rating of
enhancement mode GaN FETs. The gate drive voltage also features an Undervoltage Lockout (UVLO) protection
that ignores the inputs (IN and INB) and keeps OUTL turned on, ensuring that the GaN FET is in an OFF state
when V
the V
outputs of the ISL71040M offer the flexibility to independently adjust the turn-on and turn-off speeds by adding
additional impedance to the turn-on and turn-off paths.

is below the UVLO threshold. The ISL71040M inputs can withstand voltages up to 14.7V regardless of

DRV

voltage, which allows the ISL71040M inputs to be connected directly to most PWM controllers. The split

DD

) that is generated using an

DRV

operation,

DD

Key Features

• 24W flyback power supply

• Option to power the ISL71043M and ISL71040M using the auxiliary winding on a flyback transformer or
separate power supply

•V

• Tight line/load regulation: 0.003%/0.16%

within 1% of 12V with 0A to 2A load step

OUT

Specifications

•Wide VIN range single: 22V to 36V

•Wide V

•I

OUT

range single: 7.5V to 13.2V

DD

range: 0A to 2A

Ordering Information

Part Number Description

ISL71043MEVAL1Z Flyback Power Supply

Related Literature

For a full list of related documents, visit our website:

• ISL71043M and ISL71040M device pages

R12UZ0044EU0200 Rev.2.0 Page 1 of 14
Feb.9.21 Copyright © 2019

ISL71043MEVAL1Z 1. Functional Description

1. Functional Description

The ISL71043MEVAL1Z is a flyback power supply that takes an input voltage between 22V and 36V and outputs
12V with a max load capability of 2A.

1.1 Operating Range

The ISL71043M offers a wide operating supply range of 8V to 13.2V. The ISL71040M accepts a VDD range of

4.5V to 13.2V. The gate drive voltage for the ISL70023SEH is generated by the ISL71040M from an internal linear

regulator to keep the gate-to-source voltage below the absolute maximum VGS level of 6V.

1.2 Quick Start Guide

1. Choose how VDD for the ISL71043M and ISL71040M is provided:

a. Short Pins 1-2 on JP

b. Short Pins 2-3 on JP

2. Apply 28V to the VIN input (BA

to provide 12V VDD from an external power supply using BA3 and BA4.

1

to power the ICs from the auxiliary winding from the transformer.

1

and BA2).

1

3. Power up VIN and VDD.

4. The 12V regulated output is on BA

5. Monitor the VGS voltage using TP

6. Monitor the VDS voltage using TP

and BA6.

5

and TP3 with a short-to-ground loop connection on a scope probe.

2

and TP3 with a short-to-ground loop connection on a scope probe.

13

7. Use SP2 to monitor the current on the primary side.

1.3 Undervoltage Lockout (UVLO)

The ISL71043M UVLO follows a fairly standard implementation where the it does not allow any operation until a
valid VDD is cleared. The rising UVLO edge on the ISL71043M is 9V (maximum), while the falling edge is assured
to trigger by 8V (minimum).

The ISL71040M UVLO monitors the gate drive voltage as opposed to V
level, the output is held low and the inputs are ignored, which is done due to GaN’s low turn-on threshold
(compared to MOSFETs). When VDRV < ~1V, an internal 500Ω resistor connected between OUTL and ground
helps keep the gate voltage close to ground. When ~1.2V < VDRV < UV, OUTL is actively driven low while
ignoring the logic inputs, and OUTH is in a high impedance state. The low state has the same current sinking
capacity as during normal operation ensuring that the driven FETs are held off. The FETs are held off even if there
is a switching voltage on the drains that can inject charge into the gates from the Miller capacitance.

. Until VDRV passes an acceptable

DD

When VDRV > UVLO, the ISL71040M waits for the next rising edge on INB or falling edge on IN before the output
starts to follow the inputs. This additional check can prevent runt pulses from being generated because the first
pulse is always a controlled pulse from the PWM regulator. When the UCVLO is cleared, the outputs now respond
to the logic inputs. In the non-inverting operation (PWM signal applied to IN pin), the output is in-phase with the
input. In the inverting operation (PWM signal applied to INB pin), the output is out-phase with the input.

For the negative transition of VDRV through the UV lockout voltage, when VDRV < ~3.7V

the OUTL is active

DC

low and OUTH is high impedance regardless of the input logic states.

1.4 VDD Power Supply

The ISL71043MEVAL1Z provides the ability to choose how to power the VDD of the ISL71043M and ISL71040M.
Using JP
use an external power supply.

R12UZ0044EU0200 Rev.2.0 Page 2 of 14
Feb.9.21

, you can choose to short Pins 2-3 to use the auxiliary winding of the transformer or short Pins 1-2 to

1

ISL71043MEVAL1Z 2. General PCB Layout Guidelines

2. General PCB Layout Guidelines

The AC performance of the ISL71040M depends significantly on the design of the Printed Circuit Board (PCB).
The following layout design guidelines are recommended to achieve optimum performance:

• Place the driver as close as possible to the driven power FET.

• Understand where the switching power currents flow. The high amplitude di/dt currents of the driven power FET
induce significant voltage transients on the associated traces.

• Keep power loops as short as possible by paralleling the source and return traces.

• Use planes where practical; they are usually more effective than parallel traces.

• Avoid paralleling high amplitude di/dt traces with low level signal lines. High di/dt induces currents and
consequently, noise voltages in the low level signal lines.

• When practical, minimize impedances in low level signal circuits. The noise, magnetically induced on a 10kΩ
resistor, is 10 times larger than the noise on a 1kΩ resistor.

• Be aware of magnetic fields emanating from transformers and inductors. Gaps in the magnetic cores of these
structures are especially bad for emitting flux.

• If you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to
minimize coupling.

• The use of low inductance components such as chip resistors and chip capacitors is highly recommended

• Use decoupling capacitors to reduce the influence of parasitic inductance in the VDRV, VDD, and GND leads.
To be effective, these capacitors must also have the shortest possible conduction paths. If vias are used,
connect several paralleled vias to reduce the inductance of the vias.

• It may be necessary to add resistance to dampen resonating parasitic circuits, especially on OUTH. If an
external gate resistor is unacceptable, then the layout must be improved to minimize lead inductance.

• Keep high dv/dt nodes away from low level circuits. Guard banding can be used to shunt away dv/dt injected
currents from sensitive circuits, which is especially true for control circuits that source the input signals to the
ISL71040M.

• Avoid having a signal ground plane under a high amplitude dv/dt circuit, which injects di/dt currents into the
signal ground paths.

• Calculate power dissipation and voltage drop for the power traces. Many PCB/CAD programs have built in tools
for trace resistance calculation.

• Large power components (such as power FETs, electrolytic caps, and power resistors) have internal parasitic
inductance that cannot be eliminated., which must be accounted for in the PCB layout and circuit design.

• If you simulate your circuits, consider including parasitic components, especially parasitic inductance.

• The GaN FETs have a separate substrate connection that is internally tied to the source pin. Source and
substrate should be at the same potential. Limit the inductance in the OUTH/L to Gate trace by keeping it as
short and thick as possible.

R12UZ0044EU0200 Rev.2.0 Page 3 of 14
Feb.9.21

R12UZ0044EU0200 Rev.2.0 Page 4 of 14

29

272523

21191715131197531

30282624

22

201816

1412108642

ISL73023SEH

Source

Drain

Double U p On Several Layers as per Current Needs

Double Up On Several Layers as per Current Needs

ISL71040M

VDRV

VDD

OUTH

OUTL

VSSP

IN

INB

VSS

Feb.9.21

ISL71043MEVAL1Z 2. General PCB Layout Guidelines

Figure 1. PCB Layout Recommendation

ISL71043MEVAL1Z 2. General PCB Layout Guidelines

2.1 ISL71043MEVAL1Z Evaluation Board

Figure 2. ISL71043MEVAL1Z Evaluation Board, Top View

Figure 3. ISL71043MEVAL1Z Evaluation Board, Bottom View

R12UZ0044EU0200 Rev.2.0 Page 5 of 14
Feb.9.21