Renesas ISL70005SEHEV2Z User Manual
User’s Manual
ISL70005SEHEV2Z
High Reliability
User’s Manual: Evaluation Board
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
Renesas Electronics Corporation
www.renesas.com
Rev.1.01
Jan.6.20
User’s Manual
ISL70005SEHEV2Z
Evaluation Board
The ISL70005SEHEV2Z evaluation board is designed to evaluate the performance of the ISL70005SEH 3A buck
regulator and 1A source/sink LDO. The evaluation board is optimized for 3V to 5.5V input operation to generate a
3A, 1.8V to 3.3V buck output and a 1A source/sink, 1.2V LDO output. Input and output connections, toggle
switches, and jumper settings on the board provide the customer an easy-to-use evaluation platform for dual rail
supplies for point-of-load, FPGA, and DDR memory power.
Key Features
• Dual point-of-load regulator: 3A buck and 1A source/sink LDO
• Fully independent enable, soft-start, and power-good indicator
• 3V to 5.5V operating voltage
• On-board transient load current generators
Specifications
• Analog and buck regulator input voltage range (PVIN): 3V to 5.5V
• Maximum buck output current: 3A
• Buck preset switching frequency: 1MHz
• LDO input voltage (L_VIN) range: 1.0V to PVIN
• Maximum LDO output (L_OUT) current: 1A sourcing or 1A sinking
• Board dimension: 13.75cm width x 8cm height
• Board layers: Four
• Board PCB copper weight: 2oz.
• Board revision: B
Ordering Information
Part Number Description
ISL70005SEHEV2Z ISL70005SEH evaluation board
Related Literature
For a full list of related documents, visit our website:
• ISL70005SEH
device page
R12UZ0064EU0101 Rev.1.01 Page 2 of 23
Jan.6.20
ISL70005SEHEV2Z
B_OUT = 1.8V
26
21
25
22
24
1
2
3
4
5
B_S S
B_FB
B_CO MP
B_RT
B_V CC
B_VIN 2
B_LX2
B_LX1
B_PGND2
B_PGND1
23
28
27
6
7
8
B_SYNC
B_GND1
B_GND2
B_PG
L_PG
TEST
209VREF
B_VIN 1
19
18
10
11
B_E N
L_EN
L_VIN
L_O UT
L_P GND
1712 L_VCC
1613 L_SS L_G ND
L_E A-
1514 L_EA+
+
L_O UT = 1.2V
PVIN = 3V to 5.5V
LVIN = 1V to PVIN
PVIN
ISL70005SEH
Toggle Switch
Toggle Switch
PVIN = 3V to 5.5V
PVIN = 3V to 5.5V
PVIN = 3V to 5.5V
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Figure 1. ISL70005SEHEV2Z Block Diagram
ISL70005SEHEV2Z 1. Functional Description
1. Functional Description
1.1 Operating Range
The ISL70005SEHEV2Z has two input supply rails. One for the analog supply and buck power stage input (PVIN)
and the other for the LDO input (L_VIN). The PVIN accepts an input voltage range of 3V to 5.5V while the L_VIN
accepts an input voltage of 1.0V up to PVIN.
The buck regulator output (B_OUT) is capable of sourcing up to 3A. The buck output voltage is board jumper
selectable at 1.8V, 2.5V, 3.3V, or 4.0V. The buck regulator is preset with 1MHz switching frequency with a 2.2µH
output inductor and 150µF output capacitor with the option of being synchronized to an external clock. The LDO
regulator output (L_OUT) is capable of sourcing or sinking up to 1A. The LDO reference input (L_EA+) to the error
amplifier is board jumper selectable to either the 0.6V VREF pin voltage on the ISL70005SEH or ½ the buck
output voltage for DDR VTT rail applications. The LDO output voltage is board jumper selectable to 1.2V or set to
equal the L_EA+ reference voltage.
On-board transient load generators are available for both the buck and LDO for evaluation purposes.
1.2 Quick Start Guides
1.2.1 Dual Independent Buck and LDO Output
1. See Table 1 to set up the jumpers properly to adjust the buck output voltage and configure the LDO for
independent output.
2. Ensure jumper on JP1, JP4, and JP10 are removed. Populate jumper JP6 in the 1-2 position.
3. Apply voltage (3V to 5.5V) to PVIN banana connectors BA1 and BA2.
4. Apply voltage (1.5V to PVIN) to L_VIN banana connectors BA5 and BA7.
5. If the buck enable switch SW1 is on (up position), the buck is enabled and switching at 1MHz. A voltage defined
by the jumper settings of JP2 and JP3 is present on B_OUT at BA3. If SW1 is off (down position), the buck is
disabled and B_OUT = 0V.
6. If the LDO enable switch SW2 is on (up position), the LDO is enabled and a voltage of 1.2V is present on
L_OUT at BA6. If SW2 is off (down position), the LDO is disabled and L_OUT = 0V.
Table 1. Jumper Settings for ISL70005SEHEV2Z
Application Configuration
Independent Buck
Jumper Function Description
JP1 Connects B_EN
and L_EN Together
JP2 Connects R8 to
B_FB
JP3 Connects R7 to
B_FB
JP4 Shorts resistor R21 Populate for LDO unity gain, setting L_OUT = L_EA+. Remove jumper Populate jumper
JP5 External signal
input to SW3
JP6 Connects L_EA+ to
VREF or buck
output
Populate for single switch control of L_EN and B_EN. Remove jumper Populate jumper
Populate for buck output voltage 3.3V. Ensure JP3 is
removed. If no jumper present on JP2 and JP3, buck output
voltage is 1.8V. If JP2 and JP3 both have a jumper, buck
output voltage is programmed to 4V.
Populate for buck output voltage 2.5V. Ensure JP2 is
removed. If no jumper present on JP2 and JP3, buck output
voltage is 1.8V. If JP2 and JP3 both have a jumper, buck
output voltage is programmed to 4V.
Do not populate with jumper. This is a 2-pin header for
connecting an external signal to drive the HI input of HIP2100
when SW3 is in the 2-3 position.
Populate in the 1-2 position for connecting L_EA+ to VREF
pin. Populate in the 2-3 position for connecting to buck output
voltage divided down by the ratio of R15 and R14.
and LDO Regulator
Jumper in 1-2
position
Buck and LDO for
DDR Power
Jumper in 2-3 position
R12UZ0064EU0101 Rev.1.01 Page 4 of 23
Jan.6.20
ISL70005SEHEV2Z 1. Functional Description
Table 1. Jumper Settings for ISL70005SEHEV2Z (Continued)
Application Configuration
Jumper Function Description
JP9 Connects L_OUT
to transient load
generator
JP10 Connects buck
V
to resistor
OUT
divider
J1 Connects R18 to
BNC1
J2 Connects R19 to
BNC1
J3 L_OUT voltage
sensing
J4 Buck B_LXx
voltage sensing
J5 PVIN voltage
sensing
J6 L_VIN voltage
sensing
J7 B_OUT voltage
sensing
Populate for connecting to on board LDO transient load
generator.
Populate for connecting buck V
resistor divider network.
Populate for enabling the sinking transient load current
generator on LDO.
Populate for enabling the sourcing transient load current
generator on LDO.
Do not populate with jumper. This is a 2-pin header for
sensing LDO output voltage.
Do not populate with jumper. This is a 2-pin header for
sensing buck regulator switching node.
Do not populate with jumper. This is a 2-pin header for
sensing PVIN voltage.
Do not populate with jumper. This is a 2-pin header for
sensing LDO input voltage.
Do not populate with jumper. This is a 2-pin header for
sensing buck output voltage.
OUT
to the R14 and R15
Independent Buck
and LDO Regulator
Remove jumper Populate jumper
Buck and LDO for
DDR Power
1.2.2 Buck with LDO in DDR Tracking Mode
1. See Table 1 to set up the jumpers properly to adjust the buck output voltage and configure the LDO for tracking
buck output.
2. Ensure jumper on JP1, JP4, and JP10 are populated. Ensure either SW1 or SW2 is off (down position).
Populate jumper JP6 in the 2-3 position.
3. Place a banana cable from BA3 to BA5 to connect B_OUT to L_VIN.
4. Apply voltage (3V to 5.5V) to PVIN banana connectors BA1 and BA2.
5. Because JP1 is populated, connecting B_EN and L_EN together, either SW1 or SW2 toggle switch enables (up
position) and disables (down position) both the buck and LDO together.
6. The LDO L_OUT (VTT rail) is one-half of the buck output voltage (VDDQ rail) determined by the jumper settings
on JP2 and JP3.
7. IMPORTANT: With the buck output powering the LDO input, care must be taken on the output current loading
of the buck regulator. When the LDO is sourcing current, it is supplied by the buck regulator and the buck output
B_OUT 3A limit to external loading is decreased by the LDO load. For example, if LDO is sourcing 1A, the buck
can only provide an additional 2A to the external load.
1.3 Changing Output Voltage on Buck
Jumpers JP2 and JP3 are made available to easily configure the buck output voltage quickly. With no jumpers on
JP2 and JP3, the output voltage is 1.8V. With JP3 only populated, it is 2.5V. With JP2 only populated, it is 3.3V. If
JP2 and JP3 are both populated, it is 4V. If a different output voltage is needed, you must change the R7, R8, or
R43 values. Renesas recommends not changing R10 to preserve the characteristics of the Type III compensation
network.
R12UZ0064EU0101 Rev.1.01 Page 5 of 23
Jan.6.20
ISL70005SEHEV2Z 1. Functional Description
100
150
200
250
300
350
400
450
200
300
400
500
600
700
800
100
1000
50
500
Switching Frequency (MHz)
RT Resistor (kΩ)
Table 2. Buck V
V
(V) JP2 Jumper JP3 Jumper
OUT
1.8 Off Off
2.5 Off On
3.3 On Off
4V On On
Jumper Settings
OUT
Note: The buck regulator has minimum on and off times on the B_LXx pins, combined with the switching
frequency, can hit duty cycle limitations for producing the desired output voltage.
1.4 Changing Buck Switching Frequency
The ISL70005SEHEV2Z is configured for 1MHz switching by using a R4 = 45.3kΩ resistor on B_RT pin to
B_GND. The evaluation board includes a 2.2µH inductor and 150µF tantalum capacitor for the LC output filter. If
you need to select a different switching frequency, see Figure 2
set the switching frequency. The ISL70005SEHEV2Z includes a dual footprint for the inductor to allow for a higher
inductance value with similar saturation current characteristics for the lower switching frequencies.
for selecting the appropriate R4 value on B_RT to
Figure 2. Buck fSW vs RT Resistor on B_RT Pin
1.5 Using External Clock for Buck Switching Frequency
If you need to synchronize the buck switching frequency to an external clock, a test point TP1 is made available
for connection. See the ISL70005SEH
datasheet for more information about external synchronization.
1.6 Changing Buck Output Inductor
The ISL70005SEHEV2Z is populated with a 2.2µH inductor on the L1A footprint targeted for 1MHz switching
frequency. The inductor used on the ISL70005SEHEV2Z is a Coilcraft XFL4020-222ME. If you need to use a
lower switching frequency, a larger inductance must be used to maintain a similar ripple current. The L1B footprint
(inductor not populated) is physically larger to accommodate a larger inductance value with similar saturation
current ratings. For example, with f
= 100kHz the L1B footprint is sized to accommodate a Coilcraft XAL6060-
SW
153ME 15µH inductor.
1.7 Using the Buck Regulator Transient Load Generator
An on-board load transient generator is made available to the buck regulator output. This circuit is shown in
Figure 7
N-MOSFET driver. The HIP2100 requires 10V bias applied between TP9 (positive) and TP5 (GND) for proper
operation. The load current is set by a resistance R
voltage B_OUT. Six 2512 sized resistor SMD pads (R32-R34; R40-R42) are made available for you to connect the
desired resistance.
and comprises of an open-drain active NMOS FET load switch driven by a Renesas HIP2100
inserted between the NMOS drain and buck output
LOAD
R12UZ0064EU0101 Rev.1.01 Page 6 of 23
Jan.6.20
ISL70005SEHEV2Z 1. Functional Description
To control the load transient timing with an external signal, put switch SW3 in the down position (2-3). Connect the
external pulse generator to the JP5 2-pin header. The HIP2100 uses TTL inputs and requires 0V-10V signal
levels. Logic high drives the load on and logic low turns off the load.
The HIP2100 can be configured in an a-stable oscillation state where the load current is periodically pulsed, with
the transient duration set by RC timing components. To set the HIP2100 in a-stable state, ensure switch SW3 is in
the up position (1-2). In the first state, assume driver output HO = 0V, which turns MOSFET Q2 off. This allows
R28+R29 to charge up C34 with an RC time constant τ = (R28+R29) * C34. When the voltage across C34 (which
is connected to HI) reaches the logic high threshold of HI, HO goes into the second state and drives to a voltage
HO = VDD-0.7V. HO drives the Q3 MOSFET gate with turn-on (R30) and turn-off (R31) gate-limiting resistors.
When HO is high, Q3 is on and the buck output is loaded by the resistance across B_OUT and Q3 drain, with the
load current I
LOAD
=B_OUT/R
. At the same time when HO is high, Q2 is on discharging C34 through R29
LOAD
with RC time constant τ = R29 * C34. When the voltage across C34 reaches the logic low threshold of HI, HO = 0,
going back to its first state. Therefore, the transient load current interval is set by:
• Load Active: τ = R29*C34 to discharge C34/HI from V
• Load Inactive: τ = (R28+R29) * C34 to charge C34/HI from V
• The HIP2100 typical input thresholds are V
= 4.86V and VIL= 4.46V. The a-stable operation operates the
IH
to VIL of HIP2100.
IH
to VIH of HIP2100.
IL
HIP2100 between the hysteresis window of the HI input pin.
• The load active time with R29 = 1kΩ and C34 = 10µF is approximately 800µs.
• The load inactive time with R28 = 48.7kΩ, R29 = 1kΩ and C34 = 10µF is approximately 40ms.
Figure 3. A-Stable Transient Load Current Timing Control
1.8 Changing Output Voltage on LDO
The LDO output voltage is set by the equation: L_OUT = L_EA+ * (R21/R22 + 1)
There are three variables to control LDO output voltage. The L_EA+ voltage can be connected to the
ISL70005SEH VREF = 0.6V by setting the jumper in the 1-2 position of JP6 or to one-half of the buck output
voltage by setting the jumper in the 2-3 position. Additionally, you can put in an external reference by not having a
jumper on JP6 and applying a voltage to pin 2 of JP6 and GND. The ISL70005SEHEV2Z is preset with a
feedback gain of 2 with R21 = R22 = 1kΩ. You can populate jumper JP4 to short out R21 for unity gain feedback
to set L_OUT = L_EA+. You can also change the R21 and R22 resistor values for the desired feedback gain.
R12UZ0064EU0101 Rev.1.01 Page 7 of 23
Jan.6.20
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