USER’S MANUAL
ISL6263AEVAL1Z, ISL6263BEVAL1Z
Evaluation Boards
The ISL6263AEVAL1Z and ISL6263BEVAL1Z evaluation
boards demonstrate the performance of the ISL6263A and
ISL6263B respectively. The ISL6263A and ISL6263B are
single-phase synchronous buck PWM controllers, which
feature Intersil's Robust Ripple Regulator (R
The evaluation board design criteria is located in Table 1. An
on-board dynamic-load generator is included for evaluating
the transient-load response. The dynamic-load applies a
2.5ms pulse of 200m across V
and GND every 30ms.
OUT
What’s Inside
Contents of this document include:
• Recommended Test Equipment
• Interface Connections
• Switch Descriptions
• Jumper Descriptions
• Test Point Descriptions
• Schematic
• Bill of Materials
• Silkscreen Plots
• Board Layout Plots
TABLE 1. EVALUATION BOARD DESIGN CRITERIA
PARAMETER VALUE UNITS
VIN 5 to 25 V
VOUT 0.41200 to 1.28750 V
DROOP 8 m
FULL-LOAD 12 A
PWM FREQUENCY 300 kHz
OCP ~15.5 A
Recommended Equipment
• (QTY 1) Adjustable 25V, 5A Power Supply
• (QTY 1) Fixed 12V, 100mA Power Supply
• (QTY 1) Fixed 5V, 100mA Power Supply
• (QTY 1) Adjustable 20A Constant Current Electronic Load
• (QTY 1) Digital Multi-Meter
• (QTY 1) Four-Channel Oscilloscope
3
) technology.
DC
DC
DC
DC
AN1486
Rev 0.00
August 11, 2009
Interface Connections
• VIN: Input voltage to the power stage of the converter
- J6: VIN positive power input
- P37: VIN positive voltage sense
- J5: VIN return power input
- P38: VIN return voltage sense
• VOUT: Regulated output voltage from the converter
- J14: VOUT positive power output
- P5: VOUT positive voltage sense
- J13: VOUT return power output
- P9: VOUT return voltage sense
• 5V: +5V input voltage for VCC, PVCC, PGOOD-LED and
pull-up voltage rail
- J1: 5V positive input
- J2: 5V return input
• 3.3V: +3.3V input voltage for auxiliary circuits
- J3: 3.3V positive input
- J4: 3.3V return input
• +12V: +12V input voltage for the dynamic-load generator
- J11: 12V positive input
- J12: 12V return input
Jumper Descriptions
•J7 (SRIP) Selects the logic state of the AF_EN pin
- Install shunt jumper across pins 1 and 2 for HIGH
- Install shunt jumper across pins 2 and 3 for LOW
(default)
PGOOD circuit 5V input
•J9
- Shunt jumper installed during normal operation (default)
- Shunt jumper can be removed during efficiency tests
•J10 Selects the logic state of the FDE pin
- Install shunt jumper across pins 1 and 2 for HIGH
- Install shunt jumper across pins 2 and 3 for LOW
(default)
•J16 VDD input current measurement port
- Shunt jumper installed during normal operation (default)
- Shunt jumper replaced by DMM to measure VDD bias
current
•J17 VDD and PVCC input current measurement port
- Shunt jumper installed during normal operation (default)
- Shunt jumper replaced by DMM to measure VDD bias
current and PVCC bias current
AN1486 Rev 0.00 Page 1 of 12
August 11, 2009
•J18 PGOOD and pull-up supply selection
- Install shunt jumper across pins 1 and 2 for 5V (default)
- Install shunt jumper across pins 2 and 3 for 3.3V (3.3V
power supply should be connected to J3 and J4)
ISL6263AEVAL1Z, ISL6263BEVAL1Z
Switch Descriptions
•S1 VIDs inputs (default <00000>)
VR_ON (enable)
•S4
-OFF Converter is not enabled (default)
Converter is enabled
-ON
Transient load generator
•S5
Transient load is not enabled (default)
-OFF
Transient load is enabled
-ON
Test Point Descriptions
•PMON
- IMON test point for ISL6263A
PMON test point for ISL6263B
-
•P1 (SRIP)
•P3
•P4
•P5
•P6
•P7
•P8
•P9
•P11
•P12
•P13
•P14
•P16
•P17
•P20
•P21
• P22 (VCCP)
•P26
•P29
• P30
•P32
AF_EN
DROOP
COMP
VOUT positive voltage sense
PGOOD
OCSET
VW
VOUT return voltage sense
VSEN
FB
VSS
SOFT
FDE
VDIFF after R
network analyzer port
30
VR_ON
VDIFF
VO
VSS
VIN
VSUM
VDD
• VIDs Test Points:
TABLE 2. VID TEST POINT DESCRIPTIONS
TEST POINT (SILKSCREEN) FUNCTION DESCRIPTION
P25 VID4
P27 VID3
P28 VID2
P31 VID1
P33 VID0
•J20
PHASE (for oscilloscope probe)
VOUT positive voltage sense to VOUT return
•J22
voltage sense (for oscilloscope probe)
•J23
Transient load (for oscilloscope probe)
Resistor Current Sense Configuration
The evaluation board is pre-configured with inductor DCR
current sense. It also provides the option of resistor current
sense for more precise overcurrent protection and current
monitor. Follow the following procedure to configure the
resistor current sense:
Step 1: Replace R
Step 2: Remove R
Step 3: Place R
Step 4: Follow the datasheet to configure other resistor
current sense and overcurrent protection
components.
with the current sense shunt resistor
60
and R
50
and R54 with 0resistors
52
53
Dynamic Load Generator
The evaluation board provides an on-board dynamic load
generator for evaluating the transient-load response, which
is controlled by switch S4. The dynamic load generator
applies a 2.5ms pulse load across V
transient load slew-rate can be trimmed by adjusting the
resistor R
falling edge. A +12V power supply is needed to power the
dynamic load generator.
for the rising edge, and resistor R73 for the
74
and GND. The
OUT
• P34 (+5V)
•P35
•P36
•P37
•P38
AN1486 Rev 0.00 Page 2 of 12
August 11, 2009
PVCC
UGATE
LGATE
VIN positive voltage sense
VIN return voltage sense
AN1486 Rev 0.00 Page 3 of 12
August 11, 2009
ISL6263AEVAL1Z, ISL6263BEVAL1Z
ISL6263AHRZ
(ISL6263BHRZ)
(ISL6263BHRZ)
OFF
ON
+12V
OPEN
OFF
ON
IMON
PGND
AF_EN
PMON
(IMON)
R43
AF_EN
7.5K
R21
R29
3.57K
OPEN
C16
R7
R20
10K
0
PHASE
BAT54S
VOUT
C7
10K
VID4
P25
J20
D3
P13
0.018UF
R38
10K
R37
10K
R36
A
J16
0.01UF
C29
C82
C9
P7
0.1UF
VIN
10K
OPEN
P35
0.22UF
IRF7832
R35
0
R30
200K
P36
1
10UF
10UF
3.3V
5V
R8
Q4
R49
Q1
D2
C10
R52 R53
330UF
0
OPEN
OPEN
C6
R54
R50
4.53K
R27
0
0.88UH
L1
R60
10UF
C52
C46
C4
C5B
1UF
J12
S5
J22
10UF
180PF
J4
SD05H0SK
P12
R22
J10
0
C15
0.2
OPEN
1000PF
1000PF
C18
10K
OPEN
R26
C11
C70
10UF
C17
6.98K
1UF
S1
510R2510
P26
100
R47
1000PF
OPEN
U5
R71
C31
J9
J1
J2
J17
R39
R46
Q5
C28
R5
R14
J6
R25
P4
Q2
C13
R3
C21
C14
J23
R73
Q14
R6
P22
J7
R13
C30
D1
OPEN
10UF
49.9K
10K
10K
10K
1000PF
10
499
2N7002
249
R72
0.1UF
C83
P37
P38
P9
J5
P5
HIP2100
C81
10UF
C80
1UF
HUF76129D3S
C60
C32
R32
C54
P30
P3
R12
20
R9
R74
C5
68PF
C27
10K
10K
IRF7821
P21
P17
R10
0
C20
OPEN
249
330PF
1UF
C26
Q3
R18
J3
J14
10UF
R24
R11
2N7002
J11
J13
10UF
C2
OPEN
10UF
OPEN
0
330UF
C89
20
OPEN
P8
C22
R23
560PF
4.99K
R40
C3
OPEN
R16
2.21K
R19
C12
22PF
C8
P14
P11
S4
P33
P31
P28
VID2
VID0
VID1
VID3
P27
IRF7832
R48
150K
C1
P32
IRF7821
1K
200K
P34
J18
10
1
PGOOD
P1
P20
VR_ON
P6
FDE
P16
R1
R17
VOUT
C19
0.082UF
R4
12.4K
1K
Q15
P29
U1
C35
0.1UF
C36
1
ISL6263AHRZ
07/07/2009
OPEN
R15
PMON
C66
10UF
C65
10UF
0.068UF
68UF
68UF
TITLE:
ENGINEER:
DRAWN BY:
SHEET:
DATE:
REV:
OF
765432
1
E
D
C
B
A
F
8
1
2
RED
GRN
1
2
1X3
1
2
3
5
ONONONONON
1
324
1X3
1
2
3
1X3
1
2
3
HI
LO
HS
HO
LI
VSS
VDD
HB
EP
RBIAS
SOFT
OCSET
VW
COMP
FB
VDIFF
VSEN
RTN
DROOP
DFBVOVSUM
VIN
VSS
VDD
BOOT
UGATE
PHASE
PGND
LGATE
PVCC
VID0
VID1
VID3
VID2
VID4
I2UA
SRIP
VR_ON
PGOOD
FDE
1
2
IN
FIGURE 1. ISL6263AEVAL1Z AND ISL6263BEVAL1Z EVALUATION BOARDS SCHEMATIC
ISL6263AEVAL1Z, ISL6263BEVAL1Z
FIGURE 2. ISL6263AEVAL1Z AND ISL6263BEVAL1Z EVALUATION BOARDS PCB TOP SILKSCREEN
AN1486 Rev 0.00 Page 4 of 12
August 11, 2009
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