RENESAS ICL7660SCBA Datasheet

DATASHEET

BOOST

CAP+

GND

CAP-

1

2

3

4

8

7

6

5

V+

OSC

LV

V

OUT

NC

CAP+

GND

CAP-

1

2

3

4

8

7

6

5

V+

OSC

LV

V

OUT

ICL7660S, ICL7660A

Super Voltage Converters

The ICL7660S and ICL7660A Super Voltage Converters are
monolithic CMOS voltage conversion ICs that guarantee
significant performance advantages over other similar
devices. They are direct replacements for the industry
standard ICL7660 offering an extended operating supply
voltage range up to 12V, with lower supply current. A
Frequency Boost pin has been incorporated to enable the
user to achieve lower output impedance despite using smaller
capacitors. All improvements are highlighted in the “Electrical
Specifications” section on page 3. Critical parameters are

guaranteed over the entire commercial and industrial
temperature ranges.

The ICL7660S and ICL7660A perform supply voltage
conversions from positive to negative for an input range of

1.5V to 12V, resulting in complementary output voltages of

-1.5V to -12V. Only two non-critical external capacitors are
needed, for the charge pump and charge reservoir functions.
The ICL7660S and ICL7660A can be connected to function
as a voltage doubler and will generate up to 22.8V with a
12V input. They can also be used as a voltage multipliers or
voltage dividers.

Each chip contains a series DC power supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. The oscillator, when unloaded, oscillates at a
nominal frequency of 10kHz for an input supply voltage of

5.0V. This frequency can be lowered by the addition of an
external capacitor to the “OSC” terminal, or the oscillator
may be over-driven by an external clock.

The “LV” terminal may be tied to GND to bypass the internal
series regulator and improve low voltage (LV) operation. At
medium to high voltages (3.5V to 12V), the LV pin is left
floating to prevent device latchup.

FN3179

Rev 7.00

January 23, 2013

Features

• Guaranteed Lower Max Supply Current for All
Temperature Ranges

• Wide Operating Voltage Range: 1.5V to 12V

• 100% Tested at 3V

• Boost Pin (Pin 1) for Higher Switching Frequency

• Guaranteed Minimum Power Efficiency of 96%

• Improved Minimum Open Circuit Voltage Conversion
Efficiency of 99%

• Improved SCR Latchup Protection

• Simple Conversion of +5V Logic Supply to ±5V Supplies

• Simple Voltage Multiplication V

OUT

= (-)nV

IN

• Easy to Use; Requires Only Two External Non-Critical
Passive Components

• Improved Direct Replacement for Industry Standard
ICL7660 and Other Second Source Devices

• Pb-Free Available (RoHS Compliant)

Applications

• Simple Conversion of +5V to ±5V Supplies

• Voltage Multiplication V

• Negative Supplies for Data Acquisition Systems and
Instrumentation

• RS232 Power Supplies

• Supply Splitter, V

OUT

OUT

= ±V

= ±nV

S

IN

In some applications, an external Schottky diode from V

OUT

to CAP- is needed to guarantee latchup free operation (see
Do’s and Dont’s section on page 8).

Pin Configurations

ICL7660S

(8 LD PDIP, SOIC)

TOP VIEW

FN3179 Rev 7.00 Page 1 of 13
January 23, 2013

ICL7660A

(8 LD PDIP, SOIC)

TOP VIEW

ICL7660S, ICL7660A

Ordering Information

PART NUMBER

(NOTE 3) PART MARKING

ICL7660SCBA (Note 1) 7660 SCBA 0

ICL7660SCBAZ
(Notes 1, 2)

ICL7660SCPA 7660S CPA 0

ICL7660SCPAZ (Note 2) 7660S CPAZ 0

ICL7660SIBA (Note 1) 7660 SIBA -40

ICL7660SIBAZ
(Notes 1, 2)

ICL7660SIPA 7660 SIPA -40

ICL7660SIPAZ
(Note 2)

ICL7660ACBA (Note 1) 7660ACBA 0 to 70 8 Ld SOIC (N) M8.15

ICL7660ACBAZA
(Notes 1, 2)

ICL7660ACPA 7660ACPA 0 to 70 8 Ld PDIP E8.3

ICL7660ACPAZ (Note 2) 7660ACPAZ 0 to 70 8 Ld PDIP (Pb-free; Note 4) E8.3

ICL7660AIBA (Note 1) 7660AIBA -40 to 85 8 Ld SOIC (N) M8.15

ICL7660AIBAZA
(Notes 1, 2)

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ICL7660S
Te ch B ri e f TB363

4. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in reflow solder processing applications.

7660 SCBAZ 0

7660 SIBAZ -40

7660S IPAZ -40

7660ACBAZ 0 to 70 8 Ld SOIC (N) (Pb-free) M8.15

7660AIBAZ -40 to 85 8 Ld SOIC (N) (Pb-free) M8.15

.

TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

to +70 8 Ld SOIC M8.15

to +70 8 Ld SOIC (Pb-free) M8.15

to +70 8 Ld PDIP E8.3

to +70 8 Ld PDIP (Pb-free; Note 4) E8.3

to +85 8 Ld SOIC M8.15

to +85 8 Ld SOIC (Pb-free) M8.15

to +85 8 Ld PDIP E8.3

to +85 8 Ld PDIP (Pb-free; Note 4) E8.3

for details on reel specifications.

, ICL7660A. For more information on MSL, please see

FN3179 Rev 7.00 Page 2 of 13
January 23, 2013

ICL7660S, ICL7660A

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V

LV and OSC Input Voltage (Note 5)

V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V

V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ -5.5V to V+ +0.3V

Current into LV (Note 5)

V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20µA

Output Short Duration

V

 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

SUPPLY

Operating Conditions

Temperature Range

ICL7660SI, ICL7660AI . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

ICL7660SC, ICL7660AC . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product relia bility and
result in failures not covered by warranty.

NOTES:

5. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to “power up” of ICL7660S and ICL7660A.

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

6. 

JA

7. For 

8. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in reflow solder processing applications.

, the “case temp” location is taken at the package top center.

JC

Thermal Resistance (Typical, Notes 6, 7) 

(°C/W) 

JA

JC

(°C/W)

8 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . . 110 59

8 Ld Plastic SOIC. . . . . . . . . . . . . . . . . 160 48

Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

*Pb-free PDIPs can be used for through-hole wave solder

processing only. They are not intended for use in reflow solder
processing applications.

Electrical Specifications ICL7660S and ICL7660A, V+ = 5V, T

on page 7 and Figure 13 “ICL7660A Test Circuit” on page 7), unless otherwise specified.

PARAMETER SYMBOL TEST CONDITIONS

Supply Current (Note 11) I+ R

Supply Voltage Range - High

V+

H

(Note 12)

Supply Voltage Range - Low V+

Output Source Resistance R

Oscillator Frequency (Note 10) f

Power Efficiency P

Voltage Conversion Efficiency V

L

OUTIOUT

OSC

EFF

EFF RL =  99 99.9 - %

OUT

= , +25°C - 80 160 µA

L

0°C < T

-40°C < T

-55°C < T

< +70°C - - 180 µA

A

< +85°C - - 180 µA

A

< +125°C - - 200 µA

A

RL = 10k, LV Open, T

RL = 10k, LV to GND, T

= 20mA - 60 100 

I

= 20mA, 0°C < TA < +70°C - - 120 

OUT

I

= 20mA, -25°C < TA < +85°C - - 120 

OUT

I

= 20mA, -55°C < TA < +125°C - - 150 

OUT

I

= 3mA, V+ = 2V, LV = GND,

OUT

0°C < T

I

-40°C < T

I

-55°C < T

C

C

< +70°C

A

= 3mA, V+ = 2V, LV = GND,

OUT

OUT

OSC

OSC

< +85°C

A

= 3mA, V+ = 2V, LV = GND,

< +125°C

A

= 0, Pin 1 Open or GND 5 10 - kHz

= 0, Pin 1 = V+ - 35 - kHz

RL = 5k 96 98 - %

T

< TA < T

MIN

MAX RL

= +25°C, OSC = Free running (see Figure 12, “ICL7660S Test Circuit”

A

MIN

MIN

< TA < T

< TA < T

MAX

MAX

MIN

(Note 9) TYP

3.0 - 12 V

1.5 - 3.5 V

MAX

(Note 9) UNITS

- - 250 

- - 300 

- - 400 

= 5k 95 97 - -

FN3179 Rev 7.00 Page 3 of 13
January 23, 2013

ICL7660S, ICL7660A

Electrical Specifications ICL7660S and ICL7660A, V+ = 5V, T

on page 7 and Figure 13 “ICL7660A Test Circuit” on page 7), unless otherwise specified. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

Oscillator Impedance Z

OSC

V+ = 2V - 1 - M

= +25°C, OSC = Free running (see Figure 12, “ICL7660S Test Circuit”

A

MIN

(Note 9) TYP

MAX

(Note 9) UNITS

V+ = 5V - 100 - k

ICL7660A, V+ = 3V, T

Supply Current (Note 13) I+ V+ = 3V, R

Output Source Resistance R

Oscillator Frequency (Note 13) f

= 25°C, OSC = Free running, Test Circuit Figure 13, unless otherwise specified

A

= , +25°C - 26 100 A

L

OUT

OSC

0°C < T

-40°C < T

V+ = 3V, I

0°C < T

-40°C < T

V+ = 3V (same as 5V conditions) 5.0 8 - kHz

0°C < T

-40°C < T

< +70°C - - 125 A

A

< +85°C - - 125 A

A

= 10mA - 97 150 

OUT

< +70°C - - 200 

A

< +85°C - - 200 

A

< +70°C 3.0 - - kHz

A

< +85°C 3.0 - - kHz

A

NOTES:

9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.

10. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, on the order of 5pF.

11. The Intersil ICL7660S and ICL7660A can operate without an external diode over the full temperature and voltage range. This device will function
in existing designs that incorporate an external diode with no degradation in overall circuit performance.

12. All significant improvements over the industry standard ICL7660 are highlighted.

13. Derate linearly above 50°C by 5.5mW/°C.

FN3179 Rev 7.00 Page 4 of 13
January 23, 2013

ICL7660S, ICL7660A

VOLTAGE

LEVEL

TRANSLATOR

SUBSTRATE

NETWORK

OSC

LV

V+

CAP+

CAP-

7

OSCILLATOR

AND DIVIDE-BY-

2 COUNTER

6

INTERNAL SUPPLY

REGULATOR

3

LOGIC

Q

3

3

Q

1

V

OUT

3

8

2

Q

2

3

4

5

Q

4

GND

-55 -25 0 25 50 100 125

12

10

8

6

4

2

0

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

SUPPLY VOLTAGE RANGE

(NO DIODE REQUIRED)

250

200

150

100

50

0

02 46 81012

SUPPLY VOLTAGE (V)

OUTPUT SOURCE RESISTANCE (Ω)

TA = +125°C

TA = +25°C

TA = -55°C

350

300

250

200

150

100

50

0

OUTPUT SOURCE RESISTANCE (Ω)

-50 -25 0 25 50 75 100 125

TEMPERATURE (°C)

I

OUT

= 20mA,

V+ = 12V

I

OUT

= 20mA,

V+ = 5V

I

OUT

= 20mA,

V+ = 5V

I

OUT

= 3mA,

V+ = 2V

98

96

94

92

90

88

86

84

82

80

POWER CONVERSION EFFICIENCY (%)

100 1k 10k 50k

OSC FREQUENCY f

OSC

(Hz)

V+ = 5V
T

A

= +25°C

I

OUT

= 1mA

Functional Block Diagram

Typical Performance Curves

See Figure 12, “ICL7660S Test Circuit” on page 7) and Figure 13 “ICL7660A Test Circuit” on page 7

FIGURE 1. OPERATING VOLTAGE AS A

FUNCTION OF TEMPERATURE

FIGURE 3. OUTPUT SOURCE RESISTANCE AS A

FN3179 Rev 7.00 Page 5 of 13
January 23, 2013

FUNCTION OF TEMPERATURE

FIGURE 2. OUTPUT SOURCE RESISTANCE AS A

FUNCTION OF SUPPLY VOLTAGE

FIGURE 4. POWER CONVERSION EFFICIENCY AS A

FUNCTION OF OSCILLATOR FREQUENCY

ICL7660S, ICL7660A

1 10 100 1k

OSCILLATOR FREQUENCY f

OSC

(kHz)

10

9

8

7

6

5

4

3

2

1

0

C

OSC

(pF)

V+ = 5V

T

A

= +25°C

OSCILLATOR FREQUENCY f

OSC

(kHz)

20

18

16

14

12

10

8

-55 -25 0 25 50 75 100 125

TEMPERATURE (°C)

V+ = 10V

V+ = 5V

OUTPUT VOLTAGE (V)

1

0

-1

-2

-3

-4

-5

010203040

LOAD CURRENT (mA)

V+ = 5V

T

A

= +25°C

POWER CONVERSION EFFICIENCY (%)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

LOAD CURRENT (mA)

010203040 5060

V+ = 5V

T

A

= +25°C

SUPPLY CURRENT (mA)

OUTPUT VOLTAGE (V)

2

1

0

-1

-2
012 345 6789

LOAD CURRENT (mA)

TA = +25°C

V+ = 2V

100

90

80

70

60

50

40

30

20

10

0

16

14

12

10

8

6

4

2

0

0 1.5 3.0 4.5 6.0 7.5 9.0

LOAD CURRENT (mA)

V+ = 2V

T

A

= +25°C

POWER CONVERSION

EFFICIENCY (%)

SUPPLY CURRENT (mA) (NOTE 12)

Typical Performance Curves

See Figure 12, “ICL7660S Test Circuit” on page 7) and Figure 13 “ICL7660A Test Circuit” on page 7 (Continued)

FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION

OF EXTERNAL OSCILLATOR CAPACITANCE

FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION

OF OUTPUT CURRENT

FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A

FUNCTION OF TEMPERATURE

FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION

EFFICIENCY AS A FUNCTION OF LOAD
CURRENT

FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT

FN3179 Rev 7.00 Page 6 of 13
January 23, 2013

CURRENT

FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION

EFFICIENCY AS A FUNCTION OF LOAD CURRENT

ICL7660S, ICL7660A

OUTPUT RESISTANCE (Ω)

400

300

200

100

0

100 1k 10k 100k

OSCILLATOR FREQUENCY (Hz)

V+ = 5V
T

A

= +25°C

I = 10mA

C1 = C2 = 10mF

C1 = C2 = 1mF

C1 = C2 = 100mF

1

2

3

4

8

7

6

5

+

-

C

1

10µF

ISV+

(+5V)

I

L

R

L

-V

OUT

C

2

10µF

ICL7660S

V+

+

-

NOTE: For large values of C

OSC

(>1000pF), the values of C1 and C2

should be increased to 100µF.

FIGURE 12. ICL7660S TEST CIRCUIT

1

2

3

4

8

7

6

5

+

-

C

1

10µF

ISV+

(+5V)

I

L

R

L

-V

OUT

C

2

10µF

ICL7660A

C

OSC

+

-

(NOTE)

Typical Performance Curves

See Figure 12, “ICL7660S Test Circuit” on page 7) and Figure 13 “ICL7660A Test Circuit” on page 7 (Continued)

FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY

NOTE:

14. These curves include, in the supply current, that current fed directly into the load R
supply current goes directly to the positive side of the load, and the other half, through the ICL7660S and ICL7660A, goes to the negative side
of the load. Ideally, V

2VIN, IS  2IL, so VIN x IS  V

OUT

OUT

x IL.

from the V+ (see Figure 12). Thus, approximately half the

L

FN3179 Rev 7.00 Page 7 of 13
January 23, 2013

NOTE: For large values of C
should be increased to 100F.

(>1000pF) the values of C1 and C2

OSC

FIGURE 13. ICL7660A TEST CIRCUIT

ICL7660S, ICL7660A

V

OUT

= -V

IN

C

2

V

IN

C

1

S

3

S

4

S

1

S

2

8

2

4

33

5

7

FIGURE 14. IDEALIZED NEGATIVE VOLTAGE CONVERTER

E

1
2

---

C

1V1

2

V

2

2

–=

(EQ. 1)

Detailed Description

The ICL7660S and ICL7660A contain all the necessary
circuitry to complete a negative voltage converter, with the
exception of two external capacitors, which may be
inexpensive 10µF polarized electrolytic types. The mode of
operation of the device may best be understood by
considering Figure 14, which shows an idealized negative
voltage converter. Capacitor C
for the half cycle, when switches S
(Note: Switches S

and S4 are open during this half cycle).

2

During the second half cycle of operation, switches S
S

are closed, with S1 and S3 open, thereby shifting

4

capacitor C

to C2 such that the voltage on C2 is exactly V+,

1

assuming ideal switches and no load on C
and ICL7660A approach this ideal situation more closely
than existing non-mechanical circuits.

is charged to a voltage, V+,

1

and S3 are closed.

1

and

2

. The ICL7660S

2

Theoretical Power Efficiency
Considerations

In theory, a voltage converter can approach 100% efficiency
if certain conditions are met:

1. The drive circuitry consumes minimal power.

2. The output switches have extremely low ON resistance
and virtually no offset.

3. The impedance of the pump and reservoir capacitors are
negligible at the pump frequency.

The ICL7660S and ICL7660A approach these conditions for
negative voltage conversion if large values of C
used. ENERGY IS LOST ONLY IN THE TRANSFER OF

CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined as shown in

Equation 1:

where V

and V2 are the voltages on C1 during the pump

1

and transfer cycles. If the impedances of C
relatively high at the pump frequency (see Figure 14)
compared to the value of R
difference in the voltages, V
desirable to make C

2

, there will be a substantial

L

and V2. Therefore it is not only

1

as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C

in order to achieve maximum efficiency of

1

operation.

and C2 are

1

and C2 are

1

Do’s and Don’ts

1. Do not exceed maximum supply voltages.

In the ICL7660S and ICL7660A, the four switches of
Figure 14 are MOS power switches; S
device; and S

, S3 and S4 are N-Channel devices. The main

2

is a P-Channel

1

difficulty with this approach is that in integrating the switches,
the substrates of S

and S4 must always remain reverse

3

biased with respect to their sources, but not so much as to
degrade their “ON” resistances. In addition, at circuit start­up, and under output short circuit conditions (V

OUT

= V+),
the output voltage must be sensed and the substrate bias
adjusted accordingly. Failure to accomplish this would result
in high power losses and probable device latch-up.

This problem is eliminated in the ICL7660S and ICL7660A by
a logic network that senses the output voltage (V

OUT

)
together with the level translators, and switches the
substrates of S

and S4 to the correct level to maintain

3

necessary reverse bias.

The voltage regulator portion of the ICL7660S and
ICL7660A is an integral part of the anti-latchup circuitry;
however, its inherent voltage drop can degrade operation at
low voltages. Therefore, to improve low voltage operation,
the “LV” pin should be connected to GND, thus disabling the
regulator. For supply voltages greater than 3.5V, the LV
terminal must be left open to ensure latchup-proof operation
and to prevent device damage.

2. Do not connect LV terminal to GND for supply voltage
greater than 3.5V.

3. Do not short circuit the output to V
voltages above 5.5V for extended periods; however,
transient conditions including start-up are okay.

4. When using polarized capacitors, the + terminal of C
be connected to pin 2 of the ICL7660S and ICL7660A, and
the + terminal of C

5. If the voltage supply driving the ICL7660S and ICL7660A
has a large source impedance (25 to 30), then a

2.2µF capacitor from pin 8 to ground may be required to
limit the rate of rise of input voltage to less than 2V/µs.

6. If the input voltage is higher than 5V and it has a rise rate
more than 2V/µs, an external Schottky diode from V
to CAP- is needed to prevent latchup (triggered by
forward biasing Q4’s body diode) by keeping the output
(pin 5) from going more positive than CAP- (pin 4).

7. User should ensure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch-up will
occur under these conditions. To provide additional
protection, a 1N914 or similar diode placed in parallel
with C
these conditions, when the load on V
to pull up V
cathode pin 3).

+

supply for supply

1

must be connected to GND.

2

will prevent the device from latching up under

2

before the IC is active (anode pin 5,

OUT

creates a path

OUT

mus t

OUT

FN3179 Rev 7.00 Page 8 of 13
January 23, 2013

ICL7660S, ICL7660A

1

2

3

4

8

7

6

5

+

-

10µF

10µF

ICL7660S

V

OUT

= -V+

V+

+

-

R

O V

OUT

V+

+

-

15A. 15B.

FIGURE 15. SIMPLE NEGATIVE CONVERTER AND ITS

OUTPUT EQUIVALENT

ICL7660A

R02R

SW1RSW3

ESR

C1

++2R

SW2RSW4

ESR

C1

+++

(EQ. 2)

1

f

PUMPC1



--------------------------------

ESR

C2

+

f

PUMP

f

OSC

2

--------------

= R

SWX

MOSFET Switch Resistance=

R02xR

SW

1

f

PUMPC1



--------------------------------

4xESR

C1

ESR

C2

+++

(EQ. 3)

R02x23

1

510

3

 10 106–

---------------------------------------------------

4xESR

C1

ESR

C2

+++

(EQ. 4)

R

0

46 20 5++ ESR

C



V

RIPPLE

1

2f

PUMP

 C2

-----------------------------------------

2ESR

C2IOUT

+







(EQ. 5)

R

OUT

R

OU T of ICL7660S

n number of devices

---------------------------------------------------------

=

(EQ. 6)

V

OUT

nVIN–=

(EQ. 7)

Typical Applications

Simple Negative Voltage Converter

The majority of applications will undoubtedly utilize the
ICL7660S and ICL7660A for generation of negative supply
voltages. Figure 15 shows typical connections to provide a
negative supply where a positive supply of +1.5V to +12V is
available. Keep in mind that pin 6 (LV) is tied to the supply
negative (GND) for supply voltage below 3.5V.

The output characteristics of the circuit in Figure 15 can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 15B. The voltage source has
a value of -(V+). The output impedance (R
the ON resistance of the internal MOS switches (shown in
Figure 14), the switching frequency, the value of C
and the ESR (equivalent series resistance) of C
good first order approximation for R

O

Equation 2:

) is a function of

O

is shown in

and C2,

1

and C2. A

1

charge the capacitors every cycle. Equation 4 shows a typical
application where f

= 10kHz and C = C1 = C2 = 10µF:

OSC

Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/f

x C1 term, rendering an

PUMP

increase in switching frequency or filter capacitance
ineffective. Typical electrolytic capacitors may have ESRs as
high as 10.

Output Ripple

ESR also affects the ripple voltage seen at the output. The
peak-to-peak output ripple voltage is given by Equation 5:

A low ESR capacitor will result in a higher performance
output.

Paralleling Devices

Any number of ICL7660S and ICL7660A voltage converters
may be paralleled to reduce output resistance. The reservoir
capacitor, C
its own pump capacitor, C

, serves all devices, while each device requires

2

. The resultant output resistance

1

is approximated in Equation 6:

Cascading Devices

The ICL7660S and ICL7660A may be cascaded as shown to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined as shown in Equation 7:

Combining the four R

terms as RSW, we see in

SWX

Equation 3 that:

R

, the total switch resistance, is a function of supply

SW

voltage and temperature (see the output source resistance
graphs, Figures 2, 3, and 11), typically 23 at +25°C and 5V.
Careful selection of C
terms, minimizing the output impedance. High value
capacitors will reduce the 1/(f
ESR capacitors will lower the ESR term. Increasing the
oscillator frequency will reduce the 1/(f
may have the side effect of a net increase in output
impedance when C

FN3179 Rev 7.00 Page 9 of 13
January 23, 2013

and C2 will reduce the remaining

1

> 10µF and is not long enough to fully

1

x C1) component, and low

PUMP

x C1) term, but

PUMP

where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660S
and ICL7660A R

OUT

values.

Changing the ICL7660S and ICL7660A Oscillator
Frequency

It may be desirable in some applications, due to noise or other
considerations, to alter the oscillator frequency. This can be
achieved simply by one of several methods.

By connecting the Boost Pin (Pin 1) to V+, the oscillator
charge and discharge current is increased and, hence, the
oscillator frequency is increased by approximately 3.5 times.
The result is a decrease in the output impedance and ripple.

ICL7660S, ICL7660A

1

2

3

4

8

7

6

5

+

-

10µF

ICL7660S

V

OUT

V+

+

-

10µF

V+

CMOS
GATE

1kΩ

FIGURE 16. EXTERNAL CLOCKING

ICL7660A

1

2

3

4

8

7

6

5

+

-

ICL7660S

V

OUT

V+

+

­C

2

C

1

C

OSC

FIGURE 17. LOWERING OSCILLATOR FREQUENCY

ICL7660A

1

2

3

4

8

7

6

5

ICL7660S

V+

D

1

D

2

C

1

C

2

V

OUT

=

(2V+)

- (2V

F

)

+

-

+

-

FIGURE 18. POSITIVE VOLTAGE DOUBLER

NOTE: D1 AND D2 CAN BE ANY SUITABLE DIODE.

ICL7660A

This is of major importance for surface mount applications
where capacitor size and cost are critical. Smaller
capacitors, such as 0.1µF, can be used in conjunction with
the Boost Pin to achieve similar output currents compared to
the device free running with C

= C2 = 10µF or 100µF. (see

1

Figure 11).

Increasing the oscillator frequency can also be achieved by
overdriving the oscillator from an external clock, as shown in
Figure 16. In order to prevent device latchup, a 1k resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock
frequency using TTL logic, the addition of a 10k pull-up
resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
will be one-half of the clock frequency. Output transitions
occur on the positive going edge of the clock.

Positive Voltage Doubling

The ICL7660S and ICL7660A may be employed to achieve
positive voltage doubling using the circuit shown in Figure

18. In this application, the pump inverter switches of the
ICL7660S and ICL7660A are used to charge C
level of V+ -V
forward voltage on C
applied through diode D
created on C

, where V+ is the supply voltage and VF is the

F

becomes (2V+) - (2VF) or twice the supply

2

, plus the supply voltage (V+) is

1

to capacitor C2. The voltage thus

2

voltage minus the combined forward voltage drops of diodes
D

and D2.

1

The source impedance of the output (V

OUT

the output current, but for V+ = 5V and an output current of
10mA, it will be approximately 60.

to a voltage

1

) will depend on

It is also possible to increase the conversion efficiency of the
ICL7660S and ICL7660A at low load levels by lowering the
oscillator frequency. This reduces the switching losses, and
is shown in Figure 17. However, lowering the oscillator
frequency will cause an undesirable increase in the
impedance of the pump (C

) and reservoir (C2) capacitors;

1

this is overcome by increasing the values of C
the same factor by which the frequency has been reduced.
For example, the addition of a 100pF capacitor between pin
7 (OSC and V+) will lower the oscillator frequency to 1kHz
from its nominal frequency of 10kHz (a multiple of 10), and
thereby necessitate a corresponding increase in the value of
C

and C2 (from 10µF to 100µF).

1

FN3179 Rev 7.00 Page 10 of 13
January 23, 2013

1

and C2 by

Combined Negative Voltage Conversion and
Positive Supply Doubling

Figure 19 combines the functions shown in Figure 15 and
Figure 18 to provide negative voltage conversion and
positive voltage doubling simultaneously. This approach
would be suitable, for example, for generating +9V and -5V
from an existing +5V supply. In this instance, capacitors C
and C

perform the pump and reservoir functions,

3

respectively, for negative voltage generation, while
capacitors C

and C4 are pump and reservoir, respectively,

2

for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher, due to the finite impedance of the
common charge pump driver at pin 2 of the device.

1

ICL7660S, ICL7660A

1

2

3

4

8

7

6

5

ICL7660S

V+

D

1

D

2

C

4

V

OUT

= (2V+) -

(V

FD1

) - (V

FD2

)

+

-

C

2

+

-

C

3

+

-

V

OUT

= -V

IN

C

1

+

-

FIGURE 19. COMBINED NEGATIVE VOLTAGE CONVERTER

AND POSITIVE DOUBLER

D

3

ICL7660A

1

2

3

4

8

7

6

5

+

-

+

-

50µF

50µF

+

-

50µF

R

L1

V

OUT

=

V+ - V-

2

ICL7660S

V+

V-

R

L2

FIGURE 20. SPLITTING A SUPPLY IN HALF

ICL7660A

1

2

3

4

8

7

6

5

+

-

100µF

ICL7660S

100µF

V

OUT

+

-

10µF

ICL7611

+

-

100

50k

+8V

100k

50k

ICL8069

56k

+8V

800k

250k

VOLTAGE

ADJUST

+

-

FIGURE 21. REGULATING THE OUTPUT VOLTAGE

ICL7660A

Voltage Splitting

The bidirectional characteristics can also be used to split a
high supply in half, as shown in Figure 20. The combined load
will be evenly shared between the two sides, and a high value
resistor to the LV pin ensures start-up. Because the switches
share the load in parallel, the output impedance is much lower
than in the standard circuits, and higher currents can be drawn
from the device. By using this circuit, and then the circuit of
Figure 15, +15V can be converted, via +7.5 and -7.5, to a
nominal -15V, although with rather high series output
resistance (

250).

Regulated Negative Voltage Supply

In some cases, the output impedance of the ICL7660S and
ICL7660A can be a problem, particularly if the load current
varies substantially. The circuit of Figure 21 can be used to
overcome this by controlling the input voltage, via an ICL7611
low-power CMOS op amp, in such a way as to maintain a
nearly constant output voltage. Direct feedback is inadvisable,
since the ICL7660S’s and ICL7660A’s output does not respond
instantaneously to change in input, but only after the switching
delay. The circuit shown supplies enough delay to
accommodate the ICL7660S and ICL7660A, while maintaining
adequate feedback. An increase in pump and storage
capacitors is desirable, and the values shown provide an
output impedance of less than 5 to a load of 10mA.

FN3179 Rev 7.00 Page 11 of 13
January 23, 2013

Other Applications

Further information on the operation and use of the ICL7660S
and ICL7660A may be found in application note AN051,

“Principles and Applications of the ICL7660 CMOS Voltage
Converter”.

ICL7660S, ICL7660A

C

L

E

e

A

C

e

B

e

C

-B-

E1

INDEX

12 3 N/2

N

AREA

SEATING

BASE

PLANE

PLANE

-C-

D1

B1

B

e

D

D1

A

A2

L

A

1

-A-

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru­sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).

6. E and are measured with the leads constrained to be per­pendicular to datum .

7. e

B

and eC are measured at the lead tips with the leads uncon-

strained. e

C

must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

eA-C-

Dual-In-Line Plastic Packages (PDIP)

E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4

A1 0.015 - 0.39 - 4

A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.355 0.400 9.01 10.16 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N8 89

NOTESMIN MAX MIN MAX

Rev. 0 12/93

All trademarks and registered trademarks are the property of their respective owners.

© Copyright Intersil Americas LLC 1999-2013. All Rights Reserved.

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.

FN3179 Rev 7.00 Page 12 of 13
January 23, 2013

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

For information regarding Intersil Corporation and its products, see www.intersil.com

For additional products, see www.intersil.com/en/products.html

ICL7660S, ICL7660A

DETAIL "A"

TOP VIEW

INDEX

AREA

123

-C-

SEATING PLANE

x 45°

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1994.

2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.

8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

SIDE VIEW “A

SIDE VIEW “B”

1.27 (0.050)

6.20 (0.244)

5.80 (0.228)

4.00 (0.157)

3.80 (0.150)

0.50 (0.20)

0.25 (0.01)

5.00 (0.197)

4.80 (0.189)

1.75 (0.069)

1.35 (0.053)

0.25(0.010)

0.10(0.004)

0.51(0.020)

0.33(0.013)

8°
0°

0.25 (0.010)

0.19 (0.008)

1.27 (0.050)

0.40 (0.016)

1.27 (0.050)

5.20(0.205)

1

2

3

4

5

6

7

8

TYPICAL RECOMMENDED LAND PATTERN

2.20 (0.087)

0.60 (0.023)

Package Outline Drawing

M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 1/12

FN3179 Rev 7.00 Page 13 of 13
January 23, 2013

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