RENESAS HN58V65AI, HN58V66AI, HN58V65A-SR, HN58V66A-SR User Manual
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HN58V65AI Series
HN58V66AI Series
HN58V65A-SR Series
HN58V66A-SR Series
64k EEPROM (8-kword × 8-bit)
Ready/Busy function, RES function (HN58V66A)
Wide Temperature Range version
REJ03C0153-0300Z
(Previous ADE-203-759B(Z) Rev.2.0)
Rev. 3.00
Feb.02.2004
Description
Renesas Technology’s HN58V65A series and HN58V66A series are electrically erasable and
programmable EEPROM’s organized as 8192-word × 8-bit. They have realized high speed, low power
consumption and high reliability by employing advanced MNOS memory technology and CMOS process
and circuitry technology. They also have a 64-byte page programming function to make their write
operations faster.
Features
• Single supply: 2.7 to 5.5 V
• Access time:
100 ns (max) at 2.7 V ≤ V
70 ns (max) at 4.5 V ≤ V
• Power dissipation:
Active: 20 mW/MHz (typ)
Standby: 110 µW (max)
• On-chip latches: address, data, CE, OE, WE
• Automatic byte write: 10 ms (max)
• Automatic page write (64 bytes): 10 ms (max)
• Ready/Busy
• Data polling and Toggle bit
• Data protection circuit on power on/off
< 4.5 V
CC
≤ 5.5 V
CC
Rev.3.00, Feb.02.2004, page 1 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Features (cont)
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
5
• 10
erase/write cycles (in page mode)
• 10 years data retention
• Software data protection
• Write protection by RES pin (only the HN58V66A series)
• Operating temperature range:
HN58V65AI/HN58V66AI Series: −40 to +85°C
HN58V65A-SR/HN58V66A-SR Series: −20 to +85°C
• There are also lead free products.
Ordering Information
Access time
Type No. 2.7 V ≤ VCC < 4.5 V 4.5 V ≤ VCC ≤ 5.5 V Package
HN58V65API-10 100 ns 70 ns 600 mil 28-pin plastic DIP (DP-28)
HN58V66API-10 100 ns 70 ns
HN58V65AFPI-10 100 ns 70 ns 400 mil 28-pin plastic SOP (FP-28D)
HN58V66AFPI-10 100 ns 70 ns
HN58V65ATI-10 100 ns 70 ns 28-pin plastic TSOP(TFP-28DB)
HN58V66ATI-10 100 ns 70 ns
HN58V65AT-10SR 100 ns 70 ns
HN58V66AT-10SR 100 ns 70 ns
HN58V65API-10E 100 ns 70 ns 600 mil 28-pin plastic DIP (DP-28V)
HN58V66API-10E 100 ns 70 ns Lead free
HN58V65AFPI-10E 100 ns 70 ns 400 mil 28-p in plastic SOP (FP-28DV)
HN58V66AFPI-10E 100 ns 70 ns Lead free
HN58V65ATI-10E 100 ns 70 ns 28-pin plastic TSOP(TFP-28DBV)
HN58V66ATI-10E 100 ns 70 ns Lead free
HN58V65AT-10SRE 100 ns 70 ns
HN58V66AT-10SRE 100 ns 70 ns
Rev.3.00, Feb.02.2004, page 2 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Pin Arrangement
HN58V65API Series
HN58V65AFPI Series
RDY/Busy
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
RDY/Busy
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(Top view)
HN58V66API Series
HN58V66AFPI Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
V
CC
WE
RES
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A2
A1
A0
I/O0
I/O1
I/O2
V
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A2
A1
A0
I/O0
I/O1
I/O2
V
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
HN58V65ATI Series
HN58V65AT-SR Series
15
16
17
18
19
20
21
SS
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A4
A5
A6
A7
A12
RDY/Busy
V
CC
WE
NC
A8
A9
A11
OE
(Top view)
HN58V66ATI Series
HN58V66AT-SR Series
15
16
17
18
19
20
21
SS
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A4
A5
A6
A7
A12
RDY/Busy
V
CC
WE
RES
A8
A9
A11
OE
(Top view)
(Top view)
Rev.3.00, Feb.02.2004, page 3 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Pin Description
Pin name Function
A0 to A12 Address inp ut
I/O0 to I/O7 Data input/output
OE Output enable
CE Chip enable
WE Write enable
VCC Power supply
VSS Ground
RDY/Busy Ready busy
RES*1 Reset
NC No connection
Note: 1. This function is supported by only the HN58V66A series.
Block Diagram
Note: 1. This function is supported by only the HN58V66A series.
V
CC
V
SS
RES
OE
CE
WE
RES
A0
to
A5
A6
to
A12
1
*
1
*
High voltage generator
Control logic and timing
Address
buffer and
latch
Y decoder
X decoder
to
I/O0 I/O7
I/O buffer
and
input latch
Y gating
Memory array
Data latch
RDY/Busy
Rev.3.00, Feb.02.2004, page 4 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Operation Table
Operation CE OE WE RES*3 RDY/Busy I/O
Read VIL V
V
IL
V
IH
*1 High-Z Dout
H
Standby VIH ×*2 × × High-Z High-Z
Write VIL V
Deselect VIL V
Write Inhibit × × V
× V
Data Polling VIL V
Program reset × × × V
V
IH
V
IH
× ×
IL
V
IL
V
IL
V
IH
×
IH
V
IH
High-Z to VOL Din
H
High-Z High-Z
H
V
H
High-Z High-Z
IL
Dout (I/O7)
OL
Notes: 1. Refer to the recommended DC operating conditions.
2. × : Don’t care
3. This function supported by only the HN58V66A series.
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage relative to VSS VCC –0.6 to +7.0 V
Input voltage relative to VSS Vin –0.5*1 to
+7.0*3
Operating temperature range *2 HN58V65AI/HN58V66AI Topr –40 to +85 °C
HN58V65A-SR/HN58V66A-SR Topr –20 to +85 °C
Storage temperature range Tstg –55 to +125 °C
Notes: 1. Vin min : –3.0 V for pulse width ≤ 50 ns.
2. Including electr ical characteristics and data retention.
3. Should not exceed V
+ 1 V.
CC
V
Rev.3.00, Feb.02.2004, page 5 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Recommended DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 2.7 — 5.5 V
V
0 0 0 V
SS
Input voltage VIL –0.3*1 — 0.6*5 V
V
V
2.4*2 — VCC + 0.3*3 V
IH
*4 VCC – 0.5 — VCC + 1.0 V
H
Operating temperature Topr HN58V65AI/HN58V66AI –40 — +85 °C
HN58V65A-SR/HN58V66A-SR –20 — +85 °C
Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.
2. V
3. V
= 3.0 V for VCC = 3.6 to 5.5 V.
IH
max: VCC + 1.0 V for pulse width ≤ 50 ns.
IH
4. This function is supported by only the HN58V66A series.
5. V
= 0.8 V for VCC = 3.6 V to 5.5 V
IL
DC Characteristics
(Ta = −40 to +85°C, VCC = 2.7 to 5.5 V: HN58V66AI/HN58V66AI,
Ta = −20 to +85°C, V
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current ILI 2*1 µA VCC = 5.5 V, Vin = 5.5 V
Output leakage current ILO 2 µA VCC = 5.5 V, Vout = 5.5/0.4 V
Standby VCC current I
I
Operating VCC current I
10 mA Iout = 0 mA, Duty = 100%,
15 mA Iout = 0 mA, Duty = 100%,
25 mA Iout = 0 mA, Duty = 100%,
Output low voltage VOL 0.4 V IOL = 2.1 mA
Output high voltage VOH VCC × 0.8 V IOH = −400 µA
Note: 1. ILI on RES : 100 µA max (only the HN58V66A series)
1 to 2 5 µA CE = VCC
CC1
1 mA CE = VIH
CC2
6 mA Iout = 0 mA, Duty = 100%,
CC3
= 2.7 to 5.5 V: HN58V66A-SR/HN58V66A-SR)
CC
Cycle = 1 µs at V
= 3.6 V
CC
Cycle = 1 µs at VCC = 5.5 V
Cycle = 100 ns at V
= 3.6 V
CC
Cycle = 70 ns at VCC = 5.5 V
Rev.3.00, Feb.02.2004, page 6 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance Cin*1 6 pF Vin = 0 V
Output capacitance Cout*1 12 pF Vout = 0 V
Note: 1. This parameter is sampled and not 100% tested.
AC Characteristics
(Ta = −40 to +85°C, VCC = 2.7 to 5.5 V: HN58V65AI/HN58V66AI,
Ta = −20 to +85°C, V
Test Conditions
= 2.7 to 5.5 V: HN58V65A-SR/HN58V66A-SR)
CC
• Input pulse levels : 0.4 V to 2.4 V (V
0 V to V
(RES pin*2)
CC
= 2.7 to 3.6 V), 0.4 V to 3.0 V (VCC = 3.6 to 5.5 V)
CC
• Input rise and fall time : ≤ 5 ns
• Input timing reference levels : 0.8, 1.8 V
• Output load : 1TTL Gate +100 pF
• Output reference levels : 1.5 V, 1.5 V
Read Cycle 1 (2.7 ≤ V
HN58V65AI/HN58V66AI
-10
Parameter Symbol Min Max Unit Test conditions
Address to output delay t
CE to output delay tCE 100 ns OE = VIL, WE = VIH
OE to output delay tOE 10 50 ns CE = VIL, WE = VIH
Address to output hold tOH 0 ns CE = OE = VIL, WE = VIH
OE (CE) high to output float*1 tDF 0 40 ns CE = VIL, WE = VIH
RES low to output float*
RES to output delay*2 t
< 4.5 V)
CC
1, 2
t
HN58V65A-SR/HN58V66A-SR
100 ns CE = OE = VIL, WE = VIH
ACC
0 350 ns CE = OE = VIL, WE = VIH
DFR
0 450 ns CE = OE= VIL, WE = VIH
RR
Rev.3.00, Feb.02.2004, page 7 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Write Cycle 1 (2.7 ≤ VCC < 4.5 V)
Parameter Symbol Min*3 Typ Max Unit Test conditions
Address setup time t
Address hold time tAH 50 ns
CE to write setup time (WE controlled) tCS 0 ns
CE hold time (WE controlled) tCH 0 ns
WE to write setup time (CE controlled) tWS 0 ns
WE hold time (CE controlled) tWH 0 ns
OE to write setup time t
OE hold time t
Data setup time tDS 50 ns
Data hold time tDH 0 ns
WE pulse width (WE controlled) tWP 200 ns
CE pulse width (CE controlled) tCW 200 ns
Data latch time tDL 100 ns
Byte load cycle t
Byte load window tBL 100 µs
Write cycle time tWC 10*4 ms
Time to device busy tDB 120 ns
Write start time tDW 0*5 ns
Reset protect time*2 t
Reset high time*
Notes: 1. tDF and t
2, 6
t
are defined as the time at which the outputs achieve the open circuit conditions and
DFR
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. t
must be longer than this value unless polling techniques or RDY/Busy are used. This device
WC
automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
WE.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
CE.
9. See AC read characteristics.
0 ns
AS
0 ns
OES
0 ns
OEH
0.3 30 µs
BLC
100 µs
RP
1 µs
RES
if polling techniques or RDY/Busy are used.
DW
Rev.3.00, Feb.02.2004, page 8 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Read Cycle 2 (4.5 ≤ VCC ≤ 5.5 V)
HN58V65AI/HN58V66AI
HN58V65A-SR/HN58V66A-SR
-10
Parameter Symbol Min Max Unit Test conditions
Address to output delay t
70 ns CE = OE = VIL, WE = VIH
ACC
CE to output delay tCE 70 ns OE = VIL, WE = VIH
OE to output delay tOE 10 40 ns CE = VIL, WE = VIH
Address to output hold tOH 0 ns CE = OE = VIL, WE = VIH
OE (CE) high to output float*1 tDF 0 30 ns CE = VIL, WE = VIH
RES low to output float*
RES to output delay*2 t
1, 2
t
0 350 ns CE = OE = VIL, WE = VIH
DFR
0 450 ns CE = OE= VIL, WE = VIH
RR
Rev.3.00, Feb.02.2004, page 9 of 26
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