RENESAS Hitachi Electric, Hitachi XX User Manual

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Electric and Hitachi XX, to Renesas Technology Corp.

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Customer Support Dept.
April 1, 2003

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contained therein.

HN29V25611AT-50H

256M AND type Flash Memory

More than 16,057-sector (271,299,072-bit)

ADE-203-1334A (Z)

Rev. 1.0

Apr. 5, 2002

Description

The Hitachi HN29V25611AT-50H Series is a CMOS Flash Memory with AND type multi-level memory
cells. It has fully automatic programming and erase capabilities with a single 3.0 V power supply. The
functions are controlled by simple external commands. To fit the I/O card applications, the unit of
programming and erase is as small as (2048 + 64) bytes. Initial available sectors of HN29V25611AT-50H are
more than 16,057 (98% of all sector address) and less than 16,384 sectors.

Features

• On-board single power supply (VCC): VCC = 2.7 V to 3.6 V

• Organization
 AND Flash Memory: (2048 + 64) bytes × (More than 16,057 sectors)
 Data register: (2048 + 64) bytes

• Multi-level memory cell
 2 bit/per memory cell

• Automatic programming
 Sector program time: 1.0 ms (typ)
 System bus free
 Address, data latch function
 Internal automatic program verify function
 Status data polling function

• Automatic erase
 Single sector erase time: 1.0 ms (typ)
 System bus free
 Internal automatic erase verify function
 Status data polling function

HN29V25611AT-50H

• Erase mode
 Single sector erase ((2048 + 64) byte unit)

• Fast serial read access time:
 First access time: 50 µs (max)
 Serial access time: 50 ns (max)

• Low power dissipation:
 I

= 2 mA (typ) (Read)

CC1

 I

= 20 mA (max) (Read)

CC2

 I

= 50 µA (max) (Standby)

SB2

 I
 I

• The following architecture is required for data reliability.
 Error correction: more than 3-bit error correction per each sector read
 Spare sectors: 1.8% (290 sectors) (min) within usable sectors

Ordering Information

Type No. Available sector Package

HN29V25611AT-50H More than 16,057 sectors 12.0 × 20.00 mm

= 40 mA (max) (Erase/Program)

CC3/ICC4

= 20 µA (max) (Deep standby)

SB3

48-pin plastic TSOP I (TFP-48DA)

2

0.5 mm pitch

2

Pin Arrangement

V

CC

1

NC*

1

NC*

1

NC*

V

SS

RES

RDY/Busy

SC

OE

I/O0
I/O1
I/O2
I/O3
V

CC

V

SS

I/O4
I/O5
I/O6
I/O7

CDE

WE

CE

1

NC*

V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48-pin TSOP

(Top view)

HN29V25611AT-50H

48

NC

47

NC

46

NC

45

NC

44

NC

43

NC

42

NC

41

NC

40

NC

39

NC

38

NC

37

NC

36

NC

35

NC

34

NC

33

NC

32

NC

31

NC

30

NC

29

NC

28

NC

27

NC

26

NC

25

NC

Note: 1. This pin can be used as the VSS pin.

3

HN29V25611AT-50H

Pin Description

Pin name Function

I/O0 to I/O7 Input/output

CE Chip enable
OE Output enable
WE Write enable
CDE Command data enable

1

VCC*

1

VSS*
RDY/Busy Ready/Busy
RES Reset
SC Serial clock
NC No connection

Note: 1. All VCC and VSS pins should be connected to a common power supply and a ground, respectively.

Power supply
Ground

4

Block Diagram

HN29V25611AT-50H

2048 + 64

I/O0

to

I/O7

RDY/Busy

V

CC

V

SS

Sector
address
buffer

• •

•
Multiplexer

•

• • • • •

•

•

•

•

Data
input
buffer

X-decoder

Input

•
data

•
control

Y-address
counter

16384 × (2048 + 64) × 8

memory matrix

Data register (2048 + 64)

•

•

Y-gating

Y-decoder

16057 - 16384

Data
output
buffer

CE
OE

WE

SC

RES
CDE

Control
signal
buffer

Read/Program/Erase control

5

HN29V25611AT-50H

Memory Map and Address

Sector address

3FFFH
3FFEH

3FFDH

0002H

0001H

0000H

000H

2048 bytes
2048 bytes
2048 bytes

2048 bytes

2048 bytes
2048 bytes

64 bytes
64 bytes

64 bytes

64 bytes

64 bytes
64 bytes

800H 83FH

1

16057 - 16384 sectors *

Column address

2048 + 64 bytes

Control bytes

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

Address
Sector address

Column address

Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized

by reading the sector valid data written in a part of the column address 800 to 83F
(The specific address is TBD.). The sector valid data must be read and kept outside
of the sector before the sector erase. When the sector is programmed, the sector
valid data should be written back to the sector.

2. An × means "Don't care". The pin level can be set to either V
to DC characteristics.

Cycles
SA (1): First cycle
SA (2): Second cycle
CA (1): First cycle
CA (2): Second cycle

I/O0

A0
A8
A0
A8

A1
A9
A1
A9

A2

A10

A2

A10

A3

A11

A3

A11

A5

A4

A13

A12

A5

A4

×

×

or VIH, referred

IL

A6

×*

A6

I/O7

A7

2

×

A7

×

×

6

HN29V25611AT-50H

Pin Function

CE: CE is used to select the device. The status returns to the standby at the rising edge of CE in the reading
operation. However, the status does not return to the standby at the rising edge of CE in the busy state in
programming and erase operation.

OE: Memory data and status register data can be read, when OE is VIL.

WE: Commands and address are latched at the rising edge of WE.

SC: Programming and reading data is latched at the rising edge of SC.

RES: RES pin must be kept at the V
in the memory is protected against unintentional erase and programming. RES must be kept at the V

(VSS ± 0.2 V) level when VCC is turned on and off. In this way, data

ILR

IHR

(V

CC

± 0.2 V) level during any operations such as programming, erase and read.

CDE: Commands and data are latched when CDE is VIL and address is latched when CDE is VIH.

RDY/Busy: The RDY/Busy indicates the program/erase status of the flash memory. The RDY/ Busy signal

is initially at a high impedance state. It turns to a VOL level after the (40H) command in programming
operation or the (B0H) command in erase operation. After the erase or programming operation finishes, the
RDY/Busy signal turns back to the high impedance state.

I/O0 to I/O7: The I/O pins are used to input data, address and command, and are used to output memory data
and status register data.

Mode Selection

Mode CE OE WE SC RES CDE RDY/Busy*3I/O0 to I/O7

4

Deep standby ×*
Standby V
Output disable V
Status register read*
Command write*

1

2

×××V
×××V

IH

V

IL

IH

V

V

IL

IL

V

V

IL

IH

V

× V

IH

V

× V

IH

V

V

IL

IL

Notes: 1. Default mode after the power on is the status register read mode (refer to status transition). From

I/O0 to I/O7 pins output the status, when CE = V
condition).

2. Refer to the command definition. Data can be read, programmed and erased after commands are
written in this mode.

3. The RDY/Busy bus should be pulled up to V

to maintain the VOH level while the RDY/Busy pin

CC

outputs a high impedance.

4. An × means “Don’t care”. The pin level can be set to either V

× V

ILR

× V

IHR

× V

IHR

× V

IHR

V

IHRVIL

and OE = VIL (conventional read operation

IL

OH

OH

OH

OH

V

OH

or VIH referred to DC characteristics.

IL

High-Z
High-Z
High-Z
Status register outputs
Din

7

HN29V25611AT-50H

Command Definition*

1, 2

First bus cycle Second bus cycle

Command

Bus
cycles

Operation

3

mode*

Data in Operation

mode

Data in Data out

Read Serial read (1) (Without CA) 3 Write 00H Write SA (1)*

(With CA) 3 + 2h*6Write 00H Write SA (1)*
Serial read (2) 3 Write F0H Write SA (1)*
Read identifier codes 1 Write 90H Read ID*
Data recovery read 1 Write 01H Read Recovery

Auto erase Single sector 4 Write 20H Write SA (1)*
Auto program Program (1) (Without

CA*

7

)

4 Write 10H Write SA (1)*

(With CA*7) 4 + 2h*6Write 10H Write SA (1)*
Program (2)*

10

4 Write 1FH Write SA (1)*
Program (3) (Control bytes)*74 Write 0FH Write SA (1)*
Program (4) (WithoutCA*7) 4 Write 11H Write SA (1)*

(With CA*7) 4 + 2h*6Write 11H Write SA (1)*
Reset 1 Write FFH
Clear status register 1 Write 50H
Data recovery write 4 Write 12H Write SA (1)*

4

4

4

8, 9

data

4

4

4

4

4

4

4

4

8

Third bus cycle Fourth bus cycle

Command

Bus
cycles

Operation
mode

Data in Operation

Read Serial read (1) (Without CA) 3 Write SA (2)*

(With CA) 3 + 2h*6Write SA (2)*

Serial read (2) 3 Write SA (2)*
Read identifier codes 1

Data recovery read 1
Auto erase Single sector 4 Write SA (2)*
Auto program Program (1) (Without

CA*

7

)

4 Write SA (2)*

(With CA*7) 4 + 2h*6Write SA (2)*

Program (2)*

10

4 Write SA (2)*
Program (3) (Control bytes)*74 Write SA (2)*
Program (4) (WithoutCA*7) 4 Write SA (2)*

(With CA*7) 4 + 2h*6Write SA (2)*
Reset 1
Clear status register 1
Data recovery write 4 Write SA (2)*

HN29V25611AT-50H

Data in

mode

4

4

Write CA (1)*

4

4

Write B0H*

4

Write 40H

4

Write CA (1)

4

Write 40H

4

Write 40H

4

Write 40H

4

Write CA (1)

4

Write 40H

5

11

*11, 12

*11, 12

*11, 12

*11, 12

*11, 12

9

HN29V25611AT-50H

Fifth bus cycle Sixth bus cycle

Bus

Command

cycles

Read Serial read (1) (Without CA) 3

(With CA) 3 + 2h*6Write CA (2)*

Serial read (2) 3
Read identifier codes 1

Data recovery read 1
Auto erase Single sector 4
Auto program Program (1) (Without

CA*

7

)

4

(With CA*7) 4 + 2h*6Write CA (2)*

Program (2)*

10

4
Program (3) (Control bytes)*74
Program (4) (WithoutCA*7)4

(With CA*7) 4 + 2h*6Write CA (2) Write 40H
Reset 1
Clear status register 1
Data recovery write 4

Notes: 1. Commands and sector address are latched at rising edge of WE pulses. Program data is latched

at rising edge of SC pulses.

2. The chip is in the read status register mode when RES is set to V

3. Refer to the command read and write mode in mode selection.

4. SA (1) = Sector address (A0 to A7), SA (2) = Sector address (A8 to A13).

5. CA (1) = Column address (A0 to A7), CA (2) = Column address (A8 to A11).
(0 ≤ A11 to A0 ≤ 83FH)

6. The variable h is the input number of times of set of CA (1) and CA (2) (1 ≤ h ≤ 2048 + 64).

Set of CA (1) and CA (2) can be input without limitation.

7. By using program (1) and (3), data can additionally be programmed maximum 15 times for each

sector before erase.

8. ID = Identifier code; Manufacturer code (07H), Device code (9AH).

9. The manufacturer identifier code is output when CDE is low and the device identifier code is output

when CDE is high.

10.Before program (2) operations, data in the programmed sector must be erased.

11.No commands can be written during auto program and erase (when the RDY/Busy pin outputs a

V

).

OL

12.The fourth or sixth cycle of the auto program comes after the program data input is complete.

Operation
mode

Data in Operation

mode

5

5

Write 40H

first time after the power up.

IHR

Data in

*11, 12

*11, 12

10

HN29V25611AT-50H

Mode Description

Read

Serial Read (1): Memory data D0 to D2111 in the sector of address SA is sequentially read. Output data is

not valid after the number of the SC pulse exceeds 2112. When CA is input, memory data D (m) to D (m + j)
in the sector of address SA is sequentially read. Then output data is not valid after the number of the SC pulse
exceeds (2112 to m). The mode turns back to the standby mode at any time when CE is VIH.

Serial Read (2): Memory data D2048 to D2111 in the sector of address SA is sequentially read. Output data
is not valid after the number of the SC pulse exceeds 64. The mode turns back to the standby mode at any
time when CE is VIH.

Automatic Erase

Single Sector Erase: Memory data D0 to D2111 in the sector of address SA is erased automatically by

internal control circuits. After the sector erase starts, the erasure completion can be checked through the
RDY/Busy signal and status data polling. All the bits in the sector are "1" after the erase. The sector valid
data stored in a part of memory data D2048 to D2111 must be read and kept outside of the sector before the
sector erase.

Automatic Program

Program (1): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by

internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into
the sector of address SA automatically by internal control circuits. By using program (1), data can
additionally be programed 15 times for each sector before the following erase. When the column is
programmed, the data of the column must be [FF]. After the programming starts, the program completion can
be checked through the RDY/Busy signal and status data polling. Programmed bits in the sector turn from
"1" to "0" when they are programmed. The sector valid data should be included in the program data PD2048
to PD2111.

Program (2): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by
internal control circuits. After the programming starts, the program completion can be checked through the
RDY/Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0" when they are
programmed. The sector must be erased before programming. The sector valid data should be included in the
program data PD2048 to PD2111.

Program (3): Program data PD2048 to PD2111 is programmed into the sector of address SA automatically
by internal control circuits. By using program (3), data can additionally be programed 15 times for each
sector befor the following erase. When the column is programmed, the data of the column must be [FF].
After the programming starts, the program completion can be checked through the RDY/Busy signal and
status data polling. Programmed bits in the sector turn from "1" to "0" when they are programmed.

11

HN29V25611AT-50H

Program (4): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by

internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into
the sector of address SA automatically by internal control circuits. By using program (4), data can be
rewritten for each sector before the following erase. So the column data before programming operation are
either "1" or "0". In this mode, E/W number of times must be counted whenever program (4) execute. After
the programming starts, the program completion can be checked through the RDY/Busy signal and status data
polling. The sector valid data should be included in the program data PD2048 to PD2111.

2111

16383

Sector
address

Memory array

0

0

Serial read (2)
Program (3)

2048

Register

2111

16383

Sector
address

Memory array

0

0

Register

Serial read (1) (Without CA)
Program (1) (Without CA)
Program (2)

2111

16383

Sector
address

Memory array

0

0

Column address

Register

Serial read (1) (With CA)
Program (1) (With CA)

Status Register Read

The status returns to the status register read mode from standby mode, when CE and OE is VIL. In the status
register read mode, I/O pins output the same operation status as in the status data polling defined in the
function description.

Identifier Read

The manufacturer and device identifier code can be read in the identifier read mode. The manufacturer and
device identifier code is selected with CDE VIL and VIH, respectively.

12

HN29V25611AT-50H

Data Recovery Read

When the programming was an error, the program data can be read by using data recovery read. When an
additional programming was an error, the data compounded of the program data and the origin data in the
sector address SA can be read. Output data are not valid after the number of SA pulse exeeds 2112. The
mode turns back to the standby mode at any time when CE is VIH. The read data are invalid when addresses
are latched at a rising edge of WE pulse after the data recovery read command is written.

Data Recovery Write

When the programming into a sector of address SA was an error, the program data can be rewritten
automatically by internal control circuit into the other selected sector of address SA’. Since the data recovery
write mode is internally Program (4) mode, rewritten sector of address SA’ needs no sector erase before
rewrite. After the data recovery write mode starts, the program completion can be checked through the
RDY/Busy signal and the status data polling.

13

HN29V25611AT-50H

Command/Address/Data Input Sequence

Serial Read (1) (With CA before SC)

Command

/Address

CDE

WE

SC

00H SA (1) SA (2) CA (1) CA (2) CA (1)' CA (2)'

Low

Serial Read (1) (With CA after SC)

Command

/Address

CDE

00H SA (1) SA (2) CA (1)' CA (2)'CA (1) CA (2)

WE

Low

SC

Data output Data outputData output

Serial Read (1) (Without CA), (2)

Command/Address

CDE

WE

SC

00H/F0H SA (1) SA (2)

Low

Data output Data output

Data output

Single Sector Erase

Command/Address

14

CDE

WE

SC

20H B0HSA (1) SA (2)

Low

Erase start

Program (1), (4) (With CA before SC)

HN29V25611AT-50H

Command

/Address

10H/11H SA (1) SA (2) CA (1) CA (2) CA (1)' CA (2)' 40H

CDE

WE

Low

SC

Program (1), (4) (With CA after SC)

Command

/Address

10H/11H SA (1) SA (2) CA (1) CA (2) 40H

CDE

WE

Low

SC

Data input Data input Program start

Program (1), (4) (Without CA)

Command/Address

CDE

WE

SC

10H/11H 40HSA (1) SA (2)

Low

Data input Data input Program start

CA (1)' CA (2)'

Data input

Data input

Program start

Program (2)

Command/Address

CDE

WE

SC

1FH 40HSA (1) SA (2)

Low

Data input

Program start

15

HN29V25611AT-50H

Program (3)

Command/Address

CDE

WE

SC

Low

ID Read Mode

Command/Address

Data Recovery Read Mode

Command/Address

0FH 40HSA (1) SA (2)

90H

CDE

WE

SC

Low

Manufacture
code output

01H

Data input

Device code
output

Program start

Manufacture
code output

Data Recovery Write Mode

Command/Address

CDE

WE

SC

CDE

WE

SC

Low

12H 40HSA (1) SA (2)

Low

Data output

Program start

16

Status Transition

HN29V25611AT-50H

Deep

standby

Standby

RES

CE

V

CC

Output
disable

Power off

00H/F0H

FFH

CE

90H CDE, OE

FFH

CE

20H

10H
/11H

FFH

1FH
/0FH

FFH

Status register clear

CE*
FFH*

Read (1) / (2)

setup

ID read setup

Sector

Erase setup

FFH

Program

(1)/(4) setup

Program (2)/(3)

setup

2

2

SA (1), SA (2) OE, SC

SA (1), SA (2)

Erase finish

SA (1),

SA (2)

Program finish

SA (1),

SA (2)

Program finish

50H

Sector address

ID read

address input

Column address

CA(1)
CA(2)

Sector address

input

Sector address

input

CA(1)
CA(2)

input

Sector

input

PD0 to
PD2111

SC, CDE

PD0 to
PD2111*3

SC, CDE

Column address

input

B0H

SC, CDE

PD(m)
to

CA(1)'

PD(m+j)

CA(2)'

Program

data input

Program

data input

40H

40H

OE

CA(1)'

SC

CA(2)'

Read (1) / (2)

Erase

start

Program

start

Program

start

OE

OE

OE

BUSY

Status register

Status register

Status register

Program error or
Erase error

read

read

read

1

01H*

Data recovery

CE

Error

standby

OE

Status register

read

Notes: 1. (01H)/(12H) Data recovery read/write can be used only for Program (1), (2), (3), (4) errors.

2. When reset is done by CE or FFH, error status flag is cleared.

3. When Program (3) mode, input data is PD2048 to PD2111.

Output
disable

12H*

FFH

read setup

1

Data recovery

write setup

OE

SA(1)
SA(2)

Status register

OE, SC

Sector address

read

ERROR

Data recovery

read

40H

input

17

HN29V25611AT-50H

Absolute Maximum Ratings

Parameter Symbol Value Unit Notes

voltage V

V

CC

VSS voltage V

CC

SS

All input and output voltages Vin, Vout –0.6 to +4.6 V 1, 2
Operating temperature range Topr 0 to +70 ˚C
Storage temperature range Tstg –65 to +125 ˚C 3
Storage temperature under bias Tbias –10 to +80 ˚C

Notes: 1. Relative to VSS.

2. Vin, Vout = –2.0 V for pulse width ≤ 20 ns.

3. Device storage temperature range before programming.

Capacitance (Ta = 25˚C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance Cin — — 6 pF Vin = 0 V
Output capacitance Cout — — 12 pF Vout = 0 V

–0.6 to +4.6 V 1
0V

18

HN29V25611AT-50H

DC Characteristics (VCC = 2.7 V to 3.6 V, Ta = 0 to +70˚C)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current I
Output leakage current I
Standby VCC current I

Deep standby VCC current I
Operating VCC current I

Operating VCC current (Program) I
Operating VCC current (Erase) I
Input voltage V

Input voltage (RES pin) V

Output voltage V

LI

LO

SB1

I

SB2

SB3

CC1

I

CC2

CC3

CC4

IL

V

IH

ILR

V

IHR

OL

V

OH

Notes: 1. VIL min = –1.0 V for pulse width ≤ 50 ns in the read operation. VIL min = –2.0 V for pulse width ≤ 20

ns in the read operation.

2. V

min = –0.6 V for pulse width ≤ 20 ns in the erase/data programming operation.

IL

3. V

max = VCC + 1.5 V for pulse width ≤ 20 ns. If VIH is over the specified maximum value, the

IH

operations are not guaranteed.

——2 µA Vin = VSS to V
——2 µA Vout = VSS to V
— 0.3 1 mA CE = V

CC

CC

IH

—3050 µA CE = VCC ± 0.2 V,

RES = V

± 0.2 V

CC

—120 µA RES = VSS ± 0.2 V
— 2 20 mA Iout = 0 mA, f = 0.2 MHz
— 10 20 mA Iout = 0 mA, f = 20 MHz
— 20 40 mA In programming
— 20 40 mA In erase

1, 2

–0.3*

— 0.8 V

2.0 — VCC + 0.3*3V
–0.2 — 0.2 V
VCC – 0.2 — VCC + 0.2 V
— — 0.4 V IOL = 2 mA

2.4 —— VIOH = –2 mA

AC Characteristics (VCC = 2.7 V to 3.6 V, Ta = 0 to +70˚C)

Test Conditions

• Input pulse levels: 0.4 V/2.4 V

• Input pulse levels for RES: 0.2 V/VCC – 0.2 V

• Input rise and fall time: ≤ 5 ns

• Output load: 1 TTL gate + 100 pF (Including scope and jig.)

• Reference levels for measuring timing: 0.8 V, 1.8 V

19

HN29V25611AT-50H

Power on and off, Serial Read Mode

Parameter Symbol Min Typ Max Unit Test conditions Notes

Write cycle time t
Serial clock cycle time t

CE setup time t
CE hold time t

Write pulse time t
Write pulse high time t
Address setup time t
Address hold time t
Data setup time t
Data hold time t
SC to output delay t

OE setup time for SC t
OE low to output low-Z t
OE setup time before read t
OE setup time before

command write
SC to output hold t

OE high to output float t
WE to SC delay time t
RES to CE setup time t

SC to OE hold time t
SC pulse width t
SC pulse low time t
SC setup time for CE t

CDE setup time for WE t
CDE hold time for WE t
VCC setup time for RES t
RES to VCC hold time t
CE setup time for RES t

RDY/Busy undefined for V

CC

off

RES high to device ready t
CE pulse high time t
CE, WE setup time for RES t
RES to CE, WE hold time t

CWC

SCC

CES

CEH

WP

WPH

AS

AH

DS

DH

SAC

OES

OEL

OER

t

OEWS

SH

DF

WSD

RP

SOH

SP

SPL

SCS

CDS

CDH

VRS

VRH

CESR

t

DFP

BSY

CPH

CWRS

CWRH

120 — — ns
50——ns
0 ——ns
0 ——ns
60——nsCE = VIL, OE = V

IH

40——ns
50——ns
10——ns
50——ns
10——ns
——50nsCE = OE = VIL, WE = V

IH

0 ——ns
0 — 40 ns
100 — — ns
0 ——ns

15——nsCE = OE = VIL, WE = V
——40nsCE = VIL, WE = V

IH

IH

1

50 — — µs2

0.3 — — ms
50——ns
20——ns
20——ns
0 ——ns
0 ——ns
20——ns
1——µs CE = V
1——µs CE = V

IH

IH

1——µs
0 ——ns

— — 0.3 ms
200 — — ns
0 ——ns
0 ——ns

20

HN29V25611AT-50H

Parameter Symbol Min Typ Max Unit Test conditions Notes

SC setup for WE t
CE hold time for OE t

SA (2) to CA (2) delay time t
RDY/Busy setup for SC t
Time to device busy t
Busy time on read mode t

SW

COH

SCD

RS

DB

RBSY

Notes: 1. tDF is a time after which the I/O pins become open.

2. t

(min) is specified as a reference point only for SC, if t

WSD

limit, then access time is controlled exclusively by t

50——ns
0 ——ns
——30µs
200 — — ns
— — 150 ns
—45—µs

is greater than the specified t

WSD

.

SAC

WSD

(min)

21

HN29V25611AT-50H

Program, Erase and Erase Verify

Parameter Symbol Min Typ Max Unit Test conditions Note

Write cycle time t
Serial clock cycle time t

CE setup time t
CE hold time t

Write pulse time t
Write pulse high time t
Address setup time t
Address hold time t
Data setup time t
Data hold time t
OE setup time before command

write
OE setup time before status

polling
OE setup time before read t
Time to device busy t
Auto erase time t
Auto program time

Program(1), (3)
Program(2) t
Program(4),

Data recovery write

WE to SC delay time t
CE pulse high time t

SC pulse width t
SC pulse low time t
Data setup time for SC t
Data hold time for SC t
SC setup for WE t
SC setup for CE t
SC hold time for WE t

CWC

SCC

CES

CEH

WP

WPH

AS

AH

DS

DH

t

OEWS

t

OEPS

OER

DB

ASE

t

ASP

ASP

t

ASP

WSD

CPH

SP

SPL

SDS

SDH

SW

SCS

SCHW

120 — — ns
50——ns
0 ——ns
0 ——ns
60——ns
40——ns
50——ns
10——ns
50——ns
10——ns
0 ——ns

40——ns

100 — — ns
— — 150 ns
— 1.0 10.0 ms
— 1.5 20.0 ms

— 1.0 20.0 ms
— 2.0 30.0 ms

50 — — µs
200 — — ns
20——ns
20——ns
0 ——ns
30——nsCDE = V
50——ns
0 ——ns
20——ns

IL

22

HN29V25611AT-50H

Parameter Symbol Min Typ Max Unit Test conditions Note

CE to output delay t
OE to output delay t
OE high to output float t
RES to CE setup time t
CDE setup time for WE t
CDE hold time for WE t
CDE setup time for SC t
CDE hold time for SC t

Next cycle ready time t

CDE to OE hold time t
CDE to output delay t
CDE to output invalid t
CE hold time for OE t
OE setup time for SC t
OE low to output low-Z t

SC to output delay t
SC to output hold t
RDY/Busy setup for SC t
Busy time on read mode t

CE

OE

DF

RP

CDS

CDH

CDSS

CDSH

RDY

CDOH

CDAC

CDF

COH

OES

OEL

SAC

SH

RS

RBSY

Note: 1. tDF is a time after which the I/O pins become open.

— — 120 ns
——60ns
——40ns 1

0.3 — — ms
0 ——ns
20——ns

1.5 — — µs
30——ns
0 ——ns
50——ns
——50ns
— — 100 ns
0 ——ns
0 ——ns
0 — 40 ns
——50ns
15——ns
200 — — ns
—45—µs

23

HN29V25611AT-50H

Timing Waveforms

Power on and off Sequence

V

CC

CE

t

VRS

t

RPtCES

t

CEHtCESR

t

RP

t

CES

t

CEH

t

CESR

WE

t

CWRS

RES

1

*

t

BSY

2

*

High-Z

Ready

RDY

/Busy

Notes: 1. RES must be kept at the V
to guarantee data stored in the chip.

2. RES must be kept at the V

status data polling and RDY/Busy outputs the V

level referred to DC characteristics at the rising and falling edges of V

ILR

level referred to DC characteristics while I/O7 outputs the VOL level in the

IHR

3. : Undefined

OL

t

level.

BSY

t

CWRH

t

VRH

t

DFP

1

*

CC

24

Serial Read (1) (2) Timing Waveform

HN29V25611AT-50H

1

CE

OE

t

OEWS

t

CES

t

CWC

t

WPH

t

CWC

t

WPH

t

OER

t

COH

t

*

CPH

WE

t

CDS

CDE

SC

I/O0 to I/O7

RES

RDY

/Busy

t

SCS

t

WP

t

DS

t

RP

t

/F0H

CDS

t

CDH

t

WP

t

DH

t

AS

SA(1)

t

WP

t

AH

t

AS

SA(2)

t

DB

t

OES

t

WSD

t

AH

t

RBSY

t

OEL

t

SCC

t

SP

t

SAC

D0out/D2048out D1out/D2049out D2111out/D2111out00H

t

RS

t

SPL

t

SCC

t

SAC

t

SH

2

*

t

t

SH

SAC

t

t

SAC

SOH

t

DF

2

*

High-Z

Notes: 1. The status returns to the standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceeds 2112 and 64 in the serial read mode (1)and (2), respectively.

3. After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the V

Serial Read (1) with CA before SC Timing Waveform

t

CDS

3

*

t

CEH

t

t

CDH

WP

t

t

DS

DH

FFH

level.

IH

5

*

h-1 cycle

CE

t

CDE

I/O0 to I/O7

RES

RDY

/Busy

OE

WE

SC

t

OEWS

t

CDS

t

SCS

t

RP

CES

t

CWCtCWC

t

t

WPH

WPH

t

tWPtWPt

CDS

t

CDH

t

t

t

t

DS

DH

AStAS

AHtAH

t

CWCtCWC

t

t

WPH

WPH

WPtWPtWP

t

SCD

t

WSD

t

t

AS

AH

SA(2)

t

DB

t

RBSY

t

OER

t

OES

2

t

*

t

SCC

SCC

t

SP

t

t

SACtSAC

SPL

t

t

AH

t

AS

SAC

t

OEL

tSHt

SH

D(n)out D(n+1)out D(n+i)out00H SA(1) CA(1) CA(2) CA(2)'CA(1)' D(m)out D(m+1)out D(m+j)out FFH

t

High-Z

RS

t

t

OEWS

CWC

t

OER

t

WPH

t

SW

t

SOH

t

t

SAC

DF

2

*

t

t

WP

WP

t

SCCtSCC

t

t

SAC

SPL

t

SH

3

*

t

SAC

t

SH

tASt

t

OES

t

AS

t

SP

t

AH

SAC

t

AH

t

OEL

Notes: 1. The status returns to the Standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceeds (2112-n). (i ≤ 2111-n, 0 ≤ n ≤ 2111)

3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111)

4. After any commands are written, the status can return to the standby after the command FFH is input and CE turns

level.

to the V

5. This interval can be repeated (h-1) cycle. (1≤ h ≤ 2048 + 64)

IH

1

*

t

COH

t

CPH

t

SOH

t

t

SAC

DF

3

*

4

*

t

CEH

t

t

CDH

WP

t

CDS

t

DS

t

DH

25

HN29V25611AT-50H

Serial Read (1) with CA after SC Timing Waveform

5

*

h cycle

CE

t

CES

t

CWCtCWC

t

t

WPHtWPH

OEWS

t

WPtWPtWP

t

CDH

t

t

CDS

CDS

t

t

SCS

t

t

DS

DH

AStAS

00H SA(1) CA(2)CA(1) D(m)out D(m+1)out D(m+j)out

t

RP

t

AHtAH

SA(2)

t

DB

t

OER

t

WSD

t

RBSY

t

OEL

t

OES

t

t

SP

t

SAC

t

RS

t

SCC

SCC

*

t

SACtSAC

t

SPL

tSHt

D0out D1out

High-Z

2

SH

CDE

I/O0 to I/O7

RES

RDY

/Busy

OE

WE

SC

Notes: 1. The status returns to the Standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceeds 2112. (0 ≤ k ≤ 2111)

3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111)

4. After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the V

5. This interval can be repeated h cycle. (1≤ h ≤ 2048 + 64)

Erase and Status Data Polling Timing Waveform (Sector Erase)

t

t

OEWS

CWC

t

OER

t

WPH

t

SW

t

SOH

t

t

SAC

DF

t

2

D(k)out

*

t

t

AS

WP

WP

t

AH

t

OES

t

SCCtSCC

*

t

SP

t

AH

t

AS

t

OEL

t

t

t

SAC

SPL

SAC

t

t

SH

SH

t

3

SOH

t

t

SAC

SAC

t

1

COH

*

t

CPH

t

CDS

t

DF

3

*

t

DS

4

*

t

CEH

t

t

CDH

WP

t

DH

FFH

level.

IH

CE

t

CE

t

OE

t

ASE

OE

t

OEWS

t

CES

t

CWC

t

WPH

t

CWC

t

WPH

t

CWC

t

WPH

t

CEH

t

OEPS

WE

t

CDE

CDS

WP

t

CDS

t

CDH

t

WP

t

WP

t

CDH

t

CDS

tWPt

t

CDH

t

SCHW

SC

t

SCS

t

t

DH

DS

t

AH

t

AS

t

AH

t

AS

t

t

DH

DS

I/O0 to I/O7

20H SA(1) SA(2)

B0H

IO7 = V

RES

RDY

/Busy

t

RP

High-Z High-Z

t

DB

1

*

Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy outputs a VOL.

2. The status returns to the standby status after RDY/Busy returns to High-Z.

t

RDY

t

CDS

t

DF

OL

IO7 = V

OH

*

t

DF

2

26

Program (1) and Status Data Polling Timing Waveform

CE

t

OE

WE

CDE

SC

I/O0 to I/O7

RES

RDY

/Busy

CES

t

OEWStCWC

t

CDS

t

SCS

t

RP

t

t

WP

DS

t

WPH

t

CDS

t

CDH

t

DH

t

AStAS

t

CWC

t

WPH

t

t

WP

CDSS

t

WP

t

CDH

SCC

t

SPL

t

t

AH

SDH

t

SDS

t

SPtSP

1

*

t

t

AH

SA (1) SA (2)

High-Z High-Z

t

CEH

t

OEPS

t

t

WP

SW

t

CDH

t

SCHW

t

t

DS

DH

40H10H PD0 PD1 PD2111 I/O7 = V

t

DB

HN29V25611AT-50H

t

CE

t

t

DF

I/O7 = V

RDY

3

*

OH

t

ASP

t

OE

t

DF

OL

2

*

t

CDS

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

3. The status returns to the standby status after RDY/Busy returns to High-Z.

.

OL

4. By using program (1), data can be programmed additionally for each sector before erase.

27

HN29V25611AT-50H

Program (1) with CA before SC and Status Data Polling Timing Waveform

6

h–1 cycle*

CE

OE

WE

CDE

SC

I/O0 to I/O7

RES

RDY

/Busy

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111)

t

CES

t

SW

t

CDS

t

CDSH

1

*

SP

1

t

CWC

t

WPH

tWPt

WP

t

CDH

t

AHtAHtSDH

tAStASt

.

OL

t

CDSS

t

SCC

t

SPL

SDS

PD(m) PD(m+1)

tSPt

t

t

CWCtCWCtCWCtCWC

OEWS

t

WPHtWPHtWPHtWPH

t

CDStCDS

t

t

CDH

WP

t

DH

t

WPtWPtWP

tAHt

AHtAHtAH

t

CDSS

t

SCC

t

CDH

t

SPL

t

SDH

tSPt

PD(n+i)*

High-Z High-Z*

WP

t

SCS

t

t

DStAStAStAStAStSDS

10H SA(1) SA(2) CA(1) CA(2) CA(1)' CA(2)'PD(n) PD(n+1)

t

RP

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (1), data can be programmed additionally for each sector before erase.

6. This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64)

*

SP

PD(m+j)*

t

CEHtCE

t

t

OEPS

OE

t

RDY

t

t

WP

t

SW

2

t

DS

2

40H

t

ASP

t

CDH

t

SCHW

t

DH

I/O7=VOLI/O7=V

t

DB

t

DF

3

*

CDS

t

DF

OH

4

Program (1) with CA after SC and Status Data Polling Timing Waveform

6

h cycle*

CE

OE

WE

CDE

SC

I/O0 to I/O7

RES

RDY

/Busy

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111)

t

CES

t

CDS

1

*

SP

PD(k)*

t

SW

t

CDSH

1

t

CWC

t

WPH

t

WPtWP

tAHt

t

AStAS

t

CDSS

t

CDH

AHtSDH

t

SDS

PD(m) PD(m+1)

.

OL

t

SCC

t

SPL

tSPt

PD(m+j)*

t

t

CWCtCWC

OEWS

t

WPHtWPH

t

CDStCDS

t

t

WP

t

AHtAHtSDH

t

DH

t

WP

t

CDSS

t

SCC

t

CDH

t

SPL

tSPt

WP

t

SCS

t

CDH

t

DStAStAStSDS

10H SA(1) SA(2) PD0 PD1 CA(1) CA(2)

t

RP

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (1), data can be programmed additionally for each sector before erase.

6. This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64)

High-Z High-Z*

t

CEHtCE

t

t

OEPS

OE

t

WP

t

SW

2

*

t

SP

DS

2

40H

t

t

CDH

t

SCHW

t

DH

I/O7=VOLI/O7=V

t

DB

ASP

3

*

t

RDY

t

CDS

t

t

DF

DF

OH

4

28

Program (2) and Status Data Polling Timing Waveform

CE

t

OE

WE

CDE

SC

I/O0 to I/O7

RES

RDY

/Busy

CES

t

OEWStCWC

t

CDS

t

SCS

t

RP

t

t

WP

DS

t

WPH

t

CDS

t

CDH

t

DH

t

AStAS

t

CWC

t

WPH

t

t

WP

CDSS

t

WP

t

CDH

SCC

t

SPL

t

t

AH

SDH

t

SDS

t

SPtSP

*

t

t

AH

SA (1) SA (2)

High-Z High-Z

t

CEH

t

OEPS

t

t

WP

SW

t

1

t

DS

t

SCHW

t

DH

CDH

40H1FH PD0 PD1 PD2111 I/O7 = V

t

DB

HN29V25611AT-50H

t

CE

t

t

DF

I/O7 = V

RDY

3

*

OH

t

ASP

t

OE

t

DF

OL

2

*

t

CDS

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

3. The status returns to the standby status after RDY/Busy returns to High-Z.

.

OL

4. By using program (2), the programmed data of each sector must be erased before programming next data.

29

HN29V25611AT-50H

Program (3) and Status Data Polling Timing Waveform

CE

t

OE

WE

CDE

SC

I/O0 to I/O7

RES

RDY

/Busy

CES

t

OEWStCWC

t

CDS

t

SCS

t

RP

t

t

WP

DS

t

WPH

t

CDS

t

CDH

t

t

AStAS

DH

t

CWC

t

t

WP

CDSS

t

WP

t

CDH

SCC

t

SPL

t

t

AH

SDH

t

SDS

t

SPtSP

*

t

t

AH

SA (1) SA (2)

High-Z High-Z

t

CEH

t

OEPS

t

t

WP

SW

t

1

t

DS

t

SCHW

t

DH

CDH

40H0FH PD2048 PD2049 PD2111 I/O7 = V

t

DB

t

ASP

t

CE

t

DF

I/O7 = V

t

RDY

*

t

CDS

OH

3

t

OE

t

DF

OL

2

*

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 64.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

3. The status returns to the standby status after RDY/Busy returns to High-Z.

.

OL

4. By using program (3), the data can be programmed additionally for each sector before erase.

30

Program (4) and Status Data Polling Timing Waveform

CE

t

OE

CES

t

OEWStCWC

t

WPH

t

CWC

t

WPH

WE

t

CDSS

t

WP

t

CDH

t

WSD

SCC

t

SPL

t

t

AH

SDH

t

SPtSP

t

SDS

t

t

AH

t

SW

1

*

CDE

SC

I/O0 to I/O7

t

SCS

t

CDS

t

t

WP

DS

t

CDS

t

CDH

t

DH

t

AStAS

t

WP

SA (1) SA (2)

RES

RDY

t

RP

t

DB

t

t

DB

RS

High-Z High-Z

/Busy

t

RBSY

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

3. The status returns to the standby status after RDY/Busy returns to High-Z.

4. By using program (4), data can be rewritten for each sector.

t

CEH

t

OEPS

t

WP

t

CDH

t

SCHW

t

t

DS

DH

40H11H PD0 PD1 PD2111 I/O7 = V

t

DB

OL

HN29V25611AT-50H

t

CE

t

t

DF

I/O7 = V

RDY

*

OH

3

.

t

ASP

t

OE

t

DF

OL

2

*

t

CDS

31

HN29V25611AT-50H

Program (4) with CA before SC and Status Data Polling Timing Waveform

6

h–1 cycle*

CE

OE

WE

CDE

SC

I/O0 to I/O7

RES

RDY

/Busy

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111)

t

CES

t

SW

tWPt

t

CDS

t

CDSH

1

*

t

SP

AStAStSDS

1

OL

t

CWC

t

WPH

WP

t

t

CDH

t

AHtAHtSDH

.

CDSS

t

SCC

t

SPL

PD(m) PD(m+1)

tSPt

t

t

CWCtCWCtCWCtCWC

OEWS

t

WPHtWPHtWPHtWPH

t

CDStCDS

t

t

WP

t

SCS

t

t

DStAStAStAStAStSDS

11H SA(1) CA(1) CA(2) CA(1)' CA(2)'PD(n+1)

t

RP

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (4), data can be rewritten for each sector.

6. This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64)

t

WP

WPtWPtWP

CDH

t

AHtAHtAHtAH

t

DH

SA(2) PD(n)

t

DB

WSD

t

RBSY

t

CDSS

t

SCC

t

CDHt

t

SPL

t

SDH

tSPt

PD(n+i)*

t

RS

High-Z High-Z*

*

PD(m+j)*

t

CEHtCE

t

t

OEPS

OE

t

RDY

t

t

WP

t

SW

2

t

SP

DS

2

40H

t

ASP

t

CDH

t

SCHW

t

DH

I/O7=VOLI/O7=V

t

DB

t

DF

3

*

CDS

t

DF

OH

4

Program (4) with CA after SC and Status Data Polling Timing Waveform

6

h cycle*

CE

t

CES

OE

t

OEWS

t

CWCtCWC

t

WPHtWPH

WE

t

CDStCDS

t

t

WP

t

AHtAHtSDH

DH

t

WP

t

CDSS

t

CDH

t

SCC

t

WSD

t

SPL

t

SPtSP

CDE

SC

WP

t

SCS

t

CDH

t

DStAStAStSDS

t

I/O0 to I/O7

11H SA(1) PD1 CA(1) CA(2)

RES

t

RP

RDY

/Busy

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is V

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (4), data can be rewritten for each sector.

6. This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64)

SA(2) PD0

t

RBSY

t

DB

t

RS

High-Z High-Z*

t

CDS

1

*

PD(k)*

t

SW

t

CDSH

1

t

CWC

t

WPH

t

WPtWP

tAHt

t

AStAS

t

CDSS

t

CDH

AH

t

SDS

OL

t

SCC

t

SPL

t

SDH

tSPt

PD(m) PD(m+1)

.

PD(m+j)*

t

CEHtCE

t

t

WP

t

SW

2

*

t

t

SP

DS

2

40H

t

DB

t

OEPS

DH

t

CDH

t

SCHW

OE

t

ASP

I/O7=VOLI/O7=V

3

*

t

RDY

t

CDS

t

t

DF

DF

OH

4

32

ID and Status Register Read Timing Waveform

HN29V25611AT-50H

CE

t

CES

OE

t

OEWS

t

OEPS

WE

t

CDS

t

WP

t

CDH

CDE

t

SCHW

SC

t

SCS

t

DS

t

t

DH

OE

t

CDF

I/O0 to I/O7

90H

Manufacturer
code

RES

t

RP

RDY

/Busy

Note: 1. The status returns to the standby at the rising edge of CE.

t

CDAC

t

CDF

Device
code

t

CDOH

t

CDAC

Manufacturer
code

High-Z

t

COH

t

DF

t

COH

1

*

1

*

t

CE

t

SCS

t

OE

Status
register

t

DF

33

HN29V25611AT-50H

Data Recovery Read Timing Waveform

CE

t

CES

OE

t

OEWS

t

OER

WE

DS

t

WP

t

t

DH

CDH

t

t

OEL

t

OES

SP

t

SCC

t

SCC

t

SPL t

t

SAC

t

SAC

t

SH

CDE

SC

t

SCS

t

CDS

t

I/O0 to I/O7

01H FFH

D0out D1out D2111out

RES

RDY

/Busy

Notes: 1. The status returns to the standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceed 2112 in the recovery data read mode.

3. After any commands are written, the status can turns to the standby after the command FFH is input
and CE turns to the V

level.

IH

2

*

t

SACtSAC

t

SH

t

SOH

High

High-Z

t

COH

t

CPH

1

*

t

WP

t

CDS

DF

2

*

t

DS

3

*

t

CEH

t

CDH

t

DH

34

Data Recovery Write Timing Waveform

HN29V25611AT-50H

CE

t

CE

OE

t

OEWS

t

CES

t

CWC

t

WPH

t

CWC

t

WPH

t

CWC

t

WPH

t

CEH

t

OEPS

WE

t

CDE

CDS

WP

t

CDS

t

CDH

t

WP

t

WP

t

CDH

t

CDS

tWPt

t

CDH

t

SCHW

SC

t

SCS

t

t

DH

DS

t

AH

t

AS

t

AH

t

AS

t

DH

t

DS

I/O0 to I/O7

12H SA(1) SA(2)

40H

High

RES

t

High-Z

DB

RDY

/Busy

Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy is VOL.

2. The status returns to the standby status after RDY/Busy returns to High-Z.

t

OE

t

ASP

IO7 = V

1

*

t

RDY

t

CDS

t

DF

OL

IO7 = V

OH

t

DF

2

*

High-Z

35

HN29V25611AT-50H

Clear Status Register Timing Waveform

CE

t

CES

t

1

*

CPH

t

CES

OE

t

OEWS

t

WPH

t

CEH

WE

t

t

CDH

WP

CDE

t

CDS

SC

t

SCS

t

t

DS

DH

I/O0 to I/O7

50H

RES

RDY

High

High-Z

/Busy

Note 1. The status returns to the standby at the rising edge of CE.

t

CDS

t

CDH

t

WP

t

t

DS

DH

Next

Command

t

SCS

t

OEWS

t

CDS

t

CDH

t

WP

tDH

tDS

Next

Command

36

HN29V25611AT-50H

Function Description

Status Register: The HN29V25611AT-50H outputs the operation status data as follows: I/O7 pin outputs a

VOL to indicate that the memory is in either erase or program operation. The level of I/O7 pin turns to a V
when the operation finishes. I/O5 and I/O4 pins output VOLs to indicate that the erase and program operations
complete in a finite time, respectively. If these pins output VOHs, it indicates that these operations have timed
out. If I/O6 pin outputs VOH, it indicates a possibility that can be corrected by ECC, choose data correction by
ECC or not by reading out the data. When these pins monitor, I/O7 pin must turn to a VOH. To execute other
erase and program operation, the status data must be cleared after a time out occurs. From I/O0 to I/O3 pins
are reserved for future use. The pins output VOLs and should be masked out during the status data read mode.
The function of the status register is summarized in the following table.

I/O Flag definition Definition

I/O7 Ready/Busy V
I/O6 Program/Erase ECC

check
I/O5 Erase check VOH = Fail, VOL = Pass
I/O4 Program check VOH = Fail, VOL = Pass
I/O3 Reserved Outputs a VOL and should be masked out during the status data poling mode.
I/O2 Reserved
I/O1 Reserved
I/O0 Reserved

= Ready, VOL = Busy

OH

When I/O7 outputs VOH, VOH = ECC available, VOL = ECC not available.

OH

ECC Applicability

I/O7 I/O6 I/O5 I/O4 System data correction by ECC

V

OH

V

OH

V

OH

V

OH

V

OH

V

OL

V

OH

V

OL

V

OH

V

OH

V

OL

V

OL

V

OL

V

OL

V

OH

V

OH

Needed
Not needed. Sector replacement
Needed
Not needed. Sector replacement

This device needs to be corrected failure data by ECC on system or Spare sectors, by reading out again the
failure sector data when program/erase error occures.

37

HN29V25611AT-50H

Requirement for System

Specifications

Program/Erase Endurance: 3 × 105 cycles

Item Min Typ Max Unit

Usable sectors (initially) 16,057 — 16,834 sector
Spare sectors 290 — — sector
ECC (Error Correction Code) 3 — — bit/sector

38

HN29V25611AT-50H

Unusable Sector

Initially, the HN29V25611AT-50H includes unusable sectors. The unusable sectors must be distinguished
from the usable sectors by the system as follows.

1. Check the partial invalid sectors in the devices on the system. The usable sectors were programmed the
following data. Refer to the flowchart “Indication of unusable sectors”.

Initial Data of Usable Sectors

Column address 0H to 81FH 820H 821H 822H 823H 824H 825H 826H to 83FH

Data FFH 1CH 71H C7H 1CH 71H C7H FFH

2. Do not erase and program to the partial invalid sectors by the system.

START

Sector number = 0

Sector number =

Sector number + 1

Read data

No

Bad sector*

Notes: 1. Refer to table "Initial data of usable sectors".

2

No

2. Bad sectors are installed in system.

Check data*

Yes

Sector number = 16,383

Yes

1

END

The Unusable Sector Indication Flow

Column address = 820H to 825H

39

HN29V25611AT-50H

Requirements for High System Reliability

The device may fail during a program, erase or read operation due to write or erase cycles. The following
architecture will enable high system reliability if a failure occurs.

1. For an error in read operation: An ECC (Error Correction Code) or a similar function which can correct

3-bits per each sectors is required for data reliability. When error occurs, data must not be corrected by
replacing to spare sector.

2. For errors in program or erase operations: The device may fail during a program or erase operation due to

write or erase cycles. The status register indicates if the erase and program operation complete in a finite
time. When an error occured in the sector, try to reprogram the data into another sector. Avoid further
system access to the sector that error happens. Typically, recommended number of a spare sectors are

1.8% (290 sectors (min)) of initial usable 16,057 sectors (min) by each device. For the reprogramming, do
not use the data from the failed sectors, because the data from the failed sectors are not fixed. So the
reprogram data must be the data reloaded from the external buffer, or use the Data recovery read mode or
the Data recovery write mode (see the “Mode Description” and under figure “Spare Sector Replacement
Flow after Program Error”). To avoid consecutive sector failures, choose addresses of spare sectors as far
as possible from the failed sectors. In this case, 105 cycles of program/erase endurance is guaranteed.

3. Prolongation of flash memory life: Due to the life of the memory prolongation, to do ware leveling at

about 5000 each. The write/erase endurance is 3 × 105 cycles under the condition of the 3-bit error
correction and of ware leveling at 5000 each.

40

START

HN29V25611AT-50H

Program start

Program end

Check status

Yes

Set an usable sector

Check RDY/Busy

No

Clear status register

Load data from

external buffer

Data recovery read Data recovery write

Program start

Program end

Check status

Yes

Set another
usable sector

Check RDY/Busy

No

END

Check status: Status register read

Spare Sector Replacement Flow after Program Error

41

HN29V25611AT-50H

For Errors in program or erase operations

The device may fail during a program or erase operation. Failure mode can be confirmed by read out the
status register after complete the erase and program operations. There are two failure modes specified by
each codes:

1: Status register error flag: I/O6 = V

OL

Replace sector under the “Spare Sectors Replacement Flow at Status Register I/O6 Read”. Replacement must
be applied to one sector(2k bytes) which contains failure bits.

2: Status register error flag: I/O6 = V

OH

Escape the program data temporary under the “Replacement Flow at Status Register I/O6 Read”. If failure
data can be corrected by ECC, do not replace to spare sector. If failure data can not be corrected by ECC,
replace to spare sector. Replacement must be applied to one sector(2k bytes) which contains failure bits.

START

Program start

Program end

Check status

Yes

Set an usable sector

Check RDY/Busy

No

Check I/O6

V

OL

Sector Replacement

V

OH

Check status: Status register read
Check I/O6: I/O6 output monitor
Check ECC: Correct by ECC?

Escape program deta*

1

42

Program end

Check status Check ECC

Yes Yes

END

Note: 1. Refer to 'Spare sector replacement flow after program error' to escape the deta.

No

Read error sector

Spare Sectors Replacement Flow at Status Register I/O6 Read

No

Sector Replacement

Program end

Check status

Yes

No

Memory Structure

HN29V25611AT-50H

bit

sector

16,384 sectors

2,112 bytes (16,896 bits)

byte (8 bits)

Bit: Minimum unit of data.

Byte: Input/output data unit in programming and reading. (1 byte = 8 bits)

Sector: Page unit in erase, programming and reading. (1 sector = 2,112 bytes = 16,896 bits)

Device: 1 device = 16,384 sectors.

43

HN29V25611AT-50H

Package Dimensions

HN29V25611AT-50H (TFP-48DA)

12.00

12.40 Max

48

124

0.50

*0.22 ± 0.08

0.20 ± 0.06

1.20 Max

*Dimension including the plating thickness

Base material dimension

0.08

0.45 Max

0.10

25

M

18.40

*0.17 ± 0.05

20.00 ± 0.20

0.125 ± 0.04

0.05 ± 0.05

Hitachi Code
JEDEC
JEITA
Mass

(reference value)

As of January, 2002

Unit: mm

0.80

0˚ – 8˚

0.50 ± 0.10

TFP-48DA
Conforms
Conforms

0.52 g

44

HN29V25611AT-50H

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for

maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

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Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: [phone] Fax: [phone]

URL http://www.hitachisemiconductor.com/

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Fax: <1>[phone]

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Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.

Colophon 5.0

45