RENESAS HIP 4082 IPZ Datasheet [it]

March 1995

TM

HIP4082

80V, 1.25A Peak Current

H-Bridge FET Driver

Features

• Independently Drives 4 N-Channel FET in Half Bridge
or Full Bridge Configurations

• Bootstrap Supply Max Voltage to 95VDC

• Drives 1000pF Load in Free Air at 50

o

C with Rise and

Fall Times of Typically 15ns

• User-Programmable Dead Time (0.1 to 4.5µs)

• DIS (Disable) Overrides Input Control and Refreshes
Bootstrap Capacitor when Pulled Low

• Input Logic Thresholds Compatible with 5V to 15V
Logic Levels

• Shoot-Through Protection

• Undervoltage Protection

Applications

• UPS Systems

• DC Motor Controls

• Full Bridge Power Supplies

• Class D Audio Power Amplifiers

• Noise Cancellation Systems

• Battery Powered Vehicles

• Peripherals

• Medium/Large Voice Coil Motors

• Related Literature

- TB363, Guidelines for Handling and Processing

Moisture Sensitive Surface Mount Devices (SMDs)

Description

The HIP4082 is a medium frequency, medium voltage
H-Bridge N-Channel MOSFET driver IC, available in 16 lead
plastic SOIC (N) and DIP packages.

Specifically targeted for PWM motor control and UPS appli­cations, bridge based designs are made simple and flexible
with the HIP4082 H-bridge driver. With operation up to 80V,
the device is best suited to applications of moderate power
levels.

Similar to the HIP4081, it has a flexible input protocol for
driving every possible switch combination except those
which would cause a shoot-through condition. The
HIP4082’s reduced drive current allows smaller packaging
and it has a much wider range of programmable dead times
(0.1 to 4.5µs) making it ideal for switching frequencies up to
200kHz. The HIP4082 does not contain an internal charge
pump, but does incorporate non-latching level-shift transla­tion control of the upper drive circuits.

This set of features and specifications is optimized for appli­cations where size and cost are important. For applications
needing higher drive capability the HIP4080A and HIP4081A
are recommended.

Ordering Information

PART

NUMBER

HIP4082IB -55oC to +125oC 16 Lead Plastic SOIC (N)
HIP4082IP -55oC to +125oC 16 Lead Plastic DIP

TEMPERATURE

RANGE PACKAGE

Pinout

HIP4082 (PDIP, SOIC)

TOP VIEW

BHO

1

BHB

2

BHI

3

BLI

4

ALI

5

DEL

6

V

SS

AHI

7
8

DIS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143

16
15

BHS
BLO

14
13

ALO
V

12

DD

11

AHS

10

AHO

9

AHB

| Copyright © Intersil Corporation 1999

Application Block Diagram

12V

BHO
BHS

BHI
BLI

ALI
AHI

BLO

HIP4082

ALO
AHS
AHO

GND

1

80V

LOAD

GND

File Number 3676.1

Functional Block Diagram

BHI

2

AHI

7

DIS

8

V

DD

ALI

DEL

BLI

12

DETECTOR

UNDERVOLTAGE

4

5

3

U/V

TURN-ON

DELAY

LEVEL

SHIFT

TURN-ON

DELAY

HIP4082

DRIVER

DRIVER

AHB

9

AHO

10

AHS

11

13

ALO BLO

1

BHB

DRIVER

16

BHO

15

BHS

V

DD

DRIVER

14

LEVEL

SHIFT

TURN-ON

DELAY

TURN-ON

DELAY

U/V

V

6

SS

Typical Application (PWM Mode Switching)

BHO

BHS
BLO
ALO

V

DD

AHS
AHO
AHB

16
15
14
13

12V

12
11
10

9

PWM

INPUT

DELAY RESISTOR

FROM

OPTIONAL

OVERCURRENT

LATCH

12V

GND

DIS

1

BHB

2

BHI

3

BLI

4

ALI

5

DEL

6

V

SS

AHI

7
8

DIS

R

DIS

80V

LOAD

CURRENT CONTROLLER OR

TO OPTIONAL

OVERCURRENT LATCH

+

-

R

SH

2

Specifications HIP4082

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V

Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V

Voltage on AHS, BHS. . . . . .-6V (Transient) to 80V (25oC to 150oC)

Voltage on AHS, BHS. . . . . -6V (Transient) to 70V (-55oC to150oC)

Voltage on AHB, BHB. . . . . . . . .V

AHS, BHS

-0.3V to V

AHS, BHS

+V

Voltage on ALO, BLO. . . . . . . . . . . . . . . . . .VSS -0.3V to VDD +0.3V

Voltage on AHO, BHO . . .V

AHS, BHS

-0.3V to V

AHB, BHB

+0.3V Input

Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-5mA to 0mA

Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V/ns

NOTE: All voltages are relative VSS unless otherwise specified.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +8.5V to +15V

Voltage on VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V

Voltage on AHB, BHB. . . . . . . . V

AHS, BHS

+7.5V to V

AHS, BHS+VDD

Thermal Resistance, Junction-Ambient θ

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115oC/W

DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90oC/W

Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . See Curve

Storage Temperature Range. . . . . . . . . . . . . . . . . .-65oC to +150oC

DD

Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . +150oC

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC

(For SOIC - Lead Tips Only))

Input Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . -4mA to -100µA

JA

Electrical Specifications V

DD

= V

AHB

= V

BHB

= 12V, VSS = V

AHS

= V

BHS

= 0V, R

DEL

= 100K

TJ = -55oC

TJ = +25oC

PARAMETER SYMBOL TEST CONDITIONS

TO +150oC

UNITSMIN TYP MAX MIN MAX

SUPPLY CURRENTS & UNDER VOLTAGE PROTECTION
VDD Quiescent Current I

VDD Operating Current I

AHB, BHB Off Quiescent Current I
AHB, BHB On Quiescent Current I
AHB, BHB Operating Current I

AHBL
AHBH
AHBO

AHS, BHS Leakage Current I

VDD Rising Undervoltage Threshold V
VDD Falling Undervoltage Threshold V

DD

DDO

, I
, I
, I

HLK

DDUV+

DDUV-

All inputs = 0V, R
All inputs = 0V, R

= 100K 1.2 2.3 3.5 0.85 4 mA

DEL

= 10K 2.2 4.0 5.5 1.9 6.0 mA

DEL

f = 50kHz, no load 1.5 2.6 4.0 1.1 4.2 mA
50kHz, no load, R
AHI = BHI = 0V 0.5 1.0 1.5 0.4 1.6 mA

BHBL

AHI = BHI = V

BHBH

f = 50kHz, CL = 1000pF .65 1.1 1.8 .45 2.0 mA

BHBO

V

= V
= V

BHS
BHB

= 80V
= 96

V

AHS
AHB

= 10kΩ 2.5 4.0 6.4 2.1 6.6 mA

DEL

DD

65 145 240 40 250 µA

--1.0--µA

6.8 7.6 8.25 6.5 8.5 V

6.5 7.1 7.8 6.25 8.1 V
Undervoltage Hysteresis UVHYS 0.17 0.4 0.75 0.15 0.90 V
AHB, BHB Undervoltage Threshold VHBUV Referenced to AHS & BHS 5 6.0 7 4.5 7.5 V
INPUT PINS: ALI, BLI, AHI, BHI, & DIS
Low Level Input Voltage V
High Level Input Voltage V

IH

Full Operating Conditions - - 1.0 - 0.8 V

IL

Full Operating Conditions 2.5 - - 2.7 V
Input Voltage Hysteresis -35---mV
Low Level Input Current I
High Level Input Current I

IL
IH

VIN = 0V, Full Operating Conditions -145 -100 -60 -150 -50 µA

VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA
TURN-ON DELAY PIN DEL
Dead Time T

DEAD

R

= 100K 2.5 4.5 8.0 2.0 8.5 µS

DEL

R

= 10K 0.27 0.5 0.75 0.2 0.85 µS

DEL

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, & BHO
Low Level Output Voltage V

OL

High Level Output Voltage VDD-V
Peak Pullup Current IO+V

I

OUT

OHIOUT

OUT

= 50mA 0.65 1.1 0.5 1.2 V
= -50mA 0.7 1.2 0.5 1.3 V

= 0V 1.1 1.4 2.5 0.85 2.75 A

3

Specifications HIP4082

Electrical Specifications V

DD

= V

AHB

= V

BHB

= 12V, VSS = V

PARAMETER SYMBOL TEST CONDITIONS

Peak Pulldown Current IO-V

Switching Specifications V

DD

= V

AHB

= V

BHB

OUT

= 12V, VSS = V

PARAMETER SYMBOL TEST CONDITIONS

Lower Turn-off Propagation Delay

T

LPHL

(ALI-ALO, BLI-BLO)

Upper Turn-off Propagation Delay

T

HPHL

(AHI-AHO, BHI-BHO)

Lower Turn-on Propagation Delay

T

LPLH

(ALI-ALO, BLI-BLO)

Upper Turn-on Propagation Delay

T

HPLH

(AHI-AHO, BHI-BHO)

Rise Time T

R

= V

AHS

BHS

= 0V, R

DEL

= 100K

TJ = -55oC

TJ = +25oC

TO +150oC

UNITSMIN TYP MAX MIN MAX

= 12V 1.0 1.3 2.3 0.75 2.5 A

= V

AHS

BHS

= 0V, R

= 100K, CL = 1000pF.

DEL

TJ = -55oC

TJ = +25oC

TO +150oC

UNITSMIN TYP MAX MIN MAX

- 25 50 - 70 ns

- 55 80 - 100 ns

- 40 85 - 100 ns

- 75 110 - 150 ns

- 9 20 - 25 ns

Fall Time T

Minimum Input Pulse Width T

Output Pulse Response to 50 ns Input Pulse

Disable Turn-off Propagation Delay

PWIN-ON/OFF

T

PWOUT

T

DISLOW

F

- 9 20 - 25 ns

50 - - 50 - ns

63 80 ns

- 50 80 - 90 ns

(DIS - Lower Outputs)

Disable Turn-off Propagation Delay

T

DISHIGH

- 75 100 - 125 ns

(DIS - Upper Outputs)

Disable Turn-on Propagation Delay

T

DLPLH

- 40 70 - 100 ns

(DIS - ALO & BLO)

Disable Turn-on Propagation Delay

T

DHPLH

R

= 10K - 1.2 2 - 3 µs

DEL

(DIS- AHO & BHO)

Refresh Pulse Width (ALO & BLO) T

REF-PW

375 580 900 350 950 ns

TRUTH TABLE

INPUT OUTPUT

ALI, BLI AHI, BHI VDDUV VHBUV DIS ALO, BLO AHO, BHO

XXXX1 0 0

XX1XX 0 0

0X010 0 0

1X0X0 1 0

4

HIP4082

Pin Descriptions

PIN

NUMBER SYMBOL DESCRIPTION

1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin.

2 BHI B High-side Input. Logic lev el input that controls BHO driver (Pin 16). BLI (Pin 3) high le v el input ov errides BHI

high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides
BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal
100µA pull-up to VDD will hold BHI high, so no connection is required if high-side and low-side outputs are to
be controlled by the low-side input.

3 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 14). If BHI (Pin 2) is driven high or not con-

nected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at DEL
(Pin 5). DIS (Pin 8) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V
to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BLI high if this pin is not driven.

4 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not con-

nected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at DEL
(Pin 5). DIS (Pin 8) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V
to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold ALI high if this pin is not driven.

5 DEL Turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the dead time between

drivers. All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by de­laying the turn-on of all drivers. The voltage across the DEL resistor is approximately Vdd -2V.

6VSSChip negative supply, generally will be ground.

7 AHI A High-side Input. Logic lev el input that controls AHO driver (Pin 10). ALI (Pin 4) high le v el input ov errides AHI

high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides
AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal
100µA pull-up to VDD will hold AHI high, so no connection is required if high-side and low-side outputs are to
be controlled by the low-side input.

8 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other in-

puts. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal
levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not
driven.

9 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin.

10 AHO A High-side Output. Connect to gate of A High-side power MOSFET.

11 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of

bootstrap capacitor to this pin.

12 V

13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.

14 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.

15 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of

DD

Positive supply to control logic and lower gate drivers. De-couple this pin to VSS (Pin 6).

bootstrap capacitor to this pin.

16 BHO B High-side Output. Connect to gate of B High-side power MOSFET.

5

Timing Diagrams

X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT

T

LPHL

DIS=0

and UV

XLI

XHI

XLO

XHO

T

HIP4082

HPHL

DIS=0

and UV

XLI

XHI = HI OR NOT CONNECTED

XLO

XHO

T

DLPLH

T

HPLH

T

LPLH

FIGURE 1. INDEPENDENT MODE

FIGURE 2. BISTATE MODE

T

DIS

T

R

(10% - 90%)

T

F

(10% - 90%)

DIS or UV

XLI

XHI

XLO

XHO

T

REF-PW

T

DHPLH

FIGURE 3. DISABLE FUNCTION

6

Performance Curves

HIP4082

3.5

3.25

2.75

2.5

2.25

SUPPLY CURRENT (mA)

DD

I

1.75

1.5

VDD = 16V

3

VDD = 12V

VDD = 10V

2

VDD = 8V

-60 -40 -20 0 20 40 60 80 100 120 140

VDD = 15V

JUNCTION TEMPERATURE (oC)

FIGURE 4. IDD SUPPLY CURRENT vs TEMPERATURE AND

VDD SUPPLY VOLTAGE

8

7

6

5

4

3

2

1

LOADED, NL BIAS CURRENTS (mA)

0

0 50 100 150 200

1000pF LOAD

NO LOAD

FREQUENCY (kHz)

FIGURE 6. FLOATING (IXHB) BIAS CURRENT vs FREQUENCY

AND LOAD

16
15
14
13
12
11
10

9
8
7

SUPPLY CURRENT (mA)

6

DD

I

5
4

-60 -40 -20 0 20 40 60 80 100 120 140
JUNCTION TEMPERATURE (oC)

200kHz

100kHz

50kHz

10kHz

FIGURE 5. VDD SUPPLY CURRENT vs TEMPERATURE AND

SWITCHING FREQUENCY (1000pF LOAD)

2

1.925

1.75

1.5

I

SRC

I

SNK

PEAK GATE CURRENT (A)

)

(BIAS

1.25

(BIAS)

1

0.75

0.815

0.5
8 9 10 11 12 13 14 15

8

SOURCE

SINK

BIAS

BIAS SUPPLY VOLTAGE (V) AT 25oC

FIGURE 7. GATE SOURCE/SINK PEAK CURRENT vs BIAS

SUPPLY VOLTAGE AT 25oC

15

1.2

1.1

1

NORMALIZED GATE

0.9

SINK/SOURCE CURRENT (A)

0.8

-75 -50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (oC)

FIGURE 8. GATE CURRENT vs TEMPERATURE, NORMALIZED

TO 25oC

1.4

-40oC

1.2

(V)

OH

1

-V

DD

V

0.8

0.6

8 9 10 11 12 13 14 15

-55oC

125oC

150oC

VDD SUPPLY VOLTAGE (V)

0oC

25oC

FIGURE 9. VDD-VOH vs BIAS VOLTAGE TEMPERATURE

7

Performance Curves (Continued)

1.4

HIP4082

8

LOWER U/V RESET

7.5

1.2

(V)
V

-55oC

1

OL

0.8
125oC

150oC

0.6

8 9 10 11 12 13 14

-40oC

0oC

VDD SUPPLY VOLTAGE (V)

25oC

15

7

LOWER U/V SET

6.5

6

, BIAS SUPPLY VOLTAGE (V)
V

UPPER U/V SET/RESET

DD

5.5

5

-60 -40 -20 0 20 40 60 80 100 120 140 160
JUNCTION TEMPERATURE (oC)

FIGURE 10. VOL vs BIAS VOLTAGE AND TEMPERATURE FIGURE 11. UNDERVOLTAGE TRIP VOLTAGES vs TEMPERA-

TURE

4

100

90

80

70

60

50

40

PROPAGATION DELAYS (ns)

30

20

-60 -40 -20 0 20 40 60 80 100 120 140 160

UPPER t

ON

UPPER t

OFF

LOWER t

JUNCTION TEMPERATURE (oC)

ON

LOWER t

OFF

FIGURE 12. UPPER LOWER TURN-ON/TURN-OFF PROPAGA-

TION DELAY vs TEMPERATURE

10

DISHTON

1000

DISLTON

DISHTOFF

DISLOFF

JUNCTION TEMPERATURE (oC)

100

DIS TO TURN-ON/OFF TIME (ns)

10

-60 -40 -20 0 20 40 60 80 100 120 140 160

FIGURE 13. UPPER/LOWER DIS(ABLE) TO TURN-ON/OFF vs

TEMPERATURE (oC)

2

1.5

1

LEVEL-SHIFT CURRENT (mA)

0.5
0 20 40 60 80 100

SWITCHING FREQUENCY (kHz)

FIGURE 14. FULL BRIDGE LEVEL-SHIFT CURRENT vs

FREQUENCY (kHz)

2.5

2

16 PIN DIP

1.5
SOIC

1

0.5

TOTAL POWER DISSIPATION (W)

QUIESCENT BIAS COMPONENT

0

-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE (oC)

FIGURE 15. MAXIMUM POWER DISSIPATION vs AMBIENT

TEMPERATURE

8

Performance Curves (Continued)

4

10

HIP4082

90

VDD = 15V

85

VDD = 12V

1000

DEAD TIME (ns)

100

0 10 20 30 40 50 60 70 80 90 100

VDD = 9V

DEAD TIME RESISTANCE (kΩ)

FIGURE 16. DEAD-TIME vs DEL RESISTANCE AND BIAS

SUPPLY (VDD) VOLTAGE

SS

-V

80

XHS

V

75

70

100 50 0 50 100 150

TEMPERATURE (oC)

FIGURE 17. MAXIMUM OPERATING PEAK AHS/BHS VOLTAGE

vs TEMPERATURE

9

Dual-In-Line Plastic Packages (PDIP)

N

D1

-C-

E1

-B-

A1

A2

A

L

e

e

C

S

e

INDEX

AREA

BASE

PLANE

SEATING

PLANE

1 2 3 N/2

-A-

D1

B1

B

D

e

0.010 (0.25) C AMB

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru­sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).

6. E and are measured with the leads constrained to be per-

e

pendicular to datum .

A

-C-

7. eB and eC are measured at the lead tips with the leads uncon­strained. eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

HIP4082

E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

E

C

L

A

C

B

A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.735 0.775 18.66 19.68 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC ­e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169

NOTESMIN MAX MIN MAX

Rev. 0 12/93

10

Small Outline Plastic Packages (SOIC)

HIP4082

N

INDEX
AREA

123

-A-

0.25(0.010) B

E

SEATING PLANE

D

-C-

H

-B-

A

M

L

h x 45

M

o

α

e

B

0.25(0.010) C AMB

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.

A1

0.10(0.004)

S

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC ­H 0.2284 0.2440 5.80 6.20 -

C

h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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