Renesas HD74LV2GT14A User Manual

HD74LV2GT14A

Triple Inverters with Schmitt-trigger Inputs /
CMOS Logic Level Shifter

REJ03D0141–0200Z

(Previous ADE-205-666A (Z))

Rev.2.00

Oct.16.2003

Description

The HD74LV2GT14A has triple inverters with Schmitt-trigger inputs in an 8 pin package. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to

3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.

Features

• The basic gate function is lined up as Renesas uni logic series.

• Supplied on emboss taping for high-speed automatic mounting.

• TTL compatible input level.

Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C

• Logic-level translate function

3.0 V CMOS logic → 5.0 V CMOS logic (@V

1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@V

• All inputs V

All outputs V

• Output current ±6 mA (@V

• All the logical input has hysteresis voltage for the slow transition.

• Ordering Information

(Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

IH

(Max.) = 5.5 V (@VCC = 0 V)

O

= 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)

CC

= 5.0 V)

CC

= 3.3 V)

CC

Part Name Package Type Package Code Package

Abbreviation

HD74LV2GT14AUSE SSOP-8 pin TTP-8DBV US E (3,000 pcs/reel)

Rev.2.00, Oct.16.2003, page 1 of 9

Taping Abbreviation
(Quantity)

HD74LV2GT14A

Outline and Article Indication

• HD74LV2GT14A

Index band

Lot No.

Y M W

T 1 4

SSOP-8

Marking

Y : Year code
(the last digit of year)
M : Month code
W : Week code

Function Table

Input A Output Y

HL
LH
H : High level

L : Low level

Rev.2.00, Oct.16.2003, page 2 of 9

HD74LV2GT14A

Pin Arrangement

1A

3Y

2A

GND

1

2

3

4

8V

CC

71Y

63A

52Y

(Top view)

Absolute Maximum Ratings

Item Symbol Ratings Unit Test Conditions

Supply voltage range V
Input voltage range

*1

*1, 2

Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through

CC

V

I

V

O

IK

OK

O

ICC or I

GND

VCC or GND
Maximum power dissipation

at Ta = 25°C (in still air)

*3

P

T

Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and

furthermore no two of which may be realized at the same time.

1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.

2. This value is limited to 5.5 V maximum.

3. The maximum package power dissipation was calculated using a junction temperature of 150°C.

–0.5 to 7.0 V
–0.5 to 7.0 V
–0.5 to VCC +0.5 Output : H or LOutput voltage range
–0.5 to 7.0

V

VCC : OFF
–20 mA VI < 0
±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V

CC

±50 mA

200 mW

CC

Rev.2.00, Oct.16.2003, page 3 of 9

HD74LV2GT14A

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage range V
Input voltage range V
Output voltage range V
Output current

Operating free-air temperature T

CC

I

O

OL

I

OH

a

Note: Unused or floating inputs must be held high or low.

3.0 5.5 V

05.5V
0VCCV
—6 V
—12 V
—–6 V
— –12

mA

= 3.0 to 3.6 VI

CC

= 4.5 to 5.5 V

CC

= 3.0 to 3.6 V

CC

VCC = 4.5 to 5.5 V

–40 85 °C

Rev.2.00, Oct.16.2003, page 4 of 9

HD74LV2GT14A

Electrical Characteristic

• Ta = –40 to 85°C

Item Symbol VCC (V) * Min Typ Max Unit Test condition

+

Input voltage

V

T

–

V

T

∆V

Output voltage

Input current I
Quiescent

V

OH

V

OL

IN

I

CC

supply current

∆I

CC

Output leakage current I
Input capacitance C

OFF

IN

Note: For conditions shown as Min or Max, use the appropriate values under recommended operating

conditions.

3.0 — — 1.5

V

3.6 — — 1.6

4.5 — — 1.9

5.5 — — 2.1

3.0 0.3 — —

3.6 0.4 — —

4.5 0.5 — —

5.5 0.6 — —

3.0 0.3 — 1.2

T

3.6 0.3 — 1.3

4.5 0.4 — 1.4

5.5 0.4 — 1.5
Min to Max VCC–0.1 — — IOH = –50 µA

V

3.0 2.48 — — IOH = –6 mA

4.5 3.8 — — IOH = –12 mA
Min to Max — — 0.1 IOL = 50 µA

3.0 — — 0.44 IOL = 6 mA

4.5 — — 0.55

IOL = 12 mA

0 to 5.5 — — ±1 µAVIN = 5.5 V or GND

5.5 — — 10 µAVIN = VCC or GND,
= 0

I

O

5.5 — — 1.5 mA One input VIN = 3.4 V,

other input VCC or GND

0——5µAVIN or VO = 0 to 5.5 V

5.0 — 3.0 — pF VIN = VCC or GND

Rev.2.00, Oct.16.2003, page 5 of 9

HD74LV2GT14A

Switching Characteristics

• VCC = 3.3 ± 0.3 V

Ta = 25°C Ta = –40 to 85°C

Item Symbol

t

PLH

delay time

t

PHL

• VCC = 5.0 ±0.5 V

Min Typ Max Min Max

— 7.5 12.5 1.0 14.5 CL = 15 pFPropagation
— 10.0 15.0 1.0 17.0

Unit

ns

Test
Conditions

CL = 50 pF

FROM
(Input)TO(Output)

A or B Y

Ta = 25°C Ta = –40 to 85°C

Item Symbol

t

delay time

t

PLH
PHL

Min Typ Max Min Max

— 5.0 7.6 1.0 9.0 CL = 15 pFPropagation
— 6.5 9.6 1.0 11.0

Operating Characteristics

• CL = 50 pF

Item Symbol V

Power dissipation
capacitance

C

PD

Unit

ns

Test
Conditions

FROM
(Input)TO(Output)

A Y

CL = 50 pF

Ta = 25°C

CC

(V)

Min Typ Max

Unit Test Conditions

5.0 — 10.0 — pF f = 10 MHz

Rev.2.00, Oct.16.2003, page 6 of 9

HD74LV2GT14A

Test Circuit

V

CC

Pulse

Input

generator

50Ω

Note: C includes probe and jig capacitance.

L

Output

C

L

Rev.2.00, Oct.16.2003, page 7 of 9

HD74LV2GT14A

• Waveforms

t

r

90%

90%

t

f

V

I

Input

Output

Vref

10%

50%

t

PHL

VCC (V) Vref

INPUTS

V

I

3.3±0.3 2.5 V

≤
≤

tr / t

f

3.0 ns

3.0 ns

Vref

10%

1.5 V3 V5.0±0.5

50%

50%

t

PLH

Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω.

2. The output are measured one at a time with one transition per measurement.

GND

V

OH

V

OL

Rev.2.00, Oct.16.2003, page 8 of 9

HD74LV2GT14A

Package Dimensions

8 − 0.2

+ 0.1

− 0.05

2.0 ± 0.2

1.5 ± 0.2

(0.5)

(0.5)

(0.5)

2.3 ± 0.1

(0.17)

(0.4)

(0.4)

0.7 ± 0.1

3.1 ± 0.3

Package Code
JEDEC
JEITA
Mass

(reference value)

0 − 0.1

TTP–8DBV




0.010 g

Unit: mm

+ 0.1

− 0.05

0.13

Rev.2.00, Oct.16.2003, page 9 of 9

©

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ales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japa

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