Renesas HD74AC182 User Manual
HD74AC182
Carry Lookahead Generator
REJ03D0258–0200Z
(Previous ADE-205-378 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC182 is a high-speed carry lookahead generator. It is generally used with the HD74AC181 or HD74AC381
4-bit arithmetic logic unit to provide high-speed lookahead over word lengths of more than four bits.
Features
•
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC182FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel)
HD74AC182RPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
G
P
G
P
G
P
GND
1
1
1
2
0
3
0
4
3
5
3
6
7
P
8
(Top view)
16
15
14
13
12
11
10
V
CC
P
2
G
2
C
n
C
n+X
C
n+y
G
9
n+z
C
Rev.2.00, Jul.16.2004, page 1 of 6
HD74AC182
Logic Symbol
P
0
G0P1G
C
n
C
Pin Names
Cn Carry Input
G
, G
0
2
G
1
G
3
P
, P
0
1
P
2
P
3
C
to C
n + x
G Carry Generate Output (Active Low)
P Carry Propagate Output (Active Low)
Carry Generate Inputs (Active Low)
Carry Generate Input (Active Low)
Carry Generate Input (Active Low)
Carry Propagate Inputs (Active Low)
Carry Propagate Input (Active Low)
Carry Propagate Input (Active Low)
Carry Outputs
n + z
n+x
1
C
n+y
P2G
2
P3G
3
G
P
C
n+z
Logic Diagram
C
n
G0P
0
C
n+x
G
1
P
1
C
n+y
G2P
2
C
n+z
G3P
3
GP
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Functional Description
The HD74AC182/HD74ACT182 carry lookahead generator accepts up to four pairs of Active Low Carry Propagate (P
to P3) and Carry Generate (G0 to G3) signals and an Active High Carry input (Cn) and provides anticipated Active High
carries (C
Carry Propagate (P) and Carry Generate (G) outputs which may be used for further level of lookahead. The logic
equations provided at the outputs are:
n + x
, C
n + y
, C
) across four groups of binary adders. The HD74AC182/HD74ACT182 also has Active Low
n + z
0
Rev.2.00, Jul.16.2004, page 2 of 6
HD74AC182
C
= G0 + P0C
n + x
C
= G1 + P1G0 + P1P0C
n + y
C
= G2 + P2G1 + P2P1G0 + P2P1P0C
n + z
G = G
P = P
3P2P1P0
n
n
+ P3G2 + P3P2G1 + P3P2P1G
3
n
0
Also, the HD74AC182/HD74ACT182 can be used with binary ALUs in an active Low or active High input operand
mode. The connections (Figure a) to and from the ALU to the carry lookahead generator are identical in both cases.
Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several
possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by
dropping the last HD74AC182/HD74ACT182.
Truth Table
Inputs Outputs
C
GGGG
n
PPPP
0
GGGG
0
PPPP
1
GGGG
1
PPPP
2
GGGG
2
PPPP
3
XHH L
LHX L
XLX H
HXL H
XXXHH L
XHHHX L
LHXHX L
XXXLX H
XLXXL H
HXLXL H
XXXXXHH L
XXXHHHX L
XHHHXHX L
LHXHXHX L
XXXXXLX H
XXXLXXL H
XLXXLXL H
HXLXLXL H
X XXXXHH H
X XXHHHX H
XHHHXHX H
HHXHXHX H
X XXXXLX L
XXXLXXL L
XLXXLXL L
LXLXLXL L
HXXX H
XHXX H
XXHX H
XXXH H
LLLL L
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
C
3
n + x
C
n + y
C
n + z
GGGGP
P
PP
Rev.2.00, Jul.16.2004, page 3 of 6
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