Renesas H8 Series, H8/36094F, HD64F36094, HD64F36094G, H8/36092F Hardware Manual

To our customers,

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User’s Manual

16

H8/36094 Group

Hardware Manual

Renesas 16-Bit Single-Chip
Microcomputer
H8 Family/H8/300H Tiny Series

H8/36094F HD64F36094
HD64F36094G
H8/36092F HD64F36092
HD64F36092G

Rev.1.00 2006.08

Rev. 1.00 Aug. 28, 2006 Page ii of xxviii

Keep safety first in your circuit designs!

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Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

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Rev. 1.00 Aug. 28, 2006 Page iii of xxviii

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 1.00 Aug. 28, 2006 Page iv of xxviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 1.00 Aug. 28, 2006 Page v of xxviii

Preface

The H8/36094 Group are single-chip microcomputers made up of the high-speed H8/300H CPU
employing Renesas Technology original architecture as their cores, and the peripheral functions
required to configure a system. The H8/300H CPU has an instruction set that is compatible with
the H8/300 CPU.

Target Users: This manual was written for users who will be using the H8/36094 Group in the

design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8/36094 Group to the target users.
Refer to the H8/300H Series Software Manual for a detailed description of the
instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8/300H Series Software Manual.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 19,
List of Registers.

Example: Bit order: The MSB is on the left and the LSB is on the right.

Notes:

When using the on-chip emulator (E7, E8) for H8/36094 program development and debugging,
the following restrictions must be noted.

1. The NMI pin is reserved for the E7 or E8, and cannot be used.

2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be
provided on the user board.

3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user.

4. Area H'F780 to H'FB7F must on no account be accessed.

Rev. 1.00 Aug. 28, 2006 Page vi of xxviii

5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use
by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break
control registers must not be accessed.

6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and
P87 are input pins, and P86 is an output pin.

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/

H8/36094 Group manuals:

Document Title Document No.

H8/36094 Group Hardware Manual This manual

H8/300H Series Software Manual REJ09B0213

User's manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual

H8S, H8/300 Series Simulator/Debugger User's Manual REJ10B0211

H8S, H8/300 Series High-Performance Embedded Workshop 3, Tutorial REJ10B0024

H8S, H8/300 Series High-Performance Embedded Workshop 3, User's Manual REJ10B0026

REJ10B0058

Application notes:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464

Single Power Supply F-ZTATTM On-Board Programming REJ05B0520

Rev. 1.00 Aug. 28, 2006 Page vii of xxviii

Rev. 1.00 Aug. 28, 2006 Page viii of xxviii

Contents

Section 1 Overview................................................................................................1

1.1 Features.................................................................................................................................. 1

1.2 Internal Block Diagram..........................................................................................................3

1.3 Pin Assignments..................................................................................................................... 4

1.4 Pin Functions .........................................................................................................................6

Section 2 CPU........................................................................................................9

2.1 Address Space and Memory Map ........................................................................................ 10

2.2 Register Configuration......................................................................................................... 11

2.2.1 General Registers.................................................................................................... 12

2.2.2 Program Counter (PC) ............................................................................................ 13

2.2.3 Condition-Code Register (CCR)............................................................................. 13

2.3 Data Formats........................................................................................................................ 15

2.3.1 General Register Data Formats............................................................................... 15

2.3.2 Memory Data Formats ............................................................................................ 17

2.4 Instruction Set ...................................................................................................................... 18

2.4.1 Table of Instructions Classified by Function .......................................................... 18

2.4.2 Basic Instruction Formats ....................................................................................... 27

2.5 Addressing Modes and Effective Address Calculation........................................................ 28

2.5.1 Addressing Modes ..................................................................................................28

2.5.2 Effective Address Calculation ................................................................................ 32

2.6 Basic Bus Cycle ................................................................................................................... 34

2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 34

2.6.2 On-Chip Peripheral Modules .................................................................................. 35

2.7 CPU States ........................................................................................................................... 36

2.8 Usage Notes ......................................................................................................................... 37

2.8.1 Notes on Data Access to Empty Areas ................................................................... 37

2.8.2 EEPMOV Instruction.............................................................................................. 37

2.8.3 Bit Manipulation Instruction................................................................................... 37

Section 3 Exception Handling .............................................................................43

3.1 Exception Sources and Vector Address ............................................................................... 43

3.2 Register Descriptions...........................................................................................................45

3.2.1 Interrupt Edge Select Register 1 (IEGR1) ..............................................................45

3.2.2 Interrupt Edge Select Register 2 (IEGR2) ..............................................................46

3.2.3 Interrupt Enable Register 1 (IENR1) ...................................................................... 47

Rev. 1.00 Aug. 28, 2006 Page ix of xxviii

3.2.4 Interrupt Flag Register 1 (IRR1)............................................................................. 48

3.2.5 Wakeup Interrupt Flag Register (IWPR) ................................................................ 49

3.3 Reset Exception Handling.................................................................................................... 51

3.4 Interrupt Exception Handling .............................................................................................. 51

3.4.1 External Interrupts .................................................................................................. 51

3.4.2 Internal Interrupts ................................................................................................... 53

3.4.3 Interrupt Handling Sequence .................................................................................. 53

3.4.4 Interrupt Response Time......................................................................................... 54

3.5 Usage Notes ......................................................................................................................... 56

3.5.1 Interrupts after Reset............................................................................................... 56

3.5.2 Notes on Stack Area Use ........................................................................................ 56

3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 56

Section 4 Address Break .....................................................................................57

4.1 Register Descriptions...........................................................................................................57

4.1.1 Address Break Control Register (ABRKCR) ......................................................... 58

4.1.2 Address Break Status Register (ABRKSR) ............................................................ 59

4.1.3 Break Address Registers (BARH, BARL).............................................................. 60

4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 60

4.2 Operation ............................................................................................................................. 60

Section 5 Clock Pulse Generators .......................................................................63

5.1 Features................................................................................................................................ 64

5.2 Register Descriptions...........................................................................................................64

5.2.1 RC Control Register (RCCR) ................................................................................. 65

5.2.2 RC Trimming Data Protect Register (RCTRMDPR).............................................. 66

5.2.3 RC Trimming Data Register (RCTRMDR)............................................................ 67

5.2.4 Clock Control/Status Register (CKCSR)................................................................ 68

5.3 System Clock Select Operation ........................................................................................... 70

5.3.1 Clock Control Operation......................................................................................... 71

5.3.2 Clock Switching Timing......................................................................................... 74

5.4 Trimming of On-Chip Oscillator Frequency........................................................................ 77

5.5 External Clock Oscillators ................................................................................................... 79

5.5.1 Connecting Crystal Resonator ................................................................................ 79

5.5.2 Connecting Ceramic Resonator .............................................................................. 80

5.5.3 Inputting External Clock......................................................................................... 80

5.6 Subclock Oscillator.............................................................................................................. 81

5.6.1 Connecting 32.768-kHz Crystal Resonator ............................................................ 81

5.6.2 Pin Connection when Not Using Subclock............................................................. 82

5.7 Prescaler............................................................................................................................... 82

Rev. 1.00 Aug. 28, 2006 Page x of xxviii

5.7.1 Prescaler S .............................................................................................................. 82

5.7.2 Prescaler W............................................................................................................. 82

5.8 Usage Notes ......................................................................................................................... 83

5.8.1 Note on Resonators................................................................................................. 83

5.8.2 Notes on Board Design ........................................................................................... 83

Section 6 Power-Down Modes ............................................................................85

6.1 Register Descriptions...........................................................................................................85

6.1.1 System Control Register 1 (SYSCR1) .................................................................... 85

6.1.2 System Control Register 2 (SYSCR2) .................................................................... 87

6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 88

6.2 Mode Transitions and States of LSI..................................................................................... 89

6.2.1 Sleep Mode ............................................................................................................. 92

6.2.2 Standby Mode......................................................................................................... 92

6.2.3 Subsleep Mode........................................................................................................ 93

6.2.4 Subactive Mode ...................................................................................................... 93

6.3 Operating Frequency in Active Mode.................................................................................. 94

6.4 Direct Transition .................................................................................................................. 94

6.4.1 Direct Transition from Active Mode to Subactive Mode ....................................... 94

6.4.2 Direct Transition from Subactive Mode to Active Mode ....................................... 95

6.5 Module Standby Function.................................................................................................... 95

Section 7 ROM ....................................................................................................97

7.1 Block Configuration.............................................................................................................98

7.2 Register Descriptions...........................................................................................................99

7.2.1 Flash Memory Control Register 1 (FLMCR1)........................................................ 99

7.2.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 100

7.2.3 Erase Block Register 1 (EBR1) ............................................................................ 101

7.2.4 Flash Memory Power Control Register (FLPWCR)............................................. 102

7.2.5 Flash Memory Enable Register (FENR)............................................................... 102

7.3 On-Board Programming Modes......................................................................................... 103

7.3.1 Boot Mode ............................................................................................................ 103

7.3.2 Programming/Erasing in User Program Mode...................................................... 106

7.4 Flash Memory Programming/Erasing................................................................................ 107

7.4.1 Program/Program-Verify ...................................................................................... 107

7.4.2 Erase/Erase-Verify................................................................................................ 109

7.4.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 110

7.5 Program/Erase Protection .................................................................................................. 112

7.5.1 Hardware Protection .............................................................................................112

7.5.2 Software Protection............................................................................................... 112

Rev. 1.00 Aug. 28, 2006 Page xi of xxviii

7.5.3 Error Protection .................................................................................................... 112

7.6 Programmer Mode ............................................................................................................. 113

7.7 Power-Down States for Flash Memory.............................................................................. 113

Section 8 RAM ..................................................................................................115

Section 9 I/O Ports.............................................................................................117

9.1 Port 1.................................................................................................................................. 117

9.1.1 Port Mode Register 1 (PMR1) .............................................................................. 118

9.1.2 Port Control Register 1 (PCR1) ............................................................................ 119

9.1.3 Port Data Register 1 (PDR1) ................................................................................ 120

9.1.4 Port Pull-Up Control Register 1 (PUCR1)............................................................ 120

9.1.5 Pin Functions ........................................................................................................ 121

9.2 Port 2.................................................................................................................................. 123

9.2.1 Port Control Register 2 (PCR2) ............................................................................ 123

9.2.2 Port Data Register 2 (PDR2) ................................................................................ 124

9.2.3 Pin Functions ........................................................................................................ 124

9.3 Port 5.................................................................................................................................. 125

9.3.1 Port Mode Register 5 (PMR5) .............................................................................. 126

9.3.2 Port Control Register 5 (PCR5) ............................................................................ 127

9.3.3 Port Data Register 5 (PDR5) ................................................................................ 128

9.3.4 Port Pull-Up Control Register 5 (PUCR5)............................................................ 128

9.3.5 Pin Functions ........................................................................................................ 129

9.4 Port 7.................................................................................................................................. 131

9.4.1 Port Control Register 7 (PCR7) ............................................................................ 132

9.4.2 Port Data Register 7 (PDR7) ................................................................................ 132

9.4.3 Pin Functions ........................................................................................................ 133

9.5 Port 8.................................................................................................................................. 134

9.5.1 Port Control Register 8 (PCR8) ............................................................................ 135

9.5.2 Port Data Register 8 (PDR8) ................................................................................ 135

9.5.3 Pin Functions ........................................................................................................ 136

9.6 Port B................................................................................................................................. 139

9.6.1 Port Data Register B (PDRB) ............................................................................... 139

9.7 Port C................................................................................................................................. 140

9.7.1 Port Control Register C (PCRC)........................................................................... 140

9.7.2 Port Data Register C (PDRC) ............................................................................... 141

9.7.3 Pin Functions ........................................................................................................ 141

Rev. 1.00 Aug. 28, 2006 Page xii of xxviii

Section 10 Timer A............................................................................................143

10.1 Features.............................................................................................................................. 143

10.2 Input/Output Pins...............................................................................................................144

10.3 Register Descriptions......................................................................................................... 145

10.3.1 Timer Mode Register A (TMA)............................................................................ 145

10.3.2 Timer Counter A (TCA) ....................................................................................... 146

10.4 Operation ........................................................................................................................... 147

10.4.1 Interval Timer Operation ...................................................................................... 147

10.4.2 Clock Time Base Operation.................................................................................. 147

10.4.3 Clock Output......................................................................................................... 147

10.5 Usage Note......................................................................................................................... 147

Section 11 Timer V............................................................................................149

11.1 Features.............................................................................................................................. 149

11.2 Input/Output Pins...............................................................................................................151

11.3 Register Descriptions......................................................................................................... 151

11.3.1 Timer Counter V (TCNTV) .................................................................................. 151

11.3.2 Time Constant Registers A and B (TCORA, TCORB) ........................................ 152

11.3.3 Timer Control Register V0 (TCRV0) ...................................................................152

11.3.4 Timer Control/Status Register V (TCSRV) .......................................................... 154

11.3.5 Timer Control Register V1 (TCRV1) ...................................................................155

11.4 Operation ........................................................................................................................... 156

11.4.1 Timer V Operation................................................................................................ 156

11.5 Timer V Application Examples ......................................................................................... 159

11.5.1 Pulse Output with Arbitrary Duty Cycle............................................................... 159

11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input ..............160

11.6 Usage Notes ....................................................................................................................... 161

Section 12 Timer W...........................................................................................163

12.1 Features.............................................................................................................................. 163

12.2 Input/Output Pins...............................................................................................................166

12.3 Register Descriptions......................................................................................................... 166

12.3.1 Timer Mode Register W (TMRW) ....................................................................... 167

12.3.2 Timer Control Register W (TCRW) ..................................................................... 168

12.3.3 Timer Interrupt Enable Register W (TIERW) ...................................................... 169

12.3.4 Timer Status Register W (TSRW) ........................................................................ 170

12.3.5 Timer I/O Control Register 0 (TIOR0) ................................................................. 171

12.3.6 Timer I/O Control Register 1 (TIOR1) ................................................................. 173

12.3.7 Timer Counter (TCNT)......................................................................................... 174

Rev. 1.00 Aug. 28, 2006 Page xiii of xxviii

12.3.8 General Registers A to D (GRA to GRD)............................................................. 175

12.4 Operation ........................................................................................................................... 176

12.4.1 Normal Operation ................................................................................................. 176

12.4.2 PWM Operation .................................................................................................... 181

12.5 Operation Timing............................................................................................................... 186

12.5.1 TCNT Count Timing ............................................................................................ 186

12.5.2 Output Compare Output Timing........................................................................... 186

12.5.3 Input Capture Timing ........................................................................................... 187

12.5.4 Timing of Counter Clearing by Compare Match .................................................. 188

12.5.5 Buffer Operation Timing ...................................................................................... 188

12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ................................. 189

12.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................. 190

12.5.8 Timing of Status Flag Clearing............................................................................. 190

12.6 Usage Notes ....................................................................................................................... 191

Section 13 Watchdog Timer.............................................................................. 195

13.1 Features.............................................................................................................................. 195

13.2 Register Descriptions......................................................................................................... 196

13.2.1 Timer Control/Status Register WD (TCSRWD) .................................................. 196

13.2.2 Timer Counter WD (TCWD)................................................................................ 197

13.2.3 Timer Mode Register WD (TMWD) .................................................................... 198

13.3 Operation ........................................................................................................................... 199

Section 14 Serial Communication Interface 3 (SCI3)....................................... 201

14.1 Features.............................................................................................................................. 201

14.2 Input/Output Pins...............................................................................................................203

14.3 Register Descriptions......................................................................................................... 203

14.3.1 Receive Shift Register (RSR) ............................................................................... 204

14.3.2 Receive Data Register (RDR)............................................................................... 204

14.3.3 Transmit Shift Register (TSR) .............................................................................. 204

14.3.4 Transmit Data Register (TDR).............................................................................. 204

14.3.5 Serial Mode Register (SMR) ................................................................................ 205

14.3.6 Serial Control Register 3 (SCR3) ......................................................................... 206

14.3.7 Serial Status Register (SSR) ................................................................................. 208

14.3.8 Bit Rate Register (BRR) ....................................................................................... 210

14.4 Operation in Asynchronous Mode ..................................................................................... 215

14.4.1 Clock..................................................................................................................... 215

14.4.2 SCI3 Initialization................................................................................................. 216

14.4.3 Data Transmission ................................................................................................ 217

14.4.4 Serial Data Reception ........................................................................................... 219

Rev. 1.00 Aug. 28, 2006 Page xiv of xxviii

14.5 Operation in Clocked Synchronous Mode......................................................................... 223

14.5.1 Clock..................................................................................................................... 223

14.5.2 SCI3 Initialization ................................................................................................. 224

14.5.3 Serial Data Transmission ...................................................................................... 224

14.5.4 Serial Data Reception (Clocked Synchronous Mode)........................................... 227

14.5.5 Simultaneous Serial Data Transmission and Reception........................................ 229

14.6 Multiprocessor Communication Function.......................................................................... 231

14.6.1 Multiprocessor Serial Data Transmission ............................................................. 233

14.6.2 Multiprocessor Serial Data Reception .................................................................. 234

14.7 Interrupts............................................................................................................................ 238

14.8 Usage Notes ....................................................................................................................... 238

14.8.1 Break Detection and Processing ........................................................................... 238

14.8.2 Mark State and Break Sending.............................................................................. 239

14.8.3 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) ..................................................................... 239

14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous

Mode..................................................................................................................... 239

Section 15 I2C Bus Interface 2 (IIC2) ................................................................241

15.1 Features.............................................................................................................................. 241

15.2 Input/Output Pins...............................................................................................................243

15.3 Register Descriptions......................................................................................................... 244

15.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 244

15.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 247

15.3.3 I2C Bus Mode Register (ICMR)............................................................................ 249

15.3.4 I2C Bus Interrupt Enable Register (ICIER)........................................................... 251

15.3.5 I2C Bus Status Register (ICSR)............................................................................. 253

15.3.6 Slave Address Register (SAR).............................................................................. 255

15.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 256

15.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 256

15.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 256

15.4 Operation ........................................................................................................................... 257

15.4.1 I2C Bus Format...................................................................................................... 257

15.4.2 Master Transmit Operation ................................................................................... 258

15.4.3 Master Receive Operation..................................................................................... 260

15.4.4 Slave Transmit Operation ..................................................................................... 262

15.4.5 Slave Receive Operation....................................................................................... 264

15.4.6 Clocked Synchronous Serial Format..................................................................... 266

15.4.7 Noise Canceler ...................................................................................................... 268

15.4.8 Example of Use..................................................................................................... 269

Rev. 1.00 Aug. 28, 2006 Page xv of xxviii

15.5 Interrupt Request................................................................................................................ 273

15.6 Bit Synchronous Circuit..................................................................................................... 273

15.7 Usage Notes ....................................................................................................................... 274

15.7.1 Issue (Retransmission) of Start/Stop Conditions .................................................. 274

15.7.2 WAIT Setting in I2C Bus Mode Register (ICMR)................................................ 274

Section 16 A/D Converter ................................................................................. 275

16.1 Features.............................................................................................................................. 275

16.2 Input/Output Pins...............................................................................................................277

16.3 Register Descriptions......................................................................................................... 278

16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 278

16.3.2 A/D Control/Status Register (ADCSR) ................................................................ 279

16.3.3 A/D Control Register (ADCR) ............................................................................. 281

16.4 Operation ........................................................................................................................... 282

16.4.1 Single Mode.......................................................................................................... 282

16.4.2 Scan Mode ............................................................................................................ 282

16.4.3 Input Sampling and A/D Conversion Time .......................................................... 283

16.4.4 External Trigger Input Timing.............................................................................. 284

16.5 A/D Conversion Accuracy Definitions.............................................................................. 285

16.6 Usage Notes ....................................................................................................................... 287

16.6.1 Permissible Signal Source Impedance .................................................................. 287

16.6.2 Influences on Absolute Accuracy ......................................................................... 287

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection

Circuits ............................................................................................289

17.1 Features.............................................................................................................................. 290

17.2 Register Descriptions......................................................................................................... 292

17.2.1 Low-Voltage-Detection Control Register (LVDCR)............................................ 292

17.2.2 Low-Voltage-Detection Status Register (LVDSR)............................................... 293

17.2.3 Reset Source Decision Register (LVDRF) ........................................................... 294

17.3 Operations.......................................................................................................................... 295

17.3.1 Power-On Reset Circuit ........................................................................................ 295

17.3.2 Low-Voltage Detection Circuit............................................................................. 296

17.3.3 Deciding Reset Source.......................................................................................... 299

Section 18 Power Supply Circuit ......................................................................301

18.1 When Using Internal Power Supply Step-Down Circuit ................................................... 301

18.2 When Not Using Internal Power Supply Step-Down Circuit............................................. 302

Rev. 1.00 Aug. 28, 2006 Page xvi of xxviii

Section 19 List of Registers ...............................................................................303

19.1 Register Addresses (Address Order).................................................................................. 304

19.2 Register Bits....................................................................................................................... 309

19.3 Registers States in Each Operating Mode.......................................................................... 313

Section 20 Electrical Characteristics .................................................................317

20.1 Absolute Maximum Ratings .............................................................................................. 317

20.2 Electrical Characteristics.................................................................................................... 317

20.2.1 Power Supply Voltage and Operating Ranges ...................................................... 317

20.2.2 DC Characteristics ................................................................................................320

20.2.3 AC Characteristics ................................................................................................325

20.2.4 A/D Converter Characteristics .............................................................................. 330

20.2.5 Watchdog Timer Characteristics........................................................................... 331

20.2.6 Flash Memory Characteristics .............................................................................. 332

20.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ................... 334

20.2.8 Power-On Reset Circuit Characteristics (Optional) .............................................. 334

20.3 Operation Timing............................................................................................................... 335

20.4 Output Load Condition ...................................................................................................... 337

Appendix A Instruction Set ...............................................................................339

A.1 Instruction List................................................................................................................... 339

A.2 Operation Code Map.......................................................................................................... 354

A.3 Number of Execution States .............................................................................................. 357

A.4 Combinations of Instructions and Addressing Modes ....................................................... 368

Appendix B I/O Port Block Diagrams...............................................................369

B.1 I/O Port Block Diagrams.................................................................................................... 369

B.2 Port States in Each Operating State ................................................................................... 388

Appendix C Product Code Lineup.....................................................................389

Appendix D Package Dimensions .....................................................................390

Appendix E Function Comparison ....................................................................396

Index .........................................................................................................397

Rev. 1.00 Aug. 28, 2006 Page xvii of xxviii

Rev. 1.00 Aug. 28, 2006 Page xviii of xxviii

Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram of H8/36094 Group of F-ZTATTM.......................................... 3

Figure 1.2 Pin Assignments of H8/36094 Group of F-ZTATTM (FP-64K, FP-64A)...................... 4

Figure 1.3 Pin Assignments of H8/36094 Group of F-ZTATTM (FP-48F, FP-48B, TNP-48) ........ 5

Section 2 CPU

Figure 2.1 Memory map ...............................................................................................................10

Figure 2.2 CPU Registers .............................................................................................................11

Figure 2.3 Usage of General Registers .........................................................................................12

Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 13

Figure 2.5 General Register Data Formats (1).............................................................................. 15

Figure 2.5 General Register Data Formats (2).............................................................................. 16

Figure 2.6 Memory Data Formats.................................................................................................17

Figure 2.7 Instruction Formats......................................................................................................28

Figure 2.8 Branch Address Specification in Memory Indirect Mode........................................... 31

Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 34

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access).....................................35

Figure 2.11 CPU Operation States................................................................................................ 36

Figure 2.12 State Transitions........................................................................................................ 37

Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same

Address...................................................................................................................... 38

Section 3 Exception Handling

Figure 3.1 Reset Sequence............................................................................................................ 52

Figure 3.2 Stack Status after Exception Handling........................................................................ 54

Figure 3.3 Interrupt Sequence....................................................................................................... 55

Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 56

Section 4 Address Break

Figure 4.1 Block Diagram of Address Break................................................................................57

Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 61

Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 61

Section 5 Clock Pulse Generators

Figure 5.1 Block Diagram of Clock Pulse Generators..................................................................63

Figure 5.2 State Transition of System Clock................................................................................ 70

Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled................................... 71

Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1)

(From On-Chip Oscillator Clock to External Clock) ................................................72

Rev. 1.00 Aug. 28, 2006 Page xix of xxviii

Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2)

(From External Clock to On-Chip Oscillator Clock).................................................. 73

Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock.......... 74

Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock ...............75

Figure 5.8 External Oscillation Backup Timing........................................................................... 76

Figure 5.9 Example of Trimming Flow for On-Chip Oscillator Clock ........................................77

Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency .................................. 78

Figure 5.11 Example of Connection to Crystal Resonator ........................................................... 79

Figure 5.12 Equivalent Circuit of Crystal Resonator....................................................................79

Figure 5.13 Example of Connection to Ceramic Resonator ......................................................... 80

Figure 5.14 Example of External Clock Input.............................................................................. 80

Figure 5.15 Block Diagram of Subclock Oscillator...................................................................... 81

Figure 5.16 Typical Connection to 32.768-kHz Crystal Resonator.............................................. 81

Figure 5.17 Equivalent Circuit of 32.768-kHz Crystal Resonator................................................ 81

Figure 5.18 Pin Connection when not Using Subclock ................................................................ 82

Figure 5.19 Example of Incorrect Board Design.......................................................................... 83

Section 6 Power-Down Modes

Figure 6.1 Mode Transition Diagram ........................................................................................... 89

Section 7 ROM

Figure 7.1 Flash Memory Block Configuration............................................................................98

Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode.......................... 106

Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 108

Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 111

Section 9 I/O Ports

Figure 9.1 Port 1 Pin Configuration............................................................................................ 117

Figure 9.2 Port 2 Pin Configuration............................................................................................ 123

Figure 9.3 Port 5 Pin Configuration............................................................................................ 125

Figure 9.4 Port 7 Pin Configuration............................................................................................ 131

Figure 9.5 Port 8 Pin Configuration............................................................................................ 134

Figure 9.6 Port B Pin Configuration...........................................................................................139

Figure 9.7 Port C Pin Configuration...........................................................................................140

Section 10 Timer A

Figure 10.1 Block Diagram of Timer A .....................................................................................144

Section 11 Timer V

Figure 11.1 Block Diagram of Timer V .....................................................................................150

Figure 11.2 Increment Timing with Internal Clock.................................................................... 157

Figure 11.3 Increment Timing with External Clock................................................................... 157

Figure 11.4 OVF Set Timing...................................................................................................... 157

Rev. 1.00 Aug. 28, 2006 Page xx of xxviii

Figure 11.5 CMFA and CMFB Set Timing................................................................................ 158

Figure 11.6 TMOV Output Timing ............................................................................................158

Figure 11.7 Clear Timing by Compare Match............................................................................ 158

Figure 11.8 Clear Timing by TMRIV Input ...............................................................................159

Figure 11.9 Pulse Output Example............................................................................................. 159

Figure 11.10 Example of Pulse Output Synchronized to TRGV Input.......................................160

Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 161

Figure 11.12 Contention between TCORA Write and Compare Match..................................... 162

Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 162

Section 12 Timer W

Figure 12.1 Timer W Block Diagram......................................................................................... 165

Figure 12.2 Free-Running Counter Operation............................................................................ 176

Figure 12.3 Periodic Counter Operation..................................................................................... 177

Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 177

Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................178

Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................178

Figure 12.7 Input Capture Operating Example........................................................................... 179

Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 180

Figure 12.9 PWM Mode Example (1) ........................................................................................ 181

Figure 12.10 PWM Mode Example (2) ......................................................................................182

Figure 12.11 Buffer Operation Example (Output Compare) ......................................................183

Figure 12.12 PWM Mode Example

(TOB, TOC, and TOD = 0: initial output values are set to 0)............................... 184

Figure 12.13 PWM Mode Example

(TOB, TOC, and TOD = 1: initial output values are set to 1)............................... 185

Figure 12.14 Count Timing for Internal Clock Source............................................................... 186

Figure 12.15 Count Timing for External Clock Source.............................................................. 186

Figure 12.16 Output Compare Output Timing ...........................................................................187

Figure 12.17 Input Capture Input Signal Timing........................................................................ 187

Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 188

Figure 12.19 Buffer Operation Timing (Compare Match)..........................................................188

Figure 12.20 Buffer Operation Timing (Input Capture) .............................................................189

Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match.................................. 189

Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 190

Figure 12.23 Timing of Status Flag Clearing by CPU................................................................190

Figure 12.24 Contention between TCNT Write and Clear .........................................................191

Figure 12.25 Internal Clock Switching and TCNT Operation.................................................... 192

Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at

the Same Timing ................................................................................................... 193

Rev. 1.00 Aug. 28, 2006 Page xxi of xxviii

Section 13 Watchdog Timer

Figure 13.1 Block Diagram of Watchdog Timer........................................................................ 195

Figure 13.2 Watchdog Timer Operation Example...................................................................... 199

Section 14 Serial Communication Interface 3 (SCI3)

Figure 14.1 Block Diagram of SCI3........................................................................................... 202

Figure 14.2 Data Format in Asynchronous Communication...................................................... 215

Figure 14.3 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 215

Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 216

Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ...........................................................................217

Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 218

Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ...........................................................................219

Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)...................... 221

Figure 14.8 Sample Serial Reception Data Flowchart (2) ..........................................................222

Figure 14.9 Data Format in Clocked Synchronous Communication ..........................................223

Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode......225

Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)................ 226

Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............... 227

Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)......................228

Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

(Clocked Synchronous Mode) .............................................................................. 230

Figure 14.15 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A).......................................... 232

Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart........................................ 233

Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 235

Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 236

Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)............................. 237

Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 240

Section 15 I2C Bus Interface 2 (IIC2)

Figure 15.1 Block Diagram of I2C Bus Interface 2..................................................................... 242

Figure 15.2 External Circuit Connections of I/O Pins................................................................ 243

Figure 15.3 I2C Bus Formats ...................................................................................................... 257

Figure 15.4 I2C Bus Timing........................................................................................................ 257

Figure 15.5 Master Transmit Mode Operation Timing (1)......................................................... 259

Figure 15.6 Master Transmit Mode Operation Timing (2)......................................................... 259

Figure 15.7 Master Receive Mode Operation Timing (1) .......................................................... 261

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Figure 15.8 Master Receive Mode Operation Timing (2)........................................................... 262

Figure 15.9 Slave Transmit Mode Operation Timing (1)........................................................... 263

Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 264

Figure 15.11 Slave Receive Mode Operation Timing (1)........................................................... 265

Figure 15.12 Slave Receive Mode Operation Timing (2)........................................................... 265

Figure 15.13 Clocked Synchronous Serial Transfer Format....................................................... 266

Figure 15.14 Transmit Mode Operation Timing.........................................................................267

Figure 15.15 Receive Mode Operation Timing ..........................................................................268

Figure 15.16 Block Diagram of Noise Conceler.........................................................................268

Figure 15.17 Sample Flowchart for Master Transmit Mode.......................................................269

Figure 15.18 Sample Flowchart for Master Receive Mode ........................................................ 270

Figure 15.19 Sample Flowchart for Slave Transmit Mode......................................................... 271

Figure 15.20 Sample Flowchart for Slave Receive Mode .......................................................... 272

Figure 15.21 The Timing of the Bit Synchronous Circuit .......................................................... 274

Section 16 A/D Converter

Figure 16.1 Block Diagram of A/D Converter ...........................................................................276

Figure 16.2 A/D Conversion Timing.......................................................................................... 283

Figure 16.3 External Trigger Input Timing ................................................................................ 284

Figure 16.4 A/D Conversion Accuracy Definitions (1).............................................................. 286

Figure 16.5 A/D Conversion Accuracy Definitions (2).............................................................. 286

Figure 16.6 Analog Input Circuit Example................................................................................. 287

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Figure 17.1 Block Diagram around BGR ................................................................................... 290

Figure 17.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit....291

Figure 17.3 Operational Timing of Power-On Reset Circuit...................................................... 296

Figure 17.4 Operating Timing of LVDR Circuit........................................................................ 297

Figure 17.5 Operational Timing of LVDI Circuit.......................................................................298

Figure 17.6 Timing of Setting Bits in Reset Source Decision Register...................................... 299

Section 18 Power Supply Circuit

Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used ....................301

Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used .............302

Section 20 Electrical Characteristics

Figure 20.1 System Clock Input Timing.....................................................................................335

Figure 20.2 RES Low Width Timing.......................................................................................... 335

Figure 20.3 Input Timing............................................................................................................ 335

Figure 20.4 I2C Bus Interface Input/Output Timing................................................................... 336

Figure 20.5 SCK3 Input Clock Timing.......................................................................................336

Figure 20.6 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 337

Rev. 1.00 Aug. 28, 2006 Page xxiii of xxviii

Figure 20.7 Output Load Circuit ................................................................................................ 337

Appendix

Figure B.1 Port 1 Block Diagram (P17) .....................................................................................369

Figure B.2 Port 1 Block Diagram (P16 to P14).......................................................................... 370

Figure B.3 Port 1 Block Diagram (P12, P11)............................................................................. 371

Figure B.4 Port 1 Block Diagram (P10) .....................................................................................372

Figure B.5 Port 2 Block Diagram (P22) .....................................................................................373

Figure B.6 Port 2 Block Diagram (P21) .....................................................................................374

Figure B.7 Port 2 Block Diagram (P20) .....................................................................................375

Figure B.8 Port 5 Block Diagram (P57, P56)............................................................................. 376

Figure B.9 Port 5 Block Diagram (P55) .....................................................................................377

Figure B.10 Port 5 Block Diagram (P54 to P50)........................................................................ 378

Figure B.11 Port 7 Block Diagram (P76) ................................................................................... 379

Figure B.12 Port 7 Block Diagram (P75) ................................................................................... 380

Figure B.13 Port 7 Block Diagram (P74) ................................................................................... 381

Figure B.14 Port 8 Block Diagram (P87 to P85)........................................................................ 382

Figure B.15 Port 8 Block Diagram (P84 to P81)........................................................................ 383

Figure B.16 Port 8 Block Diagram (P80) ................................................................................... 384

Figure B.17 Port B Block Diagram (PB7 to PB0)...................................................................... 385

Figure B.18 Port C Block Diagram (PC1).................................................................................. 386

Figure B.19 Port C Block Diagram (PC0).................................................................................. 387

Figure D.1 FP-64K Package Dimensions................................................................................... 391

Figure D.2 FP-64A Package Dimensions................................................................................... 392

Figure D.3 FP-48F Package Dimensions.................................................................................... 393

Figure D.4 FP-48B Package Dimensions ...................................................................................394

Figure D.5 TNP-48 Package Dimensions................................................................................... 395

Rev. 1.00 Aug. 28, 2006 Page xxiv of xxviii

Tables

Section 1 Overview

Table 1.1

Section 2 CPU

Table 2.1 Operation Notation .................................................................................................18

Table 2.2 Data Transfer Instructions.......................................................................................19

Table 2.3 Arithmetic Operations Instructions (1) ...................................................................20

Table 2.3 Arithmetic Operations Instructions (2) ...................................................................21

Table 2.4 Logic Operations Instructions................................................................................. 22

Table 2.5 Shift Instructions.....................................................................................................22

Table 2.6 Bit Manipulation Instructions (1)............................................................................ 23

Table 2.6 Bit Manipulation Instructions (2)............................................................................ 24

Table 2.7 Branch Instructions................................................................................................. 25

Table 2.8 System Control Instructions.................................................................................... 26

Table 2.9 Block Data Transfer Instructions ............................................................................ 27

Table 2.10 Addressing Modes .................................................................................................. 29

Table 2.11 Absolute Address Access Ranges........................................................................... 30

Table 2.12 Effective Address Calculation (1)........................................................................... 32

Table 2.12 Effective Address Calculation (2)........................................................................... 33

Section 3 Exception Handling

Table 3.1 Exception Sources and Vector Address.................................................................. 43

Table 3.2 Interrupt Wait States ...............................................................................................54

Pin Functions ............................................................................................................ 6

Section 4 Address Break

Table 4.1 Access and Data Bus Used .....................................................................................59

Section 5 Clock Pulse Generators

Table 5.1 Crystal Resonator Parameters ................................................................................. 79

Section 6 Power-Down Modes

Table 6.1 Operating Frequency and Waiting Time................................................................. 87

Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling........ 90

Table 6.3 Internal State in Each Operating Mode................................................................... 91

Section 7 ROM

Table 7.1 Setting Programming Modes ................................................................................ 103

Table 7.2 Boot Mode Operation ...........................................................................................105

Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible................................................................................................................. 106

Rev. 1.00 Aug. 28, 2006 Page xxv of xxviii

Table 7.4 Reprogram Data Computation Table.................................................................... 109

Table 7.5 Additional-Program Data Computation Table...................................................... 109

Table 7.6 Programming Time............................................................................................... 109

Table 7.7 Flash Memory Operating States............................................................................ 113

Section 10 Timer A

Table 10.1 Pin Configuration.................................................................................................. 144

Section 11 Timer V

Table 11.1 Pin Configuration.................................................................................................. 151

Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 153

Section 12 Timer W

Table 12.1 Timer W Functions............................................................................................... 164

Table 12.2 Pin Configuration.................................................................................................. 166

Section 14 Serial Communication Interface 3 (SCI3)

Table 14.1 Pin Configuration.................................................................................................. 203

Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 211

Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 212

Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................213

Table 14.4 Examples of BBR Setting for Various Bit Rates

(Clocked Synchronous Mode) .............................................................................. 214

Table 14.5 SSR Status Flags and Receive Data Handling...................................................... 220

Table 14.6 SCI3 Interrupt Requests........................................................................................ 238

Section 15 I2C Bus Interface 2 (IIC2)

Table 15.1 I2C Bus Interface Pins........................................................................................... 243

Table 15.2 Transfer Rate ........................................................................................................246

Table 15.3 Interrupt Requests................................................................................................. 273

Table 15.4 Time for Monitoring SCL..................................................................................... 274

Section 16 A/D Converter

Table 16.1 Pin Configuration.................................................................................................. 277

Table 16.2 Analog Input Channels and Corresponding ADDR Registers.............................. 278

Table 16.3 A/D Conversion Time (Single Mode)................................................................... 284

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Table 17.1 LVDCR Settings and Select Functions................................................................. 293

Table 17.2 Deciding Reset Source.......................................................................................... 299

Section 20 Electrical Characteristics

Table 20.1 Absolute Maximum Ratings ................................................................................. 317

Table 20.2 DC Characteristics (1) ..........................................................................................320

Rev. 1.00 Aug. 28, 2006 Page xxvi of xxviii

Table 20.2 DC Characteristics (2)...........................................................................................324

Table 20.3 AC Characteristics ................................................................................................325

Table 20.4 I2C Bus Interface Timing...................................................................................... 328

Table 20.5 Serial Communication Interface (SCI) Timing..................................................... 329

Table 20.6 A/D Converter Characteristics.............................................................................. 330

Table 20.7 Watchdog Timer Characteristics........................................................................... 331

Table 20.8 Flash Memory Characteristics ..............................................................................332

Table 20.9 Power-Supply-Voltage Detection Circuit Characteristics.....................................334

Table 20.10 Power-On Reset Circuit Characteristics............................................................334

Appendix

Table A.1 Instruction Set....................................................................................................... 341

Table A.2 Operation Code Map (1) ....................................................................................... 354

Table A.2 Operation Code Map (2) ....................................................................................... 355

Table A.2 Operation Code Map (3) ....................................................................................... 356

Table A.3 Number of Cycles in Each Instruction.................................................................. 358

Table A.4 Number of Cycles in Each Instruction.................................................................. 359

Table A.5 Combinations of Instructions and Addressing Modes ..........................................368

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Rev. 1.00 Aug. 28, 2006 Page xxviii of xxviii

Section 1 Overview

Section 1 Overview

1.1 Features

• High-speed H8/300H central processing unit with an internal 16-bit architecture
 Upward-compatible with H8/300 CPU on an object level
 Sixteen 16-bit general registers
 62 basic instructions

• Various peripheral functions
 Timer A (can be used as a time base for a clock)
 Timer V (8-bit timer)
 Timer W (16-bit timer)
 Watchdog timer
 SCI (Asynchronous or clocked synchronous serial communication interface)

2

 I

C Bus Interface (conforms to the I2C bus interface format that is advocated by Philips

Electronics)

 10-bit A/D converter
 POR/LVD: power-on reset and low-voltage detecting circuit (optional)
 On-chip oscillator

• On-chip memory

Model

On-Chip Power­On Reset and
Low-Voltage
Detecting Circuit
Version ROM RAM Remarks

Product Classification

(F-ZTAT

TM

version)

Standard
Version

H8/36094F HD64F36094 HD64F36094G 32 kbytes 2,048 bytes Flash memory version

H8/36092F HD64F36092 HD64F36092G 16 kbytes 2,048 bytes

Rev. 1.00 Aug. 28, 2006 Page 1 of 400

REJ09B0268-0100

Section 1 Overview

• General I/O ports
 I/O pins: 31 I/O pins, including 8 large current ports (I

= 20 mA, @VOL = 1.5 V)

OL

 Input-only pins: 8 input pins (also used for analog input)

• Frequency accuracy:

20 MHz ± 1.5% V
16 MHz ± 1.5% V
20 MHz ± 3% V
16 MHz ± 3% V
20 MHz ± 4% V
16 MHz ± 4% V

= 4.0 to 5.0 V, T

CC

= 4.0 to 5.0 V, T

CC

= 4.0 to 5.5 V, T

CC

= 4.0 to 5.5 V, T

CC

= 3.0 to 5.5 V, T

CC

= 3.0 to 5.5 V, T

CC

= 25°C

a

= 25°C

a

= –20 to 75°C

a

= –20 to 75°C

a

= –20 to 75°C

a

= –20 to 75°C

a

• Supports various power-down modes

Note: F-ZTATTM is a trademark of Renesas Technology Corp.

• Compact package

Package Code Body Size Pin Pitch

LQFP-64 FP-64K 10.0

QFP-64 FP-64A 14.0 × 14.0 mm 0.8 mm
LQFP-48 FP-48F 10.0 × 10.0 mm 0.65 mm
LQFP-48 FP-48B 7.0 × 7.0 mm 0.5 mm
QFN-48 TNP-48 7.0 × 7.0 mm 0.5 mm

× 10.0 mm 0.5 mm

Rev. 1.00 Aug. 28, 2006 Page 2 of 400

REJ09B0268-0100

1.2 Internal Block Diagram

G

Section 1 Overview

P10/TMOW

P11
P12

P14/IRQ0
P15/IRQ1
P16/IRQ2

P17/IRQ3/TRGV

P20/SCK3

P21/RXD

P22/TXD

X1

Subclock

generator

Port 1

Port 2

X2

(OSC1)

External

clock

generator

(OSC2)

On-chip

oscillator

VCCVSSVCLRES

Data bus (lower)

ROM

Timer W

Timer A

Timer V

A/D

converter

Data bus (upper)

Address bus

CPU

H8/300H

Watchdog

POR/LVD
(optional)

RAM

SCI3

timer

IIC2

TEST

NMI

P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD

Port 8Port 7Port 5Port B

P85
P86
P87

P74/TMRIV
P75/TMCIV
P76/TMOV

P50/WKP0
P51/WKP1
P52/WKP2
P53/WKP3
P54/WKP4
P55/WKP5/ADTR
P56/SDA
P57/SCL

PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7

AV

CC

Port C

PC0/OSC1

PC1/OSC2/CLKOUT

Figure 1.1 Internal Block Diagram of H8/36094 Group of F-ZTATTM

Rev. 1.00 Aug. 28, 2006 Page 3 of 400

REJ09B0268-0100

Section 1 Overview

G

1.3 Pin Assignments

NC

NC

P14/IRQ0
P15/IRQ1
P16/IRQ2

P17/IRQ3/TRGV

PB4/AN4

PB5/AN5

PB6/AN6

PB7/AN7

PB3/AN3

PB2/AN2

PB1/AN1

PB0/AN0

NC

NC

NCNCP22/TXD

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

1 2 3 4 5 6 7 8 9 10111213141516

NC

NC

CC

AV

P21/RXD

P20/SCK3

P87

H8/36094 Group

X2

X1

V

P86

(Top view)

CL

RES

P85

P84/FTIOD

SS

V

TEST

P83/FTIOC

P82/FTIOB

P81/FTIOA

CC

V

PC0/OSC1

P80/FTCI

P50/WKP0

NMINCNC

NC

NC

P51/WKP1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

NC

NC

P76/TMOV

P75/TMCIV

P74/TMRIV

P57/SCL

P56/SDA

P12

P11

P10/TMOW
P55/WKP5/ADTR
P54/WKP4
P53/WKP3
P52/WKP2

NC

NC

PC1/OSC2/CLKOUT

Note: Do not connect NC pins (these pins are not connected to the internal circuitry).

Figure 1.2 Pin Assignments of H8/36094 Group of F-ZTATTM (FP-64K, FP-64A)

Rev. 1.00 Aug. 28, 2006 Page 4 of 400

REJ09B0268-0100

P22/TXD

G

P21/RXD

P20/SCK3

P87

P86

P85

P84/FTIOD

P83/FTIOC

P82/FTIOB

P81/FTIOA

P80/FTCI

NMI

Section 1 Overview

P14/IRQ0
P15/IRQ1
P16/IRQ2

P17/IRQ3/TRGV

PB4/AN4

PB5/AN5

PB6/AN6

PB7/AN7

PB3/AN3

PB2/AN2

PB1/AN1

PB0/AN0

36 35 34 33 32 31 30 29 28 27 26 25

37

38

39

40

41

42

43

44

45

46

47

48

123456789101112

AVcc

X2

X1

H8/36094 Group

(Top View)

CL

V

RES

TEST

SS

V

Vcc

PC0/OSC1

PC1/OSC2/CLKOUT

P50/WKP0

24

23

22

21

20

19

18

17

16

15

14

13

P51/WKP1

P76/TMOV

P75/TMCIV

P74/TMRIV

P57/SCL

P56/SDA

P12

P11

P10/TMOW
P55/WKP5/ADTR
P54/WKP4
P53/WKP3
P52/WKP2

Figure 1.3 Pin Assignments of H8/36094 Group of F-ZTATTM (FP-48F, FP-48B, TNP-48)

Rev. 1.00 Aug. 28, 2006 Page 5 of 400

REJ09B0268-0100

Section 1 Overview

1.4 Pin Functions

Table 1.1 Pin Functions

Pin No.

FP-48F

Type Symbol

Power

VCC 12 10 Input Power supply pin. Connect this pin to the
source
pins

VSS 9 7 Input Ground pin. Connect this pin to the system

AVCC 3 1 Input Analog power supply pin for the A/D converter.

V

CL

OSC1 11 9 Input Clock
pins

OSC2/

CLKOUT

X1 5 3 Input

X2 4 2 Output

System

RES 7 5 Input Reset pin. The pull-up resistor (typ. 150 kΩ) is
control

TEST 8 6 Input Test pin. Connect this pin to Vss.

Interrupt

NMI 35 25 Input Non-maskable interrupt request input pin. Be
pins

IRQ0 to

IRQ3
WKP0 to

WKP5

Timer A TMOW 23 17 Output This is an output pin for divided clocks.

FP-64K
FP-64A

FP-48B
TNP-48 I/O

Functions

system power supply.

power supply (0V).

When the A/D converter is not used, connect
this pin to the system power supply.

6 4 Input Internal step-down power supply pin. Connect a

capacitor of around 0.1 µF between this pin and
the Vss pin for stabilization.

These pins connect with crystal or ceramic

10 8 Output

resonator for the system clock, or can be used
to input an external clock.

See section 5, Clock Pulse Generators, for a
typical connection.

These pins connect with a 32.768-kHz crystal
resonator for the subclock. See section 5, Clock
Pulse Generators, for a typical connection.

incorporated. When driven low, the chip is reset.

sure to pull-up by a pull-up resistor.

51 to 54 37 to 40 Input External interrupt request input pins. Can select

the rising or falling edge.

13, 14,
19 to 22

11 to 16 Input External interrupt request input pins. Can select

the rising or falling edge.

Rev. 1.00 Aug. 28, 2006 Page 6 of 400

REJ09B0268-0100

Section 1 Overview

Pin No.

FP-48F

Type

Symbol

FP-64K
FP-64A

FP-48B
TNP-48 I/O

Functions

Timer V TMOV 30 24 Output This is an output pin for waveforms

generated by the output compare function.

TMCIV 29 23 Input External event input pin.

TMRIV 28 22 Input Counter reset input pin.

TRGV 54 40 Input Counter start trigger input pin.

Timer W FTCI 36 26 Input External event input pin.

FTIOA to

FTIOD

I2C bus

SDA 26 20 I/O IIC data I/O pin. Can directly drive a bus by
interface
2 (IIC2)

SCL 27 21 I/O

37 to 40 27 to 30 I/O Output compare output/ input capture input/

PWM output pins

NMOS open-drain output.

IIC clock I/O pin. Can directly drive a bus

(EEPROM:

by NMOS open-drain output.

Input)

Serial
communi­cation
interface

TXD 46 36 Output Transmit data output pin

RXD 45 35 Input Receive data input pin

SCK3 44 34 I/O Clock I/O pin
3 (SCI3)

A/D
converter

AN7 to

AN0

55 to 62 41 to 48 Input Analog input pins

ADTRG 22 16 Input A/D converter trigger input pin.

I/O ports PB7 to

55 to 62 41 to 48 Input 8-bit input port

PB0

PC1,

10, 11 8, 9 I/O 2-bit I/O port

PC0

P17 to

P14,

51 to 54,
23 to 25

37 to 40
17 to 19

I/O 7-bit I/O port

P12 to

P10

P22 to

44 to 46 34 to 36 I/O 3-bit I/O port

P20

P57 to

P50

13, 14,
19 to 22,
26, 27

20, 21,
13 to 16,
11, 12

I/O 8-bit I/O port

Rev. 1.00 Aug. 28, 2006 Page 7 of 400

REJ09B0268-0100

Section 1 Overview

Pin No.

FP-48F

Type

I/O ports P76 to

Symbol

FP-64K
FP-64A

FP-48B
TNP-48 I/O

Functions

28 to 30 22 to 24 I/O 3-bit I/O port

P74

P87 to

36 to 43 26 to 33 I/O 8-bit I/O port

P80

Rev. 1.00 Aug. 28, 2006 Page 8 of 400

REJ09B0268-0100

Section 2 CPU

Section 2 CPU

This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with
the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space.

• Upward-compatible with H8/300 CPUs

 Can execute H8/300 CPUs object programs
 Additional eight 16-bit extended registers
 32-bit transfer and arithmetic and logic instructions are added
 Signed multiply and divide instructions are added.

• General-register architecture

 Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit

registers, or eight 32-bit registers

• Sixty-two basic instructions

 8/16/32-bit data transfer and arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions

• Eight addressing modes

 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]

• 64-kbyte address space

• High-speed operation

 All frequently-used instructions execute in one or two states
 8/16/32-bit register-register add/subtract : 2 state
 8 × 8-bit register-register multiply : 14 states
 16 ÷ 8-bit register-register divide : 14 states
 16 × 16-bit register-register multiply : 22 states
 32 ÷ 16-bit register-register divide : 22 states

Rev. 1.00 Aug. 28, 2006 Page 9 of 400

REJ09B0268-0100

Section 2 CPU

• Power-down state
 Transition to power-down state by SLEEP instruction

2.1 Address Space and Memory Map

The address space of this LSI is 64 kbytes, which includes the program area and the data area.
Figure 2.1 shows the memory map.

HD64F36094, HD64F36094G

H'0000
H'0041
H'0042

H'7FFF

H'F730

H'F74F

H'F780

Interrupt vector

On-chip ROM

(32 kbytes)

Not used

Internal I/O register

Not used

(1-kbyte work area

for flash memory

programming)

HD64F36092, HD64F36092G

H'0000
H'0041
H'0042

H'3FFF

H'F730

H'F74F

H'F780

Interrupt vector

On-chip ROM

(16 kbytes)

Not used

Internal I/O register

Not used

(1-kbyte work area

for flash memory

programming)

H'FB7F
H'FB80

H'FF7F
H'FF80

H'FFFF

On-chip RAM

(2 kbytes)

(1-kbyte user area)

Internal I/O register

H'FB7F
H'FB80

H'FF7F
H'FF80

H'FFFF

Figure 2.1 Memory Map

Rev. 1.00 Aug. 28, 2006 Page 10 of 400

REJ09B0268-0100

On-chip RAM

(2 kbytes)

(1-kbyte user area)

Internal I/O register

Section 2 CPU

2.2 Register Configuration

The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition code register (CCR).

General Registers (ERn)

15 0 7 0 7 0

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7

E0

E1

E2

E3

E4

E5

E6

E7

(SP)

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

Control Registers (CR)

[Legend]

SP:

Stack pointer

PC:

Program counter

CCR:

Condition-code register

I:

Interrupt mask bit

UI:

User bit

23 0

PC

76543210

CCR

IUIHUNZVC

Half-carry flag

H:

User bit

U:

Negative flag

N:

Zero flag

Z:

Overflow flag

V:

Carry flag

C:

Figure 2.2 CPU Registers

Rev. 1.00 Aug. 28, 2006 Page 11 of 400

REJ09B0268-0100

Section 2 CPU

2.2.1 General Registers

The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L
to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.

The usage of each register can be selected independently.

• Address registers

• 32-bit registers

ER registers

(ER0 to ER7)

• 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

Figure 2.3 Usage of General Registers

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Rev. 1.00 Aug. 28, 2006 Page 12 of 400

REJ09B0268-0100

Section 2 CPU

General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the
relationship between stack pointer and the stack area.

Free area

SP (ER7)

Stack area

Figure 2.4 Relationship between Stack Pointer and Stack Area

2.2.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.

2.2.3 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.

Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.

For the action of each instruction on the flag bits, see appendix A.1, Instruction List.

Rev. 1.00 Aug. 28, 2006 Page 13 of 400

REJ09B0268-0100

Section 2 CPU

Initial

Bit Bit Name

Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.

6 UI Undefined R/W User Bit

Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.

5 H Undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.

4 U Undefined R/W User Bit

Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit of data as a
sign bit.

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to indicate a carry

The carry flag is also used as a bit accumulator by bit
manipulation instructions.

Rev. 1.00 Aug. 28, 2006 Page 14 of 400

REJ09B0268-0100

Section 2 CPU

2.3 Data Formats

The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.

2.3.1 General Register Data Formats

Figure 2.5 shows the data formats in general registers.

Data Type General Register Data Format

70

6543271

Don't care

0

1-bit data

RnH

1-bit data

4-bit BCD data

4-bit BCD data

Byte data

Byte data

7

RnL

RnH

RnL

RnH

RnL

Don't care

7 04 3

Upper Lower

Don't care

7 0

MSB LSB

Don't care

65432710

Don't care

704 3

Upper Lower

7

MSB LSB

Figure 2.5 General Register Data Formats (1)

0

Don't care

0

Rev. 1.00 Aug. 28, 2006 Page 15 of 400

REJ09B0268-0100

Section 2 CPU

Data Type Data FormatGeneral

Register

Word data

Word dataRnEn

Longword

ERn

data

[Legend]

ERn:

General register ER

En:

General register E

Rn:

General register R

RnH:

General register RH

RnL:

General register RL

MSB:

Most significant bit

LSB:

Least significant bit

15 0

MSB LSB

15 0

MSB LSB

31 16

MSB

15 0

Figure 2.5 General Register Data Formats (2)

LSB

Rev. 1.00 Aug. 28, 2006 Page 16 of 400

REJ09B0268-0100

Section 2 CPU

2.3.2 Memory Data Formats

Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.

When ER7 (SP) is used as an address register to access the stack area, the operand size should be
word or longword.

Data Type Address

1-bit data

Byte data

Word data

Longword data Address 2N

Address L

Address L

Address 2M

Address 2M+1

Address 2N+1

Address 2N+2

Address 2N+3

MSB

MSB

MSB

Figure 2.6 Memory Data Formats

Data Format

70

76 543210

LSB

LSB

LSB

Rev. 1.00 Aug. 28, 2006 Page 17 of 400

REJ09B0268-0100

Section 2 CPU

2.4 Instruction Set

2.4.1 Table of Instructions Classified by Function

The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each
functional category. The notation used in tables 2.2 to 2.9 is defined below.

Table 2.1 Operation Notation

Symbol Description

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register or address register)

(EAd) Destination operand

(EAs) Source operand

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

– Subtraction
× Multiplication

÷ Division

∧ Logical AND
∨ Logical OR
⊕ Logical XOR
→ Move

¬ NOT (logical complement)

Rev. 1.00 Aug. 28, 2006 Page 18 of 400

REJ09B0268-0100

Section 2 CPU

Symbol Description

:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length

Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).

Table 2.2 Data Transfer Instructions

Instruction Size* Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.

MOVFPE B (EAs) → Rd, Cannot be used in this LSI.
MOVTPE B Rs → (EAs) Cannot be used in this LSI.
POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.

Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword

Rev. 1.00 Aug. 28, 2006 Page 19 of 400

REJ09B0268-0100

Section 2 CPU

Table 2.3 Arithmetic Operations Instructions (1)

Instruction Size* Function

ADD
SUB

ADDX
SUBX

INC
DEC

ADDS
SUBS

DAA
DAS

MULXU B/W Rd × Rs → Rd

MULXS B/W Rd × Rs → Rd

DIVXU B/W Rd ÷ Rs → Rd

Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the
SUBX or ADD instruction.)

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

B Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.

Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.

Rev. 1.00 Aug. 28, 2006 Page 20 of 400

REJ09B0268-0100

Table 2.3 Arithmetic Operations Instructions (2)

Instruction Size* Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of data in a
general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.

Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword

Section 2 CPU

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Section 2 CPU

Table 2.4 Logic Operations Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another
general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another
general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and
another general register or immediate data.

NOT B/W/L ¬ (Rd) → (Rd)

Takes the one's complement (logical complement) of general register
contents.

Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword

Table 2.5 Shift Instructions

Instruction Size* Function

SHAL
SHAR

SHLL
SHLR

ROTL
ROTR

ROTXL
ROTXR

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

B/W/L Rd (rotate) → Rd

Rotates general register contents.

B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag.

Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword

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Table 2.6 Bit Manipulation Instructions (1)

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.

BAND

BIAND

BOR

BIOR

Note: * Refers to the operand size.
B: Byte

B

B

B

B

C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.

C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.

C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.

C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.

Section 2 CPU

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Table 2.6 Bit Manipulation Instructions (2)

Instruction Size* Function

BXOR

BIXOR

BLD

BILD

BST

BIST

Note: * Refers to the operand size.
B: Byte

B

B

B

B

B

B

C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.

C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.

(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.

¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.

C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.

¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.

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Table 2.7 Branch Instructions

Instruction Size Function

Bcc* — Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA(BT) Always (true) Always

BRN(BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1

BCC(BHS) Carry clear

(high or same)

BCS(BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1

JMP — Branches unconditionally to a specified address.

BSR — Branches to a subroutine at a specified address.

JSR — Branches to a subroutine at a specified address.

RTS — Returns from a subroutine

Note: * Bcc is the general name for conditional branch instructions.

C = 0

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Table 2.8 System Control Instructions

Instruction Size* Function

TRAPA — Starts trap-instruction exception handling.

RTE — Returns from an exception-handling routine.

SLEEP — Causes a transition to a power-down state.
LDC B/W (EAs) → CCR

Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.

STC B/W CCR → (EAd)

Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is written
by word access.

ANDC B CCR ∧ #IMM → CCR

Logically ANDs the CCR with immediate data.

ORC B CCR ∨ #IMM → CCR

Logically ORs the CCR with immediate data.

XORC B CCR ⊕ #IMM → CCR

Logically XORs the CCR with immediate data.

NOP — PC + 2 → PC

Only increments the program counter.

Note: * Refers to the operand size.
B: Byte
W: Word

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Table 2.9 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B — if R4L ≠ 0 then

Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;

EEPMOV.W — if R4 ≠ 0 then

Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;

Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.

Execution of the next instruction begins as soon as the transfer is
completed.

2.4.2 Basic Instruction Formats

Section 2 CPU

H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).

Figure 2.7 shows examples of instruction formats.

(1) Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried out
on the operand. The operation field always includes the first four bits of the instruction. Some
instructions have two operation fields.

(2) Register Field

Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.

(3) Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).

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(4) Condition Field

Specifies the branching condition of Bcc instructions.

(1) Operation field only

op

(2) Operation field and register fields

op

(3) Operation field, register fields, and effective address extension

op

EA(disp)

(4) Operation field, effective address extension, and condition field

op cc EA(disp) BRA d:8

rn

rn rm

Figure 2.7 Instruction Formats

rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm

2.5 Addressing Modes and Effective Address Calculation

The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the
generated 24-bit address, so the effective address is 16 bits.

2.5.1 Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses
a subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing
Modes.

Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode
(@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions)
or immediate (3-bit) addressing mode to specify a bit number in the operand.

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Table 2.10 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn)

4 Register indirect with post-increment

Register indirect with pre-decrement

5 Absolute address @aa:8/@aa:16/@aa:24

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

@ERn+
@–ERn

(1) Register Direct—Rn

The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

(2) Register Indirect—@ERn

The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.

(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)

A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.

(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word

or longword access, the register value should be even.

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• Register indirect with pre-decrement—@-ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result is the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access. For the word or longword access, the register value
should be even.

(5) Ab solute Address—@aa:8, @aa:16, @aa:24

The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)

For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.

The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11,

because the upper 8 bits are ignored.

Table 2.11 Absolute Address Access Ranges

Absolute Address Access Range

8 bits (@aa:8) H'FF00 to H'FFFF

16 bits (@aa:16) H'0000 to H'FFFF

24 bits (@aa:24) H'0000 to H'FFFF

(6) Immediate—#xx:8, #xx:16, or #xx:32

The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.

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(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.

(8) Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in
memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the
address range is 0 to 255 (H'0000 to H'00FF).

Note that the first part of the address range is also the exception vector area.

Specified
by @aa:8

Dummy

Branch address

Figure 2.8 Branch Address Specification in Memory Indirect Mode

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2.5.2 Effective Address Calculation

Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.

Table 2.12 Effective Address Calculation (1)

No

Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1

Register direct(Rn)

op

2

Register indirect(@ERn)

op

Register indirect with dis

3

@(d:16,ERn)

o

Register indirect with post-increment or

4

pre-decrement

•Register indirect with post-increment @ERn+

p

rn

rm

r

placement

or @(d:24,ERn)

r

disp

31

General register contents

31

General register contents

31

Sign extension

1

3

General register contents

p

dis

Operand is general register contents.

0

0

0

0

23

23

3

2

0

0

0

p

o

r

•Register indirect with pre-decrement @-ERn

p

o

r

31

General register contents

The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.

1, 2, or 4

1, 2, or 4

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0

23

0

Table 2.12 Effective Address Calculation (2)

Addressing Mode and Instruction Format

No

5

@aa:8

Absolute address

op

abs

Effective Address Calculation Effective Address (EA)

Section 2 CPU

7

0

23

H'FFFF

8

@aa:16

@aa:24

6

Immediate

#xx:8/#xx:16/#xx:32

7

P

@

M

[Legend]
r, rm,rn:
op:
disp:
IMM:
abs:

op

p

o

p

o

rogram-counter relative

(d:8,PC) @(d:16

emory indirect @@

Register field
Operation field
Displacement
Immediate data
Absolute address

,PC)

op

op8abs

23

abs

abs

IMM

23

PC contents

p

dis

:8

aa

23

Sign

extension

23

H'0000

dis

5

1

Memory contents

0

0

p

7

8

0

abs

0

Sign extension

23

Operand is immediate data.

23

23

H'00

15

16

5

1

16

0

0

0

0

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Section 2 CPU

2.6 Basic Bus Cycle

CPU operation is synchronized by a system clock (φ) or a subclock (φ
edge of φ or φ

to the next rising edge is called one state. A bus cycle consists of two states or

SUB

). The period from a rising

SUB

three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.

2.6.1 Access to On-Chip Memory (RAM, ROM)

Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.

Bus cycle

T

state

2

Read data

ø or ø

SUB

Internal address bus

Internal read signal

Internal data bus
(read access)

Internal write signal

T1 state

Address

Internal data bus
(write access)

Figure 2.9 On-Chip Memory Access Cycle

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Write data

Section 2 CPU

2.6.2 On-Chip Peripheral Modules

On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 19.1, Register Addresses (Address Order).
Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data
bus width can be accessed by byte or word size. When a register with 8-bit data bus width is
accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the
same as that for on-chip memory.

Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.

Bus cycle

ø or ø

T1 state

SUB

T2 state T3 state

Internal
address bus

Internal
read signal

Internal
data bus
(read access)

Internal
write signal

Internal
data bus
(write access)

Address

Read data

Write data

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)

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Section 2 CPU

2.7 CPU States

There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active mode and subactive mode.
For the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states
are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution
state and program halt state, refer to section 6, Power-Down Modes. For details on exception
processing, refer to section 3, Exception Handling.

CPU state Reset state

The CPU is initialized

Program

execution state

Program halt state

A state in which some
or all of the chip
functions are stopped
to conserve power

The CPU executes successive program
instructions at high speed,
synchronized by the system clock

The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock

Active

(high speed) mode

Subactive mode

Sleep mode

Standby mode

Subsleep mode

Power-down

modes

Exception-

handling state

A transient state in which the CPU changes
the processing flow due to a reset or an interrupt

Figure 2.11 CPU Operation States

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Section 2 CPU

Reset state

Reset
occurs

Program halt state

Reset cleared

Reset occurs

Reset
occurs

SLEEP instruction executed

Exception-handling state

Interrupt
source

Interrupt
source

Program execution state

Exception­handling
complete

Figure 2.12 State Transitions

2.8 Usage Notes

2.8.1 Notes on Data Access to Empty Areas

The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.

2.8.2 EEPMOV Instruction

EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).

2.8.3 Bit Manipulation Instruction

The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address or when a bit is directly manipulated for a port or a register
containing a write-only bit, because this may rewrite data of a bit other than the bit to be
manipulated.

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Section 2 CPU

(1) Bit manipulation for two registers assigned to the same address

Example 1: Bit manipulation for the timer load register and timer counter

(Applicable for timer B and timer C, not for the group of this LSI.)

Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.

1. Data is read in byte units.

2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction.

3. The written data is written again in byte units to the timer load register.

The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.

Count clock Timer counter

Reload

Timer load register

Read

Write

Internal data bus

Figure 2.13 Example of Timer Configuration with Two Regis ters Allocated to Same

Address

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Section 2 CPU

Example 2: The BSET instruction is executed for port 5.

P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.

• Prior to executing BSET instruction

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 0

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

Low
level

• BSET instruction executed instruction

BSET #0, @PDR5

The BSET instruction is executed for port 5.

• After executing BSET instruction

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 0 1 0 0 0 0 0 1

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

High
level

• Description on operation

1. When the BSET instruction is executed, first the CPU reads port 5.

Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.

2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.

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Section 2 CPU

3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.

As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.

• Prior to executing BSET instruction

MOV.B #80, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PDR5

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 0

RAM0 1 0 0 0 0 0 0 0

The PDR5 value (H'80) is written to a work area in

memory (RAM0) as well as to PDR5.

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

Low
level

• BSET instruction executed

BSET #0, @RAM0

The BSET instruction is executed designating the PDR5

work area (RAM0).

• After executing BSET instruction

MOV.B @RAM0, R0L

The work area (RAM0) value is written to PDR5.

MOV.B R0L, @PDR5

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 1

RAM0 1 0 0 0 0 0 0 1

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

High
level

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Section 2 CPU

(2) Bit Manipulation in a Register Containing a Write-Only Bit

Example 3: BCLR instruction executed designating port 5 control register PCR5

P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.

• Prior to executing BCLR instruction

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 0

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

Low
level

• BCLR instruction executed

BCLR #0, @PCR5

The BCLR instruction is executed for PCR5.

• After executing BCLR instruction

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Output Output Output Output Output Output Output Input

Pin state Low

level

PCR5 1 1 1 1 1 1 1 0

PDR5 1 0 0 0 0 0 0 0

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

High
level

• Description on operation

1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.

2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.

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Section 2 CPU

3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.

As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,
bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
To prevent this problem, store a copy of the PDR5 data in a work area in memory and
manipulate data of the bit in the work area, then write this data to PDR5.

• Prior to executing BCLR instruction

MOV.B #3F, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PCR5

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 0

RAM0 0 0 1 1 1 1 1 1

The PCR5 value (H'3F) is written to a work area in

memory (RAM0) as well as to PCR5.

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

Low
level

• BCLR instruction executed

BCLR #0, @RAM0

The BCLR instructions executed for the PCR5 work area

(RAM0).

• After executing BCLR instruction

MOV.B @RAM0, R0L

The work area (RAM0) value is written to PCR5.

MOV.B R0L, @PCR5

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 0

PDR5 1 0 0 0 0 0 0 0

RAM0 0 0 1 1 1 1 1 0

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

High
level

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Section 3 Exception Handling

Section 3 Exception Handling

Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.

• Reset

A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared
by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling
starts. Exception handling is the same as exception handling by the RES pin.

• Trap Instruction

Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction
generates a vector address corresponding to a vector number from 0 to 3, as specified in the
instruction code. Exception handling can be executed at all times in the program execution state,
regardless of the setting of the I bit in CCR.

• Interrupts

External interrupts other than NMI and internal interrupts other than address break are masked by
the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the
current instruction or exception handling ends, if an interrupt request has been issued.

3.1 Exception Sources and Vector Address

Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.

Table 3.1 Exception Sources and Vector Address

Relative Module

RES pin
Watchdog timer

 Reserved for system use 1 to 6 H'0002 to H'000D

External interrupt pin NMI 7 H'000E to H'000F

CPU Trap instruction (#0) 8 H'0010 to H'0011

(#1) 9 H'0012 to H'0013

(#2) 10 H'0014 to H'0015

(#3) 11 H'0016 to H'0017

Address break Break conditions satisfied 12 H'0018 to H'0019 Low

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Exception Sources

Reset 0 H'0000 to H'0001 High

Vector
Number Vector Address Priority

Section 3 Exception Handling

Relative Module Exception Sources

CPU Direct transition by executing the

Vector
Number Vector Address Priority

13 H'001A to H'001B High

SLEEP instruction

External interrupt
pin

IRQ0
Low-voltage detection interrupt*

14 H'001C to H'001D

IRQ1 15 H'001E to H'001F

IRQ2 16 H'0020 to H'0021

IRQ3 17 H'0022 to H'0023

WKP 18 H'0024 to H'0025

Timer A Overflow 19 H'0026 to H'0027
 Reserved for system use 20 H'0028 to H'0029

Timer W Timer W input capture A/

21 H'002A to H'002B
compare match A
Timer W input capture B/
compare match B
Timer W input capture C/
compare match C
Timer W input capture D/
compare match D
Timer W overflow

Timer V Timer V compare match A

22 H'002C to H'002D
Timer V compare match B
Timer V overflow

SCI3 SCI3 receive data full

23 H'002E to H'002F
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error

IIC2 Transmit data empty

24 H'0030 to H'0031
Transmit end
Receive data full
Arbitration lost/Overrun error
NACK detection
Stop conditions detected

A/D converter A/D conversion end 25 H'0032 to H'0033
 Reserved for system use 26 to 33 H'0034 to H'0043

Clock switching Clock switching

(from external clock to on-chip
oscillator clock)

34 H'0044 to H'0045

Low

Note * A low-voltage detection interrupt is enabled only in the product with an on-chip power-

on reset and low-voltage detection circuit.

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Section 3 Exception Handling

3.2 Register Descriptions

Interrupts are controlled by the following registers.

• Interrupt edge select register 1 (IEGR1)

• Interrupt edge select register 2 (IEGR2)

• Interrupt enable register 1 (IENR1)

• Interrupt flag register 1 (IRR1)

• Wakeup interrupt flag register (IWPR)

3.2.1 Interrupt Edge Select Register 1 (IEGR1)

IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to
IRQ0.

Initial

Bit Bit Name

7 NMIEG 0 R/W NMI Edge Select

6 to 4  All 1  Reserved

3 IEG3 0 R/W IRQ3 Edge Select

2 IEG2 0 R/W IRQ2 Edge Select

1 IEG1 0 R/W IRQ1 Edge Select

0 IEG0 0 R/W IRQ0 Edge Select

Value R/W Description

0: Falling edge of NMI pin input is detected
1: Rising edge of NMI pin input is detected

These bits are always read as 1.

0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected

0: Falling edge of IRQ2 pin input is detected
1: Rising edge of IRQ2 pin input is detected

0: Falling edge of IRQ1 pin input is detected
1: Rising edge of IRQ1 pin input is detected

0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected

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Section 3 Exception Handling

3.2.2 Interrupt Edge Select Register 2 (IEGR2)

IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and
WKP5 to WKP0.

Initial

Bit Bit Name

7, 6  All 1  Reserved

5 WPEG5 0 R/W WKP5 Edge Select

4 WPEG4 0 R/W WKP4 Edge Select

3 WPEG3 0 R/W WKP3 Edge Select

2 WPEG2 0 R/W WKP2 Edge Select

1 WPEG1 0 R/W WKP1Edge Select

0 WPEG0 0 R/W WKP0 Edge Select

Value R/W Description

These bits are always read as 1.

0: Falling edge of WKP5(ADTRG) pin input is detected
1: Rising edge of WKP5(ADTRG) pin input is detected

0: Falling edge of WKP4 pin input is detected
1: Rising edge of WKP4 pin input is detected

0: Falling edge of WKP3 pin input is detected
1: Rising edge of WKP3 pin input is detected

0: Falling edge of WKP2 pin input is detected
1: Rising edge of WKP2 pin input is detected

0: Falling edge of WKP1 pin input is detected
1: Rising edge of WKP1 pin input is detected

0: Falling edge of WKP0 pin input is detected
1: Rising edge of WKP0 pin input is detected

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Section 3 Exception Handling

3.2.3 Interrupt Enable Register 1 (IENR1)

IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts.

Initial

Bit Bit Name

7 IENDT 0 R/W Direct Transfer Interrupt Enable

6 IENTA 0 R/W Timer A Interrupt Enable

5 IENWP 0 R/W Wakeup Interrupt Enable

4  1  Reserved

3 IEN3 0 R/W IRQ3 Interrupt Enable

2 IEN2 0 R/W IRQ2 Interrupt Enable

1 IEN1 0 R/W IRQ1 Interrupt Enable

0 IEN0 0 R/W IRQ0 Interrupt Enable

Value R/W Description

When this bit is set to 1, direct transition interrupt
requests are enabled.

When this bit is set to 1, timer A overflow interrupt
requests are enabled.

This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.

This bit is always read as 1.

When this bit is set to 1, interrupt requests of the IRQ3
pin are enabled.

When this bit is set to 1, interrupt requests of the IRQ2
pin are enabled.

When this bit is set to 1, interrupt requests of the IRQ1
pin are enabled.

When this bit is set to 1, interrupt requests of the IRQ0
pin are enabled.

When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.

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Section 3 Exception Handling

3.2.4 Interrupt Flag Register 1 (IRR1)

IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3
to IRQ0 interrupt requests.

Initial

Bit Bit Name

7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag

6 IRRTA 0 R/W Timer A Interrupt Request Flag

5, 4  All 1  Reserved

3 IRRI3 0 R/W IRQ3 Interrupt Request Flag

2 IRRI2 0 R/W IRQ2 Interrupt Request Flag

Value R/W Description

[Setting condition]

When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.

[Clearing condition]

When IRRDT is cleared by writing 0

[Setting condition]

When the timer A counter value overflows

[Clearing condition]

When IRRTA is cleared by writing 0

These bits are always read as 1.

[Setting condition]
When IRQ3 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI3 is cleared by writing 0

[Setting condition]
When IRQ2 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI2 is cleared by writing 0

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REJ09B0268-0100

Initial

Bit Bit Name

Value R/W Description

1 IRRI1 0 R/W IRQ1 Interrupt Request Flag

[Setting condition]
When IRQ1 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI1 is cleared by writing 0

0 IRRl0 0 R/W IRQ0 Interrupt Request Flag

[Setting condition]
When IRQ0 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI0 is cleared by writing 0

3.2.5 Wakeup Interrupt Flag Register (IWPR)

IWPR is a status flag register for WKP5 to WKP0 interrupt requests.

Initial

Bit Bit Name

7, 6  All 1 

5 IWPF5 0 R/W

4 IWPF4 0 R/W

Value R/W Description

Reserved

These bits are always read as 1.

WKP5 Interrupt Request Flag

[Setting condition]
When WKP5 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF5 is cleared by writing 0.

WKP4 Interrupt Request Flag

[Setting condition]
When WKP4 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF4 is cleared by writing 0.

Section 3 Exception Handling

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Section 3 Exception Handling

Initial

Bit Bit Name

3 IWPF3 0 R/W

Value R/W Description

WKP3 Interrupt Request Flag

[Setting condition]
When WKP3 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF3 is cleared by writing 0.

2 IWPF2 0 R/W

WKP2 Interrupt Request Flag

[Setting condition]
When WKP2 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF2 is cleared by writing 0.

1 IWPF1 0 R/W

WKP1 Interrupt Request Flag

[Setting condition]
When WKP1 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF1 is cleared by writing 0.

0 IWPF0 0 R/W

WKP0 Interrupt Request Flag

[Setting condition]
When WKP0 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF0 is cleared by writing 0.

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Section 3 Exception Handling

3.3 Reset Exception Handling

When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1.

The reset exception handling sequence is as follows. However, for the reset exception handling
sequence of the product with on-chip power-on reset circuit, refer to section 17, Band-Gap Circuit,
Power-On Reset, and Low-Voltage Detection Circuits.

1. Set the I bit in the condition code register (CCR) to 1.

2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.

3.4 Interrupt Exception Handling

3.4.1 External Interrupts

As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.

(1) NMI Interrupt

NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either
rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1.

NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit
value in CCR.

(2) IRQ3 to IRQ0 Interrupts

IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four
interrupts are given different vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1.

When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.

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Section 3 Exception Handling

(3) WKP5 to WKP0 Interrupts

WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.

When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal
edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting bit IENWP in IENR1.

Reset cleared

Initial program
instruction prefetch

RES

ø

Vector fetch

Internal
processing

Internal
address bus

Internal read
signal

Internal write
signal

Internal data
bus (16 bits)

(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction

Figure 3.1 Reset Sequence

(2)(1)

(2) (3)

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Section 3 Exception Handling

3.4.2 Internal Interrupts

Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For timer A interrupt requests and direct transfer interrupt requests
generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1.

When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by
writing 0 to clear the corresponding enable bit.

3.4.3 Interrupt Handling Sequence

Interrupts are controlled by an interrupt controller.

Interrupt operation is described as follows.

1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request
signal is sent to the interrupt controller.

2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for
the interrupt handling with the highest priority at that time according to table 3.1. Other
interrupt requests are held pending.

3. The CPU accepts the NMI and address break without depending on the I bit value. Other
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.

4. If the CPU accepts the interrupt after processing of the current instruction is completed,
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.

5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.

6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.

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Section 3 Exception Handling

Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.

SP – 4

SP – 3

SP – 2

SP – 1

SP (R7)

[Legend]
PC

:

Upper 8 bits of program counter (PC)

H

PC

:

Lower 8 bits of program counter (PC)

L

CCR:

Condition code register

SP:

Stack pointer

1.2.PC shows the address of the first instruction to be executed upon return from the interrupt

Notes:

handling routine.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.

3. Ignored when returning from the interrupt handling routine.

Stack area

Prior to start of interrupt

exception handling

SP (R7)

SP + 1

SP + 2

SP + 3

SP + 4

PC and CCR

saved to stack

CCR

*3

CCR

PCH

PCL

After completion of interrupt

exception handling

Even address

Figure 3.2 Stack Status after Exception Handling

3.4.4 Interrupt Response Time

Table 3.2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.

Table 3.2 Interrupt Wait States

Item States Total

Waiting time for completion of executing instruction* 1 to 23 15 to 37

Saving of PC and CCR to stack 4

Vector fetch 2

Instruction fetch 4

Internal processing 4

Note: * Not including EEPMOV instruction.

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Prefetch instruction of

interrupt-handling routine

Internal

processing

Vector fetch

Stack access

Section 3 Exception Handling

(9)

Internal

processing

(3) (9)(8)(6)(5)

(4) (1) (7) (10)

Instruction

prefetch

Interrupt is

accepted

Interrupt level

decision and wait for

end of instruction

Interrupt

request signal

(1)

ø

Internal

address bus

Internal read

signal

(2)

Internal write

signal

Internal data bus

(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)

(2)(4) Instruction code (not executed)

(3) Instruction prefetch address (Instruction is not executed.)

(5) SP – 2

(6) SP – 4

(7) CCR

(8) Vector address

(9) Starting address of interrupt-handling routine (contents of vector)

(16 bits)

(10) First instruction of interrupt-handling routine

Figure 3.3 Interrupt Sequence

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Section 3 Exception Handling

3.5 Usage Notes

3.5.1 Interrupts after Reset

If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.W #xx: 16, SP).

3.5.2 Notes on Stack Area Use

When word data is accessed, the least significant bit of the address is regarded as 0. Access to the
stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd
address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore
register values.

3.5.3 Notes on Rewriting Port Mode Registers

When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3 to
IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1.

When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0.

Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.

Interrupts masked. (Another possibility

←

CCR I bit 1

Set port mode register bit

Execute NOP instruction

Clear interrupt request flag to 0

←

CCR I bit 0

is to disable the relevant interrupt in
interrupt enable register 1.)

After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0.

Interrupt mask cleared

Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure

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Section 4 Address Break

Section 4 Address Break

The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program. Figure 4.1 shows a block diagram of the address break.

Internal address bus

Comparator

BARH BARL

Interrupt

generation

control circuit

BDRH BDRL

[Legend]
BARH, BARL: Break address register
BDRH, BDRL: Break data register
ABRKCR: Address break control register
ABRKSR: Address break status register

Figure 4.1 Block Diagram of Address Break

4.1 Register Descriptions

Address break has the following registers.

• Address break control register (ABRKCR)

• Address break status register (ABRKSR)

• Break address register (BARH, BARL)

ABRKCR

ABRKSR

Internal data bus

Comparator

Interrupt

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Section 4 Address Break

• Break data register (BDRH, BDRL)

4.1.1 Address Break Control Register (ABRKCR)

ABRKCR sets address break conditions.

Initial

Bit Bit Name

7 RTINTE 1 R/W RTE Interrupt Enable

6

5

4

3

2

1

0

Legend: X: Don't care.

CSEL1

CSEL0 0 0

ACMP2

ACMP1

ACMP0

DCMP1

DCMP0 0 0

Value R/W Description

When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.

R/W

R/W

0

0

0

R/W

R/W

R/W

R/W

R/W

Condition Select 1 and 0

These bits set address break conditions.

00: Instruction execution cycle

01: CPU data read cycle

10: CPU data write cycle

11: CPU data read/write cycle

Address Compare Condition Select 2 to 0

These bits set the comparison condition between the
address set in BAR and the internal address bus.

000: Compares 16-bit addresses

001: Compares upper 12-bit addresses

010: Compares upper 8-bit addresses

011: Compares upper 4-bit addresses

1XX: Reserved (setting prohibited)

Data Compare Condition Select 1 and 0

These bits set the comparison condition between the data
set in BDR and the internal data bus.

00: No data comparison

01: Compares lower 8-bit data between BDRL and data

bus

10: Compares upper 8-bit data between BDRH and data

bus

11: Compares 16-bit data between BDR and data bus

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Section 4 Address Break

When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 19.1,
Register Addresses (Address Order).

Table 4.1 Access and Data Bus Used

Word Access Byte Access
Even Address Odd Address Even Address Odd Address

ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits

RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits

I/O register with 8-bit data bus
width

I/O register with 16-bit data
bus width

Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits

Upper 8 bits Lower 8 bits — —

4.1.2 Address Break Status Register (ABRKSR)

ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.

Initial

Bit Bit Name

7 ABIF 0 R/W Address Break Interrupt Flag

6 ABIE 0 R/W Address Break Interrupt Enable

5 to 0 — All 1 — Reserved

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REJ09B0268-0100

Value R/W Description

[Setting condition]

When the condition set in ABRKCR is satisfied

[Clearing condition]

When 0 is written after ABIF=1 is read

When this bit is 1, an address break interrupt request is
enabled.

These bits are always read as 1.

Section 4 Address Break

4.1.3 Break Address Registers (BARH, BARL)

BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.

4.1.4 Break Data Registers (BDRH, BDRL)

BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8­bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section

4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.

4.2 Operation

When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked by the I bit in CCR of the CPU.

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REJ09B0268-0100

Section 4 Address Break

Figures 4.2 show the operation examples of the address break interrupt setting.

When the address break is specified in instruction execution cycle

Register setting

• ABRKCR = H'80

• BAR = H'025A

NOP

instruc-

tion

prefetch

φ

Address
bus

Interrupt
request

0258

Program

0258

NOP

025A

*

NOP

025C

MOV.W @H'025A,R0

0260

NOP

0262

NOP

:

:

NOP

instruc-

prefetch

MOV

instruc-

tion

tion 1

prefetch

025A 025C 025E SP-2 SP-4

Interrupt acceptance

MOV

instruc-

tion 2

prefetch

Figure 4.2 Address Break Interrupt Operation Example (1)

When the address break is specified in the data read cycle

Register setting

• ABRKCR = H'A0

• BAR = H'025A

Program

0258

NOP

025A

NOP

025C

*

MOV.W @H'025A,R0

0260

NOP

0262

NOP

:

:

Underline indicates the address
to be stacked.

Internal

processing

Underline indicates the address
to be stacked.

Stack save

φ

Address
bus

Interrupt
request

MOV

instruc-

tion 1

prefetch

025C

MOV

instruc-

tion 2

prefetch

NOP

instruc-

tion

prefetch

025E 0260 025A 0262 0264 SP-2

MOV

instruc-

tion

execution

NOP

instruc-

tion

prefetch

Interrupt acceptance

Next

instru-

ction

prefetch

Internal

processing

Stack

save

Figure 4.2 Address Break Interrupt Operation Example (2)

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Section 4 Address Break

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REJ09B0268-0100

Section 5 Clock Pulse Generators

Section 5 Clock Pulse Generators

The clock pulse generator (CPG) consists of a system clock generating circuitry, a subclock
generating circuitry, and two prescalers. The system clock generating circuitry includes an
external clock oscillator, a duty correction circuit, an on-chip oscillator, an RC clock divider, a
clock select circuit, and a system clock divider. The subclock generating circuitry includes a
subclock oscillator, and a subclock divider. The CPG can function as a clock generating circuitry
itself or in combination with an external oscillator. Figure 5.1 shows a block diagram of the clock
pulse generator.

OSC1

OSC2

X

1

X

2

External

clock

oscillator

On-chip
oscillator

System clock generating circuitry

Subclock
oscillator

Subclock generating circuitry

φ

R

OSC

OSC

Duty

correction

circuit

RC clock
divider

φ

(fW)

φ

OSC

Clock

R

OSC

R

/2

OSC

R

/4

OSC

W

select
circuit

φ

RC

φ

Subclock

divider

System

clock

divider

φ

W

φ

W

φW/8

φ
φ/8

φ

φ/16
φ/32

SUB

φ/2
to
φ/8192

/8

φ

W

to

φ

/128

W

φ/64

/2

/4

Prescaler S

(13 bits)

φ

Prescaler W

(5 bits)

Figure 5.1 Block Diagram of Clock Pulse Generators

The system clock (φ) and subclock (φ

) are basic clocks on which the CPU and on-chip

SUB

peripheral modules operate. The system clock is divided into from φ/2 to φ/8192 by prescaler S.
The subclock is divided into from φ

/8 to φ

W

/128 by prescaler W. These divided clocks are

W

supplied to respective peripheral modules.

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Section 5 Clock Pulse Generators

5.1 Features

• Choice of two clock sources

On-chip oscillator clock

Clock by an external oscillator output

• Choice of two types of RC oscillation frequency by the user software

16 MHz

20 MHz

• Frequency trimming

Since the initial frequency of the on-chip oscillator is within the range of two frequencies
shown above, it is normally unnecessary to trim the frequency. It is, however, still possible to
adjust it by rewriting the trimming registers.

• Backup of the external oscillation halt

This system detects the external oscillator halt. If detected, the system clock source is
automatically switched to the on-chip oscillator clock.

• Interrupt can be requested to the CPU when the system clock is switched from the external

clock to the on-chip oscillator clock.

5.2 Register Descriptions

Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance
crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a crystal resonator. A
resonator having the characteristics given in table 5.1 should be used.

The CPG has the following registers.

• RC control register (RCCR)

• RC trimming data protect register (RCTRMDPR)

• RC trimming data register (RCTRMDR)

• Clock control/status register (CKCSR)

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Section 5 Clock Pulse Generators

5.2.1 RC Control Register (RCCR)

RCCR controls the on-chip oscillator.

Initial

Bit Bit Name

7 RCSTP 0 R/W On-Chip Oscillator Standby

6 FSEL 1 R/W Frequency Select for On-chip Oscillator

5 VCLSEL 0 R/W Power Supply Select for On-chip Oscillator

4 to 2  All 0  Reserved

1

0

RCPSC1

RCPSC0 1 0

Value R/W Description

The on-chip oscillator standby state is entered by setting
this bit to 1.

0: 16 MHz

1: 20 MHz

0: Selects VBGR

1: Selects VCL

When the VCL power is selected, the accuracy of the on­chip oscillator frequency cannot be guaranteed.

These bits are always read as 0.

R/W

R/W

Division Ratio Select for On-chip Oscillator

The division ratio of R
bit.

These bits can be written to only when the CKSTA bit in
CKCSR is 0.

0X: R

10: R

11: R

(not divided)

OSC

/2

OSC

/4

OSC

changes right after rewriting this

OSC

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Section 5 Clock Pulse Generators

5.2.2 RC Trimming Data Protect Register (RCTRMDPR)

RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to
rewrite this register. Bit manipulation instruction cannot change the settings.

Initial

Bit Bit Name

7 WRI 1 W Write Inhibit

6 PRWE 0 R/W Protect Information Write Enable

5 LOCKDW 0 R/W Trimming Data Register Lock Down

Value R/W Description

Only when writing 0 to this bit, this register can be written
to. This bit is always read as 1.

Bits 5 and 4 can be written to when this bit is set to 1.

[Setting condition]

• When writing 0 to the WRI bit and writing 1 to the

PRWE bit

[Clearing conditions]

• Reset

• When writing 0 to the WRI bit and writing 0 to the

PRWE bit

The RC trimming data register (RCTRMDR) cannot be
written to when this bit is set to 1. Once this bit is set to 1,
this register cannot be written to until a reset is input even
if 0 is written to this bit.

[Setting condition]

• When writing 0 to the WRI bit and writing 1 to the

LOCKDW bit while the PRWE bit is 1

[Clearing condition]

• Reset

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Section 5 Clock Pulse Generators

Initial

Bit Bit Name

Value R/W Description

4 TRMDRWE 0 R/W Trimming Data Register Write Enable

This register can be written to when the LOCKDW bit is 0
and this bit is 1.

[Setting condition]

• When writing 0 to the WRI bit while writing 1 to the

TRMDRWE bit while the PRWE bit is 1

[Clearing conditions]

• Reset

• When writing 0 to the WRI bit and writing 0 to the

TRMDRWE bit while the PRWE bit is 1

3 to 0  All 1  Reserved

These bits are always read as 1.

5.2.3 RC Trimming Data Register (RCTRMDR)

RCTRMDR stores the trimming data of the on-chip oscillator frequency (FSEL = 1, 20 MHz).

Initial

Bit Bit Name

7 TRMD7 (0)* R/W

6 TRMD6 (0)* R/W

5 TRMD5 (0)* R/W

4 TRMD4 (0)* R/W

3 TRMD3 (0)* R/W

2 TRMD2 (0)* R/W

1 TRMD1 (0)* R/W

0 TRMD0 (0)* R/W

Value R/W Description

Trimming Data (FSEL = 1, 20 MHz)

The trimming data is loaded from the flash memory to this
register right after a reset.

The on-chip oscillator clock (FSEL = 1, 20 MHz) can be
trimmed by changing these bits.

The frequency of the on-chip oscillator clock changes
right after writing these bits. These bits are initialized to
H'00.

Changes in frequency are shown below (bit TRMD7 is a
sign bit).

(Min.) H'80 ← … ← H'FF ← … ← H'00 → … →H'01 → …
→ H'7F (Max.)

Note: * These values are initialized to the trimming data loaded from the flash memory.

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Section 5 Clock Pulse Generators

5.2.4 Clock Control/Status Register (CKCSR)

CKCSR selects the port C function, controls switching the system clocks, and indicates the system
clock state.

Initial

Bit Bit Name

7

6

5 OSCBAKE 0 R/W External Clock Backup Enable

PMRC1

PMRC0 0 0

Value R/W Description

R/W

R/W

Port C Function Select 1 and 2
PMRC1 PMRC0 PC1 PC0

0 0 I/O I/O

1 0 CLKOUT I/O

0 1 Open OSC1 (external

1 1 OSC2 OSC1

0: External clock backup disabled

1: External clock backup enabled

The external oscillation detecting circuit is enabled when
this bit is 1. When the external oscillator halt is detected
while this LSI operates on the external input signal, the
system clock source is automatically switched to the on­chip oscillator regardless of the value of bit 4 in this
register.

Note: The external oscillation detecting circuit operates

on the on-chip oscillator clock. When this bit is set
to 1, do not set the on-chip oscillator to the standby
mode by the RCSTP bit in RCCR.

clock input)

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Section 5 Clock Pulse Generators

Initial

Bit Bit Name

Value R/W Description

4 OSCSEL 0 R/W LSI Operating Clock Select

• When OSCBAKE = 0

This bit is used to forcibly select the system clock of this
LSI.

0: The on-chip oscillator clock selected as the system

clock source

1: The external input selected as the system clock source

• When OSCBAKE = 1

This bit is used to switch the on-chip oscillator clock to the
external clock. While this LSI is operating on the on-chip
oscillator clock, setting this bit to 1 switches the system
clocks to the external clock.

[Setting condition]

• When 1 is written to this bit while CKSWIF = 0

[Clearing conditions]

• When 0 is written to this bit

• When the external oscillator halt is detected while

OSCBAKE = 1

3 CKSWIE 0 R/W Clock Switching Interrupt Enable

Setting this bit to 1 enables the clock switching interrupt
request.

2 CKSWIF 0 R/W Clock Switching Interrupt Request Flag

[Setting condition]

• When the external clock is switched to the on-chip

oscillator clock as the system clock source

[Clearing condition]

• When writing 0 after reading as 1

1 OSCHLT 1 R External Oscillator Halt Detecting Flag

• When OSCBAKE = 1

This bit indicates the checking result of the external
oscillator state.

0: External oscillator is running

1: External oscillator is halted.

• When OSCBAKE = 0

This bit is non-deterministic; always read as 1.

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Section 5 Clock Pulse Generators

Initial

Bit Bit Name

Value R/W Description

0 CKSTA 0 R LSI Operating Clock Status

0: This LSI operates on the on-chip oscillator clock.

1: This LSI operates on the external clock.

5.3 System Clock Select Operation

Figure 5.2 shows the state transition of the system clock.

LSI operates on on-chip oscillator clock

Reset state

On-chip oscillator: Halted
External oscillator: Operated

Note: * Conditions for the state transition are as follows:

• When the external oscillator halt is detected while the backup function is enabled

• When the external clock is switched to the on-chip oscillator clock by user software
while the backup function is disabled

Reset release

Oscillator halted

Oscillator operated

On-chip oscillator: Operated
External oscillator: Halted

*

On-chip oscillator: Operated
External oscillator: Operated

LSI operates on external oscillator

Switching to
external clock

Figure 5.2 State Transition of System Clock

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