Renesas H8 Series, H8/36094F, HD64F36094, HD64F36094G, H8/36092F Hardware Manual

To our customers,

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User’s Manual

16

H8/36094 Group

Hardware Manual

Renesas 16-Bit Single-Chip
Microcomputer
H8 Family/H8/300H Tiny Series

H8/36094F HD64F36094
HD64F36094G
H8/36092F HD64F36092
HD64F36092G

Rev.1.00 2006.08

Rev. 1.00 Aug. 28, 2006 Page ii of xxviii

Keep safety first in your circuit designs!

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Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

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Rev. 1.00 Aug. 28, 2006 Page iii of xxviii

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 1.00 Aug. 28, 2006 Page iv of xxviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 1.00 Aug. 28, 2006 Page v of xxviii

Preface

The H8/36094 Group are single-chip microcomputers made up of the high-speed H8/300H CPU
employing Renesas Technology original architecture as their cores, and the peripheral functions
required to configure a system. The H8/300H CPU has an instruction set that is compatible with
the H8/300 CPU.

Target Users: This manual was written for users who will be using the H8/36094 Group in the

design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8/36094 Group to the target users.
Refer to the H8/300H Series Software Manual for a detailed description of the
instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8/300H Series Software Manual.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 19,
List of Registers.

Example: Bit order: The MSB is on the left and the LSB is on the right.

Notes:

When using the on-chip emulator (E7, E8) for H8/36094 program development and debugging,
the following restrictions must be noted.

1. The NMI pin is reserved for the E7 or E8, and cannot be used.

2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be
provided on the user board.

3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user.

4. Area H'F780 to H'FB7F must on no account be accessed.

Rev. 1.00 Aug. 28, 2006 Page vi of xxviii

5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use
by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break
control registers must not be accessed.

6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and
P87 are input pins, and P86 is an output pin.

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/

H8/36094 Group manuals:

Document Title Document No.

H8/36094 Group Hardware Manual This manual

H8/300H Series Software Manual REJ09B0213

User's manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual

H8S, H8/300 Series Simulator/Debugger User's Manual REJ10B0211

H8S, H8/300 Series High-Performance Embedded Workshop 3, Tutorial REJ10B0024

H8S, H8/300 Series High-Performance Embedded Workshop 3, User's Manual REJ10B0026

REJ10B0058

Application notes:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464

Single Power Supply F-ZTATTM On-Board Programming REJ05B0520

Rev. 1.00 Aug. 28, 2006 Page vii of xxviii

Rev. 1.00 Aug. 28, 2006 Page viii of xxviii

Contents

Section 1 Overview................................................................................................1

1.1 Features.................................................................................................................................. 1

1.2 Internal Block Diagram..........................................................................................................3

1.3 Pin Assignments..................................................................................................................... 4

1.4 Pin Functions .........................................................................................................................6

Section 2 CPU........................................................................................................9

2.1 Address Space and Memory Map ........................................................................................ 10

2.2 Register Configuration......................................................................................................... 11

2.2.1 General Registers.................................................................................................... 12

2.2.2 Program Counter (PC) ............................................................................................ 13

2.2.3 Condition-Code Register (CCR)............................................................................. 13

2.3 Data Formats........................................................................................................................ 15

2.3.1 General Register Data Formats............................................................................... 15

2.3.2 Memory Data Formats ............................................................................................ 17

2.4 Instruction Set ...................................................................................................................... 18

2.4.1 Table of Instructions Classified by Function .......................................................... 18

2.4.2 Basic Instruction Formats ....................................................................................... 27

2.5 Addressing Modes and Effective Address Calculation........................................................ 28

2.5.1 Addressing Modes ..................................................................................................28

2.5.2 Effective Address Calculation ................................................................................ 32

2.6 Basic Bus Cycle ................................................................................................................... 34

2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 34

2.6.2 On-Chip Peripheral Modules .................................................................................. 35

2.7 CPU States ........................................................................................................................... 36

2.8 Usage Notes ......................................................................................................................... 37

2.8.1 Notes on Data Access to Empty Areas ................................................................... 37

2.8.2 EEPMOV Instruction.............................................................................................. 37

2.8.3 Bit Manipulation Instruction................................................................................... 37

Section 3 Exception Handling .............................................................................43

3.1 Exception Sources and Vector Address ............................................................................... 43

3.2 Register Descriptions...........................................................................................................45

3.2.1 Interrupt Edge Select Register 1 (IEGR1) ..............................................................45

3.2.2 Interrupt Edge Select Register 2 (IEGR2) ..............................................................46

3.2.3 Interrupt Enable Register 1 (IENR1) ...................................................................... 47

Rev. 1.00 Aug. 28, 2006 Page ix of xxviii

3.2.4 Interrupt Flag Register 1 (IRR1)............................................................................. 48

3.2.5 Wakeup Interrupt Flag Register (IWPR) ................................................................ 49

3.3 Reset Exception Handling.................................................................................................... 51

3.4 Interrupt Exception Handling .............................................................................................. 51

3.4.1 External Interrupts .................................................................................................. 51

3.4.2 Internal Interrupts ................................................................................................... 53

3.4.3 Interrupt Handling Sequence .................................................................................. 53

3.4.4 Interrupt Response Time......................................................................................... 54

3.5 Usage Notes ......................................................................................................................... 56

3.5.1 Interrupts after Reset............................................................................................... 56

3.5.2 Notes on Stack Area Use ........................................................................................ 56

3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 56

Section 4 Address Break .....................................................................................57

4.1 Register Descriptions...........................................................................................................57

4.1.1 Address Break Control Register (ABRKCR) ......................................................... 58

4.1.2 Address Break Status Register (ABRKSR) ............................................................ 59

4.1.3 Break Address Registers (BARH, BARL).............................................................. 60

4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 60

4.2 Operation ............................................................................................................................. 60

Section 5 Clock Pulse Generators .......................................................................63

5.1 Features................................................................................................................................ 64

5.2 Register Descriptions...........................................................................................................64

5.2.1 RC Control Register (RCCR) ................................................................................. 65

5.2.2 RC Trimming Data Protect Register (RCTRMDPR).............................................. 66

5.2.3 RC Trimming Data Register (RCTRMDR)............................................................ 67

5.2.4 Clock Control/Status Register (CKCSR)................................................................ 68

5.3 System Clock Select Operation ........................................................................................... 70

5.3.1 Clock Control Operation......................................................................................... 71

5.3.2 Clock Switching Timing......................................................................................... 74

5.4 Trimming of On-Chip Oscillator Frequency........................................................................ 77

5.5 External Clock Oscillators ................................................................................................... 79

5.5.1 Connecting Crystal Resonator ................................................................................ 79

5.5.2 Connecting Ceramic Resonator .............................................................................. 80

5.5.3 Inputting External Clock......................................................................................... 80

5.6 Subclock Oscillator.............................................................................................................. 81

5.6.1 Connecting 32.768-kHz Crystal Resonator ............................................................ 81

5.6.2 Pin Connection when Not Using Subclock............................................................. 82

5.7 Prescaler............................................................................................................................... 82

Rev. 1.00 Aug. 28, 2006 Page x of xxviii

5.7.1 Prescaler S .............................................................................................................. 82

5.7.2 Prescaler W............................................................................................................. 82

5.8 Usage Notes ......................................................................................................................... 83

5.8.1 Note on Resonators................................................................................................. 83

5.8.2 Notes on Board Design ........................................................................................... 83

Section 6 Power-Down Modes ............................................................................85

6.1 Register Descriptions...........................................................................................................85

6.1.1 System Control Register 1 (SYSCR1) .................................................................... 85

6.1.2 System Control Register 2 (SYSCR2) .................................................................... 87

6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 88

6.2 Mode Transitions and States of LSI..................................................................................... 89

6.2.1 Sleep Mode ............................................................................................................. 92

6.2.2 Standby Mode......................................................................................................... 92

6.2.3 Subsleep Mode........................................................................................................ 93

6.2.4 Subactive Mode ...................................................................................................... 93

6.3 Operating Frequency in Active Mode.................................................................................. 94

6.4 Direct Transition .................................................................................................................. 94

6.4.1 Direct Transition from Active Mode to Subactive Mode ....................................... 94

6.4.2 Direct Transition from Subactive Mode to Active Mode ....................................... 95

6.5 Module Standby Function.................................................................................................... 95

Section 7 ROM ....................................................................................................97

7.1 Block Configuration.............................................................................................................98

7.2 Register Descriptions...........................................................................................................99

7.2.1 Flash Memory Control Register 1 (FLMCR1)........................................................ 99

7.2.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 100

7.2.3 Erase Block Register 1 (EBR1) ............................................................................ 101

7.2.4 Flash Memory Power Control Register (FLPWCR)............................................. 102

7.2.5 Flash Memory Enable Register (FENR)............................................................... 102

7.3 On-Board Programming Modes......................................................................................... 103

7.3.1 Boot Mode ............................................................................................................ 103

7.3.2 Programming/Erasing in User Program Mode...................................................... 106

7.4 Flash Memory Programming/Erasing................................................................................ 107

7.4.1 Program/Program-Verify ...................................................................................... 107

7.4.2 Erase/Erase-Verify................................................................................................ 109

7.4.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 110

7.5 Program/Erase Protection .................................................................................................. 112

7.5.1 Hardware Protection .............................................................................................112

7.5.2 Software Protection............................................................................................... 112

Rev. 1.00 Aug. 28, 2006 Page xi of xxviii

7.5.3 Error Protection .................................................................................................... 112

7.6 Programmer Mode ............................................................................................................. 113

7.7 Power-Down States for Flash Memory.............................................................................. 113

Section 8 RAM ..................................................................................................115

Section 9 I/O Ports.............................................................................................117

9.1 Port 1.................................................................................................................................. 117

9.1.1 Port Mode Register 1 (PMR1) .............................................................................. 118

9.1.2 Port Control Register 1 (PCR1) ............................................................................ 119

9.1.3 Port Data Register 1 (PDR1) ................................................................................ 120

9.1.4 Port Pull-Up Control Register 1 (PUCR1)............................................................ 120

9.1.5 Pin Functions ........................................................................................................ 121

9.2 Port 2.................................................................................................................................. 123

9.2.1 Port Control Register 2 (PCR2) ............................................................................ 123

9.2.2 Port Data Register 2 (PDR2) ................................................................................ 124

9.2.3 Pin Functions ........................................................................................................ 124

9.3 Port 5.................................................................................................................................. 125

9.3.1 Port Mode Register 5 (PMR5) .............................................................................. 126

9.3.2 Port Control Register 5 (PCR5) ............................................................................ 127

9.3.3 Port Data Register 5 (PDR5) ................................................................................ 128

9.3.4 Port Pull-Up Control Register 5 (PUCR5)............................................................ 128

9.3.5 Pin Functions ........................................................................................................ 129

9.4 Port 7.................................................................................................................................. 131

9.4.1 Port Control Register 7 (PCR7) ............................................................................ 132

9.4.2 Port Data Register 7 (PDR7) ................................................................................ 132

9.4.3 Pin Functions ........................................................................................................ 133

9.5 Port 8.................................................................................................................................. 134

9.5.1 Port Control Register 8 (PCR8) ............................................................................ 135

9.5.2 Port Data Register 8 (PDR8) ................................................................................ 135

9.5.3 Pin Functions ........................................................................................................ 136

9.6 Port B................................................................................................................................. 139

9.6.1 Port Data Register B (PDRB) ............................................................................... 139

9.7 Port C................................................................................................................................. 140

9.7.1 Port Control Register C (PCRC)........................................................................... 140

9.7.2 Port Data Register C (PDRC) ............................................................................... 141

9.7.3 Pin Functions ........................................................................................................ 141

Rev. 1.00 Aug. 28, 2006 Page xii of xxviii

Section 10 Timer A............................................................................................143

10.1 Features.............................................................................................................................. 143

10.2 Input/Output Pins...............................................................................................................144

10.3 Register Descriptions......................................................................................................... 145

10.3.1 Timer Mode Register A (TMA)............................................................................ 145

10.3.2 Timer Counter A (TCA) ....................................................................................... 146

10.4 Operation ........................................................................................................................... 147

10.4.1 Interval Timer Operation ...................................................................................... 147

10.4.2 Clock Time Base Operation.................................................................................. 147

10.4.3 Clock Output......................................................................................................... 147

10.5 Usage Note......................................................................................................................... 147

Section 11 Timer V............................................................................................149

11.1 Features.............................................................................................................................. 149

11.2 Input/Output Pins...............................................................................................................151

11.3 Register Descriptions......................................................................................................... 151

11.3.1 Timer Counter V (TCNTV) .................................................................................. 151

11.3.2 Time Constant Registers A and B (TCORA, TCORB) ........................................ 152

11.3.3 Timer Control Register V0 (TCRV0) ...................................................................152

11.3.4 Timer Control/Status Register V (TCSRV) .......................................................... 154

11.3.5 Timer Control Register V1 (TCRV1) ...................................................................155

11.4 Operation ........................................................................................................................... 156

11.4.1 Timer V Operation................................................................................................ 156

11.5 Timer V Application Examples ......................................................................................... 159

11.5.1 Pulse Output with Arbitrary Duty Cycle............................................................... 159

11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input ..............160

11.6 Usage Notes ....................................................................................................................... 161

Section 12 Timer W...........................................................................................163

12.1 Features.............................................................................................................................. 163

12.2 Input/Output Pins...............................................................................................................166

12.3 Register Descriptions......................................................................................................... 166

12.3.1 Timer Mode Register W (TMRW) ....................................................................... 167

12.3.2 Timer Control Register W (TCRW) ..................................................................... 168

12.3.3 Timer Interrupt Enable Register W (TIERW) ...................................................... 169

12.3.4 Timer Status Register W (TSRW) ........................................................................ 170

12.3.5 Timer I/O Control Register 0 (TIOR0) ................................................................. 171

12.3.6 Timer I/O Control Register 1 (TIOR1) ................................................................. 173

12.3.7 Timer Counter (TCNT)......................................................................................... 174

Rev. 1.00 Aug. 28, 2006 Page xiii of xxviii

12.3.8 General Registers A to D (GRA to GRD)............................................................. 175

12.4 Operation ........................................................................................................................... 176

12.4.1 Normal Operation ................................................................................................. 176

12.4.2 PWM Operation .................................................................................................... 181

12.5 Operation Timing............................................................................................................... 186

12.5.1 TCNT Count Timing ............................................................................................ 186

12.5.2 Output Compare Output Timing........................................................................... 186

12.5.3 Input Capture Timing ........................................................................................... 187

12.5.4 Timing of Counter Clearing by Compare Match .................................................. 188

12.5.5 Buffer Operation Timing ...................................................................................... 188

12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ................................. 189

12.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................. 190

12.5.8 Timing of Status Flag Clearing............................................................................. 190

12.6 Usage Notes ....................................................................................................................... 191

Section 13 Watchdog Timer.............................................................................. 195

13.1 Features.............................................................................................................................. 195

13.2 Register Descriptions......................................................................................................... 196

13.2.1 Timer Control/Status Register WD (TCSRWD) .................................................. 196

13.2.2 Timer Counter WD (TCWD)................................................................................ 197

13.2.3 Timer Mode Register WD (TMWD) .................................................................... 198

13.3 Operation ........................................................................................................................... 199

Section 14 Serial Communication Interface 3 (SCI3)....................................... 201

14.1 Features.............................................................................................................................. 201

14.2 Input/Output Pins...............................................................................................................203

14.3 Register Descriptions......................................................................................................... 203

14.3.1 Receive Shift Register (RSR) ............................................................................... 204

14.3.2 Receive Data Register (RDR)............................................................................... 204

14.3.3 Transmit Shift Register (TSR) .............................................................................. 204

14.3.4 Transmit Data Register (TDR).............................................................................. 204

14.3.5 Serial Mode Register (SMR) ................................................................................ 205

14.3.6 Serial Control Register 3 (SCR3) ......................................................................... 206

14.3.7 Serial Status Register (SSR) ................................................................................. 208

14.3.8 Bit Rate Register (BRR) ....................................................................................... 210

14.4 Operation in Asynchronous Mode ..................................................................................... 215

14.4.1 Clock..................................................................................................................... 215

14.4.2 SCI3 Initialization................................................................................................. 216

14.4.3 Data Transmission ................................................................................................ 217

14.4.4 Serial Data Reception ........................................................................................... 219

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14.5 Operation in Clocked Synchronous Mode......................................................................... 223

14.5.1 Clock..................................................................................................................... 223

14.5.2 SCI3 Initialization ................................................................................................. 224

14.5.3 Serial Data Transmission ...................................................................................... 224

14.5.4 Serial Data Reception (Clocked Synchronous Mode)........................................... 227

14.5.5 Simultaneous Serial Data Transmission and Reception........................................ 229

14.6 Multiprocessor Communication Function.......................................................................... 231

14.6.1 Multiprocessor Serial Data Transmission ............................................................. 233

14.6.2 Multiprocessor Serial Data Reception .................................................................. 234

14.7 Interrupts............................................................................................................................ 238

14.8 Usage Notes ....................................................................................................................... 238

14.8.1 Break Detection and Processing ........................................................................... 238

14.8.2 Mark State and Break Sending.............................................................................. 239

14.8.3 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) ..................................................................... 239

14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous

Mode..................................................................................................................... 239

Section 15 I2C Bus Interface 2 (IIC2) ................................................................241

15.1 Features.............................................................................................................................. 241

15.2 Input/Output Pins...............................................................................................................243

15.3 Register Descriptions......................................................................................................... 244

15.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 244

15.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 247

15.3.3 I2C Bus Mode Register (ICMR)............................................................................ 249

15.3.4 I2C Bus Interrupt Enable Register (ICIER)........................................................... 251

15.3.5 I2C Bus Status Register (ICSR)............................................................................. 253

15.3.6 Slave Address Register (SAR).............................................................................. 255

15.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 256

15.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 256

15.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 256

15.4 Operation ........................................................................................................................... 257

15.4.1 I2C Bus Format...................................................................................................... 257

15.4.2 Master Transmit Operation ................................................................................... 258

15.4.3 Master Receive Operation..................................................................................... 260

15.4.4 Slave Transmit Operation ..................................................................................... 262

15.4.5 Slave Receive Operation....................................................................................... 264

15.4.6 Clocked Synchronous Serial Format..................................................................... 266

15.4.7 Noise Canceler ...................................................................................................... 268

15.4.8 Example of Use..................................................................................................... 269

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15.5 Interrupt Request................................................................................................................ 273

15.6 Bit Synchronous Circuit..................................................................................................... 273

15.7 Usage Notes ....................................................................................................................... 274

15.7.1 Issue (Retransmission) of Start/Stop Conditions .................................................. 274

15.7.2 WAIT Setting in I2C Bus Mode Register (ICMR)................................................ 274

Section 16 A/D Converter ................................................................................. 275

16.1 Features.............................................................................................................................. 275

16.2 Input/Output Pins...............................................................................................................277

16.3 Register Descriptions......................................................................................................... 278

16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 278

16.3.2 A/D Control/Status Register (ADCSR) ................................................................ 279

16.3.3 A/D Control Register (ADCR) ............................................................................. 281

16.4 Operation ........................................................................................................................... 282

16.4.1 Single Mode.......................................................................................................... 282

16.4.2 Scan Mode ............................................................................................................ 282

16.4.3 Input Sampling and A/D Conversion Time .......................................................... 283

16.4.4 External Trigger Input Timing.............................................................................. 284

16.5 A/D Conversion Accuracy Definitions.............................................................................. 285

16.6 Usage Notes ....................................................................................................................... 287

16.6.1 Permissible Signal Source Impedance .................................................................. 287

16.6.2 Influences on Absolute Accuracy ......................................................................... 287

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection

Circuits ............................................................................................289

17.1 Features.............................................................................................................................. 290

17.2 Register Descriptions......................................................................................................... 292

17.2.1 Low-Voltage-Detection Control Register (LVDCR)............................................ 292

17.2.2 Low-Voltage-Detection Status Register (LVDSR)............................................... 293

17.2.3 Reset Source Decision Register (LVDRF) ........................................................... 294

17.3 Operations.......................................................................................................................... 295

17.3.1 Power-On Reset Circuit ........................................................................................ 295

17.3.2 Low-Voltage Detection Circuit............................................................................. 296

17.3.3 Deciding Reset Source.......................................................................................... 299

Section 18 Power Supply Circuit ......................................................................301

18.1 When Using Internal Power Supply Step-Down Circuit ................................................... 301

18.2 When Not Using Internal Power Supply Step-Down Circuit............................................. 302

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Section 19 List of Registers ...............................................................................303

19.1 Register Addresses (Address Order).................................................................................. 304

19.2 Register Bits....................................................................................................................... 309

19.3 Registers States in Each Operating Mode.......................................................................... 313

Section 20 Electrical Characteristics .................................................................317

20.1 Absolute Maximum Ratings .............................................................................................. 317

20.2 Electrical Characteristics.................................................................................................... 317

20.2.1 Power Supply Voltage and Operating Ranges ...................................................... 317

20.2.2 DC Characteristics ................................................................................................320

20.2.3 AC Characteristics ................................................................................................325

20.2.4 A/D Converter Characteristics .............................................................................. 330

20.2.5 Watchdog Timer Characteristics........................................................................... 331

20.2.6 Flash Memory Characteristics .............................................................................. 332

20.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ................... 334

20.2.8 Power-On Reset Circuit Characteristics (Optional) .............................................. 334

20.3 Operation Timing............................................................................................................... 335

20.4 Output Load Condition ...................................................................................................... 337

Appendix A Instruction Set ...............................................................................339

A.1 Instruction List................................................................................................................... 339

A.2 Operation Code Map.......................................................................................................... 354

A.3 Number of Execution States .............................................................................................. 357

A.4 Combinations of Instructions and Addressing Modes ....................................................... 368

Appendix B I/O Port Block Diagrams...............................................................369

B.1 I/O Port Block Diagrams.................................................................................................... 369

B.2 Port States in Each Operating State ................................................................................... 388

Appendix C Product Code Lineup.....................................................................389

Appendix D Package Dimensions .....................................................................390

Appendix E Function Comparison ....................................................................396

Index .........................................................................................................397

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Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram of H8/36094 Group of F-ZTATTM.......................................... 3

Figure 1.2 Pin Assignments of H8/36094 Group of F-ZTATTM (FP-64K, FP-64A)...................... 4

Figure 1.3 Pin Assignments of H8/36094 Group of F-ZTATTM (FP-48F, FP-48B, TNP-48) ........ 5

Section 2 CPU

Figure 2.1 Memory map ...............................................................................................................10

Figure 2.2 CPU Registers .............................................................................................................11

Figure 2.3 Usage of General Registers .........................................................................................12

Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 13

Figure 2.5 General Register Data Formats (1).............................................................................. 15

Figure 2.5 General Register Data Formats (2).............................................................................. 16

Figure 2.6 Memory Data Formats.................................................................................................17

Figure 2.7 Instruction Formats......................................................................................................28

Figure 2.8 Branch Address Specification in Memory Indirect Mode........................................... 31

Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 34

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access).....................................35

Figure 2.11 CPU Operation States................................................................................................ 36

Figure 2.12 State Transitions........................................................................................................ 37

Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same

Address...................................................................................................................... 38

Section 3 Exception Handling

Figure 3.1 Reset Sequence............................................................................................................ 52

Figure 3.2 Stack Status after Exception Handling........................................................................ 54

Figure 3.3 Interrupt Sequence....................................................................................................... 55

Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 56

Section 4 Address Break

Figure 4.1 Block Diagram of Address Break................................................................................57

Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 61

Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 61

Section 5 Clock Pulse Generators

Figure 5.1 Block Diagram of Clock Pulse Generators..................................................................63

Figure 5.2 State Transition of System Clock................................................................................ 70

Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled................................... 71

Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1)

(From On-Chip Oscillator Clock to External Clock) ................................................72

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Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2)

(From External Clock to On-Chip Oscillator Clock).................................................. 73

Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock.......... 74

Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock ...............75

Figure 5.8 External Oscillation Backup Timing........................................................................... 76

Figure 5.9 Example of Trimming Flow for On-Chip Oscillator Clock ........................................77

Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency .................................. 78

Figure 5.11 Example of Connection to Crystal Resonator ........................................................... 79

Figure 5.12 Equivalent Circuit of Crystal Resonator....................................................................79

Figure 5.13 Example of Connection to Ceramic Resonator ......................................................... 80

Figure 5.14 Example of External Clock Input.............................................................................. 80

Figure 5.15 Block Diagram of Subclock Oscillator...................................................................... 81

Figure 5.16 Typical Connection to 32.768-kHz Crystal Resonator.............................................. 81

Figure 5.17 Equivalent Circuit of 32.768-kHz Crystal Resonator................................................ 81

Figure 5.18 Pin Connection when not Using Subclock ................................................................ 82

Figure 5.19 Example of Incorrect Board Design.......................................................................... 83

Section 6 Power-Down Modes

Figure 6.1 Mode Transition Diagram ........................................................................................... 89

Section 7 ROM

Figure 7.1 Flash Memory Block Configuration............................................................................98

Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode.......................... 106

Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 108

Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 111

Section 9 I/O Ports

Figure 9.1 Port 1 Pin Configuration............................................................................................ 117

Figure 9.2 Port 2 Pin Configuration............................................................................................ 123

Figure 9.3 Port 5 Pin Configuration............................................................................................ 125

Figure 9.4 Port 7 Pin Configuration............................................................................................ 131

Figure 9.5 Port 8 Pin Configuration............................................................................................ 134

Figure 9.6 Port B Pin Configuration...........................................................................................139

Figure 9.7 Port C Pin Configuration...........................................................................................140

Section 10 Timer A

Figure 10.1 Block Diagram of Timer A .....................................................................................144

Section 11 Timer V

Figure 11.1 Block Diagram of Timer V .....................................................................................150

Figure 11.2 Increment Timing with Internal Clock.................................................................... 157

Figure 11.3 Increment Timing with External Clock................................................................... 157

Figure 11.4 OVF Set Timing...................................................................................................... 157

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Figure 11.5 CMFA and CMFB Set Timing................................................................................ 158

Figure 11.6 TMOV Output Timing ............................................................................................158

Figure 11.7 Clear Timing by Compare Match............................................................................ 158

Figure 11.8 Clear Timing by TMRIV Input ...............................................................................159

Figure 11.9 Pulse Output Example............................................................................................. 159

Figure 11.10 Example of Pulse Output Synchronized to TRGV Input.......................................160

Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 161

Figure 11.12 Contention between TCORA Write and Compare Match..................................... 162

Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 162

Section 12 Timer W

Figure 12.1 Timer W Block Diagram......................................................................................... 165

Figure 12.2 Free-Running Counter Operation............................................................................ 176

Figure 12.3 Periodic Counter Operation..................................................................................... 177

Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 177

Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................178

Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................178

Figure 12.7 Input Capture Operating Example........................................................................... 179

Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 180

Figure 12.9 PWM Mode Example (1) ........................................................................................ 181

Figure 12.10 PWM Mode Example (2) ......................................................................................182

Figure 12.11 Buffer Operation Example (Output Compare) ......................................................183

Figure 12.12 PWM Mode Example

(TOB, TOC, and TOD = 0: initial output values are set to 0)............................... 184

Figure 12.13 PWM Mode Example

(TOB, TOC, and TOD = 1: initial output values are set to 1)............................... 185

Figure 12.14 Count Timing for Internal Clock Source............................................................... 186

Figure 12.15 Count Timing for External Clock Source.............................................................. 186

Figure 12.16 Output Compare Output Timing ...........................................................................187

Figure 12.17 Input Capture Input Signal Timing........................................................................ 187

Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 188

Figure 12.19 Buffer Operation Timing (Compare Match)..........................................................188

Figure 12.20 Buffer Operation Timing (Input Capture) .............................................................189

Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match.................................. 189

Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 190

Figure 12.23 Timing of Status Flag Clearing by CPU................................................................190

Figure 12.24 Contention between TCNT Write and Clear .........................................................191

Figure 12.25 Internal Clock Switching and TCNT Operation.................................................... 192

Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at

the Same Timing ................................................................................................... 193

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Section 13 Watchdog Timer

Figure 13.1 Block Diagram of Watchdog Timer........................................................................ 195

Figure 13.2 Watchdog Timer Operation Example...................................................................... 199

Section 14 Serial Communication Interface 3 (SCI3)

Figure 14.1 Block Diagram of SCI3........................................................................................... 202

Figure 14.2 Data Format in Asynchronous Communication...................................................... 215

Figure 14.3 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 215

Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 216

Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ...........................................................................217

Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 218

Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ...........................................................................219

Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)...................... 221

Figure 14.8 Sample Serial Reception Data Flowchart (2) ..........................................................222

Figure 14.9 Data Format in Clocked Synchronous Communication ..........................................223

Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode......225

Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)................ 226

Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............... 227

Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)......................228

Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

(Clocked Synchronous Mode) .............................................................................. 230

Figure 14.15 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A).......................................... 232

Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart........................................ 233

Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 235

Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 236

Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)............................. 237

Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 240

Section 15 I2C Bus Interface 2 (IIC2)

Figure 15.1 Block Diagram of I2C Bus Interface 2..................................................................... 242

Figure 15.2 External Circuit Connections of I/O Pins................................................................ 243

Figure 15.3 I2C Bus Formats ...................................................................................................... 257

Figure 15.4 I2C Bus Timing........................................................................................................ 257

Figure 15.5 Master Transmit Mode Operation Timing (1)......................................................... 259

Figure 15.6 Master Transmit Mode Operation Timing (2)......................................................... 259

Figure 15.7 Master Receive Mode Operation Timing (1) .......................................................... 261

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Figure 15.8 Master Receive Mode Operation Timing (2)........................................................... 262

Figure 15.9 Slave Transmit Mode Operation Timing (1)........................................................... 263

Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 264

Figure 15.11 Slave Receive Mode Operation Timing (1)........................................................... 265

Figure 15.12 Slave Receive Mode Operation Timing (2)........................................................... 265

Figure 15.13 Clocked Synchronous Serial Transfer Format....................................................... 266

Figure 15.14 Transmit Mode Operation Timing.........................................................................267

Figure 15.15 Receive Mode Operation Timing ..........................................................................268

Figure 15.16 Block Diagram of Noise Conceler.........................................................................268

Figure 15.17 Sample Flowchart for Master Transmit Mode.......................................................269

Figure 15.18 Sample Flowchart for Master Receive Mode ........................................................ 270

Figure 15.19 Sample Flowchart for Slave Transmit Mode......................................................... 271

Figure 15.20 Sample Flowchart for Slave Receive Mode .......................................................... 272

Figure 15.21 The Timing of the Bit Synchronous Circuit .......................................................... 274

Section 16 A/D Converter

Figure 16.1 Block Diagram of A/D Converter ...........................................................................276

Figure 16.2 A/D Conversion Timing.......................................................................................... 283

Figure 16.3 External Trigger Input Timing ................................................................................ 284

Figure 16.4 A/D Conversion Accuracy Definitions (1).............................................................. 286

Figure 16.5 A/D Conversion Accuracy Definitions (2).............................................................. 286

Figure 16.6 Analog Input Circuit Example................................................................................. 287

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Figure 17.1 Block Diagram around BGR ................................................................................... 290

Figure 17.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit....291

Figure 17.3 Operational Timing of Power-On Reset Circuit...................................................... 296

Figure 17.4 Operating Timing of LVDR Circuit........................................................................ 297

Figure 17.5 Operational Timing of LVDI Circuit.......................................................................298

Figure 17.6 Timing of Setting Bits in Reset Source Decision Register...................................... 299

Section 18 Power Supply Circuit

Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used ....................301

Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used .............302

Section 20 Electrical Characteristics

Figure 20.1 System Clock Input Timing.....................................................................................335

Figure 20.2 RES Low Width Timing.......................................................................................... 335

Figure 20.3 Input Timing............................................................................................................ 335

Figure 20.4 I2C Bus Interface Input/Output Timing................................................................... 336

Figure 20.5 SCK3 Input Clock Timing.......................................................................................336

Figure 20.6 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 337

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Figure 20.7 Output Load Circuit ................................................................................................ 337

Appendix

Figure B.1 Port 1 Block Diagram (P17) .....................................................................................369

Figure B.2 Port 1 Block Diagram (P16 to P14).......................................................................... 370

Figure B.3 Port 1 Block Diagram (P12, P11)............................................................................. 371

Figure B.4 Port 1 Block Diagram (P10) .....................................................................................372

Figure B.5 Port 2 Block Diagram (P22) .....................................................................................373

Figure B.6 Port 2 Block Diagram (P21) .....................................................................................374

Figure B.7 Port 2 Block Diagram (P20) .....................................................................................375

Figure B.8 Port 5 Block Diagram (P57, P56)............................................................................. 376

Figure B.9 Port 5 Block Diagram (P55) .....................................................................................377

Figure B.10 Port 5 Block Diagram (P54 to P50)........................................................................ 378

Figure B.11 Port 7 Block Diagram (P76) ................................................................................... 379

Figure B.12 Port 7 Block Diagram (P75) ................................................................................... 380

Figure B.13 Port 7 Block Diagram (P74) ................................................................................... 381

Figure B.14 Port 8 Block Diagram (P87 to P85)........................................................................ 382

Figure B.15 Port 8 Block Diagram (P84 to P81)........................................................................ 383

Figure B.16 Port 8 Block Diagram (P80) ................................................................................... 384

Figure B.17 Port B Block Diagram (PB7 to PB0)...................................................................... 385

Figure B.18 Port C Block Diagram (PC1).................................................................................. 386

Figure B.19 Port C Block Diagram (PC0).................................................................................. 387

Figure D.1 FP-64K Package Dimensions................................................................................... 391

Figure D.2 FP-64A Package Dimensions................................................................................... 392

Figure D.3 FP-48F Package Dimensions.................................................................................... 393

Figure D.4 FP-48B Package Dimensions ...................................................................................394

Figure D.5 TNP-48 Package Dimensions................................................................................... 395

Rev. 1.00 Aug. 28, 2006 Page xxiv of xxviii

Tables

Section 1 Overview

Table 1.1

Section 2 CPU

Table 2.1 Operation Notation .................................................................................................18

Table 2.2 Data Transfer Instructions.......................................................................................19

Table 2.3 Arithmetic Operations Instructions (1) ...................................................................20

Table 2.3 Arithmetic Operations Instructions (2) ...................................................................21

Table 2.4 Logic Operations Instructions................................................................................. 22

Table 2.5 Shift Instructions.....................................................................................................22

Table 2.6 Bit Manipulation Instructions (1)............................................................................ 23

Table 2.6 Bit Manipulation Instructions (2)............................................................................ 24

Table 2.7 Branch Instructions................................................................................................. 25

Table 2.8 System Control Instructions.................................................................................... 26

Table 2.9 Block Data Transfer Instructions ............................................................................ 27

Table 2.10 Addressing Modes .................................................................................................. 29

Table 2.11 Absolute Address Access Ranges........................................................................... 30

Table 2.12 Effective Address Calculation (1)........................................................................... 32

Table 2.12 Effective Address Calculation (2)........................................................................... 33

Section 3 Exception Handling

Table 3.1 Exception Sources and Vector Address.................................................................. 43

Table 3.2 Interrupt Wait States ...............................................................................................54

Pin Functions ............................................................................................................ 6

Section 4 Address Break

Table 4.1 Access and Data Bus Used .....................................................................................59

Section 5 Clock Pulse Generators

Table 5.1 Crystal Resonator Parameters ................................................................................. 79

Section 6 Power-Down Modes

Table 6.1 Operating Frequency and Waiting Time................................................................. 87

Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling........ 90

Table 6.3 Internal State in Each Operating Mode................................................................... 91

Section 7 ROM

Table 7.1 Setting Programming Modes ................................................................................ 103

Table 7.2 Boot Mode Operation ...........................................................................................105

Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible................................................................................................................. 106

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Table 7.4 Reprogram Data Computation Table.................................................................... 109

Table 7.5 Additional-Program Data Computation Table...................................................... 109

Table 7.6 Programming Time............................................................................................... 109

Table 7.7 Flash Memory Operating States............................................................................ 113

Section 10 Timer A

Table 10.1 Pin Configuration.................................................................................................. 144

Section 11 Timer V

Table 11.1 Pin Configuration.................................................................................................. 151

Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 153

Section 12 Timer W

Table 12.1 Timer W Functions............................................................................................... 164

Table 12.2 Pin Configuration.................................................................................................. 166

Section 14 Serial Communication Interface 3 (SCI3)

Table 14.1 Pin Configuration.................................................................................................. 203

Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 211

Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 212

Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................213

Table 14.4 Examples of BBR Setting for Various Bit Rates

(Clocked Synchronous Mode) .............................................................................. 214

Table 14.5 SSR Status Flags and Receive Data Handling...................................................... 220

Table 14.6 SCI3 Interrupt Requests........................................................................................ 238

Section 15 I2C Bus Interface 2 (IIC2)

Table 15.1 I2C Bus Interface Pins........................................................................................... 243

Table 15.2 Transfer Rate ........................................................................................................246

Table 15.3 Interrupt Requests................................................................................................. 273

Table 15.4 Time for Monitoring SCL..................................................................................... 274

Section 16 A/D Converter

Table 16.1 Pin Configuration.................................................................................................. 277

Table 16.2 Analog Input Channels and Corresponding ADDR Registers.............................. 278

Table 16.3 A/D Conversion Time (Single Mode)................................................................... 284

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Table 17.1 LVDCR Settings and Select Functions................................................................. 293

Table 17.2 Deciding Reset Source.......................................................................................... 299

Section 20 Electrical Characteristics

Table 20.1 Absolute Maximum Ratings ................................................................................. 317

Table 20.2 DC Characteristics (1) ..........................................................................................320

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Table 20.2 DC Characteristics (2)...........................................................................................324

Table 20.3 AC Characteristics ................................................................................................325

Table 20.4 I2C Bus Interface Timing...................................................................................... 328

Table 20.5 Serial Communication Interface (SCI) Timing..................................................... 329

Table 20.6 A/D Converter Characteristics.............................................................................. 330

Table 20.7 Watchdog Timer Characteristics........................................................................... 331

Table 20.8 Flash Memory Characteristics ..............................................................................332

Table 20.9 Power-Supply-Voltage Detection Circuit Characteristics.....................................334

Table 20.10 Power-On Reset Circuit Characteristics............................................................334

Appendix

Table A.1 Instruction Set....................................................................................................... 341

Table A.2 Operation Code Map (1) ....................................................................................... 354

Table A.2 Operation Code Map (2) ....................................................................................... 355

Table A.2 Operation Code Map (3) ....................................................................................... 356

Table A.3 Number of Cycles in Each Instruction.................................................................. 358

Table A.4 Number of Cycles in Each Instruction.................................................................. 359

Table A.5 Combinations of Instructions and Addressing Modes ..........................................368

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