RENESAS HD64F36077G, HD64F36074G User Manual
REJ09B0216-0100
H8/36077 Group
16
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family/H8/300H Tiny Series
H8/36077GF HD64F36077G
H8/36074GF HD64F36074G
Rev.1.00
Revision Date: Sep. 16, 2005
Rev. 1.00 Sep. 16, 2005 Page ii of xxx
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 1.00 Sep. 16, 2005 Page iii of xxx
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are hi g h-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Rese r ved Ad dresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 1.00 Sep. 16, 2005 Page iv of xxx
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.00 Sep. 16, 2005 Page v of xxx
Preface
The H8/36077 Group are single-chip microcom put ers made up of the high-speed H8/300H CPU
employing Renesas Technology original architecture as their cores, and the peripheral functions
required to configure a system. The H8/300H CPU has an instruction set that is compatible with
the H8/300 CPU.
Target Users: This manual was written for users who will be using the H8/36077 Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8/36077 Group to the target users.
Refer to the H8/300H Series Programming Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughl y categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8/300H Series Programming Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 21,
List of Registers.
Example: Register name: The follo wi n g notat i on is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Rev. 1.00 Sep. 16, 2005 Page vi of xxx
Notes:
When using an on-chip emulator (E7, E8) for H8/36077 program development and debugging, the
following restrictions must be noted.
1. The NMI pin is reserved for the E7 or E8, and cannot be used.
2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional ha rdware must be
provided on the user board.
3. Area H’D000 to H’DFFF is used by the E7 or E8, and is not available to the user.
4. Area H’F780 to H’FB7F must on no account be accessed.
5. When the E7or E8 is used, address breaks can be set as either available to the user or for use
by the E7 or E8. If address breaks are set as being used by the E7, the address break control
registers must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and
P87 are input pins, and P86 is an output pin.
7. Use channel 1 of the SCI3 (P21/RXD, P22/TXD) in on-board programming mode by boot
mode.
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev. 1.00 Sep. 16, 2005 Page vii of xxx
H8/36077 Group manuals:
Document Title Document No.
H8/36077 Group Hardware Manual This manual
H8/300H Series Programming Manual ADE-602-053
User's manuals for development tools:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual
H8S, H8/300 Series High-Performance Embedded Workshop 3, Tutorial REJ10B0024
H8S, H8/300 Series High-Performance Embedded Workshop 3, User's
Manual
REJ10B0058
ADE-702-282
REJ10B0026
Application notes:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464
Single Power Supply F-ZTATTM On-Board Programming ADE-502-055
Rev. 1.00 Sep. 16, 2005 Page viii of xxx
Contents
Section 1 Overview................................................................................................1
1.1 Features..................................................................................................................................1
1.2 Block Diagram....................................................................................................................... 3
1.3 Pin Arrangement.................................................................................................................... 4
1.4 Pin Functions ......................................................................................................................... 5
Section 2 CPU........................................................................................................9
2.1 Address Space and Memory Map........................................................................................10
2.2 Register Configuration.........................................................................................................11
2.2.1 General Registers....................................................................................................12
2.2.2 Program Counter (PC)............................................................................................13
2.2.3 Condition-Code Register (CCR).............................................................................13
2.3 Data Formats........................................................................................................................ 15
2.3.1 General Register Data Formats...............................................................................15
2.3.2 Memory Data Formats............................................................................................ 17
2.4 Instruction Set...................................................................................................................... 18
2.4.1 Table of Instructions Classified by Function..........................................................18
2.4.2 Basic Instruction Formats.......................................................................................28
2.5 Addressing Modes and Effective Address Calculation........................................................ 29
2.5.1 Addressing Modes ..................................................................................................29
2.5.2 Effective Address Calculation ................................................................................ 32
2.6 Basic Bus Cycle................................................................................................................... 34
2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................34
2.6.2 On-Chip Peripheral Modules.................................................................................. 35
2.7 CPU States...........................................................................................................................36
2.8 Usage Notes.........................................................................................................................37
2.8.1 Notes on Data Access to Empty Areas ................................................................... 37
2.8.2 EEPMOV Instruction.............................................................................................. 37
2.8.3 Bit-Manipulation Instruction .................................................................................. 37
Section 3 Exception Handling .............................................................................43
3.1 Exception Sources and Vector Address............................................................................... 44
3.2 Register Descriptions...........................................................................................................46
3.2.1 Interrupt Edge Select Register 1 (IEGR1)..............................................................46
3.2.2 Interrupt Edge Select Register 2 (IEGR2)..............................................................47
3.2.3 Interrupt Enable Register 1 (IENR1)......................................................................48
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3.2.4 Interrupt Enable Register 2 (IENR2)...................................................................... 49
3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 49
3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 51
3.2.7 Wakeup Interrupt Flag Register (IWPR)................................................................ 51
3.3 Reset Exception Handling.................................................................................................... 53
3.4 Interrupt Exception Handling .............................................................................................. 54
3.4.1 External Interrupts..................................................................................................54
3.4.2 Internal Interrupts ................................................................................................... 56
3.4.3 Interrupt Handling Sequence..................................................................................56
3.4.4 Interrupt Response Time......................................................................................... 57
3.5 Usage Notes......................................................................................................................... 59
3.5.1 Interrupts after Reset............................................................................................... 59
3.5.2 Notes on Stack Area Use........................................................................................59
3.5.3 Notes on Rewriting Port Mode Registers............................................................... 59
Section 4 Address Break .....................................................................................61
4.1 Register Descriptions...........................................................................................................62
4.1.1 Address Break Control Register (ABRKCR) ......................................................... 62
4.1.2 Address Break Status Register (ABRKSR)............................................................64
4.1.3 Break Address Registers (BARH, BARL).............................................................. 64
4.1.4 Break Data Registers (BDRH, BDRL)...................................................................64
4.2 Operation ............................................................................................................................. 65
Section 5 Clock Pulse Generator.........................................................................67
5.1 Features................................................................................................................................ 68
5.2 Register Descriptions...........................................................................................................68
5.2.1 RC Control Register (RCCR) ................................................................................. 69
5.2.2 RC Trimming Data Protect Register (RCTRMDPR)..............................................70
5.2.3 RC Trimming Data Register (RCTRMDR)............................................................ 71
5.2.4 Clock Control/Status Register (CKCSR)................................................................ 72
5.3 System Clock Select Operation ........................................................................................... 75
5.3.1 Clock Control Operation......................................................................................... 75
5.3.2 Clock Switching Timing......................................................................................... 79
5.4 Trimming of On-Chip Oscillator Frequency........................................................................82
5.5 External Oscillators.............................................................................................................. 83
5.5.1 Connecting Crystal Resonator................................................................................ 83
5.5.2 Connecting Ceramic Resonator..............................................................................84
5.5.3 Inputting External Clock......................................................................................... 85
5.6 Subclock Oscillator.............................................................................................................. 85
5.6.1 Connecting 32.768-kHz Crystal Resonator ............................................................ 86
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5.6.2 Pin Connection when Not Using Subclock............................................................. 86
5.7 Prescaler............................................................................................................................... 87
5.7.1 Prescaler S .............................................................................................................. 87
5.7.2 Prescaler W............................................................................................................. 87
5.8 Usage Notes.........................................................................................................................88
5.8.1 Note on Resonators.................................................................................................88
5.8.2 Notes on Board Design........................................................................................... 88
Section 6 Power-Down Modes ............................................................................89
6.1 Register Descriptions...........................................................................................................90
6.1.1 System Control Register 1 (SYSCR1).................................................................... 90
6.1.2 System Control Register 2 (SYSCR2).................................................................... 93
6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 94
6.1.4 Module Standby Control Register 2 (MSTCR2) .................................................... 95
6.2 Mode Transitions and States of LSI..................................................................................... 96
6.2.1 Sleep Mode.............................................................................................................99
6.2.2 Standby Mode.........................................................................................................99
6.2.3 Subsleep Mode...................................................................................................... 100
6.2.4 Subactive Mode .................................................................................................... 100
6.3 Operating Frequency in Active Mode................................................................................ 101
6.4 Direct Transition................................................................................................................ 101
6.4.1 Direct Transition from Active Mode to Subactive Mode ..................................... 101
6.4.2 Direct Transition from Subactive Mode to Active Mode ..................................... 102
6.5 Module Standby Function.................................................................................................. 102
Section 7 ROM ..................................................................................................103
7.1 Block Configuration...........................................................................................................103
7.2 Register Descriptions......................................................................................................... 105
7.2.1 Flash Memory Control Register 1 (FLMCR1)......................................................105
7.2.2 Flash Memory Control Register 2 (FLMCR2)......................................................106
7.2.3 Erase Block Register 1 (EBR1) ............................................................................ 107
7.2.4 Flash Memory Power Control Register (FLPWCR)............................................. 108
7.2.5 Flash Memory Enable Register (FENR) ............................................................... 108
7.3 On-Board Programming Modes......................................................................................... 109
7.3.1 Boot Mode............................................................................................................109
7.3.2 Programming/Erasing in User Program Mode......................................................112
7.4 Flash Memory Programming/Erasing................................................................................113
7.4.1 Program/Program-Verify...................................................................................... 113
7.4.2 Erase/Erase-Verify................................................................................................ 116
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory...........................116
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7.5 Program/Erase Protection.................................................................................................. 118
7.5.1 Hardware Protection.............................................................................................118
7.5.2 Software Protection .............................................................................................. 118
7.5.3 Error Protection .................................................................................................... 118
7.6 Programmer Mode............................................................................................................. 119
7.7 Power-Down States for Flash Memory.............................................................................. 119
Section 8 RAM..................................................................................................121
Section 9 I/O Ports.............................................................................................123
9.1 Port 1.................................................................................................................................. 123
9.1.1 Port Mode Register 1 (PMR1).............................................................................. 124
9.1.2 Port Control Register 1 (PCR1)............................................................................ 125
9.1.3 Port Data Register 1 (PDR1) ................................................................................ 125
9.1.4 Port Pull-Up Control Register 1 (PUCR1)............................................................126
9.1.5 Pin Functions........................................................................................................126
9.2 Port 2.................................................................................................................................. 129
9.2.1 Port Control Register 2 (PCR2)............................................................................ 129
9.2.2 Port Data Register 2 (PDR2) ................................................................................ 130
9.2.3 Port Mode Register 3 (PMR3).............................................................................. 130
9.2.4 Pin Functions........................................................................................................131
9.3 Port 3.................................................................................................................................. 133
9.3.1 Port Control Register 3 (PCR3)............................................................................ 133
9.3.2 Port Data Register 3 (PDR3) ................................................................................ 134
9.3.3 Pin Functions........................................................................................................134
9.4 Port 5.................................................................................................................................. 137
9.4.1 Port Mode Register 5 (PMR5).............................................................................. 138
9.4.2 Port Control Register 5 (PCR5)............................................................................ 139
9.4.3 Port Data Register 5 (PDR5) ................................................................................ 139
9.4.4 Port Pull-Up Control Register 5 (PUCR5)............................................................140
9.4.5 Pin Functions........................................................................................................140
9.5 Port 6.................................................................................................................................. 143
9.5.1 Port Control Register 6 (PCR6)............................................................................ 143
9.5.2 Port Data Register 6 (PDR6) ................................................................................ 144
9.5.3 Pin Functions........................................................................................................144
9.6 Port 7.................................................................................................................................. 148
9.6.1 Port Control Register 7 (PCR7)............................................................................ 148
9.6.2 Port Data Register 7 (PDR7) ................................................................................ 149
9.6.3 Pin Functions........................................................................................................149
9.7 Port 8.................................................................................................................................. 151
Rev. 1.00 Sep. 16, 2005 Page xii of xxx
9.7.1 Port Control Register 8 (PCR8)............................................................................151
9.7.2 Port Data Register 8 (PDR8).................................................................................151
9.7.3 Pin Functions........................................................................................................152
9.8 Port B................................................................................................................................. 153
9.8.1 Port Data Register B (PDRB)...............................................................................153
9.8.2 Pin Functions........................................................................................................154
9.9 Port C................................................................................................................................. 157
9.9.1 Port Control Register C (PCRC)........................................................................... 157
9.9.2 Port Data Register C (PDRC)...............................................................................158
9.9.3 Pin Functions........................................................................................................158
Section 10 Realtime Clock (RTC).....................................................................159
10.1 Features..............................................................................................................................159
10.2 Input/Output Pin.................................................................................................................160
10.3 Register Descriptions......................................................................................................... 161
10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) ............. 161
10.3.2 Minute Data Register (RMINDR)......................................................................... 162
10.3.3 Hour Data Register (RHRDR)..............................................................................163
10.3.4 Day-of-Week Data Register (RWKDR) ............................................................... 164
10.3.5 RTC Control Register 1 (RTCCR1)...................................................................... 165
10.3.6 RTC Control Register 2 (RTCCR2)...................................................................... 166
10.3.7 Clock Source Select Register (RTCCSR).............................................................167
10.4 Operation ........................................................................................................................... 168
10.4.1 Initial Settings of Registers after Power-On ......................................................... 168
10.4.2 Initial Setting Procedure .......................................................................................168
10.4.3 Data Reading Procedure .......................................................................................169
10.5 Interrupt Sources................................................................................................................ 170
Section 11 Timer B1..........................................................................................171
11.1 Features..............................................................................................................................171
11.2 Input/Output Pin.................................................................................................................172
11.3 Register Descriptions......................................................................................................... 173
11.3.1 Timer Mode Register B1 (TMB1) ........................................................................173
11.3.2 Timer Counter B1 (TCB1).................................................................................... 174
11.3.3 Timer Load Register B1 (TLB1) ..........................................................................174
11.4 Operation ........................................................................................................................... 174
11.4.1 Interval Timer Operation ...................................................................................... 174
11.4.2 Auto-Reload Timer Operation..............................................................................175
11.4.3 Event Counter Operation ...................................................................................... 175
11.5 Timer B1 Operating Modes...............................................................................................175
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Section 12 Timer V ...........................................................................................177
12.1 Features.............................................................................................................................. 177
12.2 Input/Output Pins...............................................................................................................179
12.3 Register Descriptions......................................................................................................... 179
12.3.1 Timer Counter V (TCNTV).................................................................................. 179
12.3.2 Time Constant Registers A and B (TCORA, TCORB) ........................................ 180
12.3.3 Timer Control Register V0 (TCRV0)................................................................... 180
12.3.4 Timer Control/Status Register V (TCSRV).......................................................... 181
12.3.5 Timer Control Register V1 (TCRV1)................................................................... 183
12.4 Operation ........................................................................................................................... 184
12.4.1 Timer V Operation................................................................................................ 184
12.5 Timer V Application Examples......................................................................................... 187
12.5.1 Pulse Output with Arbitrary Duty Cycle............................................................... 187
12.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input..............188
12.6 Usage Notes....................................................................................................................... 189
Section 13 Timer Z............................................................................................191
13.1 Features.............................................................................................................................. 191
13.2 Input/Output Pins...............................................................................................................196
13.3 Register Descriptions......................................................................................................... 197
13.3.1 Timer Start Register (TSTR) ................................................................................ 198
13.3.2 Timer Mode Register (TMDR)............................................................................. 198
13.3.3 Timer PWM Mode Register (TPMR)...................................................................199
13.3.4 Timer Function Control Register (TFCR) ............................................................ 200
13.3.5 Timer Output Master Enable Register (TOER) .................................................... 202
13.3.6 Timer Output Control Register (TOCR)............................................................... 204
13.3.7 Timer Counter (TCNT)......................................................................................... 205
13.3.8 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)........................ 205
13.3.9 Timer Control Register (TCR).............................................................................. 206
13.3.10 Timer I/O Control Register (TIORA and TIORC)............................................... 207
13.3.11 Timer Status Register (TSR)................................................................................. 210
13.3.12 Timer Interrupt Enable Register (TIER)............................................................... 212
13.3.13 PWM Mode Output Level Control Register (POCR)........................................... 213
13.3.14 Interface with CPU ............................................................................................... 214
13.4 Operation ........................................................................................................................... 215
13.4.1 Counter Operation ................................................................................................ 215
13.4.2 Waveform Output by Compare Match.................................................................. 219
13.4.3 Input Capture Function ......................................................................................... 221
13.4.4 Synchronous Operation......................................................................................... 225
13.4.5 PWM Mode .......................................................................................................... 226
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13.4.6 Reset Synchronous PWM Mode...........................................................................232
13.4.7 Complementary PWM Mode................................................................................ 236
13.4.8 Buffer Operation...................................................................................................246
13.4.9 Timer Z Output Timing ........................................................................................ 254
13.5 Interrupts............................................................................................................................257
13.5.1 Status Flag Set Timing.......................................................................................... 257
13.5.2 Status Flag Clearing Timing ................................................................................. 259
13.6 Usage Notes.......................................................................................................................260
Section 14 Watchdog Timer..............................................................................267
14.1 Features..............................................................................................................................267
14.2 Register Descriptions......................................................................................................... 268
14.2.1 Timer Control/Status Register WD (TCSRWD)................................................... 268
14.2.2 Timer Counter WD (TCWD)................................................................................ 270
14.2.3 Timer Mode Register WD (TMWD) .................................................................... 270
14.3 Operation ........................................................................................................................... 271
Section 15 14-Bit PWM.....................................................................................273
15.1 Features..............................................................................................................................273
15.2 Input/Output Pin.................................................................................................................274
15.3 Register Descriptions......................................................................................................... 275
15.3.1 PWM Control Register (PWCR) ..........................................................................275
15.3.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................. 275
15.4 Operation ........................................................................................................................... 276
Section 16 Serial Communication Interface 3 (SCI3) .......................................277
16.1 Features..............................................................................................................................277
16.2 Input/Output Pins...............................................................................................................280
16.3 Register Descriptions......................................................................................................... 281
16.3.1 Receive Shift Register (RSR) ...............................................................................281
16.3.2 Receive Data Register (RDR)............................................................................... 281
16.3.3 Transmit Shift Register TSR (SCI3)..................................................................... 281
16.3.4 Transmit Data Register (TDR).............................................................................. 282
16.3.5 Serial Mode Register (SMR) ................................................................................ 282
16.3.6 Serial Control Register 3 (SCR3).......................................................................... 284
16.3.7 Serial Status Register (SSR) ................................................................................. 286
16.3.8 Bit Rate Register (BRR) .......................................................................................288
16.4 Operation in Asynchronous Mode.....................................................................................295
16.4.1 Clock..................................................................................................................... 295
16.4.2 SCI3 Initialization................................................................................................. 296
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16.4.3 Data Transmission ................................................................................................ 297
16.4.4 Serial Data Reception ........................................................................................... 299
16.5 Operation in Clock Synchronous Mode............................................................................. 303
16.5.1 Clock..................................................................................................................... 303
16.5.2 SCI3 Initialization................................................................................................. 303
16.5.3 Serial Data Transmission......................................................................................304
16.5.4 Serial Data Reception (Clock Synchronous Mode).............................................. 306
16.5.5 Simultaneous Serial Data Transmission and Reception........................................ 308
16.6 Multiprocessor Communication Function..........................................................................310
16.6.1 Multiprocessor Serial Data Transmission.............................................................311
16.6.2 Multiprocessor Serial Data Reception .................................................................. 313
16.7 Interrupts............................................................................................................................ 317
16.8 Usage Notes....................................................................................................................... 318
16.8.1 Break Detection and Processing ........................................................................... 318
16.8.2 Mark State and Break Sending ............................................................................. 318
16.8.3 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only)......................................................................... 318
16.8.4 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode......................................................................................... 319
Section 17 I2C Bus Interface 2 (IIC2)................................................................321
17.1 Features.............................................................................................................................. 321
17.2 Input/Output Pins...............................................................................................................323
17.3 Register Descriptions......................................................................................................... 324
17.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 324
17.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 327
17.3.3 I2C Bus Mode Register (ICMR)............................................................................ 328
17.3.4 I2C Bus Interrupt Enable Register (ICIER)........................................................... 330
17.3.5 I2C Bus Status Register (ICSR)............................................................................. 332
17.3.6 Slave Address Register (SAR).............................................................................. 335
17.3.7 I2C Bus Transmit Data Register (ICDRT) ............................................................ 336
17.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 336
17.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 336
17.4 Operation ........................................................................................................................... 337
17.4.1 I2C Bus Format......................................................................................................337
17.4.2 Master Transmit Operation................................................................................... 338
17.4.3 Master Receive Operation .................................................................................... 340
17.4.4 Slave Transmit Operation ..................................................................................... 342
17.4.5 Slave Receive Operation....................................................................................... 344
17.4.6 Clock Synchronous Serial Format ........................................................................ 346
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17.4.7 Noise Filter ...........................................................................................................349
17.4.8 Example of Use.....................................................................................................349
17.5 Interrupt Request................................................................................................................354
17.6 Bit Synchronous Circuit..................................................................................................... 355
17.7 Usage Notes.......................................................................................................................356
17.7.1 Issue (Retransmission) of Start/Stop Conditions .................................................. 356
17.7.2 WAIT Setting in I2C Bus Mode Register (ICMR)................................................ 356
Section 18 A/D Converter..................................................................................357
18.1 Features..............................................................................................................................357
18.2 Input/Output Pins...............................................................................................................359
18.3 Register Descriptions......................................................................................................... 360
18.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ..............................................360
18.3.2 A/D Control/Status Register (ADCSR) ................................................................ 361
18.3.3 A/D Control Register (ADCR) ............................................................................. 362
18.4 Operation ........................................................................................................................... 363
18.4.1 Single Mode.......................................................................................................... 363
18.4.2 Scan Mode ............................................................................................................ 363
18.4.3 Input Sampling and A/D Conversion Time ..........................................................364
18.4.4 External Trigger Input Timing.............................................................................. 365
18.5 A/D Conversion Accuracy Definitions.............................................................................. 366
18.6 Usage Notes.......................................................................................................................368
18.6.1 Permissible Signal Source Impedance..................................................................368
18.6.2 Influences on Absolute Accuracy ......................................................................... 368
Section 19 Band-Gap Circuit, Power-On Reset, and
Low-Voltage Detection Circuits......................................................369
19.1 Features..............................................................................................................................370
19.2 Register Descriptions......................................................................................................... 372
19.2.1 Low-Voltage-Detection Control Register (LVDCR)............................................ 372
19.2.2 Low-Voltage-Detection Status Register (LVDSR)............................................... 373
19.2.3 Reset Source Decision Register (LVDRF) ...........................................................374
19.3 Operations..........................................................................................................................376
19.3.1 Power-On Reset Circuit ........................................................................................376
19.3.2 Low-Voltage Detection Circuit............................................................................. 377
19.3.3 Deciding Reset Source.......................................................................................... 382
Section 20 Power Supply Circuit.......................................................................383
20.1 When Using Internal Power Supply Step-Down Circuit....................................................383
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Section 21 List of Registers...............................................................................385
21.1 Register Addresses (Address Order).................................................................................. 386
21.2 Register Bits....................................................................................................................... 393
21.3 Registers States in Each Operating Mode.......................................................................... 399
Section 22 Electrical Characteristics.................................................................405
22.1 Absolute Maximum Ratings..............................................................................................405
22.2 Electrical Characteristics (F-ZTAT™ Version)................................................................. 406
22.2.1 Power Supply Voltage and Operating Ranges...................................................... 406
22.2.2 DC Characteristics................................................................................................ 409
22.2.3 AC Characteristics................................................................................................ 415
22.2.4 A/D Converter Characteristics.............................................................................. 419
22.2.5 Watchdog Timer Characteristics........................................................................... 420
22.2.6 Flash Memory Characteristics .............................................................................. 421
22.2.7 Power-Supply-Voltage Detection Circuit Characteristics..................................... 423
22.2.8 LVDI External Input Voltage Detection Circuit Characteristics .......................... 423
22.2.9 Power-On Reset Circuit Characteristics ............................................................... 424
22.3 Operation Timing............................................................................................................... 425
22.4 Output Load Condition......................................................................................................427
Appendix A Instruction Set...............................................................................429
A.1 Instruction List................................................................................................................... 429
A.2 Operation Code Map.......................................................................................................... 444
A.3 Number of Execution States .............................................................................................. 447
A.4 Com binations of Instructions and Addressing Modes....................................................... 458
Appendix B I/O Port Block Diagrams...............................................................459
B.1 I/O Port Block Diagrams ................................................................................................... 459
B.2 Port States in Each Operating State................................................................................... 483
Appendix C Product Code Lineup ....................................................................484
Appendix D Package Dimensions.....................................................................485
Index .........................................................................................................487
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Figures
Section 1 Overview
Figure 1.1 Block Diagram of H8/36077 Group.............................................................................. 3
Figure 1.2 Pin Arrangements of H8/36077 Group (FP-64K, FP-64A)........................................... 4
Section 2 CPU
Figure 2.1 Memory Map............................................................................................................... 10
Figure 2.2 CPU Registers .............................................................................................................11
Figure 2.3 Usage of General Registers .........................................................................................12
Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 13
Figure 2.5 General Register Data Formats (1).............................................................................. 15
Figure 2.5 General Register Data Formats (2).............................................................................. 16
Figure 2.6 Memory Data Formats.................................................................................................17
Figure 2.7 Instruction Formats......................................................................................................28
Figure 2.8 Branch Address Specification in Memory Indirect Mode........................................... 32
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 34
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access).....................................35
Figure 2.11 CPU Operation States................................................................................................ 36
Figure 2.12 State Transitions........................................................................................................ 37
Figure 2.13 Example of Timer Configuration with Two Registers Allocated
to Same Address........................................................................................................ 38
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 55
Figure 3.2 Stack Status after Exception Handling........................................................................ 57
Figure 3.3 Interrupt Sequence....................................................................................................... 58
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 59
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................61
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 65
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 66
Section 5 Clock Pulse Generator
Figure 5.1 Block Diagram of Clock Pulse Generator................................................................... 67
Figure 5.2 State Transition of System Clock................................................................................ 75
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled................................... 76
Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1)
(From On-Chip Oscillator Clock to External Clock)...................................................77
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Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2)
(From External Clock to On-Chip Oscillator Clock)................................................... 78
Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock.......... 79
Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock ...............80
Figure 5.8 External Oscillation Backup Timing........................................................................... 81
Figure 5.9 Example of Trimming Flow for On-Chip Oscillator Clock ........................................82
Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency .................................. 83
Figure 5.11 Example of Connection to Crystal Resonator ........................................................... 84
Figure 5.12 Equivalent Circuit of Crystal Resonator....................................................................84
Figure 5.13 Example of Connection to Ceramic Resonator ......................................................... 84
Figure 5.14 Example of External Clock Input.............................................................................. 85
Figure 5.15 Block Diagram of Subclock Oscillator...................................................................... 85
Figure 5.16 Typical Connection to 32.768-kHz Crystal Resonator.............................................. 86
Figure 5.17 Equivalent Circuit of 32.768-kHz Crystal Resonator................................................ 86
Figure 5.18 Pin Connection when not Using Subclock ................................................................ 86
Figure 5.19 Example of Incorrect Board Design.......................................................................... 88
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ........................................................................................... 96
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration..........................................................................104
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode.......................... 112
Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 114
Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 117
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................ 123
Figure 9.2 Port 2 Pin Configuration............................................................................................ 129
Figure 9.3 Port 3 Pin Configuration............................................................................................ 133
Figure 9.4 Port 5 Pin Configuration............................................................................................ 137
Figure 9.5 Port 6 Pin Configuration............................................................................................ 143
Figure 9.6 Port 7 Pin Configuration............................................................................................ 148
Figure 9.7 Port 8 Pin Configuration............................................................................................ 151
Figure 9.8 Port B Pin Configuration...........................................................................................153
Figure 9.9 Port C Pin Configuration...........................................................................................157
Section 10 Realtime Clock (RTC)
Figure 10.1 Block Diagram of RTC ........................................................................................... 159
Figure 10.2 Definition of Time Expression ................................................................................ 165
Figure 10.3 Initial Setting Procedure.......................................................................................... 168
Figure 10.4 Example: Reading of Inaccurate Time Data............................................................169
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Section 11 Timer B1
Figure 11.1 Block Diagram of Timer B1.................................................................................... 171
Section 12 Timer V
Figure 12.1 Block Diagram of Timer V......................................................................................178
Figure 12.2 Increment Timing with Internal Clock.................................................................... 185
Figure 12.3 Increment Timing with External Clock................................................................... 185
Figure 12.4 OVF Set Timing ...................................................................................................... 185
Figure 12.5 CMFA and CMFB Set Timing................................................................................ 186
Figure 12.6 TMOV Output Timing ............................................................................................186
Figure 12.7 Clear Timing by Compare Match............................................................................ 186
Figure 12.8 Clear Timing by TMRIV Input ...............................................................................187
Figure 12.9 Pulse Output Example............................................................................................. 187
Figure 12.10 Example of Pulse Output Synchronized to TRGV Input.......................................188
Figure 12.11 Contention between TCNTV Write and Clear ...................................................... 189
Figure 12.12 Contention between TCORA Write and Compare Match..................................... 190
Figure 12.13 Internal Clock Switching and TCNTV Operation ................................................. 190
Section 13 Timer Z
Figure 13.1 Timer Z Block Diagram .......................................................................................... 193
Figure 13.2 Timer Z (Channel 0) Block Diagram ...................................................................... 194
Figure 13.3 Timer Z (Channel 1) Block Diagram ...................................................................... 195
Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode
and Complementary PWM Mode............................................................................ 202
Figure 13.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits))........ 214
Figure 13.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits)).............214
Figure 13.7 Example of Counter Operation Setting Procedure ..................................................215
Figure 13.8 Free-Running Counter Operation............................................................................ 216
Figure 13.9 Periodic Counter Operation..................................................................................... 217
Figure 13.10 Count Timing at Internal Clock Operation............................................................ 217
Figure 13.11 Count Timing at External Clock Operation (Both Edges Detected)......................218
Figure 13.12 Example of Setting Procedure for Waveform Output by Compare Match............ 219
Figure 13.13 Example of 0 Output/1 Output Operation .............................................................220
Figure 13.14 Example of Toggle Output Operation ...................................................................220
Figure 13.15 Output Compare Timing........................................................................................221
Figure 13.16 Example of Input Capture Operation Setting Procedure ....................................... 222
Figure 13.17 Example of Input Capture Operation.....................................................................223
Figure 13.18 Input Capture Signal Timing................................................................................. 224
Figure 13.19 Example of Synchronous Operation Setting Procedure ........................................225
Figure 13.20 Example of Synchronous Operation...................................................................... 226
Figure 13.21 Example of PWM Mode Setting Procedure ..........................................................227
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Figure 13.22 Example of PWM Mode Operation (1)................................................................. 228
Figure 13.23 Example of PWM Mode Operation (2)................................................................. 229
Figure 13.24 Example of PWM Mode Operation (3)................................................................. 230
Figure 13.25 Example of PWM Mode Operation (4)................................................................. 231
Figure 13.26 Example of Reset Synchronous PWM Mode Setting Procedure........................... 233
Figure 13.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) ...... 234
Figure 13.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) ...... 235
Figure 13.29 Example of Complementary PWM Mode Setting Procedure................................237
Figure 13.30 Canceling Procedure of Complementary PWM Mode.......................................... 238
Figure 13.31 Example of Complementary PWM Mode Operation (1) ...................................... 239
Figure 13.32 (1) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 = 0) (2)......................................................................241
Figure 13.32 (2) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 ≠ 0) (3)......................................................................242
Figure 13.33 Timing of Overshooting........................................................................................ 243
Figure 13.34 Timing of Undershooting ...................................................................................... 243
Figure 13.35 Compare Match Buffer Operation......................................................................... 246
Figure 13.36 Input Capture Buffer Operation............................................................................. 247
Figure 13.37 Example of Buffer Operation Setting Procedure................................................... 247
Figure 13.38 Example of Buffer Operation (1)
(Buffer Operation for Output Compare Register).................................................. 248
Figure 13.39 Example of Compare Match Timing for Buffer Operation ................................... 249
Figure 13.40 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register) ...................................................... 250
Figure 13.41 Input Capture Timing of Buffer Operation............................................................ 251
Figure 13.42 Buffer Operation (3)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............ 252
Figure 13.43 Buffer Operation (4)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............ 253
Figure 13.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 254
Figure 13.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 255
Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 256
Figure 13.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 256
Figure 13.48 IMF Flag Set Timing when Compare Match Occurs ............................................257
Figure 13.49 IMF Flag Set Timing at Input Capture.................................................................. 258
Figure 13.50 OVF Flag Set Timing............................................................................................ 258
Figure 13.51 Status Flag Clearing Timing.................................................................................. 259
Figure 13.52 Contention between TCNT Write and Clear Operations....................................... 260
Figure 13.53 Contention between TCNT Write and Increment Operations............................... 261
Figure 13.54 Contention between GR Write and Compare Match............................................. 261
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Figure 13.55 Contention between TCNT Write and Overflow...................................................262
Figure 13.56 Contention between GR Read and Input Capture..................................................263
Figure 13.57 Contention between Count Clearing and Increment Operations
by Input Capture.................................................................................................... 264
Figure 13.58 Contention between GR Write and Input Capture................................................. 265
Figure 13.59 When Compare Match and Bit Manipulation Instruction to TOCR
Occur at the Same Timing..................................................................................... 266
Section 14 Watchdog Timer
Figure 14.1 Block Diagram of Watchdog Timer........................................................................ 267
Figure 14.2 Watchdog Timer Operation Example...................................................................... 271
Section 15 14-Bit PWM
Figure 15.1 Block Diagram of 14-Bit PWM ..............................................................................273
Figure 15.2 Waveform Output by 14-Bit PWM ......................................................................... 276
Section 16 Serial Communication Interface 3 (SCI3)
Figure 16.1 Block Diagram of SCI3........................................................................................... 279
Figure 16.2 Data Format in Asynchronous Communication ...................................................... 295
Figure 16.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) .............295
Figure 16.4 Sample SCI3 Initialization Flowchart .....................................................................296
Figure 16.5 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ...........................................................................297
Figure 16.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 298
Figure 16.7 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ...........................................................................299
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)......................301
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)......................302
Figure 16.9 Data Format in Clock Synchronous Communication.............................................. 303
Figure 16.10 Example of SCI3 Transmission in Clock Synchronous Mode .............................. 304
Figure 16.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode).................... 305
Figure 16.12 Example of SCI3 Reception in Clock Synchronous Mode.................................... 306
Figure 16.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) ......................... 307
Figure 16.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clock Synchronous Mode)................................................................................... 309
Figure 16.15 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)...........................................311
Figure 16.16 Sample Multiprocessor Serial Transmission Flowchart........................................ 312
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 314
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 315
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Figure 16.18 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 316
Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 319
Section 17 I2C Bus Interface 2 (IIC2)
Figure 17.1 Block Diagram of I
2
C Bus Interface 2..................................................................... 322
Figure 17.2 External Circuit Connections of I/O Pins................................................................ 323
Figure 17.3 I2C Bus Formats ...................................................................................................... 337
Figure 17.4 I2C Bus Timing........................................................................................................ 337
Figure 17.5 Master Transmit Mode Operation Timing (1)......................................................... 339
Figure 17.6 Master Transmit Mode Operation Timing (2)......................................................... 339
Figure 17.7 Master Receive Mode Operation Timing (1) .......................................................... 341
Figure 17.8 Master Receive Mode Operation Timing (2) .......................................................... 342
Figure 17.9 Slave Transmit Mode Operation Timing (1)........................................................... 343
Figure 17.10 Slave Transmit Mode Operation Timing (2)......................................................... 344
Figure 17.11 Slave Receive Mode Operation Timing (1)........................................................... 345
Figure 17.12 Slave Receive Mode Operation Timing (2)........................................................... 345
Figure 17.13 Clock Synchronous Serial Transfer Format .......................................................... 346
Figure 17.14 Transmit Mode Operation Timing.........................................................................347
Figure 17.15 Receive Mode Operation Timing .......................................................................... 348
Figure 17.16 Block Diagram of Noise Filter .............................................................................. 349
Figure 17.17 Sample Flowchart for Master Transmit Mode ......................................................350
Figure 17.18 Sample Flowchart for Master Receive Mode........................................................ 351
Figure 17.19 Sample Flowchart for Slave Transmit Mode......................................................... 352
Figure 17.20 Sample Flowchart for Slave Receive Mode .......................................................... 353
Figure 17.21 The Timing of the Bit Synchronous Circuit.......................................................... 355
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 358
Figure 18.2 A/D Conversion Timing.......................................................................................... 364
Figure 18.3 External Trigger Input Timing ................................................................................ 365
Figure 18.4 A/D Conversion Accuracy Definitions (1).............................................................. 367
Figure 18.5 A/D Conversion Accuracy Definitions (2).............................................................. 367
Figure 18.6 Analog Input Circuit Example ................................................................................ 368
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
Figure 19.1 Block Diagram around BGR ................................................................................... 370
Figure 19.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit....371
Figure 19.3 Operational Timing of Power-On Reset Circuit...................................................... 377
Figure 19.4 Operating Timing of LVDR Circuit........................................................................ 378
Figure 19.5 Operational Timing of LVDI Circuit ......................................................................379
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Figure 19.6 Operational Timing of LVDI Circuit
(When Compared Voltage is Input through ExtU and ExtD Pins).......................... 381
Figure 19.7 Timing of Setting Bits in Reset Source Decision Register...................................... 382
Section 20 Power Supply Circuit
Figure 20.1 Power Supply Connection when Internal Step-Down Circuit is Used ....................383
Section 22 Electrical Characteristics
Figure 22.1 System Clock Input Timing.....................................................................................425
Figure 22.2 RES Low Width Timing.......................................................................................... 425
Figure 22.3 Input Timing............................................................................................................ 425
Figure 22.4 I2C Bus Interface Input/Output Timing................................................................... 426
Figure 22.5 SCK3 Input Clock Timing.......................................................................................426
Figure 22.6 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 427
Figure 22.7 Output Load Circuit................................................................................................. 427
Appendix
Figure B.1 Port 1 Block Diagram (P17) .....................................................................................459
Figure B.2 Port 1 Block Diagram (P14, P16)............................................................................. 460
Figure B.3 Port 1 Block Diagram (P15) .....................................................................................461
Figure B.4 Port 1 Block Diagram (P12) .....................................................................................462
Figure B.5 Port 2 Block Diagram (P11) .....................................................................................463
Figure B.6 Port 1 Block Diagram (P10) .....................................................................................464
Figure B.7 Port 2 Block Diagram (P24, P23)............................................................................. 465
Figure B.8 Port 2 Block Diagram (P22) .....................................................................................466
Figure B.9 Port 2 Block Diagram (P21) .....................................................................................467
Figure B.10 Port 2 Block Diagram (P20) ...................................................................................468
Figure B.11 Port 3 Block Diagram (P37 to P30) ........................................................................ 469
Figure B.12 Port 5 Block Diagram (P57, P56) ...........................................................................470
Figure B.13 Port 5 Block Diagram (P55) ...................................................................................471
Figure B.14 Port 5 Block Diagram (P54 to P50) ........................................................................ 472
Figure B.15 Port 6 Block Diagram (P67 to P60) ........................................................................ 473
Figure B.16 Port 7 Block Diagram (P76) ...................................................................................474
Figure B.17 Port 7 Block Diagram (P75) ...................................................................................475
Figure B.18 Port 7 Block Diagram (P74) ...................................................................................476
Figure B.19 Port 7 Block Diagram (P72) ...................................................................................477
Figure B.20 Port 7 Block Diagram (P71) ...................................................................................478
Figure B.21 Port 7 Block Diagram (P70) ...................................................................................478
Figure B.22 Port 8 Block Diagram (P87 to P85) ........................................................................ 479
Figure B.23 Port B Block Diagram (PB7 and PB6) ................................................................... 480
Figure B.24 Port B Block Diagram (PB5 to PB0)...................................................................... 480
Figure B.25 Port B Block Diagram (PC1).................................................................................. 481
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Figure B.26 Port B Block Diagram (PC0).................................................................................. 482
Figure D.1 FP-64K Package Dimensions................................................................................... 485
Figure D.2 FP-64A Package Dimensions................................................................................... 486
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Tables
Section 1 Overview
Table 1.1
Section 2 CPU
Table 2.1
Table 2.2 Data Transfer Instructions.......................................................................................19
Table 2.3 Arithmetic Operations Instructions (1) ...................................................................20
Table 2.3 Arithmetic Operations Instructions (2) ...................................................................21
Table 2.4 Logic Operations Instructions................................................................................. 22
Table 2.5 Shift Instructions.....................................................................................................22
Table 2.6 Bit Manipulation Instructions (1)............................................................................ 23
Table 2.6 Bit Manipulation Instructions (2)............................................................................ 24
Table 2.7 Branch Instructions................................................................................................. 25
Table 2.8 System Control Instructions.................................................................................... 26
Table 2.9 Block Data Transfer Instructions ............................................................................ 27
Table 2.10 Addressing Modes .................................................................................................. 29
Table 2.11 Absolute Address Access Ranges........................................................................... 31
Table 2.12 Effective Address Calculation (1)........................................................................... 32
Table 2.12 Effective Address Calculation (2)........................................................................... 33
Section 3 Exception Handling
Table 3.1
Table 3.2 Interrupt Wait States ...............................................................................................57
Pin Functions ............................................................................................................ 5
Operation Notation ................................................................................................. 18
Exception Sources and Vector Address .................................................................. 44
Section 4 Address Break
Table 4.1
Section 5 Clock Pulse Generator
Table 5.1
Section 6 Power-Down Modes
Table 6.1
Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode
Table 6.3 Internal State in Each Operating Mode................................................................... 98
Section 7 ROM
Table 7.1
Table 7.2 Boot Mode Operation ...........................................................................................111
Access and Data Bus Used .....................................................................................63
Crystal Resonator Parameters.................................................................................84
Operating Frequency and Waiting Time................................................................. 92
due to Interrupt........................................................................................................97
Setting Programming Modes ................................................................................109
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Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate
is Possible ............................................................................................................. 112
Table 7.4 Reprogram Data Computation Table .................................................................... 115
Table 7.5 Additional-Program Data Computation Table...................................................... 115
Table 7.6 Programming Time............................................................................................... 115
Table 7.7 Flash Memory Operating States............................................................................ 120
Section 10 Realtime Clock (RTC)
Table 10.1
Table 10.2 Interrupt Sources................................................................................................... 170
Section 11 Timer B1
Table 11.1
Table 11.2 Timer B1 Operating Modes.................................................................................. 175
Section 12 Timer V
Table 12.1
Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 181
Section 13 Timer Z
Table 13.1
Table 13.2 Pin Configuration.................................................................................................. 196
Table 13.3 Initial Output Level of FTIOB0 Pin...................................................................... 227
Table 13.4 Output Pins in Reset Synchronous PWM Mode................................................... 232
Table 13.5 Register Settings in Reset Synchronous PWM Mode........................................... 232
Table 13.6 Output Pins in Complementary PWM Mode........................................................ 236
Table 13.7 Register Settings in Complementary PWM Mode................................................ 236
Table 13.8 Register Combinations in Buffer Operation ......................................................... 246
Pin Configuration.................................................................................................. 160
Pin Configuration.................................................................................................. 172
Pin Configuration.................................................................................................. 179
Timer Z Functions ................................................................................................192
Section 15 14-Bit PWM
Table 15.1
Section 16 Serial Communication Interface 3 (SCI3)
Table 16.1
Table 16.2 Pin Configuration.................................................................................................. 280
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 289
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 290
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 291
Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................292
Table 16.5 Examples of BRR Settings for Various Bit Rates
Table 16.5 Examples of BRR Settings for Various Bit Rates
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Pin Configuration.................................................................................................. 274
Channel Configuration.......................................................................................... 278
(Clock Synchronous Mode) (1) ............................................................................293
(Clock Synchronous Mode) (2) ............................................................................294
Table 16.6 SSR Status Flags and Receive Data Handling...................................................... 300
Table 16.7 SCI3 Interrupt Requests........................................................................................ 317
Section 17 I2C Bus Interface 2 (IIC2)
Table 17.1
Table 17.2 Transfer Rate ........................................................................................................326
Table 17.3 Interrupt Requests................................................................................................. 354
Table 17.4 Time for Monitoring SCL..................................................................................... 355
Section 18 A/D Converter
Table 18.1
Table 18.2 Analog Input Channels and Corresponding ADDR Registers.............................. 360
Table 18.3 A/D Conversion Time (Single Mode)................................................................... 365
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
Table 19.1
Table 19.2 Deciding Reset Source.......................................................................................... 382
Section 22 Electrical Characteristics
Table 22.1
Table 22.2 DC Characteristics (1)...........................................................................................409
Table 22.2 DC Characteristics (2)...........................................................................................414
Table 22.3 AC Characteristics ................................................................................................415
Table 22.4 I2C Bus Interface Timing...................................................................................... 417
Table 22.5 Serial Communication Interface (SCI) Timing..................................................... 418
Table 22.6 A/D Converter Characteristics.............................................................................. 419
Table 22.7 Watchdog Timer Characteristics........................................................................... 420
Table 22.8 Flash Memory Characteristics ..............................................................................421
Table 22.9 Power-Supply-Voltage Detection Circuit Characteristics.....................................423
Table 22.10 LVDI External Input Voltage Detection Circuit Characteristics ......................423
Table 22.11 Power-On Reset Circuit Characteristics............................................................ 424
2
I
C Bus Interface Pins........................................................................................... 323
Pin Configuration.................................................................................................. 359
LVDCR Settings and Select Functions................................................................. 373
Absolute Maximum Ratings .................................................................................405
Appendix
Table A.1
Table A.2 Operation Code Map (1) ....................................................................................... 444
Table A.2 Operation Code Map (2) ....................................................................................... 445
Table A.2 Operation Code Map (3) ....................................................................................... 446
Table A.3 Number of Cycles in Each Instruction.................................................................. 448
Table A.4 Number of Cycles in Each Instruction.................................................................. 449
Table A.5 Combinations of Instructions and Addressing Modes ..........................................458
Instruction Set....................................................................................................... 431
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