RENESAS HD64F36077G, HD64F36074G User Manual

Download

REJ09B0216-0100

H8/36077 Group

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8 Family/H8/300H Tiny Series

H8/36077GF HD64F36077G H8/36074GF HD64F36074G

Rev.1.00 Revision Date: Sep. 16, 2005

Rev. 1.00 Sep. 16, 2005 Page ii of xxx

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Rev. 1.00 Sep. 16, 2005 Page iii of xxx

General Precautions on Handling of Product

1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are hi g h-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.

3. Processing before Initialization Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Rese r ved Ad dresses Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.

Rev. 1.00 Sep. 16, 2005 Page iv of xxx

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual.

11. Index

Rev. 1.00 Sep. 16, 2005 Page v of xxx

Preface

The H8/36077 Group are single-chip microcom put ers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU.

Target Users: This manual was written for users who will be using the H8/36077 Group in the

design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8/36077 Group to the target users. Refer to the H8/300H Series Programming Manual for a detailed description of the instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughl y categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions Read the H8/300H Series Programming Manual.

• In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the

Example: Register name: The follo wi n g notat i on is used for cases when the same or a

similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number)

Bit order: The MSB is on the left and the LSB is on the right.

Rev. 1.00 Sep. 16, 2005 Page vi of xxx

Notes:

When using an on-chip emulator (E7, E8) for H8/36077 program development and debugging, the following restrictions must be noted.

1. The NMI pin is reserved for the E7 or E8, and cannot be used.

2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional ha rdware must be provided on the user board.

3. Area H’D000 to H’DFFF is used by the E7 or E8, and is not available to the user.

4. Area H’F780 to H’FB7F must on no account be accessed.

5. When the E7or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7, the address break control registers must not be accessed.

6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and P87 are input pins, and P86 is an output pin.

7. Use channel 1 of the SCI3 (P21/RXD, P22/TXD) in on-board programming mode by boot mode.

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require. http://www.renesas.com/

Rev. 1.00 Sep. 16, 2005 Page vii of xxx

H8/36077 Group manuals:

Document Title Document No.

H8/36077 Group Hardware Manual This manual

H8/300H Series Programming Manual ADE-602-053

User's manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual

Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's Manual

H8S, H8/300 Series High-Performance Embedded Workshop 3, Tutorial REJ10B0024

H8S, H8/300 Series High-Performance Embedded Workshop 3, User's Manual

REJ10B0058

ADE-702-282

REJ10B0026

Application notes:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464

Single Power Supply F-ZTATTM On-Board Programming ADE-502-055

Rev. 1.00 Sep. 16, 2005 Page viii of xxx

Section 1 Overview................................................................................................1

1.1 Features..................................................................................................................................1

1.2 Block Diagram....................................................................................................................... 3

1.3 Pin Arrangement.................................................................................................................... 4

1.4 Pin Functions ......................................................................................................................... 5

Section 2 CPU........................................................................................................9

2.1 Address Space and Memory Map........................................................................................10

2.2 Register Configuration.........................................................................................................11

2.2.1 General Registers....................................................................................................12

2.2.2 Program Counter (PC)............................................................................................13

2.2.3 Condition-Code Register (CCR).............................................................................13

2.3 Data Formats........................................................................................................................ 15

2.3.1 General Register Data Formats...............................................................................15

2.3.2 Memory Data Formats............................................................................................ 17

2.4 Instruction Set...................................................................................................................... 18

2.4.1 Table of Instructions Classified by Function..........................................................18

2.4.2 Basic Instruction Formats.......................................................................................28

2.5 Addressing Modes and Effective Address Calculation........................................................ 29

2.5.1 Addressing Modes ..................................................................................................29

2.5.2 Effective Address Calculation ................................................................................ 32

2.6 Basic Bus Cycle................................................................................................................... 34

2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................34

2.6.2 On-Chip Peripheral Modules.................................................................................. 35

2.7 CPU States...........................................................................................................................36

2.8 Usage Notes.........................................................................................................................37

2.8.1 Notes on Data Access to Empty Areas ................................................................... 37

2.8.2 EEPMOV Instruction.............................................................................................. 37

2.8.3 Bit-Manipulation Instruction .................................................................................. 37

Section 3 Exception Handling .............................................................................43

3.1 Exception Sources and Vector Address............................................................................... 44

3.2 Register Descriptions...........................................................................................................46

3.2.1 Interrupt Edge Select Register 1 (IEGR1)..............................................................46

3.2.2 Interrupt Edge Select Register 2 (IEGR2)..............................................................47

3.2.3 Interrupt Enable Register 1 (IENR1)......................................................................48

Rev. 1.00 Sep. 16, 2005 Page ix of xxx

3.2.4 Interrupt Enable Register 2 (IENR2)...................................................................... 49

3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 49

3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 51

3.2.7 Wakeup Interrupt Flag Register (IWPR)................................................................ 51

3.3 Reset Exception Handling.................................................................................................... 53

3.4 Interrupt Exception Handling .............................................................................................. 54

3.4.1 External Interrupts..................................................................................................54

3.4.2 Internal Interrupts ................................................................................................... 56

3.4.3 Interrupt Handling Sequence..................................................................................56

3.4.4 Interrupt Response Time......................................................................................... 57

3.5 Usage Notes......................................................................................................................... 59

3.5.1 Interrupts after Reset............................................................................................... 59

3.5.2 Notes on Stack Area Use........................................................................................59

3.5.3 Notes on Rewriting Port Mode Registers............................................................... 59

Section 4 Address Break .....................................................................................61

4.1 Register Descriptions...........................................................................................................62

4.1.1 Address Break Control Register (ABRKCR) ......................................................... 62

4.1.2 Address Break Status Register (ABRKSR)............................................................64

4.1.3 Break Address Registers (BARH, BARL).............................................................. 64

4.1.4 Break Data Registers (BDRH, BDRL)...................................................................64

4.2 Operation ............................................................................................................................. 65

Section 5 Clock Pulse Generator.........................................................................67

5.1 Features................................................................................................................................ 68

5.2 Register Descriptions...........................................................................................................68

5.2.1 RC Control Register (RCCR) ................................................................................. 69

5.2.2 RC Trimming Data Protect Register (RCTRMDPR)..............................................70

5.2.3 RC Trimming Data Register (RCTRMDR)............................................................ 71

5.2.4 Clock Control/Status Register (CKCSR)................................................................ 72

5.3 System Clock Select Operation ........................................................................................... 75

5.3.1 Clock Control Operation......................................................................................... 75

5.3.2 Clock Switching Timing......................................................................................... 79

5.4 Trimming of On-Chip Oscillator Frequency........................................................................82

5.5 External Oscillators.............................................................................................................. 83

5.5.1 Connecting Crystal Resonator................................................................................ 83

5.5.2 Connecting Ceramic Resonator..............................................................................84

5.5.3 Inputting External Clock......................................................................................... 85

5.6 Subclock Oscillator.............................................................................................................. 85

5.6.1 Connecting 32.768-kHz Crystal Resonator ............................................................ 86

Rev. 1.00 Sep. 16, 2005 Page x of xxx

5.6.2 Pin Connection when Not Using Subclock............................................................. 86

5.7 Prescaler............................................................................................................................... 87

5.7.1 Prescaler S .............................................................................................................. 87

5.7.2 Prescaler W............................................................................................................. 87

5.8 Usage Notes.........................................................................................................................88

5.8.1 Note on Resonators.................................................................................................88

5.8.2 Notes on Board Design........................................................................................... 88

Section 6 Power-Down Modes ............................................................................89

6.1 Register Descriptions...........................................................................................................90

6.1.1 System Control Register 1 (SYSCR1).................................................................... 90

6.1.2 System Control Register 2 (SYSCR2).................................................................... 93

6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 94

6.1.4 Module Standby Control Register 2 (MSTCR2) .................................................... 95

6.2 Mode Transitions and States of LSI..................................................................................... 96

6.2.1 Sleep Mode.............................................................................................................99

6.2.2 Standby Mode.........................................................................................................99

6.2.3 Subsleep Mode...................................................................................................... 100

6.2.4 Subactive Mode .................................................................................................... 100

6.3 Operating Frequency in Active Mode................................................................................ 101

6.4 Direct Transition................................................................................................................ 101

6.4.1 Direct Transition from Active Mode to Subactive Mode ..................................... 101

6.4.2 Direct Transition from Subactive Mode to Active Mode ..................................... 102

6.5 Module Standby Function.................................................................................................. 102

Section 7 ROM ..................................................................................................103

7.1 Block Configuration...........................................................................................................103

7.2 Register Descriptions......................................................................................................... 105

7.2.1 Flash Memory Control Register 1 (FLMCR1)......................................................105

7.2.2 Flash Memory Control Register 2 (FLMCR2)......................................................106

7.2.3 Erase Block Register 1 (EBR1) ............................................................................ 107

7.2.4 Flash Memory Power Control Register (FLPWCR)............................................. 108

7.2.5 Flash Memory Enable Register (FENR) ............................................................... 108

7.3 On-Board Programming Modes......................................................................................... 109

7.3.1 Boot Mode............................................................................................................109

7.3.2 Programming/Erasing in User Program Mode......................................................112

7.4 Flash Memory Programming/Erasing................................................................................113

7.4.1 Program/Program-Verify...................................................................................... 113

7.4.2 Erase/Erase-Verify................................................................................................ 116

7.4.3 Interrupt Handling when Programming/Erasing Flash Memory...........................116

Rev. 1.00 Sep. 16, 2005 Page xi of xxx

7.5 Program/Erase Protection.................................................................................................. 118

7.5.1 Hardware Protection.............................................................................................118

7.5.2 Software Protection .............................................................................................. 118

7.5.3 Error Protection .................................................................................................... 118

7.6 Programmer Mode............................................................................................................. 119

7.7 Power-Down States for Flash Memory.............................................................................. 119

Section 8 RAM..................................................................................................121

Section 9 I/O Ports.............................................................................................123

9.1 Port 1.................................................................................................................................. 123

9.1.1 Port Mode Register 1 (PMR1).............................................................................. 124

9.1.2 Port Control Register 1 (PCR1)............................................................................ 125

9.1.3 Port Data Register 1 (PDR1) ................................................................................ 125

9.1.4 Port Pull-Up Control Register 1 (PUCR1)............................................................126

9.1.5 Pin Functions........................................................................................................126

9.2 Port 2.................................................................................................................................. 129

9.2.1 Port Control Register 2 (PCR2)............................................................................ 129

9.2.2 Port Data Register 2 (PDR2) ................................................................................ 130

9.2.3 Port Mode Register 3 (PMR3).............................................................................. 130

9.2.4 Pin Functions........................................................................................................131

9.3 Port 3.................................................................................................................................. 133

9.3.1 Port Control Register 3 (PCR3)............................................................................ 133

9.3.2 Port Data Register 3 (PDR3) ................................................................................ 134

9.3.3 Pin Functions........................................................................................................134

9.4 Port 5.................................................................................................................................. 137

9.4.1 Port Mode Register 5 (PMR5).............................................................................. 138

9.4.2 Port Control Register 5 (PCR5)............................................................................ 139

9.4.3 Port Data Register 5 (PDR5) ................................................................................ 139

9.4.4 Port Pull-Up Control Register 5 (PUCR5)............................................................140

9.4.5 Pin Functions........................................................................................................140

9.5 Port 6.................................................................................................................................. 143

9.5.1 Port Control Register 6 (PCR6)............................................................................ 143

9.5.2 Port Data Register 6 (PDR6) ................................................................................ 144

9.5.3 Pin Functions........................................................................................................144

9.6 Port 7.................................................................................................................................. 148

9.6.1 Port Control Register 7 (PCR7)............................................................................ 148

9.6.2 Port Data Register 7 (PDR7) ................................................................................ 149

9.6.3 Pin Functions........................................................................................................149

9.7 Port 8.................................................................................................................................. 151

Rev. 1.00 Sep. 16, 2005 Page xii of xxx

9.7.1 Port Control Register 8 (PCR8)............................................................................151

9.7.2 Port Data Register 8 (PDR8).................................................................................151

9.7.3 Pin Functions........................................................................................................152

9.8 Port B................................................................................................................................. 153

9.8.1 Port Data Register B (PDRB)...............................................................................153

9.8.2 Pin Functions........................................................................................................154

9.9 Port C................................................................................................................................. 157

9.9.1 Port Control Register C (PCRC)........................................................................... 157

9.9.2 Port Data Register C (PDRC)...............................................................................158

9.9.3 Pin Functions........................................................................................................158

Section 10 Realtime Clock (RTC).....................................................................159

10.1 Features..............................................................................................................................159

10.2 Input/Output Pin.................................................................................................................160

10.3 Register Descriptions......................................................................................................... 161

10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) ............. 161

10.3.2 Minute Data Register (RMINDR)......................................................................... 162

10.3.3 Hour Data Register (RHRDR)..............................................................................163

10.3.4 Day-of-Week Data Register (RWKDR) ............................................................... 164

10.3.5 RTC Control Register 1 (RTCCR1)...................................................................... 165

10.3.6 RTC Control Register 2 (RTCCR2)...................................................................... 166

10.3.7 Clock Source Select Register (RTCCSR).............................................................167

10.4 Operation ........................................................................................................................... 168

10.4.1 Initial Settings of Registers after Power-On ......................................................... 168

10.4.2 Initial Setting Procedure .......................................................................................168

10.4.3 Data Reading Procedure .......................................................................................169

10.5 Interrupt Sources................................................................................................................ 170

Section 11 Timer B1..........................................................................................171

11.1 Features..............................................................................................................................171

11.2 Input/Output Pin.................................................................................................................172

11.3 Register Descriptions......................................................................................................... 173

11.3.1 Timer Mode Register B1 (TMB1) ........................................................................173

11.3.2 Timer Counter B1 (TCB1).................................................................................... 174

11.3.3 Timer Load Register B1 (TLB1) ..........................................................................174

11.4 Operation ........................................................................................................................... 174

11.4.1 Interval Timer Operation ...................................................................................... 174

11.4.2 Auto-Reload Timer Operation..............................................................................175

11.4.3 Event Counter Operation ...................................................................................... 175

11.5 Timer B1 Operating Modes...............................................................................................175

Rev. 1.00 Sep. 16, 2005 Page xiii of xxx

Section 12 Timer V ...........................................................................................177

12.1 Features.............................................................................................................................. 177

12.2 Input/Output Pins...............................................................................................................179

12.3 Register Descriptions......................................................................................................... 179

12.3.1 Timer Counter V (TCNTV).................................................................................. 179

12.3.2 Time Constant Registers A and B (TCORA, TCORB) ........................................ 180

12.3.3 Timer Control Register V0 (TCRV0)................................................................... 180

12.3.4 Timer Control/Status Register V (TCSRV).......................................................... 181

12.3.5 Timer Control Register V1 (TCRV1)................................................................... 183

12.4 Operation ........................................................................................................................... 184

12.4.1 Timer V Operation................................................................................................ 184

12.5 Timer V Application Examples......................................................................................... 187

12.5.1 Pulse Output with Arbitrary Duty Cycle............................................................... 187

12.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input..............188

12.6 Usage Notes....................................................................................................................... 189

Section 13 Timer Z............................................................................................191

13.1 Features.............................................................................................................................. 191

13.2 Input/Output Pins...............................................................................................................196

13.3 Register Descriptions......................................................................................................... 197

13.3.1 Timer Start Register (TSTR) ................................................................................ 198

13.3.2 Timer Mode Register (TMDR)............................................................................. 198

13.3.3 Timer PWM Mode Register (TPMR)...................................................................199

13.3.4 Timer Function Control Register (TFCR) ............................................................ 200

13.3.5 Timer Output Master Enable Register (TOER) .................................................... 202

13.3.6 Timer Output Control Register (TOCR)............................................................... 204

13.3.7 Timer Counter (TCNT)......................................................................................... 205

13.3.8 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)........................ 205

13.3.9 Timer Control Register (TCR).............................................................................. 206

13.3.10 Timer I/O Control Register (TIORA and TIORC)............................................... 207

13.3.11 Timer Status Register (TSR)................................................................................. 210

13.3.12 Timer Interrupt Enable Register (TIER)............................................................... 212

13.3.13 PWM Mode Output Level Control Register (POCR)........................................... 213

13.3.14 Interface with CPU ............................................................................................... 214

13.4 Operation ........................................................................................................................... 215

13.4.1 Counter Operation ................................................................................................ 215

13.4.2 Waveform Output by Compare Match.................................................................. 219

13.4.3 Input Capture Function ......................................................................................... 221

13.4.4 Synchronous Operation......................................................................................... 225

13.4.5 PWM Mode .......................................................................................................... 226

Rev. 1.00 Sep. 16, 2005 Page xiv of xxx

13.4.6 Reset Synchronous PWM Mode...........................................................................232

13.4.7 Complementary PWM Mode................................................................................ 236

13.4.8 Buffer Operation...................................................................................................246

13.4.9 Timer Z Output Timing ........................................................................................ 254

13.5 Interrupts............................................................................................................................257

13.5.1 Status Flag Set Timing.......................................................................................... 257

13.5.2 Status Flag Clearing Timing ................................................................................. 259

13.6 Usage Notes.......................................................................................................................260

Section 14 Watchdog Timer..............................................................................267

14.1 Features..............................................................................................................................267

14.2 Register Descriptions......................................................................................................... 268

14.2.1 Timer Control/Status Register WD (TCSRWD)................................................... 268

14.2.2 Timer Counter WD (TCWD)................................................................................ 270

14.2.3 Timer Mode Register WD (TMWD) .................................................................... 270

14.3 Operation ........................................................................................................................... 271

Section 15 14-Bit PWM.....................................................................................273

15.1 Features..............................................................................................................................273

15.2 Input/Output Pin.................................................................................................................274

15.3 Register Descriptions......................................................................................................... 275

15.3.1 PWM Control Register (PWCR) ..........................................................................275

15.3.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................. 275

15.4 Operation ........................................................................................................................... 276

Section 16 Serial Communication Interface 3 (SCI3) .......................................277

16.1 Features..............................................................................................................................277

16.2 Input/Output Pins...............................................................................................................280

16.3 Register Descriptions......................................................................................................... 281

16.3.1 Receive Shift Register (RSR) ...............................................................................281

16.3.2 Receive Data Register (RDR)............................................................................... 281

16.3.3 Transmit Shift Register TSR (SCI3)..................................................................... 281

16.3.4 Transmit Data Register (TDR).............................................................................. 282

16.3.5 Serial Mode Register (SMR) ................................................................................ 282

16.3.6 Serial Control Register 3 (SCR3).......................................................................... 284

16.3.7 Serial Status Register (SSR) ................................................................................. 286

16.3.8 Bit Rate Register (BRR) .......................................................................................288

16.4 Operation in Asynchronous Mode.....................................................................................295

16.4.1 Clock..................................................................................................................... 295

16.4.2 SCI3 Initialization................................................................................................. 296

Rev. 1.00 Sep. 16, 2005 Page xv of xxx

16.4.3 Data Transmission ................................................................................................ 297

16.4.4 Serial Data Reception ........................................................................................... 299

16.5 Operation in Clock Synchronous Mode............................................................................. 303

16.5.1 Clock..................................................................................................................... 303

16.5.2 SCI3 Initialization................................................................................................. 303

16.5.3 Serial Data Transmission......................................................................................304

16.5.4 Serial Data Reception (Clock Synchronous Mode).............................................. 306

16.5.5 Simultaneous Serial Data Transmission and Reception........................................ 308

16.6 Multiprocessor Communication Function..........................................................................310

16.6.1 Multiprocessor Serial Data Transmission.............................................................311

16.6.2 Multiprocessor Serial Data Reception .................................................................. 313

16.7 Interrupts............................................................................................................................ 317

16.8 Usage Notes....................................................................................................................... 318

16.8.1 Break Detection and Processing ........................................................................... 318

16.8.2 Mark State and Break Sending ............................................................................. 318

16.8.3 Receive Error Flags and Transmit Operations

(Clock Synchronous Mode Only)......................................................................... 318

16.8.4 Receive Data Sampling Timing and Reception Margin

in Asynchronous Mode......................................................................................... 319

Section 17 I2C Bus Interface 2 (IIC2)................................................................321

17.1 Features.............................................................................................................................. 321

17.2 Input/Output Pins...............................................................................................................323

17.3 Register Descriptions......................................................................................................... 324

17.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 324

17.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 327

17.3.3 I2C Bus Mode Register (ICMR)............................................................................ 328

17.3.4 I2C Bus Interrupt Enable Register (ICIER)........................................................... 330

17.3.5 I2C Bus Status Register (ICSR)............................................................................. 332

17.3.6 Slave Address Register (SAR).............................................................................. 335

17.3.7 I2C Bus Transmit Data Register (ICDRT) ............................................................ 336

17.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 336

17.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 336

17.4 Operation ........................................................................................................................... 337

17.4.1 I2C Bus Format......................................................................................................337

17.4.2 Master Transmit Operation................................................................................... 338

17.4.3 Master Receive Operation .................................................................................... 340

17.4.4 Slave Transmit Operation ..................................................................................... 342

17.4.5 Slave Receive Operation....................................................................................... 344

17.4.6 Clock Synchronous Serial Format ........................................................................ 346

Rev. 1.00 Sep. 16, 2005 Page xvi of xxx

17.4.7 Noise Filter ...........................................................................................................349

17.4.8 Example of Use.....................................................................................................349

17.5 Interrupt Request................................................................................................................354

17.6 Bit Synchronous Circuit..................................................................................................... 355

17.7 Usage Notes.......................................................................................................................356

17.7.1 Issue (Retransmission) of Start/Stop Conditions .................................................. 356

17.7.2 WAIT Setting in I2C Bus Mode Register (ICMR)................................................ 356

Section 18 A/D Converter..................................................................................357

18.1 Features..............................................................................................................................357

18.2 Input/Output Pins...............................................................................................................359

18.3 Register Descriptions......................................................................................................... 360

18.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ..............................................360

18.3.2 A/D Control/Status Register (ADCSR) ................................................................ 361

18.3.3 A/D Control Register (ADCR) ............................................................................. 362

18.4 Operation ........................................................................................................................... 363

18.4.1 Single Mode.......................................................................................................... 363

18.4.2 Scan Mode ............................................................................................................ 363

18.4.3 Input Sampling and A/D Conversion Time ..........................................................364

18.4.4 External Trigger Input Timing.............................................................................. 365

18.5 A/D Conversion Accuracy Definitions.............................................................................. 366

18.6 Usage Notes.......................................................................................................................368

18.6.1 Permissible Signal Source Impedance..................................................................368

18.6.2 Influences on Absolute Accuracy ......................................................................... 368

Section 19 Band-Gap Circuit, Power-On Reset, and

Low-Voltage Detection Circuits......................................................369

19.1 Features..............................................................................................................................370

19.2 Register Descriptions......................................................................................................... 372

19.2.1 Low-Voltage-Detection Control Register (LVDCR)............................................ 372

19.2.2 Low-Voltage-Detection Status Register (LVDSR)............................................... 373

19.2.3 Reset Source Decision Register (LVDRF) ...........................................................374

19.3 Operations..........................................................................................................................376

19.3.1 Power-On Reset Circuit ........................................................................................376

19.3.2 Low-Voltage Detection Circuit............................................................................. 377

19.3.3 Deciding Reset Source.......................................................................................... 382

Section 20 Power Supply Circuit.......................................................................383

20.1 When Using Internal Power Supply Step-Down Circuit....................................................383

Rev. 1.00 Sep. 16, 2005 Page xvii of xxx

Section 21 List of Registers...............................................................................385

21.1 Register Addresses (Address Order).................................................................................. 386

21.2 Register Bits....................................................................................................................... 393

21.3 Registers States in Each Operating Mode.......................................................................... 399

Section 22 Electrical Characteristics.................................................................405

22.1 Absolute Maximum Ratings..............................................................................................405

22.2 Electrical Characteristics (F-ZTAT™ Version)................................................................. 406

22.2.1 Power Supply Voltage and Operating Ranges...................................................... 406

22.2.2 DC Characteristics................................................................................................ 409

22.2.3 AC Characteristics................................................................................................ 415

22.2.4 A/D Converter Characteristics.............................................................................. 419

22.2.5 Watchdog Timer Characteristics........................................................................... 420

22.2.6 Flash Memory Characteristics .............................................................................. 421

22.2.7 Power-Supply-Voltage Detection Circuit Characteristics..................................... 423

22.2.8 LVDI External Input Voltage Detection Circuit Characteristics .......................... 423

22.2.9 Power-On Reset Circuit Characteristics ............................................................... 424

22.3 Operation Timing............................................................................................................... 425

22.4 Output Load Condition......................................................................................................427

Appendix A Instruction Set...............................................................................429

A.1 Instruction List................................................................................................................... 429

A.2 Operation Code Map.......................................................................................................... 444

A.3 Number of Execution States .............................................................................................. 447

A.4 Com binations of Instructions and Addressing Modes....................................................... 458

Appendix B I/O Port Block Diagrams...............................................................459

B.1 I/O Port Block Diagrams ................................................................................................... 459

B.2 Port States in Each Operating State................................................................................... 483

Appendix C Product Code Lineup ....................................................................484

Appendix D Package Dimensions.....................................................................485

Index .........................................................................................................487

Rev. 1.00 Sep. 16, 2005 Page xviii of xxx

Figures

Section 1 Overview

Figure 1.1 Block Diagram of H8/36077 Group.............................................................................. 3

Figure 1.2 Pin Arrangements of H8/36077 Group (FP-64K, FP-64A)........................................... 4

Section 2 CPU

Figure 2.1 Memory Map............................................................................................................... 10

Figure 2.2 CPU Registers .............................................................................................................11

Figure 2.3 Usage of General Registers .........................................................................................12

Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 13

Figure 2.5 General Register Data Formats (1).............................................................................. 15

Figure 2.5 General Register Data Formats (2).............................................................................. 16

Figure 2.6 Memory Data Formats.................................................................................................17

Figure 2.7 Instruction Formats......................................................................................................28

Figure 2.8 Branch Address Specification in Memory Indirect Mode........................................... 32

Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 34

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access).....................................35

Figure 2.11 CPU Operation States................................................................................................ 36

Figure 2.12 State Transitions........................................................................................................ 37

Figure 2.13 Example of Timer Configuration with Two Registers Allocated

to Same Address........................................................................................................ 38

Section 3 Exception Handling

Figure 3.1 Reset Sequence............................................................................................................ 55

Figure 3.2 Stack Status after Exception Handling........................................................................ 57

Figure 3.3 Interrupt Sequence....................................................................................................... 58

Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 59

Section 4 Address Break

Figure 4.1 Block Diagram of Address Break................................................................................61

Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 65

Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 66

Section 5 Clock Pulse Generator

Figure 5.1 Block Diagram of Clock Pulse Generator................................................................... 67

Figure 5.2 State Transition of System Clock................................................................................ 75

Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled................................... 76

Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1)

(From On-Chip Oscillator Clock to External Clock)...................................................77

Rev. 1.00 Sep. 16, 2005 Page xix of xxx

Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2)

(From External Clock to On-Chip Oscillator Clock)................................................... 78

Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock.......... 79

Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock ...............80

Figure 5.8 External Oscillation Backup Timing........................................................................... 81

Figure 5.9 Example of Trimming Flow for On-Chip Oscillator Clock ........................................82

Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency .................................. 83

Figure 5.11 Example of Connection to Crystal Resonator ........................................................... 84

Figure 5.12 Equivalent Circuit of Crystal Resonator....................................................................84

Figure 5.13 Example of Connection to Ceramic Resonator ......................................................... 84

Figure 5.14 Example of External Clock Input.............................................................................. 85

Figure 5.15 Block Diagram of Subclock Oscillator...................................................................... 85

Figure 5.16 Typical Connection to 32.768-kHz Crystal Resonator.............................................. 86

Figure 5.17 Equivalent Circuit of 32.768-kHz Crystal Resonator................................................ 86

Figure 5.18 Pin Connection when not Using Subclock ................................................................ 86

Figure 5.19 Example of Incorrect Board Design.......................................................................... 88

Section 6 Power-Down Modes

Figure 6.1 Mode Transition Diagram ........................................................................................... 96

Section 7 ROM

Figure 7.1 Flash Memory Block Configuration..........................................................................104

Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode.......................... 112

Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 114

Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 117

Section 9 I/O Ports

Figure 9.1 Port 1 Pin Configuration............................................................................................ 123

Figure 9.2 Port 2 Pin Configuration............................................................................................ 129

Figure 9.3 Port 3 Pin Configuration............................................................................................ 133

Figure 9.4 Port 5 Pin Configuration............................................................................................ 137

Figure 9.5 Port 6 Pin Configuration............................................................................................ 143

Figure 9.6 Port 7 Pin Configuration............................................................................................ 148

Figure 9.7 Port 8 Pin Configuration............................................................................................ 151

Figure 9.8 Port B Pin Configuration...........................................................................................153

Figure 9.9 Port C Pin Configuration...........................................................................................157

Section 10 Realtime Clock (RTC)

Figure 10.1 Block Diagram of RTC ........................................................................................... 159

Figure 10.2 Definition of Time Expression ................................................................................ 165

Figure 10.3 Initial Setting Procedure.......................................................................................... 168

Figure 10.4 Example: Reading of Inaccurate Time Data............................................................169

Rev. 1.00 Sep. 16, 2005 Page xx of xxx

Section 11 Timer B1

Figure 11.1 Block Diagram of Timer B1.................................................................................... 171

Section 12 Timer V

Figure 12.1 Block Diagram of Timer V......................................................................................178

Figure 12.2 Increment Timing with Internal Clock.................................................................... 185

Figure 12.3 Increment Timing with External Clock................................................................... 185

Figure 12.4 OVF Set Timing ...................................................................................................... 185

Figure 12.5 CMFA and CMFB Set Timing................................................................................ 186

Figure 12.6 TMOV Output Timing ............................................................................................186

Figure 12.7 Clear Timing by Compare Match............................................................................ 186

Figure 12.8 Clear Timing by TMRIV Input ...............................................................................187

Figure 12.9 Pulse Output Example............................................................................................. 187

Figure 12.10 Example of Pulse Output Synchronized to TRGV Input.......................................188

Figure 12.11 Contention between TCNTV Write and Clear ...................................................... 189

Figure 12.12 Contention between TCORA Write and Compare Match..................................... 190

Figure 12.13 Internal Clock Switching and TCNTV Operation ................................................. 190

Section 13 Timer Z

Figure 13.1 Timer Z Block Diagram .......................................................................................... 193

Figure 13.2 Timer Z (Channel 0) Block Diagram ...................................................................... 194

Figure 13.3 Timer Z (Channel 1) Block Diagram ...................................................................... 195

Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode

and Complementary PWM Mode............................................................................ 202

Figure 13.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits))........ 214

Figure 13.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits)).............214

Figure 13.7 Example of Counter Operation Setting Procedure ..................................................215

Figure 13.8 Free-Running Counter Operation............................................................................ 216

Figure 13.9 Periodic Counter Operation..................................................................................... 217

Figure 13.10 Count Timing at Internal Clock Operation............................................................ 217

Figure 13.11 Count Timing at External Clock Operation (Both Edges Detected)......................218

Figure 13.12 Example of Setting Procedure for Waveform Output by Compare Match............ 219

Figure 13.13 Example of 0 Output/1 Output Operation .............................................................220

Figure 13.14 Example of Toggle Output Operation ...................................................................220

Figure 13.15 Output Compare Timing........................................................................................221

Figure 13.16 Example of Input Capture Operation Setting Procedure ....................................... 222

Figure 13.17 Example of Input Capture Operation.....................................................................223

Figure 13.18 Input Capture Signal Timing................................................................................. 224

Figure 13.19 Example of Synchronous Operation Setting Procedure ........................................225

Figure 13.20 Example of Synchronous Operation...................................................................... 226

Figure 13.21 Example of PWM Mode Setting Procedure ..........................................................227

Rev. 1.00 Sep. 16, 2005 Page xxi of xxx

Figure 13.22 Example of PWM Mode Operation (1)................................................................. 228

Figure 13.23 Example of PWM Mode Operation (2)................................................................. 229

Figure 13.24 Example of PWM Mode Operation (3)................................................................. 230

Figure 13.25 Example of PWM Mode Operation (4)................................................................. 231

Figure 13.26 Example of Reset Synchronous PWM Mode Setting Procedure........................... 233

Figure 13.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) ...... 234

Figure 13.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) ...... 235

Figure 13.29 Example of Complementary PWM Mode Setting Procedure................................237

Figure 13.30 Canceling Procedure of Complementary PWM Mode.......................................... 238

Figure 13.31 Example of Complementary PWM Mode Operation (1) ...................................... 239

Figure 13.32 (1) Example of Complementary PWM Mode Operation

(TPSC2 = TPSC1 = TPSC0 = 0) (2)......................................................................241

Figure 13.32 (2) Example of Complementary PWM Mode Operation

(TPSC2 = TPSC1 = TPSC0 ≠ 0) (3)......................................................................242

Figure 13.33 Timing of Overshooting........................................................................................ 243

Figure 13.34 Timing of Undershooting ...................................................................................... 243

Figure 13.35 Compare Match Buffer Operation......................................................................... 246

Figure 13.36 Input Capture Buffer Operation............................................................................. 247

Figure 13.37 Example of Buffer Operation Setting Procedure................................................... 247

Figure 13.38 Example of Buffer Operation (1)

(Buffer Operation for Output Compare Register).................................................. 248

Figure 13.39 Example of Compare Match Timing for Buffer Operation ................................... 249

Figure 13.40 Example of Buffer Operation (2)

(Buffer Operation for Input Capture Register) ...................................................... 250

Figure 13.41 Input Capture Timing of Buffer Operation............................................................ 251

Figure 13.42 Buffer Operation (3)

(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............ 252

Figure 13.43 Buffer Operation (4)

(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............ 253

Figure 13.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 254

Figure 13.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 255

Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 256

Figure 13.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 256

Figure 13.48 IMF Flag Set Timing when Compare Match Occurs ............................................257

Figure 13.49 IMF Flag Set Timing at Input Capture.................................................................. 258

Figure 13.50 OVF Flag Set Timing............................................................................................ 258

Figure 13.51 Status Flag Clearing Timing.................................................................................. 259

Figure 13.52 Contention between TCNT Write and Clear Operations....................................... 260

Figure 13.53 Contention between TCNT Write and Increment Operations............................... 261

Figure 13.54 Contention between GR Write and Compare Match............................................. 261

Rev. 1.00 Sep. 16, 2005 Page xxii of xxx

Figure 13.55 Contention between TCNT Write and Overflow...................................................262

Figure 13.56 Contention between GR Read and Input Capture..................................................263

Figure 13.57 Contention between Count Clearing and Increment Operations

by Input Capture.................................................................................................... 264

Figure 13.58 Contention between GR Write and Input Capture................................................. 265

Figure 13.59 When Compare Match and Bit Manipulation Instruction to TOCR

Occur at the Same Timing..................................................................................... 266

Section 14 Watchdog Timer

Figure 14.1 Block Diagram of Watchdog Timer........................................................................ 267

Figure 14.2 Watchdog Timer Operation Example...................................................................... 271

Section 15 14-Bit PWM

Figure 15.1 Block Diagram of 14-Bit PWM ..............................................................................273

Figure 15.2 Waveform Output by 14-Bit PWM ......................................................................... 276

Section 16 Serial Communication Interface 3 (SCI3)

Figure 16.1 Block Diagram of SCI3........................................................................................... 279

Figure 16.2 Data Format in Asynchronous Communication ...................................................... 295

Figure 16.3 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) .............295

Figure 16.4 Sample SCI3 Initialization Flowchart .....................................................................296

Figure 16.5 Example of SCI3 Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ...........................................................................297

Figure 16.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 298

Figure 16.7 Example of SCI3 Reception in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ...........................................................................299

Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)......................301

Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)......................302

Figure 16.9 Data Format in Clock Synchronous Communication.............................................. 303

Figure 16.10 Example of SCI3 Transmission in Clock Synchronous Mode .............................. 304

Figure 16.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode).................... 305

Figure 16.12 Example of SCI3 Reception in Clock Synchronous Mode.................................... 306

Figure 16.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) ......................... 307

Figure 16.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

(Clock Synchronous Mode)................................................................................... 309

Figure 16.15 Example of Inter-Processor Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)...........................................311

Figure 16.16 Sample Multiprocessor Serial Transmission Flowchart........................................ 312

Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 314

Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 315

Rev. 1.00 Sep. 16, 2005 Page xxiii of xxx

Figure 16.18 Example of SCI3 Reception Using Multiprocessor Format

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 316

Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 319

Section 17 I2C Bus Interface 2 (IIC2) Figure 17.1 Block Diagram of I

C Bus Interface 2..................................................................... 322

Figure 17.2 External Circuit Connections of I/O Pins................................................................ 323

Figure 17.3 I2C Bus Formats ...................................................................................................... 337

Figure 17.4 I2C Bus Timing........................................................................................................ 337

Figure 17.5 Master Transmit Mode Operation Timing (1)......................................................... 339

Figure 17.6 Master Transmit Mode Operation Timing (2)......................................................... 339

Figure 17.7 Master Receive Mode Operation Timing (1) .......................................................... 341

Figure 17.8 Master Receive Mode Operation Timing (2) .......................................................... 342

Figure 17.9 Slave Transmit Mode Operation Timing (1)........................................................... 343

Figure 17.10 Slave Transmit Mode Operation Timing (2)......................................................... 344

Figure 17.11 Slave Receive Mode Operation Timing (1)........................................................... 345

Figure 17.12 Slave Receive Mode Operation Timing (2)........................................................... 345

Figure 17.13 Clock Synchronous Serial Transfer Format .......................................................... 346

Figure 17.14 Transmit Mode Operation Timing.........................................................................347

Figure 17.15 Receive Mode Operation Timing .......................................................................... 348

Figure 17.16 Block Diagram of Noise Filter .............................................................................. 349

Figure 17.17 Sample Flowchart for Master Transmit Mode ......................................................350

Figure 17.18 Sample Flowchart for Master Receive Mode........................................................ 351

Figure 17.19 Sample Flowchart for Slave Transmit Mode......................................................... 352

Figure 17.20 Sample Flowchart for Slave Receive Mode .......................................................... 353

Figure 17.21 The Timing of the Bit Synchronous Circuit.......................................................... 355

Section 18 A/D Converter

Figure 18.1 Block Diagram of A/D Converter ........................................................................... 358

Figure 18.2 A/D Conversion Timing.......................................................................................... 364

Figure 18.3 External Trigger Input Timing ................................................................................ 365

Figure 18.4 A/D Conversion Accuracy Definitions (1).............................................................. 367

Figure 18.5 A/D Conversion Accuracy Definitions (2).............................................................. 367

Figure 18.6 Analog Input Circuit Example ................................................................................ 368

Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Figure 19.1 Block Diagram around BGR ................................................................................... 370

Figure 19.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit....371

Figure 19.3 Operational Timing of Power-On Reset Circuit...................................................... 377

Figure 19.4 Operating Timing of LVDR Circuit........................................................................ 378

Figure 19.5 Operational Timing of LVDI Circuit ......................................................................379

Rev. 1.00 Sep. 16, 2005 Page xxiv of xxx

Figure 19.6 Operational Timing of LVDI Circuit

(When Compared Voltage is Input through ExtU and ExtD Pins).......................... 381

Figure 19.7 Timing of Setting Bits in Reset Source Decision Register...................................... 382

Section 20 Power Supply Circuit

Figure 20.1 Power Supply Connection when Internal Step-Down Circuit is Used ....................383

Section 22 Electrical Characteristics

Figure 22.1 System Clock Input Timing.....................................................................................425

Figure 22.2 RES Low Width Timing.......................................................................................... 425

Figure 22.3 Input Timing............................................................................................................ 425

Figure 22.4 I2C Bus Interface Input/Output Timing................................................................... 426

Figure 22.5 SCK3 Input Clock Timing.......................................................................................426

Figure 22.6 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 427

Figure 22.7 Output Load Circuit................................................................................................. 427

Appendix

Figure B.1 Port 1 Block Diagram (P17) .....................................................................................459

Figure B.2 Port 1 Block Diagram (P14, P16)............................................................................. 460

Figure B.3 Port 1 Block Diagram (P15) .....................................................................................461

Figure B.4 Port 1 Block Diagram (P12) .....................................................................................462

Figure B.5 Port 2 Block Diagram (P11) .....................................................................................463

Figure B.6 Port 1 Block Diagram (P10) .....................................................................................464

Figure B.7 Port 2 Block Diagram (P24, P23)............................................................................. 465

Figure B.8 Port 2 Block Diagram (P22) .....................................................................................466

Figure B.9 Port 2 Block Diagram (P21) .....................................................................................467

Figure B.10 Port 2 Block Diagram (P20) ...................................................................................468

Figure B.11 Port 3 Block Diagram (P37 to P30) ........................................................................ 469

Figure B.12 Port 5 Block Diagram (P57, P56) ...........................................................................470

Figure B.13 Port 5 Block Diagram (P55) ...................................................................................471

Figure B.14 Port 5 Block Diagram (P54 to P50) ........................................................................ 472

Figure B.15 Port 6 Block Diagram (P67 to P60) ........................................................................ 473

Figure B.16 Port 7 Block Diagram (P76) ...................................................................................474

Figure B.17 Port 7 Block Diagram (P75) ...................................................................................475

Figure B.18 Port 7 Block Diagram (P74) ...................................................................................476

Figure B.19 Port 7 Block Diagram (P72) ...................................................................................477

Figure B.20 Port 7 Block Diagram (P71) ...................................................................................478

Figure B.21 Port 7 Block Diagram (P70) ...................................................................................478

Figure B.22 Port 8 Block Diagram (P87 to P85) ........................................................................ 479

Figure B.23 Port B Block Diagram (PB7 and PB6) ................................................................... 480

Figure B.24 Port B Block Diagram (PB5 to PB0)...................................................................... 480

Figure B.25 Port B Block Diagram (PC1).................................................................................. 481

Rev. 1.00 Sep. 16, 2005 Page xxv of xxx

Figure B.26 Port B Block Diagram (PC0).................................................................................. 482

Figure D.1 FP-64K Package Dimensions................................................................................... 485

Figure D.2 FP-64A Package Dimensions................................................................................... 486

Rev. 1.00 Sep. 16, 2005 Page xxvi of xxx

Tables

Section 1 Overview

Table 1.1

Section 2 CPU Table 2.1

Table 2.2 Data Transfer Instructions.......................................................................................19

Table 2.3 Arithmetic Operations Instructions (1) ...................................................................20

Table 2.3 Arithmetic Operations Instructions (2) ...................................................................21

Table 2.4 Logic Operations Instructions................................................................................. 22

Table 2.5 Shift Instructions.....................................................................................................22

Table 2.6 Bit Manipulation Instructions (1)............................................................................ 23

Table 2.6 Bit Manipulation Instructions (2)............................................................................ 24

Table 2.7 Branch Instructions................................................................................................. 25

Table 2.8 System Control Instructions.................................................................................... 26

Table 2.9 Block Data Transfer Instructions ............................................................................ 27

Table 2.10 Addressing Modes .................................................................................................. 29

Table 2.11 Absolute Address Access Ranges........................................................................... 31

Table 2.12 Effective Address Calculation (1)........................................................................... 32

Table 2.12 Effective Address Calculation (2)........................................................................... 33

Section 3 Exception Handling Table 3.1

Table 3.2 Interrupt Wait States ...............................................................................................57

Pin Functions ............................................................................................................ 5

Operation Notation ................................................................................................. 18

Exception Sources and Vector Address .................................................................. 44

Section 4 Address Break Table 4.1

Section 5 Clock Pulse Generator Table 5.1

Section 6 Power-Down Modes Table 6.1 Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode

Table 6.3 Internal State in Each Operating Mode................................................................... 98

Section 7 ROM Table 7.1

Table 7.2 Boot Mode Operation ...........................................................................................111

Access and Data Bus Used .....................................................................................63

Crystal Resonator Parameters.................................................................................84

Operating Frequency and Waiting Time................................................................. 92

due to Interrupt........................................................................................................97

Setting Programming Modes ................................................................................109

Rev. 1.00 Sep. 16, 2005 Page xxvii of xxx

Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate

is Possible ............................................................................................................. 112

Table 7.4 Reprogram Data Computation Table .................................................................... 115

Table 7.5 Additional-Program Data Computation Table...................................................... 115

Table 7.6 Programming Time............................................................................................... 115

Table 7.7 Flash Memory Operating States............................................................................ 120

Section 10 Realtime Clock (RTC) Table 10.1

Table 10.2 Interrupt Sources................................................................................................... 170

Section 11 Timer B1 Table 11.1

Table 11.2 Timer B1 Operating Modes.................................................................................. 175

Section 12 Timer V Table 12.1

Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 181

Section 13 Timer Z Table 13.1

Table 13.2 Pin Configuration.................................................................................................. 196

Table 13.3 Initial Output Level of FTIOB0 Pin...................................................................... 227

Table 13.4 Output Pins in Reset Synchronous PWM Mode................................................... 232

Table 13.5 Register Settings in Reset Synchronous PWM Mode........................................... 232

Table 13.6 Output Pins in Complementary PWM Mode........................................................ 236

Table 13.7 Register Settings in Complementary PWM Mode................................................ 236

Table 13.8 Register Combinations in Buffer Operation ......................................................... 246

Pin Configuration.................................................................................................. 160

Pin Configuration.................................................................................................. 172

Pin Configuration.................................................................................................. 179

Timer Z Functions ................................................................................................192

Section 15 14-Bit PWM Table 15.1

Section 16 Serial Communication Interface 3 (SCI3) Table 16.1

Table 16.2 Pin Configuration.................................................................................................. 280

Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 289

Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 290

Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 291

Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................292

Table 16.5 Examples of BRR Settings for Various Bit Rates

Rev. 1.00 Sep. 16, 2005 Page xxviii of xxx

Pin Configuration.................................................................................................. 274

Channel Configuration.......................................................................................... 278

(Clock Synchronous Mode) (1) ............................................................................293

(Clock Synchronous Mode) (2) ............................................................................294

Table 16.6 SSR Status Flags and Receive Data Handling...................................................... 300

Table 16.7 SCI3 Interrupt Requests........................................................................................ 317

Section 17 I2C Bus Interface 2 (IIC2) Table 17.1

Table 17.2 Transfer Rate ........................................................................................................326

Table 17.3 Interrupt Requests................................................................................................. 354

Table 17.4 Time for Monitoring SCL..................................................................................... 355

Section 18 A/D Converter Table 18.1

Table 18.2 Analog Input Channels and Corresponding ADDR Registers.............................. 360

Table 18.3 A/D Conversion Time (Single Mode)................................................................... 365

Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Table 19.1

Table 19.2 Deciding Reset Source.......................................................................................... 382

Section 22 Electrical Characteristics Table 22.1

Table 22.2 DC Characteristics (1)...........................................................................................409

Table 22.2 DC Characteristics (2)...........................................................................................414

Table 22.3 AC Characteristics ................................................................................................415

Table 22.4 I2C Bus Interface Timing...................................................................................... 417

Table 22.5 Serial Communication Interface (SCI) Timing..................................................... 418

Table 22.6 A/D Converter Characteristics.............................................................................. 419

Table 22.7 Watchdog Timer Characteristics........................................................................... 420

Table 22.8 Flash Memory Characteristics ..............................................................................421

Table 22.9 Power-Supply-Voltage Detection Circuit Characteristics.....................................423

Table 22.10 LVDI External Input Voltage Detection Circuit Characteristics ......................423

Table 22.11 Power-On Reset Circuit Characteristics............................................................ 424

C Bus Interface Pins........................................................................................... 323

Pin Configuration.................................................................................................. 359

LVDCR Settings and Select Functions................................................................. 373

Absolute Maximum Ratings .................................................................................405

Appendix Table A.1

Table A.2 Operation Code Map (1) ....................................................................................... 444

Table A.2 Operation Code Map (2) ....................................................................................... 445

Table A.2 Operation Code Map (3) ....................................................................................... 446

Table A.3 Number of Cycles in Each Instruction.................................................................. 448

Table A.4 Number of Cycles in Each Instruction.................................................................. 449

Table A.5 Combinations of Instructions and Addressing Modes ..........................................458

Instruction Set....................................................................................................... 431

Rev. 1.00 Sep. 16, 2005 Page xxix of xxx

Rev. 1.00 Sep. 16, 2005 Page xxx of xxx

Section 1 Overview

1.1 Features

• High-speed H8/300H CPU with an in ternal 16-bit architecture  Upward-compatible with H8/300 CPU at the object level  Si xteen 1 6- bi t gene ral re gi st ers  62 basic instructions

• Various peripheral functions  RTC (can be used as a free running counter)  Timer B1 (8-bit timer)  Timer V (8-bit timer)  Timer Z (16-bit timer)  14-bit PWM  Watchdog timer  SCI (asynchronous or clock synchronous serial communication interface) × 2 channels

 I

C bus interface (conforms to the I2C bus interface format that is advocated by Philips

Electronics)

 10-bit A/D converter  POR/LVD (power-on reset & low-voltage detection circuit)  On-chip oscillator

Rev. 1.00 Sep. 16, 2005 Page 1 of 490

REJ09B0216-0100

Section 1 Overview

• On-chip memory

Product Classification Model ROM RAM Remarks

(F-ZTATTM version)

H8/36077F HD64F36077G 56 kbytes 4 kbytes Flash memory version

H8/36074F HD64F36074G 32 kbytes 4 kbytes

Power-on reset & low-voltage detection circuit included

• General I/O ports  I/O pins: 47 I/O pins, including 8 large current ports (I

= 20 mA, @VOL = 1.5 V)

 Input-only pins: 8 input pins (also used for analog input)

• I

C bus interface (conforms to the I2C bus interface format that is advocated by Philips

Electronics)

• Supports various power-down modes

Note: F-ZTATTM is a trademark of Renesas Technology Corp.

• Compact package

Package Code Body Size Pin Pitch

LQFP-64 FP-64K 10.0 QFP-64 FP-64A 14.0 × 14.0 mm 0.8 mm

× 10.0 mm 0.5 mm

Rev. 1.00 Sep. 16, 2005 Page 2 of 490

REJ09B0216-0100

1.2 Block Diagram

(OSC1)

(OSC2)

Section 1 Overview

VCC

VSS

RES

TEST

NMI

P10/TMOW

P11/PWM

P12

P14/IRQ0

P15/IRQ1/TMIB1

P16/IRQ2

P17/IRQ3/TRGV

P20/SCK3

P21/RXD P22/TXD

P23 P24

P30 P31 P32 P33 P34 P35 P36 P37

P57/SCL P56/SDA

P55/WKP5/ADTRG

P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0

Subclock oscillator

Port 3Port 5 Port 2 Port 1

External

clock

oscillator

On-chip

oscillator

Data bus (lower)

ROM

RTC

14-bit PWM

Timer Z

Timer V

A/D converter

Data bus (upper)

CPU

H8/300H

POR&LVD

Address bus

RAM

IIC2

SCI3

SCI3_2

Watchdog

timer

Timer B1

Port 6Port 7Port 8

P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0

P76/TMOV P75/TMCIV P74/TMRIV P72/TXD_2 P71/RXD_2 P70/SCK3_2

P87 P86 P85

PB0/AN0

PB1/AN1

Port B

PB2/AN2

PB3/AN3

PB4/AN4

PB5/AN5

PB6/AN6/ExtD

PB7/AN7/ExtU

Port C

PC0/OSC1

PC1/OSC2/CLKOUT

Figure 1.1 Block Diagram of H8/36077 Group

Rev. 1.00 Sep. 16, 2005 Page 3 of 490

REJ09B0216-0100

Section 1 Overview

1.3 Pin Arrangement

P70/SCK3_2

P23

P22/TXD

P21/RXD

P20/SCK3

P87

P86

P85

P67/FTIOD1

P66/FTIOC1

P65/FTIOB1

P64/FTIOA1

P60/FTIOA0

NMI

P61/FTIOB0

P62/FTIOC0

P71/RXD_2

P72/TXD_2

P14/IRQ0

P15/IRQ1/TMIB1

P16/IRQ2

P17/IRQ3/TRGV

P33

P32

P31

P30

PB3/AN3

PB2/AN2

PB1/AN1

PB0/AN0

PB4/AN4

PB5/AN5

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1 2 3 4 5 6 7 8 9 10111213141516

AVcc

PB6/AN6/ExtD

PB7/AN7/ExtU

H8/36077 Group

Top View

RES

TEST

Vss

Vcc

P50/WKP0

PC0/OSC1

PC1/OSC2/CLKOUT

P34

P51/WKP1

P35

P63/FTIOD0

P24

P76/TMOV

P75/TMCIV

P74/TMRIV

P57/SCL

P56/SDA

P12

P11/PWM

P10/TMOW P55/WKP5/ADTR P54/WKP4 P53/WKP3 P52/WKP2

P37

P36

Figure 1.2 Pin Arrangements of H8/36077 Group

(FP-64K, FP-64A)

Rev. 1.00 Sep. 16, 2005 Page 4 of 490

REJ09B0216-0100

Section 1 Overview

1.4 Pin Functions

Table 1.1 Pin Functions

Pin No.

Type

Power source pins

AVCC 3 Input Analog power supply pin for the A/D converter.

Clock pins OSC1 11 Input

OSC2/

X1 5 Input

X2 4 Output

System control

TEST 8 Input Test pin. Connect this pin to Vss.

Interrupt pins

IRQ0 to

WKP0 to

RTC TMOW 23 Output This is an output pin for a divided clock.

Timer B1 TMIB1 52 Input External event input pin

Symbol

FP-64K FP-64A

I/O

Functions

VCC 12 Input Power supply pin. Connect this pin to the

system power supply.

9 Input Ground pin. Connect this pin to the system

power supply (0V).

When the A/D converter is not used, connect this pin to the system power supply.

6 Input Internal step-down power supply pin. Connect a

capacitor of around 0.1 µF between this pin and the Vss pin for stabilization.

These pins connect with crystal or ceramic

10 Output

CLKOUT

resonator for the system clock, or can be used to input an external clock. When the on-chip oscillator is used, the system clock can be output on OSC2 pin.

See section 5, Clock Pulse Generator, for a typical connection.

These pins connect with a 32.768 kHz crystal resonator for the subclock. See section 5, Clock Pulse Generator, for a typical connection.

RES 7 Input Reset pin. The pull-up resistor (typ. 150 kΩ) is

incorporated. When driven low, this LSI is reset.

NMI 35 Input Non-maskable interrupt request input pin. Be

sure to pull up by a resistor.

51 to 54 Input External interrupt request input pins. Can select

IRQ3

WKP5

13, 14, 19 to 22

Input External interrupt request input pins. Can select

the rising or falling edge.

Rev. 1.00 Sep. 16, 2005 Page 5 of 490

REJ09B0216-0100

Section 1 Overview

Pin No.

Type

Symbol

FP-64K FP-64A I/O

Functions

Timer V TMOV 30 Output This is an output pin for a waveform generated

by the output compare function.

TMCIV 29 Input External event input pin

TMRIV 28 Input Counter reset input pin

TRGV 54 Input Counter start trigger input pin

Timer Z FTIOA0 36 I/O Output compare output/input capture

input/external clock input pin

FTIOB0 34 I/O Output compare output/input capture

input/PWM output pin

FTIOC0 33 I/O Output compare output/input capture

input/PWM sync output pin (at a reset, complementary PWM mode)

FTIOD0 32 I/O Output compare output/input capture

input/PWM output pin

FTIOA1 37 I/O Output compare output/input capture

input/PWM output pin (at a reset, complementary PWM mode)

FTIOB1 to

FTIOD1

38 to 40 I/O Output compare output/input capture

input/PWM output pin

14-bit PWM PWM 24 Output 14-bit PWM square wave output pin

I2C bus interface 2 (IIC2)

SDA 26 I/O I2C data I/O pin. Can directly drive a bus by

NMOS open-drain output. When using this pin, external pull-up resistor is required.

SCL 27 I/O I2C clock I/O pin. Can directly drive a bus by

NMOS open-drain output. When using this pin, external pull-up resistor is required.

TXD, munication interface 3 (SCI3)

TXD_2

RXD,

RXD_2

SCK3,

46, 50 Output Transmit data output pin Serial com-

45, 49 Input Receive data input pin

44, 48 I/O Clock I/O pin

SCK3_2

Rev. 1.00 Sep. 16, 2005 Page 6 of 490

REJ09B0216-0100

Section 1 Overview

Pin No.

Type

A/D converter

Symbol

FP-64K FP-64A I/O

AN7 to AN0 2, 1

64, 63

Functions

Input Analog input pin

59 to 62

ADTRG 22 Input A/D conversion start trigger input pin

I/O ports PB7 to PB0 2, 1

Input 8-bit input port 64, 63 59 to 62

PC1, PC0 10, 11 I/O 2-bit I/O port

P17 to P14,

P12 to P10

54 to 51, 25 to 23

I/O 7-bit I/O port

P24 to P20 31, 47 to 44 I/O 5-bit I/O port

P37 to P30 18 to 15,

I/O 8-bit I/O port 55 to 58

P57 to P50 27, 26

I/O 8-bit I/O port 22 to 19 14, 13

P67 to P60 40 to 37

I/O 8-bit I/O port 32 to 34, 36

P76 to P74,

P72 to P70

30 to 28, 50 to 48

I/O 6-bit I/O port

P87 to P85 43 to 41 I/O 3-bit I/O port

Low-voltage detection circuit

ExtU

ExtD

Input This pin is used to externally input the

detection voltage for the low-voltage detection circuit.

Rev. 1.00 Sep. 16, 2005 Page 7 of 490

REJ09B0216-0100

Section 1 Overview

Rev. 1.00 Sep. 16, 2005 Page 8 of 490

REJ09B0216-0100

Section 2 CPU

This LSI has an H8/300H CPU with an internal 32-bit architecture that is upw ard -compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space.

• Upward-compatible with H8/300 CPUs  Can execute H8/300 CPUs object programs  Additional eight 16-bit extended registers  32-bit transfer and arithmetic and logic instructions are added  Signed multiply and divide instructions are added.

• General-register architecture  Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit

registers, or eight 32-bit registers

• Sixty-two basic instructions  8/16/32-bit data transfer and arithmetic and logic instructions  Multiply and divide instructions  Powerful bit-manipulation instructions

• Eight addressing modes  Register direct [Rn]  Register indirect [@ERn]  R egi st er in di rect with displacement [@(d:16,ERn) or @( d:24,ERn)]  Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]  Absolute address [@aa:8, @aa:16, @aa:24]  Immediate [#xx:8, #xx:16, or #xx:32]  Pr ogram-counter relative [@(d:8,PC) or @(d:16,PC)]  Memory indirect [@@aa:8]

• 64-kbyte address space

• High-speed operation  All frequently-used instructions execute in one or two states  8/16/32-bit register-register add/subtract : 2 state  8 × 8-bit register-register multiply : 14 states  16 ÷ 8-bit register-register divide : 14 states  16 × 16-bit register-register multiply : 22 states  32 ÷ 16-bit register-register divide : 22 states

CPU30H2C_000120030300 Rev. 1.00 Sep. 16, 2005 Page 9 of 490

REJ09B0216-0100

Section 2 CPU

• Power-down state  Transition to power-down state by SLEEP instruction

2.1 Address Space and Memory Map

The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map.

HD64F36077G

(Flash memory version)

H'0000 H'0041 H'0042

H'DFFF

H'E800

H'EFFF

H'F700

Internal I/O register

H'F77F H'F780

(1 kbyte work area

for flash memory

H'FB7F H'FB80

(1 kbyte user area)

H'FF7F H'FF80

Internal I/O register

H'FFFF

Interrupt vector

On-chip ROM

(56 kbytes)

Not used

On-chip RAM

(2 kbytes)

Not used

programming)

On-chip RAM

(2 kbytes)

HD64F36074G

(Flash memory version)

H'0000 H'0041 H'0042

H'7FFF

H'E800

H'EFFF

H'F700 H'F77F H'F780

H'FB7F H'FB80

H'FF7F H'FF80

H'FFFF

Interrupt vector

Internal I/O register

(1 kbyte work area

for flash memory

(1 kbyte user area)

Internal I/O register

On-chip ROM

(32 kbytes)

Not used

On-chip RAM

(2 kbytes)

Not used

programming)

On-chip RAM

(2 kbytes)

Figure 2.1 Memory Map

Rev. 1.00 Sep. 16, 2005 Page 10 of 490

REJ09B0216-0100

Section 2 CPU

2.2 Register Configuration

The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).

General Registers (ERn)

15 0 7 0 7 0

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7

(SP)

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

Control Registers (CR)

[Legend]

SP:

Stack pointer

PC:

Program counter

CCR:

Condition-code register

Interrupt mask bit

UI:

User bit

23 0

76543210

CCR

IUIHUNZVC

Half-carry flag

User bit

Negative flag

Zero flag

Overflow flag

Carry flag

Figure 2.2 CPU Registers

Rev. 1.00 Sep. 16, 2005 Page 11 of 490

REJ09B0216-0100

Section 2 CPU

2.2.1 General Registers

The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers.

The usage of each register can be selected independently.

• Address registers

• 32-bit registers

ER registers

(ER0 to ER7)

• 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers (R0L to R7L)

Figure 2.3 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between the stack pointer and the stack area.

Rev. 1.00 Sep. 16, 2005 Page 12 of 490

REJ09B0216-0100

Section 2 CPU

Empty area

SP (ER7)

Stack area

Figure 2.4 Relationship between Stack Pointer and Stack Area

2.2.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence.

2.2.3 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized.

Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.

For the action of each instruction on the flag bits, see appendix A.1, Instruction List.

Rev. 1.00 Sep. 16, 2005 Page 13 of 490

REJ09B0216-0100

Section 2 CPU

Initial

Bit Bit Name

Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.

6 UI Undefined R/W User Bit

Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.

5 H Undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.

4 U Undefined R/W User Bit

Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit of data as a sign bit.

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to indicate a carry

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Rev. 1.00 Sep. 16, 2005 Page 14 of 490

REJ09B0216-0100

Section 2 CPU

2.3 Data Formats

The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instruct i o ns treat byte dat a as two digits of 4-bit BCD data.

2.3.1 General Register Data Formats

Figure 2.5 shows the data formats in general registers.

Data Type General Register Data Format

6543271

Don't care

1-bit data

RnH

1-bit data

4-bit BCD data

Byte data

RnL

RnH

RnL

RnH

RnL

Don't care

7 04 3

Upper Lower

Don't care

7 0

MSB LSB

Don't care

65432710

Don't care

704 3

Upper Lower

MSB LSB

Figure 2.5 General Register Data Formats (1)

Don't care

Rev. 1.00 Sep. 16, 2005 Page 15 of 490

REJ09B0216-0100

Section 2 CPU

Data Type Data FormatGeneral

Word data

Word dataRnEn

Longword

ERn

data

[Legend]

ERn:

General register ER

En:

General register E

Rn:

General register R

RnH:

General register RH

RnL:

General register RL

MSB:

Most significant bit

LSB:

Least significant bit

15 0

MSB LSB

15 0

MSB LSB

31 16

MSB

15 0

Figure 2.5 General Register Data Formats (2)

LSB

Rev. 1.00 Sep. 16, 2005 Page 16 of 490

REJ09B0216-0100

Section 2 CPU

2.3.2 Memory Data Formats

Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.

When ER7 (SP) is used as an address register to access the stack area, the operand size should be word or longword.

Data Type Address

1-bit data

Byte data

Word data

Longword data Address 2N

Address L

Address 2M

Address 2M+1

Address 2N+1

Address 2N+2

Address 2N+3

Figure 2.6 Memory Data Formats

Data Format

76 543210

MSB

LSB

Rev. 1.00 Sep. 16, 2005 Page 17 of 490

REJ09B0216-0100

Section 2 CPU

2.4 Instruction Set

2.4.1 Table of Instructions Classified by Function

The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below.

Table 2.1 Operation Notation

Symbol Description

Rd General register (destination)* Rs General register (source)* Rn General register*

ERn General register (32-bit register or address register)

(EAd) Destination operand

(EAs) Source operand

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

– Subtraction

× Multiplication

÷ Division

∧ Logical AND

∨ Logical OR

⊕ Logical XOR

→ Move

∼ NOT (logical complement)

:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length

Rev. 1.00 Sep. 16, 2005 Page 18 of 490

REJ09B0216-0100

Section 2 CPU

Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).

Table 2.2 Data Transfer Instructions

Instruction Size* Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.

MOVFPE B (EAs) → Rd

Cannot be used in this LSI.

MOVTPE B Rs → (EAs)

Cannot be used in this LSI.

POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.

Note: * Refers to the operand size. B: Byte W: Word L: Longword

Rev. 1.00 Sep. 16, 2005 Page 19 of 490

REJ09B0216-0100

Section 2 CPU

Table 2.3 Arithmetic Operations Instructions (1)

Instruction Size* Function

ADD SUB

ADDX SUBX

INC DEC

ADDS SUBS

DAA DAS

MULXU B/W Rd × Rs → Rd

MULXS B/W Rd × Rs → Rd

DIVXU B/W Rd ÷ Rs → Rd

Note: * Refers to the operand size. B: Byte W: Word L: Longword

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.)

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register.

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.)

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

B Rd (decimal adjust) → Rd

Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data.

Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

Rev. 1.00 Sep. 16, 2005 Page 20 of 490

REJ09B0216-0100

Table 2.3 Arithmetic Operations Instructions (2)

Instruction Size* Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of data in a general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.

Note: * Refers to the operand size. B: Byte W: Word L: Longword

Section 2 CPU

Rev. 1.00 Sep. 16, 2005 Page 21 of 490

REJ09B0216-0100

Section 2 CPU

Table 2.4 Logic Operations Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and another general register or immediate data.

NOT B/W/L ∼(Rd) → (Rd)

Takes the one's complement (logical complement) of general register contents.

Note: * Refers to the operand size. B: Byte W: Word L: Longword

Table 2.5 Shift Instructions

Instruction Size* Function

SHAL SHAR

SHLL SHLR

ROTL ROTR

ROTXL ROTXR

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

B/W/L Rd (rotate) → Rd

Rotates general register contents.

B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag.

Note: * Refers to the operand size. B: Byte W: Word L: Longword

Rev. 1.00 Sep. 16, 2005 Page 22 of 490

REJ09B0216-0100

Table 2.6 Bit Manipulation Instructions (1)

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BNOT B ∼(<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BTST B ∼(<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BAND

BIAND

BOR

BIOR

Note: * Refers to the operand size. B: Byte

C ∧ (<bit-No.> of <EAd>) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

C ∧ ¬ (<bit-No.> of <EAd>) → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

C ∨ ∼(<bit-No.> of <EAd>) → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

Section 2 CPU

Rev. 1.00 Sep. 16, 2005 Page 23 of 490

REJ09B0216-0100

Section 2 CPU

Table 2.6 Bit Manipulation Instructions (2)

Instruction Size* Function

BXOR

BIXOR

BLD

BILD

BST

BIST

Note: * Refers to the operand size. B: Byte

C ⊕ (<bit-No.> of <EAd>) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

C ⊕ ∼(<bit-No.> of <EAd>) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

(<bit-No.> of <EAd>) → C Transfers a specified bit in a general register or memory operand to the carry flag.

∼(<bit-No.> of <EAd>) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data.

C → (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand.

∼C → (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.

Rev. 1.00 Sep. 16, 2005 Page 24 of 490

REJ09B0216-0100

Section 2 CPU

Table 2.7 Branch Instructions

Instruction Size Function

Bcc*  Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA(BT) Always (true) Always

BRN(BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC(BHS) Carry clear

(high or same)

BCS(BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z∨(N ⊕ V) = 0

BLE Less or equal Z∨(N ⊕ V) = 1

JMP  Branches unconditionally to a specified address.

BSR  Branches to a subroutine at a specified address.

JSR  Branches to a subroutine at a specified address.

RTS  Returns from a subroutine

Note: * Bcc is the general name for conditional branch instructions.

C = 0

Rev. 1.00 Sep. 16, 2005 Page 25 of 490

REJ09B0216-0100

Section 2 CPU

Table 2.8 System Control Instructions

Instruction Size* Function

TRAPA  Starts trap-instruction exception handling.

RTE  Returns from an exception-handling routine.

SLEEP  Causes a transition to a power-down state.

LDC B/W (EAs) → CCR

Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access.

STC B/W CCR → (EAd)

Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access.

ANDC B CCR ∧ #IMM → CCR

Logically ANDs the CCR with immediate data.

ORC B CCR ∨ #IMM → CCR

Logically ORs the CCR with immediate data.

XORC B CCR ⊕ #IMM → CCR

Logically XORs the CCR with immediate data.

NOP  PC + 2 → PC

Only increments the program counter.

Note: * Refers to the operand size. B: Byte W: Word

Rev. 1.00 Sep. 16, 2005 Page 26 of 490

REJ09B0216-0100

Table 2.9 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B  if R4L ≠ 0 then

Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next;

EEPMOV.W  if R4 ≠ 0 then

Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next;

Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6.

Execution of the next instruction begins as soon as the transfer is completed.

Section 2 CPU

Rev. 1.00 Sep. 16, 2005 Page 27 of 490

REJ09B0216-0100

Section 2 CPU

2.4.2 Basic Instruction Formats

H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc).

Figure 2.7 shows examples of instruction formats.

• Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried

out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields.

• Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3

bits or 4 bits. Some instructions have two regist er fiel ds. Some have no register field.

• Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit

address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).

• Condition Field Specifies the branching condition of Bcc instructions.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

EA(disp)

(4) Operation field, effective address extension, and condition field

op cc EA(disp) BRA d:8

rn rm

Figure 2.7 Instruction Formats

Rev. 1.00 Sep. 16, 2005 Page 28 of 490

REJ09B0216-0100

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm

Section 2 CPU

2.5 Addressing Modes and Effective Address Calculation

The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits.

2.5.1 Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used dif fer de pen din g on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes.

Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.10 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn)

4 Register indirect with post-increment

5 Absolute address @aa:8/@aa:16/@aa:24

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

@ERn+ @–ERn

The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

Rev. 1.00 Sep. 16, 2005 Page 29 of 490

REJ09B0216-0100

Section 2 CPU

The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory.

A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added.

• Register indirect with post-increment@ERn+

The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even.

• Register indirect with pre-decrement@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even.

Absolute Address@aa:8, @aa:16, @aa:24

The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bi t s long (@aa: 2 4 )

For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space.

The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11, because the upper 8 bits are ignored.

Rev. 1.00 Sep. 16, 2005 Page 30 of 490

REJ09B0216-0100

Section 2 CPU

Table 2.11 Absolute Address Access Ranges

Absolute Address Access Range

8 bits (@aa:8) H'FF00 to H'FFFF

16 bits (@aa:16) H'0000 to H'FFFF

24 bits (@aa:24) H'0000 to H'FFFF

Immediate#xx:8, #xx:16, or #xx:32

The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address.

Program-Counter Relative@(d:8, PC) or @(d:16, PC)

This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch in struction. The resulting value should be an even number.

Memory Indirect@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF).

Note that the first part of the address range is also the exception vector area.

Rev. 1.00 Sep. 16, 2005 Page 31 of 490

REJ09B0216-0100

Section 2 CPU

Specified

Dummy

by @aa:8

Branch address

Figure 2.8 Branch Address Specification in Memory Indirect Mode

2.5.2 Effective Address Calculation

Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.

Table 2.12 Effective Address Calculation (1)

Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

@(d:16,ERn) or @(d:24,ERn)

disp

General register contents

Sign extension

dis

Operand is general register contents.

pre-decrement

•Register indirect with post-increment @ERn+

•Register indirect with pre-decrement @-ERn

General register contents

1, 2, or 4

General register contents

1, 2, or 4

The value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.

Rev. 1.00 Sep. 16, 2005 Page 32 of 490

REJ09B0216-0100

Table 2.12 Effective Address Calculation (2)

Addressing Mode and Instruction Format

Absolute address

@aa:8

abs

Effective Address Calculation Effective Address (EA)

Section 2 CPU

H'FFFF

@aa:16

@aa:24

Immediate

#xx:8/#xx:16/#xx:32

[Legend] r, rm,rn : op : disp : IMM : abs :

rogram-counter relative

(d:8,PC) @(d:16,PC)

emory indirect @@aa:8

op8abs

abs

IMM

dis

Sign extension

Operand is immediate data.

PC contents

Sign

extension

H'0000

dis

Memory contents

abs

H'00

Rev. 1.00 Sep. 16, 2005 Page 33 of 490

REJ09B0216-0100

Section 2 CPU

2.6 Basic Bus Cycle

CPU operation is synchronized by a system clock (φ) or a subclock (φ edge of φ or φ

to the next rising edge is called one state. A bus cycle consists of two states or

SUB

). The period from a rising

SUB

three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.

2.6.1 Access to On-Chip Memory (RAM, ROM)

Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle.

Bus cycle

state

Read data

ø or ø

SUB

Internal address bus

Internal read signal

Internal data bus (read access)

Internal write signal

T1 state

Address

Internal data bus (write access)

Figure 2.9 On-Chip Memory Access Cycle

Rev. 1.00 Sep. 16, 2005 Page 34 of 490

REJ09B0216-0100

Write data

Section 2 CPU

2.6.2 On-Chip Peripheral Modules

On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 21.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by wor d size onl y. Regist ers wi t h 8- bi t data bus width can be accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the same as that for on-chip memory.

Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module.

Bus cycle

ø or ø

T1 state

SUB

T2 state T3 state

Internal address bus

Internal read signal

Internal data bus (read access)

Internal write signal

Internal data bus (write access)

Address

Read data

Write data

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)

Rev. 1.00 Sep. 16, 2005 Page 35 of 490

REJ09B0216-0100

Section 2 CPU

2.7 CPU States

There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes. For details on exception processing, refer to section 3, Exception Handling.

CPU state Reset state

The CPU is initialized

Program

execution state

Program halt state

A state in which some or all of the chip functions are stopped to conserve power

The CPU executes successive program instructions at high speed, synchronized by the system clock

The CPU executes successive program instructions at reduced speed, synchronized by the subclock

Active

(high speed) mode

Subactive mode

Sleep mode

Standby mode

Subsleep mode

Power-down

modes

Exception-

handling state

A transient state in which the CPU changes the processing flow due to a reset or an interrupt

Figure 2.11 CPU Operation States

Rev. 1.00 Sep. 16, 2005 Page 36 of 490

REJ09B0216-0100

Section 2 CPU

Reset state

Reset occurs

Program halt state

Reset cleared

Reset occurs

SLEEP instruction executed

Exception-handling state

Interrupt source

Program execution state

Exceptionhandling complete

Figure 2.12 State Transitions

2.8 Usage Notes

2.8.1 Notes on Data Access to Empty Areas

The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed.

2.8.2 EEPMOV Instruction

EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution).

2.8.3 Bit-Manipulation Instruction

The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, because this may rewrite data of a bit other than the bit to be manipulated.

Rev. 1.00 Sep. 16, 2005 Page 37 of 490

REJ09B0216-0100

Section 2 CPU

(1) Bit Manipulation for Two Registers Assigned to the Same Address

Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B1 in the H8/36077 Group.)

Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place.

1. Data is read in byte units.

2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction.

3. The written data is written again in byte units to the timer load register.

The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register.

Count clock Timer counter

Reload

Timer load register

Read

Write

Internal data bus

Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same

Address

Example 2: The BSET instruction is executed for port 5.

P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.

Rev. 1.00 Sep. 16, 2005 Page 38 of 490

REJ09B0216-0100

Section 2 CPU

• Prior to executing BSET instruction

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 0

High level

Low level

• BSET instruction executed instruction

BSET #0, @PDR5

The BSET instruction is executed for port 5.

• After executing BSET instruction

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 0 1 0 0 0 0 0 1

High level

Low level

High level

• Description on operation

1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level

input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40.

2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.

3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction. As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level

signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5.

Rev. 1.00 Sep. 16, 2005 Page 39 of 490

REJ09B0216-0100

Section 2 CPU

• Prior to executing BSET instruction

MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PDR5

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 0

RAM0 1 0 0 0 0 0 0 0

The PDR5 value (H'80) is written to a work area in

memory (RAM0) as well as to PDR5.

High level

Low level

• BSET instruction executed

BSET #0, @RAM0

The BSET instruction is executed designating the PDR5

work area (RAM0).

• After executing BSET instruction

MOV.B @RAM0, R0L

The work area (RAM0) value is written to PDR5.

MOV.B R0L, @PDR5

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 1

RAM0 1 0 0 0 0 0 0 1

High level

Low level

High level

Rev. 1.00 Sep. 16, 2005 Page 40 of 490

REJ09B0216-0100

Section 2 CPU

(2) Bit manipulation in a register containing a write-only bit

Example 3: BCLR instruction executed designating port 5 control register PCR5

P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin.

• Prior to executing BCLR instruction

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 0

High level

Low level

• BCLR instruction executed

BCLR #0, @PCR5

The BCLR instruction is executed for PCR5.

• After executing BCLR instruction

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Output Output Output Output Output Output Output Input

Pin state Low

level

PCR5 1 1 1 1 1 1 1 0

PDR5 1 0 0 0 0 0 0 0

High level

Low level

High level

• Description on operation

1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only register, the CPU reads a value of H'FF, even though the PC R 5 value is act ual ly H' 3F .

2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.

3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,

bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PDR5.

Rev. 1.00 Sep. 16, 2005 Page 41 of 490

REJ09B0216-0100

Section 2 CPU

• Prior to executing BCLR instruction

MOV.B #3F, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PCR5

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 1

PDR5 1 0 0 0 0 0 0 0

RAM0 0 0 1 1 1 1 1 1

The PCR5 value (H'3F) is written to a work area in

memory (RAM0) as well as to PCR5.

High level

Low level

• BCLR instruction executed

BCLR #0, @RAM0

The BCLR instructions executed for the PCR5 work area (RAM0).

• After executing BCLR instruction

MOV.B @RAM0, R0L

The work area (RAM0) value is written to PCR5.

MOV.B R0L, @PCR5

P57 P56 P55 P54 P53 P52 P51 P50

Input/output Input Input Output Output Output Output Output Output

Pin state Low

level

PCR5 0 0 1 1 1 1 1 0

PDR5 1 0 0 0 0 0 0 0

RAM0 0 0 1 1 1 1 1 0

High level

Low level

High level

Rev. 1.00 Sep. 16, 2005 Page 42 of 490

REJ09B0216-0100

Section 3 Exception Handling

Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.

• Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is

cleared by the RES pin. The chip is also reset when the watchdog timer overf lows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.

• Trap Instruction Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA

instruction generates a vector address corresponding to a vector number from 0 to 3, as specified in the instruction code. Exception handling can be executed at all times in the program execution state, regardless of the setting of the I bit in CCR.

• Interrupts External interrupts other than NMI and internal interrupts other than address break are masked

by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued.

Rev. 1.00 Sep. 16, 2005 Page 43 of 490

REJ09B0216-0100

Section 3 Exception Handling

3.1 Exception Sources and Vector Address

Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority.

Table 3.1 Exception Sources and Vector Address

Relative Module Exception Sources

RES pin Watchdog timer

 Reserved for system use 1 to 6 H'0002 to H'000D

External interrupt pin

CPU Trap instruction (#0) 8 H'0010 to H'0011

(#1) 9 H'0012 to H'0013

(#2) 10 H'0014 to H'0015

(#3) 11 H'0016 to H'0017

Address break Break conditions satisfied 12 H'0018 to H'0019

CPU Direct transition by executing

External interrupt pin

IRQ1 15 H'001E to H'001F

IRQ2 16 H'0020 to H'0021

IRQ3 17 H'0022 to H'0023

WKP 18 H'0024 to H'0025

RTC Overflow 19 H'0026 to H'0027

 Reserved for system use 20 H'0028 to H'0029

Timer V Timer V compare match A

SCI3 SCI3 receive data full

Reset 0 H'0000 to H'0001 High

NMI 7 H'000E to H'000F

the SLEEP instruction

IRQ0 Low-voltage detection interrupt

Timer V compare match B Timer V overflow

SCI3 transmit data empty SCI3 transmit end SCI3 receive error

Vector Number Vector Address Priority

13 H'001A to H'001B

14 H'001C to H'001D

22 H'002C to H'002D

23 H'002E to H'002F

Low

Rev. 1.00 Sep. 16, 2005 Page 44 of 490

REJ09B0216-0100

Section 3 Exception Handling

Relative Module Exception Sources

IIC2 Transmit data empty

Vector Number Vector Address Priority

24 H'0030 to H'0031 High Transmit end Receive data full Arbitration lost/Overrun error NACK detection Stop conditions detected

A/D converter A/D conversion end 25 H'0032 to H'0033

Timer Z Compare match/input capture

26 H'0034 to H'0035 A0 to D0 Timer Z overflow

Compare match/input capture

27 H'0036 to H'0037 A1 to D1 Timer Z overflow Timer Z underflow

Timer B1 Timer B1 overflow 29 H'003A to H'003B

SCI3_2 Receive data full

32 H'0040 to H'0041 Transmit data empty Transmit end Receive error

 Reserved for system use 33 H'0042 to H'0043

Clock source switching

Clock source switching (from external clock to on-chip oscillator)

34 H'0044 to H'0045

Low

Note: * A low-voltage detection interrupt is enabled only in the product with an on-chip power-

on reset and low-voltage detection circuit.

Rev. 1.00 Sep. 16, 2005 Page 45 of 490

REJ09B0216-0100

Section 3 Exception Handling

3.2 Register Descriptions

Interrupts are controlled by the following registers.

• Interrupt edge select register 1 (IEGR1)

• Interrupt edge select register 2 (IEGR2)

• Interrupt enable register 1 (IENR1)

• Interrupt enable register 2 (IENR2)

• Interrupt flag register 1 (IRR1)

• Interrupt flag register 2 (IRR2)

• Wakeup interrupt flag register (IWPR)

3.2.1 Interrupt Edge Select Register 1 (IEGR1)

IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to IRQ0.

Initial

Bit Bit Name

7 NMIEG 0 R/W NMI Edge Select

6 to 4  All 1  Reserved

3 IEG3 0 R/W IRQ3 Edge Select

2 IEG2 0 R/W IRQ2 Edge Select

1 IEG1 0 R/W IRQ1 Edge Select

0 IEG0 0 R/W IRQ0 Edge Select

Value R/W Description

0: Falling edge of NMI pin input is detected 1: Rising edge of NMI pin input is detected

These bits are always read as 1.

0: Falling edge of IRQ3 pin input is detected 1: Rising edge of IRQ3 pin input is detected

0: Falling edge of IRQ2 pin input is detected 1: Rising edge of IRQ2 pin input is detected

0: Falling edge of IRQ1 pin input is detected 1: Rising edge of IRQ1 pin input is detected

0: Falling edge of IRQ0 pin input is detected 1: Rising edge of IRQ0 pin input is detected

Rev. 1.00 Sep. 16, 2005 Page 46 of 490

REJ09B0216-0100

Section 3 Exception Handling

3.2.2 Interrupt Edge Select Register 2 (IEGR2)

IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0.

Initial

Bit Bit Name

7, 6  All 1  Reserved

5 WPEG5 0 R/W WKP5 Edge Select

4 WPEG4 0 R/W WKP4 Edge Select

3 WPEG3 0 R/W WKP3 Edge Select

2 WPEG2 0 R/W WKP2 Edge Select

1 WPEG1 0 R/W WKP1Edge Select

0 WPEG0 0 R/W WKP0 Edge Select

Value R/W Description

These bits are always read as 1.

0: Falling edge of WKP5(ADTRG) pin input is detected 1: Rising edge of WKP5(ADTRG) pin input is detected

0: Falling edge of WKP4 pin input is detected 1: Rising edge of WKP4 pin input is detected

0: Falling edge of WKP3 pin input is detected 1: Rising edge of WKP3 pin input is detected

0: Falling edge of WKP2 pin input is detected 1: Rising edge of WKP2 pin input is detected

0: Falling edge of WKP1 pin input is detected 1: Rising edge of WKP1 pin input is detected

0: Falling edge of WKP0 pin input is detected 1: Rising edge of WKP0 pin input is detected

Rev. 1.00 Sep. 16, 2005 Page 47 of 490

REJ09B0216-0100

Section 3 Exception Handling

3.2.3 Interrupt Enable Register 1 (IENR1)

IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts.

Initial

Bit Bit Name

7 IENDT 0 R/W Direct Transfer Interrupt Enable

6 IENTA 0 R/W RTC Interrupt Enable

5 IENWP 0 R/W Wakeup Interrupt Enable

4  1  Reserved

3 IEN3 0 R/W IRQ3 Interrupt Enable

2 IEN2 0 R/W IRQ2 Interrupt Enable

1 IEN1 0 R/W IRQ1 Interrupt Enable

0 IEN0 0 R/W IRQ0 Interrupt Enable

Value R/W Description

When this bit is set to 1, direct transition interrupt requests are enabled.

When this bit is set to 1, RTC interrupt requests are enabled.

This bit is an enable bit, which is common to the pins WKP5 to WKP0. When the bit is set to 1, interrupt requests are enabled.

This bit is always read as 1.

When this bit is set to 1, interrupt requests of the IRQ3 pin are enabled.

When this bit is set to 1, interrupt requests of the IRQ2 pin are enabled.

When this bit is set to 1, interrupt requests of the IRQ1 pin are enabled.

When this bit is set to 1, interrupt requests of the IRQ0 pin are enabled.

When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed.

Rev. 1.00 Sep. 16, 2005 Page 48 of 490

REJ09B0216-0100

Section 3 Exception Handling

3.2.4 Interrupt Enable Register 2 (IENR2)

IENR2 enables, timer B1 overflow interrupts.

Initial

Bit Bit Name

7, 6  All 0  Reserved

5 IENTB1 0 R/W Timer B1 Interrupt Enable

4 to 0  All 1  Reserved

Value R/W Description

These bits are always read as 0.

When this bit is set to 1, timer B1 overflow interrupt requests are enabled.

These bits are always read as 1.

3.2.5 Interrupt Flag Register 1 (IRR1)

IRR1 is a status flag register for direct transition interrupts, RTC interrupts, and IRQ3 to IRQ0 interrupt requests.

Initial

Bit Bit Name

7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag

Rev. 1.00 Sep. 16, 2005 Page 49 of 490

REJ09B0216-0100

Value R/W Description

[Setting condition]

When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1.

[Clearing condition]

When IRRDT is cleared by writing 0

Section 3 Exception Handling

Initial

Bit Bit Name

Value R/W Description

6 IRRTA 0 R/W RTC Interrupt Request Flag

[Setting condition]

When the RTC counter value overflows

[Clearing condition]

When IRRTA is cleared by writing 0

5, 4  All 1  Reserved

These bits are always read as 1.

3 IRRI3 0 R/W IRQ3 Interrupt Request Flag

[Setting condition] When IRQ3 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI3 is cleared by writing 0

2 IRRI2 0 R/W IRQ2 Interrupt Request Flag

[Setting condition] When IRQ2 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI2 is cleared by writing 0

1 IRRI1 0 R/W IRQ1 Interrupt Request Flag

[Setting condition] When IRQ1 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI1 is cleared by writing 0

0 IRRl0 0 R/W IRQ0 Interrupt Request Flag

[Setting condition] When IRQ0 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI0 is cleared by writing 0

Rev. 1.00 Sep. 16, 2005 Page 50 of 490

REJ09B0216-0100

3.2.6 Interrupt Flag Register 2 (IRR2)

IRR2 is a status flag register for timer B1 overflow interrupts.

Initial

Bit Bit Name

7, 6  All 0  Reserved

5 IRRTB1 0 R/W Timer B1 Interrupt Request flag

4 to 0  All 1  Reserved

Value R/W Description

These bits are always read as 0.

[Setting condition]

When the timer B1 counter value overflows

[Clearing condition]

When IRRTB1 is cleared by writing 0

These bits are always read as 1.

3.2.7 Wakeup Interrupt Flag Register (IWPR)

IWPR is a status flag register for WKP5 to WKP0 interrupt requests.

Initial

Bit Bit Name

7, 6  All 1  Reserved

5 IWPF5 0 R/W WKP5 Interrupt Request Flag

4 IWPF4 0 R/W WKP4 Interrupt Request Flag

Value R/W Description

These bits are always read as 1.

[Setting condition] When WKP5 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF5 is cleared by writing 0.

[Setting condition] When WKP4 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF4 is cleared by writing 0.

Section 3 Exception Handling

Rev. 1.00 Sep. 16, 2005 Page 51 of 490

REJ09B0216-0100

Section 3 Exception Handling

Initial

Bit Bit Name

Value R/W Description

3 IWPF3 0 R/W WKP3 Interrupt Request Flag

[Setting condition] When WKP3 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF3 is cleared by writing 0.

2 IWPF2 0 R/W WKP2 Interrupt Request Flag

[Setting condition] When WKP2 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF2 is cleared by writing 0.

1 IWPF1 0 R/W WKP1 Interrupt Request Flag

[Setting condition] When WKP1 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF1 is cleared by writing 0.

0 IWPF0 0 R/W WKP0 Interrupt Request Flag

[Setting condition] When WKP0 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF0 is cleared by writing 0.

Rev. 1.00 Sep. 16, 2005 Page 52 of 490

REJ09B0216-0100

Section 3 Exception Handling

3.3 Reset Exception Handling

When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling. The reset exception handling sequence is shown in figure 3.1. However, for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer to section 19, Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits.

The reset exception handling sequence is as follows:

1. Set the I bit in the condition code register (CCR) to 1.

2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the data in that address is sent to the program counter (PC) as the start address, and program execution starts from that address.

Rev. 1.00 Sep. 16, 2005 Page 53 of 490

REJ09B0216-0100

Section 3 Exception Handling

3.4 Interrupt Exception Handling

3.4.1 External Interrupts

As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.

(1) NMI Interrupt

NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1.

NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit value in CCR.

(2) IRQ3 to IRQ0 Interrupts

IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four interrupts are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1.

When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.

(3) WKP5 to WKP0 Interrupts

WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.

When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bit IENWP in IENR1.

Rev. 1.00 Sep. 16, 2005 Page 54 of 490

REJ09B0216-0100

RES

Reset cleared

Vector fetch

Internal processing

Section 3 Exception Handling

Initial program instruction prefetch

Internal address bus

Internal read signal

Internal write signal

Internal data bus (16 bits)

(1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction

Figure 3.1 Reset Sequence

(2)(1)

(2) (3)

Rev. 1.00 Sep. 16, 2005 Page 55 of 490

REJ09B0216-0100

Section 3 Exception Handling

3.4.2 Internal Interrupts

Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For RTC interrupt requests and direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1, IRR2, IENR1, and IENR2.

When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by writing 0 to clear the corresponding enable bit.

3.4.3 Interrupt Handling Sequence

Interrupts are controlled by an interrupt controller.

Interrupt operation is described as follows.

1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller.

2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending.

3. The CPU accepts the NMI and address break without dependi ng on the I bit value. Othe r interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the interrupt request is held pending.

4. If the CPU accepts the interrupt after processing of the current instruction is completed, interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling.

5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be restored and returned to the values prior to the start of interrupt exception handling.

6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and

transfers the address to PC as a start address of the interrupt handling-routine. Then a program starts executing from the address indicated in PC.

Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.

Rev. 1.00 Sep. 16, 2005 Page 56 of 490

REJ09B0216-0100

Section 3 Exception Handling

SP – 4

SP – 3

SP – 2

SP – 1

SP (R7)

[Legend]

Upper 8 bits of program counter (PC)

Lower 8 bits of program counter (PC)

CCR:

Condition code register

SP:

Stack pointer

1.2.PC shows the address of the first instruction to be executed upon return from the interrupt

Notes:

handling routine. Register contents must always be saved and restored by word length, starting from an even-numbered address.

3. Ignored when returning from the interrupt handling routine.

Stack area

Prior to start of interrupt

exception handling

SP (R7)

SP + 1

SP + 2

SP + 3

SP + 4

PC and CCR

saved to stack

CCR

PCH

PCL

After completion of interrupt

exception handling

Even address

Figure 3.2 Stack Status after Exception Handling

3.4.4 Interrupt Response Time

Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed.

Table 3.2 Interrupt Wait States

Item States Total

Waiting time for completion of executing instruction* 1 to 23 15 to 37

Saving of PC and CCR to stack 4

Vector fetch 2

Instruction fetch 4

Internal processing 4

Note: * Not including EEPMOV instruction.

Rev. 1.00 Sep. 16, 2005 Page 57 of 490

REJ09B0216-0100

Section 3 Exception Handling

Prefetch instruction of

interrupt-handling routine

Internal

processing

Vector fetch

Stack access

(9)

Internal

processing

(3) (9)(8)(6)(5)

Instruction

prefetch

Interrupt is

accepted

Interrupt level

decision and wait for

end of instruction

Interrupt

request signal

(1)

Internal

address bus

Internal read

signal

Internal write

Figure 3.3 Interrupt Sequence

Rev. 1.00 Sep. 16, 2005 Page 58 of 490

REJ09B0216-0100

(4) (1) (7) (10)

(2)

signal

Internal data bus

(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)

(2)(4) Instruction code (not executed)

(3) Instruction prefetch address (Instruction is not executed.)

(5) SP – 2

(6) SP – 4

(7) CCR

(8) Vector address

(9) Starting address of interrupt-handling routine (contents of vector)

(16 bits)

(10) First instruction of interrupt-handling routine

Section 3 Exception Handling

3.5 Usage Notes

3.5.1 Interrupts after Reset

If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.W #xx: 16, SP).

3.5.2 Notes on Stack Area Use

When word data is accessed, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values.

3.5.3 Notes on Rewriting Port Mode Registers

When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3 to IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1.

When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0.

Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.

Interrupts masked. (Another possibility

CCR I bit 1

Set port mode register bit

Execute NOP instruction

Clear interrupt request flag to 0

CCR I bit 0

←

is to disable the relevant interrupt in interrupt enable register 1.)

After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0.

Interrupt mask cleared

Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure

Rev. 1.00 Sep. 16, 2005 Page 59 of 490

REJ09B0216-0100

Section 3 Exception Handling

Rev. 1.00 Sep. 16, 2005 Page 60 of 490

REJ09B0216-0100

Section 4 Address Break

The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address. With the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. Figure 4.1 shows a block diagram of the address break.

Internal address bus

Comparator

BARH BARL

Interrupt

generation

control circuit

BDRH BDRL

Comparator

[Legend] BARH, BARL: Break address registers BDRH, BDRL: Break data registers ABRKCR: Address break control register ABRKSR: Address break status register

ABRKCR

ABRKSR

Figure 4.1 Block Diagram of Address Break

Internal data bus

Interrupt

ABK0001A_000020020200 Rev. 1.00 Sep. 16, 2005 Page 61 of 490

REJ09B0216-0100

Section 4 Address Break

4.1 Register Descriptions

Address break has the following registers.

• Address break control register (ABRKCR)

• Address break status register (ABRKSR)

• Break address register (BARH, BARL)

• Break data register (BDRH, BDRL)

4.1.1 Address Break Control Register (ABRKCR)

ABRKCR sets address break conditions.

Initial

Bit Bit Name

7 RTINTE 1 R/W RTE Interrupt Enable

CSEL1

CSEL0 0 0

ACMP2

ACMP1

ACMP0

Value R/W Description

When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked.

R/W

Condition Select 1 and 0

These bits set address break conditions.

00: Instruction execution cycle

01: CPU data read cycle

10: CPU data write cycle

11: CPU data read/write cycle

Address Compare Condition Select 2 to 0

These bits set the comparison condition between the address set in BAR and the internal address bus.

000: Compares 16-bit addresses

001: Compares upper 12-bit addresses

010: Compares upper 8-bit addresses

011: Compares upper 4-bit addresses

1XX: Reserved (setting prohibited)

Rev. 1.00 Sep. 16, 2005 Page 62 of 490

REJ09B0216-0100

Section 4 Address Break

Initial

Bit Bit Name

[Legend] X: Don't care.

DCMP1

DCMP0 0 0

Value R/W Description

R/W

Data Compare Condition Select 1 and 0

These bits set the comparison condition between the data set in BDR and the internal data bus.

00: No data comparison

01: Compares lower 8-bit data between BDRL and data

bus

10: Compares upper 8-bit data between BDRH and data

bus

11: Compares 16-bit data between BDR and data bus

When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 21.1, Register Addresses (Address Order).

Table 4.1 Access and Data Bus Used

Word Access Byte Access Even Address Odd Address Even Address Odd Address

ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits

RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits

I/O register with 8-bit data bus width

I/O register with 16-bit data bus width

Rev. 1.00 Sep. 16, 2005 Page 63 of 490

REJ09B0216-0100

Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits

Upper 8 bits Lower 8 bits  

Section 4 Address Break

4.1.2 Address Break Status Register (ABRKSR)

ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.

Initial

Bit Bit Name

7 ABIF 0 R/W Address Break Interrupt Flag

6 ABIE 0 R/W Address Break Interrupt Enable

5 to 0  All 1  Reserved

Value R/W Description

[Setting condition]

When the condition set in ABRKCR is satisfied

[Clearing condition]

When 0 is written after ABIF=1 is read

When this bit is 1, an address break interrupt request is enabled.

These bits are always read as 1.

4.1.3 Break Address Registers (BARH, BARL)

BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instru ction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF.

4.1.4 Break Data Registers (BDRH, BDRL)

BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH for byte access. For word access, the data bus used depends on the address. See section 4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is undefined.

Rev. 1.00 Sep. 16, 2005 Page 64 of 490

REJ09B0216-0100

Section 4 Address Break

4.2 Operation

When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU.

Figures 4.2 show the operation examples of the address break interrupt setting.

When the address break is specified in instruction execution cycle

• ABRKCR = H'80

• BAR = H'025A

NOP

instruc-

tion

prefetch

Address bus

Interrupt request

0258

Program

0258

NOP

025A

NOP

025C

MOV.W @H'025A,R0

0260

NOP

0262

NOP

instruc-

prefetch

MOV

instruc-

tion

tion 1

prefetch

025A 025C 025E SP-2 SP-4

Interrupt acceptance

MOV

instruc-

tion 2

prefetch

Underline indicates the address to be stacked.

Internal

processing

Stack save

Figure 4.2 Address Break Interrupt Operation Example (1)

Rev. 1.00 Sep. 16, 2005 Page 65 of 490

REJ09B0216-0100

Section 4 Address Break

When the address break is specified in the data read cycle

• ABRKCR = H'A0

• BAR = H'025A

Program

0258 025A 025C

0260 0262 :

NOP NOP MOV.W @H'025A,R0 NOP NOP :

Underline indicates the address to be stacked.

Address bus

Interrupt request

MOV

instruc-

tion 1

prefetch

025C

MOV

instruc-

tion 2

prefetch

NOP

instruc-

tion

prefetch

025E 0260 025A 0262 0264 SP-2

MOV

instruc-

tion

execution

tion

instru-

ction

prefetch

NOP

instruc-

prefetch

Interrupt acceptance

Internal

processing

Figure 4.2 Address Break Interrupt Operation Example (2)

Stack

save

Rev. 1.00 Sep. 16, 2005 Page 66 of 490

REJ09B0216-0100

Section 5 Clock Pulse Generator

The clock pulse generator (CPG) consists of a system clock generating circuitry, a subclock generating circuitry, and two prescalers. The system clock generating circuitry includes an external clock oscillator, a duty correction circuit, an on-chip oscillator, an RC clock divider, a clock select circuit, and a system clock divider. The subclock generating circuitry includes a subclock oscillator, and a subclock divider. The CPG can function as a clock generating circuitry itself or in combination with an external oscillator. Figure 5.1 shows a block diagram of the clock pulse generator.

OSC1

OSC2

External

clock

oscillator

On-chip oscillator

Subclock

oscillator

System clock generating circuitry

Subclock generating circuitry

OSC

Duty

correction

circuit

RC clock divider

(fW)

OSC

Clock

select circuit

Subclock

divider

System

clock

divider

φW/8

φ/8

φ/16

φ/32

SUB

φ/2 to φ/8192

/128

φ/64

Prescaler S

(13 bits)

Prescaler W

(5 bits)

Figure 5.1 Block Diagram of Clock Pulse Generator

The system clock (φ) and subclock (φ

) are basic clocks on which the CPU and on-chip

SUB

peripheral modules operate. The system clock is divided into from φ/2 to φ/8192 by prescaler S. The subclock is divided into from φ

/8 to φW/128 by prescaler W. These divided clocks are

supplied to respective peripheral modules.

CPG0200A_000020020200 Rev. 1.00 Sep. 16, 2005 Page 67 of 490

REJ09B0216-0100

Section 5 Clock Pulse Generator

5.1 Features

• Choice of two clock sources On-chip oscillator clock Clock by an external oscillator output

• Choice of two types of RC oscillation frequency by the user software 16 MHz 20 MHz

• Frequency trimming Since the initial frequency of the on-chip oscillator in the flash memory version is within the

range of two frequencies shown above, it is normally unnecessary to trim the frequency. It is, however, still possible to adjust it by rewriting the trimming registers.

• Backup of the external oscillation halt This system detects the external oscillator halt. If detected, the system clock source is

automatically switched to the on-chip oscillator clock.

• Interrupt can be requested to the CPU when the system clock is switched from the external clock to the on-chip oscillator clock.

5.2 Register Descriptions

The CPG has the following registers.

• RC control register (RCCR)

• RC trimming data protect register (RCTRMDPR)

• RC trimming data register (RCTRMDR)

• Clock control/status register (CKCSR)

Rev. 1.00 Sep. 16, 2005 Page 68 of 490

REJ09B0216-0100

Section 5 Clock Pulse Generator

5.2.1 RC Control Register (RCCR)

RCCR controls the on-chip oscillator.

Initial

Bit Bit Name

7 RCSTP 0 R/W On-Chip Oscillator Standby

6 FSEL 1 R/W Frequency Select for On-chip Oscillator

5 VCLSEL 0 R/W Power Supply Select for On-chip Oscillator

4 to 2  All 0  Reserved

RCPSC1

RCPSC0 1 0

Value R/W Description

The on-chip oscillator standby state is entered by setting this bit to 1.

0: 16 MHz

1: 20 MHz

0: Selects VBGR

1: Selects VCL

When the VCL power is selected, the accuracy of the onchip oscillator frequency cannot be guaranteed.

These bits are always read as 0.

R/W

Division Ratio Select for On-chip Oscillator

The division ratio of φ bit.

These bits can be written to only when the CKSTA bit in CKCSR is 0.

(not divided)

0X: φ

10: φ

11: φ

changes right after rewriting this

Rev. 1.00 Sep. 16, 2005 Page 69 of 490

REJ09B0216-0100

Section 5 Clock Pulse Generator

5.2.2 RC Trimming Data Protect Register (RCTRMDPR)

RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings.

Initial

Bit Bit Name

7 WRI 1 W Write Inhibit

6 PRWE 0 R/W Protect Information Write Enable

5 LOCKDW 0 R/W Trimming Data Register Lock Down

Value R/W Description

Only when writing 0 to this bit, this register can be written to. This bit is always read as 1.

Bits 5 and 4 can be written to when this bit is set to 1.

[Setting condition]

• When writing 0 to the WRI bit and writing 1 to the PRWE bit

[Clearing conditions]

• Reset

• When writing 0 to the WRI bit and writing 0 to the

PRWE bit

The RC trimming data register (RCTRMDR) cannot be written to when this bit is set to 1. Once this bit is set to 1, this register cannot be written to until a reset is input even if 0 is written to this bit.

[Setting condition]

• When writing 0 to the WRI bit and writing 1 to the LOCKDW bit while the PRWE bit is 1

[Clearing condition]

• Reset

Rev. 1.00 Sep. 16, 2005 Page 70 of 490

REJ09B0216-0100

RENESAS HD64F36077G, HD64F36074G User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Keep safety first in your circuit designs!

Notes regarding these materials

General Precautions on Handling of Product

Configuration of This Manual

Preface

Contents

Figures

Tables

Section 1 Overview

1.1 Features

1.2 Block Diagram

1.3 Pin Arrangement

1.4 Pin Functions

Section 2 CPU

2.1 Address Space and Memory Map

2.2 Register Configuration

2.2.1 General Registers

2.2.2 Program Counter (PC)

2.2.3 Condition-Code Register (CCR)

2.3 Data Formats

2.3.1 General Register Data Formats

2.3.2 Memory Data Formats

2.4 Instruction Set

2.4.1 Table of Instructions Classified by Function

2.4.2 Basic Instruction Formats

2.5 Addressing Modes and Effective Address Calculation

2.5.1 Addressing Modes

2.5.2 Effective Address Calculation

2.6 Basic Bus Cycle

2.6.1 Access to On-Chip Memory (RAM, ROM)

2.6.2 On-Chip Peripheral Modules

2.7 CPU States

2.8 Usage Notes

2.8.1 Notes on Data Access to Empty Areas

2.8.2 EEPMOV Instruction

2.8.3 Bit-Manipulation Instruction

Section 3 Exception Handling

3.1 Exception Sources and Vector Address

3.2 Register Descriptions

3.2.1 Interrupt Edge Select Register 1 (IEGR1)

3.2.2 Interrupt Edge Select Register 2 (IEGR2)

3.2.3 Interrupt Enable Register 1 (IENR1)

3.2.4 Interrupt Enable Register 2 (IENR2)

3.2.5 Interrupt Flag Register 1 (IRR1)

3.2.6 Interrupt Flag Register 2 (IRR2)

3.2.7 Wakeup Interrupt Flag Register (IWPR)

3.3 Reset Exception Handling

3.4 Interrupt Exception Handling

3.4.1 External Interrupts

3.4.2 Internal Interrupts

3.4.3 Interrupt Handling Sequence

3.4.4 Interrupt Response Time

3.5 Usage Notes

3.5.1 Interrupts after Reset

3.5.2 Notes on Stack Area Use

3.5.3 Notes on Rewriting Port Mode Registers

Section 4 Address Break

4.1 Register Descriptions

4.1.1 Address Break Control Register (ABRKCR)

4.1.2 Address Break Status Register (ABRKSR)

4.1.3 Break Address Registers (BARH, BARL)

4.1.4 Break Data Registers (BDRH, BDRL)

4.2 Operation

Section 5 Clock Pulse Generator

5.1 Features

5.2 Register Descriptions

5.2.1 RC Control Register (RCCR)

5.2.2 RC Trimming Data Protect Register (RCTRMDPR)