RENESAS HD6432236R, HD6432258, HD6432236RW, HD64F2258, HD6432258W User Manual

REJ09B0054-0500

The revision list can be viewed directly by
clicking the title page.

The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.

H8S/2258, H8S/2239, H8S/2238,

16

Renesas 16-Bit Single-Chip Microcomputer

H8S/2258 HD64F2258 H8S/2236R HD6432236R

H8S/2256 HD6432256 HD6432237

H8S/2239 HD64F2239 H8S/2233 HD6432233

H8S/2238B HD64F2238B H8S/2225 HD6432225

H8S/2238R HD64F2238R

H8S/2236B HD6432236B

H8S/2237, H8S/2227

Groups

Hardware Manual

H8S Family/H8S/2200 Series

HD6432258 HD6432236RW
HD6432258W H8S/2237 HD6472237

HD6432256W H8S/2235 HD6432235

HD6432239 H8S/2227 HD64F2227
HD6432239W HD6432227

HD6432238B H8S/2224 HD6432224
HD6432238BW H8S/2223 HD6432223

HD6432238R
HD6432238RW

HD6432236BW

Rev. 5.00
Revision Date: Aug 08, 2006

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 5.00 Aug 08, 2006 page ii of lxxxvi

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.

Rev. 5.00 Aug 08, 2006 page iii of lxxxvi

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Main Revisions in This Edition

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

5. Contents

6. Overview

7. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

8. List of Registers

9. Electrical Characteristics

10. Appendix

11. Index

Rev. 5.00 Aug 08, 2006 page iv of lxxxvi

Preface

The H8S/2558 Group, H8S/2239 Group, H8S/2238 Group, H8S/2237 Group, and H8S/2227
Group are high-performance microcomputers made up of the internal 32-bit configuration
H8S/2000 CPU as their cores, and the peripheral functions required to configure a system.

TM

*

A single-power flash memory (F-ZTAT
these LSIs’ ROM. These versions provide flexibility as they can be reprogrammed in no time to
cope with all situations from the early stages of mass production to full-scale mass production.
This is particularly applicable to application devices of which the specifications frequently
changeable.

On-chip peripheral functions of each microcomputer are summarized below.

Note: * F-ZTAT is a trademark of Renesas Technology Corp.

) version and masked ROM version are available for

Rev. 5.00 Aug 08, 2006 page v of lxxxvi

List of On-Chip Peripheral Functions:

Group Name

Microcomputer

H8S/2258
Group

H8S/2258
H8S/2256

H8S/2239
Group

H8S/2239

H8S/2238
Group

H8S/2238B
H8S/2238R
H8S/2236B
H8S/2236R

H8S/2237
Group

H8S/2237
H8S/2235
H8S/2233

H8S/2227
Group

H8S/2227
H8S/2225
H8S/2224
H8S/2223

Bus controller (BSC) O (16 bits) O (16 bits) O (16 bits) O (16bits) O (16 bits)

Data transfer controller

OOOOO

(DTC)

DMA controller (DMAC)  O 
PC break controller (PBC) ×2 ×2 ×2 ×2 ×2

16-bit timer pulse unit

×6 ×6 ×6 ×6 ×3

(TPU)

8-bit timer (TMR) ×4 ×4 ×4 ×2 ×2
Watchdog timer (WDT) ×2 ×2 ×2 ×2 ×2

Serial communication

×4 ×4 ×4 ×4 ×3

interface (SCI)

2

I

C bus interface (IIC) ×2 (option) ×2 (option) ×2 (option) 

D/A converter ×2 ×2 ×2 ×2 

A/D

Analog input ×8 ×8 ×8 ×8 ×8

converter

IEBus* controller (IEB) ×1 

Note: * IEBus (Inter Equipment Bus) is a trademark of NEC Electronics Corp.

Target Users: This manual was written for users who will be using the H8S/2258 Group,

H8S/2239 Group, H8S/2238 Group, H8S/2237 Group, and H8S/2227 Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the H8S/2258 Group, H8S/2239 Group,

H8S/2238 Group, H8S/2237 Group, and H8S/2227 Group hardware functions and
electrical characteristics of this LSI to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed
description of the instruction set.

Rev. 5.00 Aug 08, 2006 page vi of lxxxvi

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into
descriptions on the CPU, system control functions, peripheral functions, and electrical
characteristics.

• In order to understand the details of the CPU’s functions

Read the H8S/2600 Series, H8S/2000 Series Software Manual.

• In order to understand the details of a register whole name is already known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 26,
List of Registers.

Rules: Register name: The following notation is used for cases when the same or a

similar function, e.g., 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)

Bit order: The MSB is on the left and the LSB is on the right.

Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, and decimal is

xxxx.

Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents.
http://www.renesas.com/

H8S/2258 Group, H8S/2239 Group, H8S/2238 Group, H8S/2237 Group, H8S/2227 Group
manuals:

Document Title Document No.

H8S/2258 Group, H8S/2239 Group, H8S/2238 Group, H8S/2237 Group,
H8S/2227 Group Hardware Manual

H8S/2600 Series, H8S/2000 Series Software Manual REJ09B0139

Rev. 5.00 Aug 08, 2006 page vii of lxxxvi

This manual

User's Manuals for Development Tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage
Editor Compiler Package Ver. 6.01 User's Manual

H8S, H8/300 Series High-performance Embedded Workshop 3
Tutorial

H8S, H8/300 Series High-performance Embedded Workshop 3
User's Manual

High-performance Embedded Workshop V.4.00 User's Manual REJ10J0886

REJ10B0161

REJ10B0024

REJ10B0026

Application Notes:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464

Rev. 5.00 Aug 08, 2006 page viii of lxxxvi

Main Revisions for This Edition

Item Page Revision (See Manual for Details)

All  Description of "under development" for HD64F2239 deleted

1.1 Features 2

1.3.1 Pin Arrangement

Figure 1.11 Pin
Arrangement of H8S/2238
Group (FP-100A, FP-100AV:
Top View, Only for
H8S/2238B

and H8S/2236B)

• On-chip memory

Table amended

ROM Model ROM RAM Remarks

version

3

• Compact package

Package (Code)

TQFP-100 TFP-100B,

TQFP-100

QFP-100
QFP-100
LFBGA-112
TFBGA-112

HD6432258 256 kbytes 16 kbytesMasked ROM
HD6432258W 256 kbytes 16 kbytes
HD6432256 128 kbytes 8 kbytes
HD6432256W 128 kbytes 8 kbytes

6

*

4

5

TFP-100BV
TFP-100G,

TFP-100GV
FP-100A, FP-100AV
FP-100B, FP-100BV
BP-112, BP-112V
TBP-112A,

TBP-112AV

1

*

2

*

3

*

*
*

Notes amended

1. Not supported by the H8S/2258 Group.

Notes:

2. Supported only by the H8S/2258 Group, H8S/2238B,
H8S/2236B, H8S/2237 Group, and HD6432227.

3. Not supported by the HD64F2227.

4. Supported only by the HD64F2238R.

5. Supported only by the HD64F2238R and HD64F2239.

6. Package code ending in the letter V designate Pb-free
Product.

14 Figure 1.11 title amended

Rev. 5.00 Aug 08, 2006 page ix of lxxxvi

Item Page Revision (See Manual for Details)

1.3.1 Pin Arrangement

19 Figure 1.16 title amended

Figure 1.16 Pin
Arrangement of H8S/2227
Group (FP-100A, FP-100AV:
Top View, Only for
HD6432227)

Table 1.3 Pin Arrangements
in Each Mode of H8S/2238
Group

1.3.2 Pin Arrangement in
Each Mode

33 Notes amended

Notes: 1. Supported only by H8S/

2. Supported only by the

in the H8S/2238B and H8S/2236B.

3. V

CC

39 to43Table 1.5 amended

1

*

FP-100B

FP-100BV

HD64F2238R.

1

*

FP-100A
Table 1.5 Pin Arrangements
in Each Mode of H8S/2227
Group

41 Table 1.5 amended

Pin No. Pin Name

TFP-100B
TFP-100BV
TFP-100G
TFP-100GV

1

*

FP-100B

*

FP-100BV

57 60 OSC2 OSC2 OSC2 OSC2 NC
58 61 OSC1 OSC1 OSC1 OSC1 VSS
59 62 RES RES RES RES RES

FP-100A

1

FP-100AV

2

*

2

*

Mode 4 Mode 5 Mode 6 Mode 7

43 Note 2 added

1. Supported only by masked ROM version.

Notes:

2. Supported only by the HD6432227.

1.3.3 Pin Functions

Table 1.6 Pin Functions of
H8S/2258 Group

45 Table 1.6 amended

RES* STBY* NMI

49

Note: * Measures should be taken to deal with noise, which

*

can cause operation errors otherwise.

Table 1.7 Pin Functions of
H8S/2239 Group and
H8S/2238 Group

50 Table 1.7 amended

CVCC in power supply

... (H8S/2239, H8S/2378R

, and H8S/2236R used), ...

51 Table 1.7 amended

RES

5

*

STBY

5

*

NMI

5

*

2238B and H8S/2236B.

2

*

FP-100BAV

2

*

Flash Memory
Programmable
Mode

Rev. 5.00 Aug 08, 2006 page x of lxxxvi

Item Page Revision (See Manual for Details)

1.3.3 Pin Functions

Table 1.7 Pin Functions of
H8S/2239 Group and
H8S/2238 Group

53

Type Symbol

DMA

DREQ1

controller

DREQ08990

2

*

(DMAC)

TEND1
TEND08788

DACK1
DACK03534

TFP-100B
TFP-100BV
TFP-100G
TFP-100GV
FP-100B
FP-100BV

Pin No.

3

*

FP-100A

3

*

FP-100AV

B6

C6

J5

1

*

BP-112

1

*

BP-112V

4

*

TBP-112A

4

*

TBP-112AV

I/O Function

Input Request DMAC activation.

D6

Output Indicate that the DMAC has ended

A6

Output These pins function as single address

H5

55 P47 to P40 in I/O ports

L10, L9, K11, K10, K9, K8, H7, J8

56 Notes: 1. Supported only by the HD64F2238R.

2. Supported only by the H8S/2239 Group.

3. Supported only by the H8S/2238B

4. Supported only by the

HD64F2238R and HD64F2239.

5. Measures should be taken to deal with noise, which can
cause operation errors otherwise.

Table 1.8 Pin Functions of
H8S/2237 Group and
H8S/2227 Group

57 to61Table 1.8 amended

1

*

3

*

STBY

FP-100BV

3

*

NMI

FP-100B

RES

1

*

FP-100A

3

*

61 Notes amended

1. Supported only by masked ROM version.

Notes:

2. Supported only by the HD6432227.

3. Measures should be taken to deal with noise, which can
cause operation errors otherwise.

3.4 Memory Map in Each
Operating Mode

115 Figure 3.7 amended

(Before) On-chip R

AM → (After) On-chip ROM

Figure 3.7 H8S/2235 and
H8S/2225 Memory Map in
Each Operating Mode

5.1 Features

Figure 5.1 Block Diagram of

128 Figure 5.1 amended

(Before)

IRQ → (After) IRQ

Interrupt Controller

5.3.2 IRQ Enable Register
(IER)

131 Description amended

(Before)

IRQn → (After) IRQn

(Supported only by the H8S/2239 Group.)

transmitting data.
(Supported only by the H8S/2239 Group.)

transmitting acknowledge of DMAC.
(Supported only by the H8S/2239 Group.)

and H8S/2236B.

2

*

FP-100BAV

2

*

Rev. 5.00 Aug 08, 2006 page xi of lxxxvi

Item Page Revision (See Manual for Details)

5.3.4 IRQ Status Register
(ISR)

134 Description amended

ISR indicates the status of IRQn (n=7 to 0) interrupt
requests.

6.3.4 Operation in Transition
to Power-Down Modes

161,
162

Description amended

• When the SLEEP instruction causes a transition from

high-speed (medium-speed) mode to sleep mode
from subactive mode to subsleep mode: After execution
of the SLEEP instruction, a transition is not made to
sleep mode or subsleep mode, and PC break interrupt

handling is executed. ...

• When the SLEEP instruction causes a transition to

software standby mode or watch mode:

8.3 Register Descriptions 205 Description amended

TCR_0A)

TCR_0B)

8.7.1 DMAC Register
Access during Operation

• Transfer count register_0A (E

• Transfer count register_0B (E

276 Figure 8.38 amended

DMA last transfer cycle

Figure 8.38 DMAC
Register Update Timing

DMA read

DMA write

DMA
dead

, or

Transfer

destination

[2'] [3]

G, DTCERI

9.1 Features

Figure 9.1 Block Diagram of
DTC

nsfer

urce

ead

282 Figure 9.1 amended

(Before) DTCERA to DTCER
to DTCER

9.2 Register Descriptions 283 Description amended

... When activated, ... back to the RAM.

• DTC Enable Registers A to G, and I (DCTERA to

DTCERG, and DTCERI) ...

Rev. 5.00 Aug 08, 2006 page xii of lxxxvi

DeadWrite

Idle

F, DTCERI → (After) DTCERA

Item Page Revision (See Manual for Details)

t

9.2.7 DTC Enable Registers
A to G, and I

9.2.8 DTC Vector Register
(DTVECR)

9.4 Location of Register
Information and DTC Vector
Table

286,
287

Section 9.2.7 description replaced and bit table amended

9.2.7 DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI)

DTCER is a set of registers to specify the DTC activation interrupt source, and comprised of eigh
registers; DTCERA to DTCERG, and DTCERI. The correspondence between interrupt sources
and DTCE bits, and vector numbers generated by the interrupt controller are shown in table 9.2.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. When multiple activation sources are to be set at one time, only at the initial setting,
writing data is enabled after executing a dummy read on the relevant register with all the interrupt
being masked.

Bit Bit Name

7

DTCEn7

6

DTCEn6

5

DTCEn5

4

DTCEn4

3

DTCEn3

2

DTCEn2

1

DTCEn1

0

DTCEn0

Note: n = A to G, and I

Initial
Value R/W Description

0

R/W
0
0
0
0
0
0
0

DTC Activation Enable

R/W

0: Disables an interrupt for DTC activation.

R/W

1: Specifies a relevant interrupt source as a DTC

activation source.

R/W

[Clearing conditions]

R/W

• When the DISEL bit is 1 and the data transfer

R/W

has ended

R/W

• When the specified number of transfers have

R/W

ended
[Retaining condition]
When the DISEL bit is 0 and the specifiednumber

of transfers have not been completed

288 Bit table amended

Bit Bit Name

7SWDTE 0 R/W DTC Software Activation Enable

Initial
Value R/W Description

Enables or disables the DTC software activation.
0: Disables the DTC software activation.
1: Enables the DTC software activation.
[Clearing conditions]

• When the DISEL bit is 0 and the specified
number of transfers have not ended

• When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the CPU.

[Retaining conditions]

• When the DISEL bit is 1 and data transfer has
ended

• When the specified number of transfers have
ended

• When the software-activated data transfer is in
process

293 DTCE description of IERxI (RxRDY) and IETxI (TxRDY)

amended

EG6 DTCEG5

DTC
Table 9.2 Interrupt Sources,
DTC Vector Addresses, and
Corresponding DTCEs

Rev. 5.00 Aug 08, 2006 page xiii of lxxxvi

Item Page Revision (See Manual for Details)

9.8.2 On-Chip RAM 304 Description amended

The MRA, ... in the on-chip RAM. When the DTC is used,
the RAME bit in SYSCR should not be cleared to 0.

Section 10 I/O Ports

Table 10.1 Port Functions

306 Port 3 input/output and output type description amended

1

... NMOS push-pull output*

(P35, P34, SCK1)

10.2 Port 3 315 Description amended

Port 3 is ... following registers. The P34, P35,
function as NMOS push/pull outputs.*

10.2.5 Pin Functions 317 Description amended

As shown in figure 10.1, when the pins P35, P34,
SCK0

, or SDA0 type open drain output is used, ...

and SCK1

SCK1,

Figure 10.1 Types of Open

318 Figure 10.1 amended

Drain Outputs

318 Description amended

319 Table amended

320

10.4.4 Pin Functions 324

(a) Open drain output type for P34, P35,

SCK1, SCL0, and

SDA0 pins

P2 V

(Before) ... output the

level.

V

CC

level. → (After) ... output the

CC

• P35/SCK1/SCL0/IRQ5

SCK1

input pin SCL0 I/O pin*

3

• P34/RxD1/SDA0

SDA0 I/O pin*

2

• P33/TxD1/SCL1

2

SCL1 I/O pin

*

• P32/SCK0/SDA0

SDA1 I/O pin*

3

• P75/TMO3/SCK3

Description amended

... OS3 to OS0 bits in TCSR_3 of TMR_3

*, CKE1 and ...

Table amended

OS3 to OS0

* TMO3* output pin

Note added

Note: * Not available in the H8S/2237 Group and H8S/2227
Group.

Rev. 5.00 Aug 08, 2006 page xiv of lxxxvi

Item Page Revision (See Manual for Details)

10.4.4 Pin Functions 325

• P74/TMO2/MRES

Description amended

... OS3 to OS0 bits in TCSR_2 of TMR_2

Table amended

OS3 to OS0

* TMO2* output

Note added

Note: * Not available in the H8S/2237 Group and H8S/2227

Group.

325

• P73/TMO1/TEND1/CS7

Description amended

... DMATCR of DMAC

*, OS3 to OS0 ...

Table amended

* output pin

325

TEND1

• P72/TMO0/TEND0/CS6

Description amended

... DMATCR of DMAC

*, OS3 to OS0 ...

Table amended

* output pin

326

TEND0

• P71/TMRI23/TMCI23/DREQ1/CS5

Table amended

Operating
mode Modes 4 to 6 Mode 7

P71DDR0101

P71 input pin CS5 output pin P71 input pin P71 output pinPin functions

DREQ1

TMRI23
TMCI23

*

*
*

2

input pin

1

,

1

,

 TMRI23

Note 1 added

1. Not available in the H8S/2237 Group and

Note:

H8S/2227 Group.

326

• P70/TMRI01/TMCI01/DREQ0/CS4

Table amended

TMRI01, TMCI01, DREQ0

* input pin

*, the MRESE ...

1

1

*

*

, TMCI23

, DREQ1

pin

*

2

input

Rev. 5.00 Aug 08, 2006 page xv of lxxxvi

Item Page Revision (See Manual for Details)

10.6.6 Pin Functions 330

• PA3/A19/SCK2

Description amended

... SMR_2 of SCI_2

*2, CKE1 and CKE0 bits...

Table amended

Operating mode Modes 4 to 6

AE3 to AE0 B'11xx Other than B'11xx
CKE1 —

2

*

C/A
CKE0 0 1 — —
PA3DDR 0 1 — — —
Pin functions A19

Operating
mode Mode 7

AE3 to AE0
CKE1 0 1

2

*

C/A
CKE0 0 1 ——
PA3DDR 0 1 ———
Pin functions PA3 input pin PA3 output

—
—
—

output

pin

PA3 input

pin

0 1 —

PA3 output

1

*

pin

01—

SCK2

1

*

pin

output pin

Note 2 added

2. Not available in the H8S/2227 Group.

Note:

331

• PA2/A18/RxD2

Description amended

... SCR_2 of SCI_2

*2, and the PA2DDR bit.

Table amended

Operating
mode Modes 4 to 6 Mode 7

AE3 to AE0 B'1011

2

*

RE
PA2DDR  01 01
Pin functions A18

Other than (B'1011 or B'11xx) 

or

B'11xx

 0101

PA2

PA2

output

pin

input pin

output

pin

RxD2
input pin

1

*

Note 2 added

2. Not available in the H8S/2227 Group.

Note:

0 1

SCK2

output

2

*

2

*

pin

1

*

2

*

1

*

output pin

PA2

input pin

SCK2

SCK2

output

pin

*

*

2

*

output

pin

1

1

PA2

2

*

SCK2

input pin

SCK2

pin

RxD2

input pin

1

*

*

2

input

2

*

2

*

Rev. 5.00 Aug 08, 2006 page xvi of lxxxvi

Item Page Revision (See Manual for Details)

10.6.6 Pin Functions 331

• PA1/A17/TxD2

Description amended

... SCR_2 of SCI_2

*2, and the PA1DDR bit.

Table amended

Operating
mode Modes 4 to 6 Mode 7

AE3 to AE0 B'101x or

2

*

TE
PA1DDR  01 01
Pin functions A17

B'11xx

output pin

Other than (B'101x or B'11xx) 

 01 0 1

PA1

PA1

TxD2

input pin

output

pin

output

1

*

Note 2 added

2. Not available in the H8S/2227 Group.

Note:

10.7.5 Pin Functions 335

• PB7/A15/TIOCB5

Description amended

... the TPU channel 5

*3 setting, AE3 to AE0 bits...

Table amended

Operating
mode Modes 4 to 6 Mode 7

AE3 to AE0 B'1xxx Other than B'1xxx 
TPU channel 5

*1*

setting
PB7DDR 01  01
Pin functions A15

 Output Input or initial value Output Input or initial

3

3

*

output

pin

TIOCB5
output pin

PB7

input pin

TIOCB5

2

*

pin

*

3

input

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

pin

PB7

output

pin

2

*

PA1

input pin

1

*

TIOCB5
output pin

PA1

output

1

*

pin

3

*

PB7

input

pin

TIOCB5

*

pin

2

*

TxD2

output

1

*

pin

value

PB7

output

pin

3

*

input

2

Rev. 5.00 Aug 08, 2006 page xvii of lxxxvi

Item Page Revision (See Manual for Details)

10.7.5 Pin Functions 335

• PB6/A14/TIOCA5

Description amended

... the TPU channel 5

*3 setting, AE3 to AE0 bits...

Table amended

Operating
mode

AE3 to AE0 B'0111 or

TPU channel 5

*

setting
PB6DDR 01  01
Pin functions A14

B'1xxx

1

3

*

output pin

Modes 4 to 6 Mode 7

Other than (B'0111 or B'1xxx) 

 Output Input or initial value Output Input or initial

3

*

TIOCA5
output pin

PB6
input

pin

TIOCA5

2

*

pin

*

3

input

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

336

• PB5/A13/TIOCB4

Description amended

... the TPU channel 4

*3 setting, AE3 to AE0 bits...

Table amended

Operating
mode Modes 4 to 6 Mode 7

AE3 to AE0 B'011x or

TPU channel 4

*

setting
PB5DDR 01  01
Pin functions A13

B'1xxx

1*3

output pin

Other than (B'011x or B'1xxx) 

 Output Input or initial value Output Input or initial

3

*

TIOCB4
output pin

PB5
input

pin

TIOCB4

2

*

pin

*

3

input

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

PB6

output

pin

PB5

output

pin

TIOCA5
output pin

TIOCB4
output pin

value

3

*

PB6

PB6

input

output

pin

pin

3

*

input

TIOCA5

2

*

pin

value

3

*

PB5

PB5

input

output

pin

pin

3

*

input

TIOCB4

2

*

pin

Rev. 5.00 Aug 08, 2006 page xviii of lxxxvi

Item Page Revision (See Manual for Details)

10.7.5 Pin Functions 336

• PB4/A12/TIOCA4

Description amended

... the TPU channel 4

*3 setting, AE3 to AE0 bits...

Table amended

Operating
mode Modes 4 to 6 Mode 7

AE3 to AE0

TPU channel 4
setting

PB4DDR 01  01
Pin functions A12

Other than
(B'0100 or

B'00xx)

1*3

*

 Output Input or initial value Output Input or initial

output pin

B'0100 or B'00xx 

3

*

TIOCA4

output pin

PB4

input

pin

TIOCA4

2

*

pin

*

3

input

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

337

• PB3/A11/TIOCD3

Description amended

... the TPU channel 3

*3 setting, AE3 to AE0 bits...

Table amended

Operating
mode Modes 4 to 6 Mode 7

AE3 to AE0 Other than

TPU channel 3

*

setting
PB3DDR 01  0
Pin functions A11 output

B'00xx

1*3

 Output Input or initial value Output Input or initial

TIOCD3

pin

output pin

B'00xx 

3

*

PB3

input pin

3

*

input

TIOCD3

2

*

pin

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

PB4

output

pin

PB3

output

pin

TIOCA4
output pin

TIOCD3

output pin

value

3

*

PB4

PB4

input

output

pin

pin

3

*

input

TIOCA4

2

*

pin

value

PB3

input

pin

TIOCD3

2

*

pin

3

*

1

PB3

output

pin

input

3

*

Rev. 5.00 Aug 08, 2006 page xix of lxxxvi

Item Page Revision (See Manual for Details)

10.7.5 Pin Functions 337

• PB2/A10/TIOCC3

Description amended

... the TPU channel 3

*3 setting, AE3 to AE0 bits...

Table amended

Operating mode Modes 4 to 6 Mode 7
AE3 to AE0 Other than

TPU channel 3

*1*

setting
PB2DDR 01  01
Pin functions A10 output

(B'0010 or

B'000x)

3

 Output Input or initial

pin

B'0010 or B'000x 

value

3

*

TIOCC3
output pin

PB2

input

pin

TIOCC3

2

*

pin

*

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

338

• PB1/A9/TIOCB3

Description amended

... the TPU channel 3

*3 setting, AE3 to AE0 bits...

Table amended

Operating mode Modes 4 to 6 Mode 7
AE3 to AE0 Other than

TPU channel 3

*1*

setting
PB1DDR 01  0
Pin functions A9 output

B'000x

3

 Output Input or initial

pin

B'000x 

value

3

*

3

PB1

input

pin

TIOCB3

2

*

pin

3

*

TIOCB

output pin

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

output

3

input

PB1

output

input

PB2

pin

pin

TIOCB3
output pin

Output Input or initial

TIOCC3

output pin

Output Input or initial

*

*

3

3

PB2

input

pin

TIOCC3

*

pin

PB1

input

pin

TIOCB3

2

*

pin

2

value

value

*

*

3

PB2

output

3

input

PB1

output

input

pin

1

pin

Rev. 5.00 Aug 08, 2006 page xx of lxxxvi

Item Page Revision (See Manual for Details)

10.7.5 Pin Functions 338

• PB0/A8/TIOCA3

Description amended

... the TPU channel 3

*3 setting, AE3 to AE0 bits...

Table amended

Operating mode Modes 4 to 6 Mode 7
AE3 to AE0 Other than

TPU channel 3

1*3

*

setting
PB0DDR 01  01
Pin functions A8 output

B'0000

 Output Input or initial

pin

B'0000 

value

3

*

TIOCA3
output pin

PB0

input

pin

TIOCA3

2

*

pin

3

*

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

10.9.6 Input Pull-Up MOS
States in Port D

Table 10.5 Input Pull-Up
MOS States in Port D

10.12.4 Pin Functions 356

345 Table 10.5 amended

Port I/O (modes 4

Port input (mod

to 6)

e 7)

• PG3/Rx/CS1

Description amended

... IECTR of IEB

*3, operating mode...

• PG2/Tx/CS2

Description amended

*3, operating mode...

three 16-bit timer channels or six 16-bit

11. 16-Bit Timer Pulse Unit
(TPU)

... IECTR of IEB

359 Description amended

... that comprises

timer channels. ...

11.3.1 Timer Control
Register (TCR)

367 Description amended

... for each channel.

The TPU of the H8S/2227 Group has a
total of three TCR registers, one each for channels 0 to 2. In
other groups, the TPU has a total of six TCR registers, one
each for channels 0 to 5. TCR register settings ...

CKEG1 and CKEG0 description amended

... channels 1, 2, 4

*, and 5*, this setting is ignored ...

Note * added

Note: * Not available in the H8S/2227 Group.

PB0

output

input

TIOCA3
output pin

pin

Output Input or initial

value

3

*

PB0

PB0

input

output

pin

3

*

input

TIOCA3

2

*

pin

pin

Rev. 5.00 Aug 08, 2006 page xxi of lxxxvi

Item Page Revision (See Manual for Details)

11.3.1 Timer Control
Register (TCR)

Table 11.3 CCLR2 to
CCLR0 (Channels 0 and 3)

Table 11.4 CCLR2 to
CCLR0 (Channels 1, 2, 4,
and 5)

368 Table 11.3 amended

Channel 0, 3*

3

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

368 Table 11.4 amended

Channel 1, 2, 4

*3, 5*

3

Note 3 added

3. Not available in the H8S/2227 Group.

Note:

11.3.2 Timer Mode Register
(TMDR)

372 Description amended

... for each channel.

The TPU of the H8S/2227 Group has a
total of three TMDR registers, one each for channels 0 to 2.
In other groups, the TPU has a total of six TMDR registers,
one each for channels 0 to 5. TMDR register settings ...

BFB and BFA description amended

... In channels 1, 2, 4

*, and 5*, which have no ...

Note * added

Note: * Not available in the H8S/2227 Group.

11.3.3 Timer I/C Control
Register (TIOR)

373 Description amended

... the TGR registers.

The TPU of the H8S/2227 Group has a
total of four TIOR registers, two for channel 0 and one each
for channels 1 and 2. In other groups, the TPU has a total of
eight TIOR registers, two each for channels 0 and 3, and
one each for channels 1, 2, 4, and 5. Care is required since
...

374 TIORH_0, TIOR_1, TIOR_2, TIORH_3*, TIOR_4*, TIOR_5*

Note * added

Note: * Not available in the H8S/2227 Group.

TIORL_0, TIORL_3*

Note * added

Note: * Not available in the H8S/2227 Group.

Rev. 5.00 Aug 08, 2006 page xxii of lxxxvi

Item Page Revision (See Manual for Details)

11.3.4 Timer Interrupt
Enable Register (TIER)

391 Description amended

... for each channel. The TPU of the H8S/2227 Group has a
total of three TIER registers, one each for channels 0 to 2. In
other groups, the TPU has a total of six TIER registers, one
each for channels 0 to 5. Care is required since ...

391,
392

TCIEU, TGIED, TGIEC description amended

... in channels 1, 2, 4

*, and 5* ... channels 0 and 3*, ...

392 Note * added

Note: * Not available in the H8S/2227 Group.

11.3.5 Timer Status
Register (TSR)

393 Description amended

... of each channel.

The TPU of the H8S/2227 Group has a
total of three TSR registers, one each for channels 0 to 2. In
other groups, the TPU has a total of six TSR registers, one
each for channels 0 to 5.

393,
394

Table amended

... channels 1, 2, 4

*3, and 5*3 ... channels 0 and 3*

395 Note 3 added

3. Not available in the H8S/2227 Group.

Note:

11.3.6 Timer Counter
(TCNT)

396 Description amended

... readable/writable counters.

The TPU of the H8S/2227
Group has a total of three TCNT registers, one each for
channels 0 to 2. In other groups, the TPU has a total of six
TCNT registers, one each for channels 0 to 5.

11.3.7 Timer General
Register (TGR)

396 Description amended

... input capture registers.

The TPU of the H8S/2227 Group
has a total of four TGR registers, two for channel 0 and one
each for channels 1 and 2. In other groups, the TPU has a
total of eight TGR registers, two each for channels 0 and 3,
and one each for channels 1, 2, 4, and 5.

11.3.8 Timer Start Register
(TSTR)

396 Description amended

In the H8S/2227 Group, TSTR selects operate/stop for
channels 0 to 2. In other groups, TSTR selects operate/stop
for channels 0 to 5. When setting ...

Table amended

* CDT4* CDT3*

CDT5

Note * added

Note: * In the H8S/2227 Group, bits 5 to 3 are reserved.
The write value should always be 0.

3

Rev. 5.00 Aug 08, 2006 page xxiii of lxxxvi

Item Page Revision (See Manual for Details)

11.3.9 Timer Synchronous
Register (TSYR)

11.4.1 Basic Functions 398 Description amended

11.4.2 Synchronous
Operation

11.4.3 Buffer Operation

Table 11.28 Register
Combinations in Buffer
Operation

11.4.6 Phase Counting
Mode

Table 11.31 Clock Input
Pins in Phase Counting Mode

397 Description amended

In the H8S/2227 Group, TSYR selects independent or
synchronous TCNT operation for channels 0 to 2. In other
groups, TSYR selects independent or synchronous TCNT
operation for channels 0 to 5. A channel performs ...

Table amended

SYNC5

Note * added

Note: * In the H8S/2227 Group, bits 5 to 3 are reserved.
The write value should always be 0.

Counter Operation:
(H8S/2227 Group) or bits CST5 to CST0 (groups other than
H8S/2227) in TSTR is set to 1, the TCNT counter for the
corresponding channel starts counting. TCNT can operate ...

402 Description amended

... For channels 0, 1, 3

Note * added

Note: * Not available in the H8S/2227 Group.

403 Description amended

... single time base.
to 5 (groups other than H8S/2227) can all be designated for
synchronous operation.

405 Table 11.28 amended

Channel 3

Note * added

Note: * Not available in the H8S/2227 Group.

416 Description amended

... incremented/decremented accordingly.
Group, this mode can be set for channels 1 and 2. In other
groups, it can be set for channels 1, 2, 4, and 5.

416 Table 11.31 amended

channel 1 or 5

Note * added

Note: * Not available in the H8S/2227 Group.

* SYNC4* SYNC3*

When one of bits CST2 to CST0

*

* channel 2 or 4*

*, and 4*, it is also possible ...

Channels 0 to 2 (H8S/2227 Group) or 0

In the H8S/2227

Rev. 5.00 Aug 08, 2006 page xxiv of lxxxvi

Item Page Revision (See Manual for Details)

11.4.6 Phase Counting
Mode

Figure 11.26 Example of
Phase Counting Mode 1
Operation

Table 11.32 Up/Down-Count
Conditions in Phase Counting
Mode 1

Figure 11.27 Example of
Phase Counting Mode 2
Operation

Table 11.33 Up/Down-Count
Conditions in Phase Counting
Mode 2

Figure 11.28 Example of
Phase Counting Mode 3
Operation

Table 11.34 Up/Down-Count
Conditions in Phase Counting
Mode 3

Figure 11.29 Example of
Phase Counting Mode 4
Operation

Table 11.35 Up/Down-Count
Conditions in Phase Counting
Mode 4

417 Figure 11.26 amended

(channels 1 and 5*) (channels 2 and 4*)

Note * added

Note: * Not available in the H8S/2227 Group.

418 Table 11.32 amended

(channels 1 and 5

Note * added

Note: * Not available in the H8S/2227 Group.

419 Figure 11.27 amended

(channels 1 and 5

Note * added

Note: * Not available in the H8S/2227 Group.

419 Table 11.33 amended

(channels 1 and 5

Note * added

Note: * Not available in the H8S/2227 Group.

419 Figure 11.28 amended

(channels 1 and 5

Note * added

Note: * Not available in the H8S/2227 Group.

420 Table 11.34 amended

(channels 1 and 5

Note * added

Note: * Not available in the H8S/2227 Group.

421 Figure 11.29 amended

(channels 1 and 5

Note * added

Note: * Not available in the H8S/2227 Group.

421 Table 11.35 amended

(channels 1 and 5

Note * added

Note: * Not available in the H8S/2227 Group.

*) (channels 2 and 4*)

*) (channels 2 and 4*)

*) (channels 2 and 4*)

*) (channels 2 and 4*)

*) (channels 2 and 4*)

*) (channels 2 and 4*)

*) (channels 2 and 4*)

Rev. 5.00 Aug 08, 2006 page xxv of lxxxvi

Item Page Revision (See Manual for Details)

11.5 Interrupt Sources 425 Description amended

Input Capture/Compare Match Interrupt:

In the H8S/2227 Group, the TPU has eight input

...
capture/compare match interrupts, four for channel 10 and
two each for channels 1 and 2. In other groups, the TPU has
16 input capture/compare match interrupts, four each for
channels 0 and 3, and two each for channels 1, 2, 4, and 5.

Overflow Interrupt:

In the H8S/2227 Group, the TPU has three overflow

...
interrupts, one each for channels 0 to 2. In other groups, the
TPU has six overflow interrupts, one each for channels 0 to

5.

Underflow Interrupt:

The TPU of the H8S/2227 Group has two underflow

...
interrupts, one each for channels 1 and 2. In other groups,
the TPU has four underflow interrupts, one each for
channels 1, 2, 4, and 5.

11.6 DTC Activation 425 Description amended

... Data Transfer Controller (DTC).
total of eight TPU input capture/compare match interrupts
can be used as DTC activation sources, four for channel 0
and two each for channels 1 and 2. In other groups, a total
of 16 TPU input capture/compare match interrupts can be
used as DTC activation sources, four each for channels 0
and 3, and two each for channels 1, 2, 4, and 5.

11.10.12 Contention
between TCNT Write and
Overflow/Underflow

Figure 11.54 Contention
between TCNT Write and
Overflow

11.10.14 Interrupts and
Module Stop Mode

440 Figure 11.54 replaced

440 Description amended

... source or the DMAC

Note * added

Note: * Supported only by the H8S/2239 Group.

* or DTC activation ...

In the H8S/2227 Group, a

Rev. 5.00 Aug 08, 2006 page xxvi of lxxxvi

Item Page Revision (See Manual for Details)

12.1 Features 441 Description amended

• Cascading of the two channels
... MR_2

* and TMR_3* cascading ...

442 Note * added

Note: *

Not available in the H8S/2237 Group and H8S/2227

Group.

Figure 12.1 Block Diagram
of 8-Bit Timer Module

12.2 Input/Output Pins

Table 12.1 Pin Configuration

442 Note * amended

Note: *

When a sub-clock is operating in power-down

mode, φ will be φ

443 Note * amended

Note: *

Not available in the H8S/2237 Group and H8S/2227

SUB

.

Group.

12.3 Register Descriptions 444 Note * amended

Note: *

Not available in the H8S/2237 Group and H8S/2227

Group.

12.3.1 Timer Counter
(TCNT)

444 Description amended

... (TCNT_2 and TCNT_3)

* comprise ...

Note * added

Note: * Not available in the H8S/2237 Group and H8S/2227
Group.

12.3.2 Time Constant
Register A (TCORA)

444 Description amended

... (TCORA_2 and TCORA_3)

* comprise ...

Note * added

Note: * Not available in the H8S/2237 Group and H8S/2227
Group.

12.3.3 Time Constant
Register B (TCORB)

445 Description amended

... (TCORB_2 and TCORB_3)

* comprise ...

Note * added

Note: * Not available in the H8S/2237 Group and H8S/2227
Group.

Rev. 5.00 Aug 08, 2006 page xxvii of lxxxvi

Item Page Revision (See Manual for Details)

12.3.4 Timer Control
Register (TCR)

446 Table amended

Bit Bit Name

2

CKS2

1

CKS1

0

CKS0

Initial
Value

0
0
0

R/W Description

R/W

Clock Select 2 to 0

R/W

The input clock can be selected from three clocks
divided from the system clock ( ). When use of an

R/W

external clock is selected, three types of count can be
selected: at the rising edge, the falling edge, and both
rising and falling edges.

000: Clock input disabled
001: φ/8 internal clock source, counted on the falling

edge

010: φ /64 internal clock source, counted on the falling

edge

011: φ /8192 internal clock source, counted on the

falling edge

100: For channel 0:

Counted on TCNT1 overflow signal

For channel 1:
Counted on TCNT0 compare-match A

For channel 2:
Counted on TCNT3 overflow signal

For channel 3:
Counted on TCNT2 compare-match A

101: External clock source, counted at rising edge
110: External clock source, counted at falling edge
111: External clock source, counted at both rising and

falling edges

Note 2 added

2. Not available in the H8S/2237 Group and

Note:
H8S/2227 Group.

12.3.5 Timer Control/Status
Register (TCSR)

449

• TCSR_1 and TCSR_3

Table amended

2

R/(W)*

1

*

450 Note 1 added

1. Not available in the H8S/2237 Group and

Note:
H8S/2227 Group.

451

• TCSR_2

1

*

Table amended

2

R/(W)*

452 Note 1 added

1. Not available in the H8S/2237 Group and

Note:
H8S/2227 Group.

1

*

1

2

*

2

*

*

1

*

1

*

Rev. 5.00 Aug 08, 2006 page xxviii of lxxxvi

Item Page Revision (See Manual for Details)

12.6 Operation with
Cascaded Connection

457 Description amended

... (TCR_2 and TCR_3)* ... (channel 2)* ... (channel 3)*

Note * added

Note: * Not available in the H8S/2237 Group and H8S/2227
Group.

12.7.1 Interrupt Sources and
DTC Activation

Table 12.2 8-Bit Timer
Interrupt Sources

458 Table 12.2 amended

Interrupt source Description

*

CMIA2
CMIB2
OVI2
CMIA3
CMIB3
OVI3

*

*

*
*

*

TCORA_2 compare-match
TCORB_2 compare-match
TCNT_2 overflow
TCORA_3 compare-match
TCORB_3 compare-match
TCNT_3 overflow

Note * added

Note: * Not available in the H8S/2237 Group and H8S/2227
Group.

12.8.7 Mode Setting of
Cascaded Connection

464 Description amended

... (TCNT_2 and TCNT_3)

* ...

Note * added

Note: * Not available in the H8S/2237 Group and H8S/2227
Group.

13.1 Features

Figure 13.1 Block Diagram
of WDT_0 (1)

Figure 13.1 Block Diagram

466 Figure 13.1 amended

Internal clock sources

Note 2 amended

Note: 2.

mode, φ will be φ

When a sub-clock is operating in power-down

SUB

467 Note *2 deleted

2

*

.

of WDT_1 (2)

13.4.2 Interval Timer Mode 474 Description added

... TCNT overflows.

(The NMI interrupt is not generated.)

Therefore, an interrupt can be generated at intervals.

13.4.4 Timing of Setting
Watchdog Timer Overflow
Flag (WOVF)

476 Description added

... If TCNT overflows ... entire chip.
not generated.) This timing is illustrated in figure 13.5.

(The WOVI interrupt is

Rev. 5.00 Aug 08, 2006 page xxix of lxxxvi

Item Page Revision (See Manual for Details)

14.1.3 Transfer Data (Data
Field Contents)

495 Subheading amended

(4) Locking/Unlocking (Control Bits: Setting (H'3, H'A, H'B),
Cancellation: (H'6))

14.3.3 IEBus Master Control
Register (IEMCR)

14.4.2 Slave Receive
Operation

Figure 14.10 Error

503 R/W description of CTL 3 to 0 amended

R/W

533 Figure 14.10 amended

Set the RxE flag and the master unit address in IE

MA2.

IE
Occurrence in the Broadcast
Reception (DEE=1)

15.3.2 Receive Data
Register (RDR)

15.3.5 Serial Mode Register
(SMR)

552 Description amended

subactive mode, subsleep mode, or ...

555

... watch mode,

• Smart Card Interface Mode (When SMIF in SCMR is 1)

Bit 7 GM and bit 6 BLK description added

Bit Bit Name

7 GM 0 R/W GSM Mode

Initial
Value R/W Description

When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND
setting is advanced by 11.0 etu (Elementary Time
Unit: the time for transfer of 1 bit), and clock output
control mode addition is performed. For details,
refer to section 15.7.8, Clock Output Control.

0: Normal smart card interface mode operation

(initial value)

• The TEND flag is generated 12.5 etu (11.5 etu
in the block transfer mode) after the beginning
of the start bit.

• Clock output on/off control only

1: GSM mode operation in smart card interface

mode

• The TEND flag is generated 11.0 etu after the
beginning of the start bit.

• In addition to clock output on/off control,
high/low fixed control is supported (set using
SCR).

MA1 and

Rev. 5.00 Aug 08, 2006 page xxx of lxxxvi