Renesas HD49335HNP, HD49335NP User Manual

HD49335NP/HNP

CDS/PGA & 10-bit A/D TG Converter

REJ03F0097-0100Z

Rev.1.0

Feb.12.2004

Description

The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip.

There are address map and timing generator charts besides this specification. May be contacted to our sales department
if examining the details.

Functions

• Correlated double sampling

• PGA

• Serial interface control

• 10-bit ADC

• Timing gener at or

• Operates using only the 3 V voltage

• Corresponds to switching mode of power dissipation and operating frequency

Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HNP)
Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335NP)

• ADC direct input mode

• QFN 64-pin package

Features

• Suppresses low-frequency noise, which output from CCD by the correlated double sampling.

• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and

registers.

• High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.

• PGA, pulse timing, standby mode, etc., is achieved via a serial interface.

• High precision is provided by a 10-bit-resolution A/D converter.

• Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization

(wave pattern). It is patented by Renesas.

• Timing gene rator generates the all of pulse which are needed for CCD driving.

Rev.1.0, Feb.12.2004, page 1 of 29

HD49335NP/HNP

Pin Arrangement

VRM

VRT

VRB

BIAS

ADC_in

3

SS

AVSSDV

STROB

SUB_PD

SUB_SW

XSUB

CH4

CH3

CH2

CH1

XV4

Pin Description

AV

DD

BLKC

CDS_in

AV

DD

BLKFB

BLKSH

AV

SS

Test2
Test1

DLL_C

DV

DD

MON

41cont

CS

SDATA

SCK

48 47 3946 45 44 43 42 41 40 38 36 35 3437

49
50
51
52
53
54
55
56
57
58

1

59
60
61
62
63
64

12 103 4 5 6 7 8 9 11 12 13 14 15

ID

D0D1D2D3D4D5D6D7D8

1,2

SS

DV

(Top view)

D9

2

DD

DV

3

SS

DV

33

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

16

HD_in

CLK_in

XV3
XV2
XV1

3

DV

DD

4

DV

DD

1/4clk_o
H2A

4

DV

SS

4

DV

SS

1/2clk_o
H1A

4

DV

DD

3

DV

DD

RG
Reset
VD_in

Pin No. Symbol Description

1 ID Odd/even number line detecting pulse output pin O D 2 mA/10 pF
2 DVSS1,2 CDS Digital ground + ADC output buffer ground (0 V) — D
3 to 12 D0 to D9 Digital output (D0; LSB, D9; MSB) O D 2 mA/10 pF
13 DVDD2 ADC output buffer power supply (3 V) — D
14 DVSS3 General ground for TG (0 V) — D
15 CLK_in CLK input (max 72 MHz) I D
16 HD_in HD input I/O D
17 VD_in VD input I/O D
18 Reset Hardware reset (for DLL reset) I D Schmitt trigger
19 RG Reset gate pulse output O D 3 mA/10 pF
20 DVDD3 General power supply for TG (3 V) — D
21 DVDD4 H1 buffer power supply (3 V) — D
22 H1A H.CCD transfer pulse output-1A O D 30 mA/165 pF
23 1/2clk_o CLK_in 2 divided output. 3 divided out put at 3 divided m ode O D 2 mA/10 pF
24 DVSS4 H1 buffer ground (0 V) — D
25 DVSS4 H1 buffer ground (0 V) — D
26 H2A H.CCD transfer pulse output-2A O D 30 mA/165 pF
27 1/4clk_o CLK_in 4 divided output. 6 divided out put at 3 divided m ode O D 2 mA/10 pF
28 DVDD4 H2 buffer power supply (3 V) — D
29 DVDD3 General power supply for TG (3 V) — D

I/O

Analog(A) or
Digital(D)

Remarks

Rev.1.0, Feb.12.2004, page 2 of 29

HD49335NP/HNP

Pin Description (cont.)

Pin No. Symbol Description

30 XV1 V.CCD transfer pulse output-1 O D 2 mA/10 pF
31 XV2 V.CCD transfer pulse output-2 O D 2 mA/10 pF
32 XV3 V.CCD transfer pulse output-3 O D 2 mA/10 pF
33 XV4 V.CCD transfer pulse output-4 O D 2 mA/10 pF
34 CH1 Read out pulse output-1 O D 2 mA/10 pF
35 CH2 Read out pulse output-2 O D 2 mA/10 pF
36 CH3 Read out pulse output-3 O D 2 mA/10 pF
37 CH4 Read out pulse output-4/XV6 at stripe mode O D 2 mA/10 pF
38 XSUB Pulse output for electronic shutter O D 2 mA/10 pF
39 SUB_SW SUB voltage control output-1. ADCK input I/O D 2 mA/10 pF
40 SUB_PD SUB voltage control output-2/ XV5 at stripe mode O D 2 mA/10 pF
41 STROB Flash control output. Input Vgate at Hi of pin 61 I/O D 2 mA/10 pF
42 DVSS3 General ground for TG (0 V) — D
43 AVSS Analog ground (0 V) — A
44 ADC_in AD converter input pin I A
45 BIAS Bias standard resistance — A
46 VRB ADC bottom standard voltage (0.1 µF for GND) — A
47 VRT ADC top standard voltage (0.1 µF for GND) — A
48 VRM ADC middle standard voltage (0.1 µF for GND) — A
49 AVDD Analog power supply (3 V) — A
50 BLKC Black level C pin (1000 pF for GND) — A
51 CDS_in CDS input pin I A
52 AVDD Analog power supply (3 V) — A
53 BLKFB Black level FB pin (1 µF between BLKFB and BLKSH) I A
54 BLKSH Black level S/H pin O A
55 AVSS Analog ground (0 V) — A
56 Test2

57 Test1 L: Slave mode, H: Master mode I D
58 DLL_C Analog delay DLL external C pin (100 pF for GND) O A
59 DVDD1 Digital power supply (3 V) CDS, PAG, ADC part — D
60 MON Pulse monitor (SP1, SP2, ADCK, OBP, CPDM, PBLK input) O D 2 mA/10 pF
61 41cont

62 CS Serial data CS at CDS part I D
63 SDATA Input serial data I D
64 SCK Input serial clock I D

H: Normal operation, L: CDS single operation mode
Input 36; PBLK at testing, Input 37; OBP, Input 38; CPDM,
Input 39; ADCK, Input 40; SP2, Input 41; SP1

Input STROB = pin 41, Input SUB_SW = pin 39 at Low
Input Vgate = pin 41, Input ADCK = pin 39 at Hi

Analog(A) or

I/O

Digital(D)

I D

I D

Remarks

Rev.1.0, Feb.12.2004, page 3 of 29

HD49335NP/HNP

A

Input/Output Equivalent Circuit

Pin Name Equivalent Circuit

Digital output

Digital input CLK_in, HD_in, VD_in,

Analog

D0 to D9, HD_in, VD_in,
H1A, H2A, 1/2clk_o,
1/4clk_o, 41cont,
SUB_SW, SUB_PD

ID, RG, MON, XV1 to XV4,
CH1 to CH4, XSUB

ADCLK, OBP, SPBLK,
SPSIG, CS, SCK, SDATA,
PBLK, OEB, Reset, Test1,
Test2, SUB_SW, STROB

CDS_in

DIN

ENABLE

DIN

Digital
input

Note: Only OEB is pulled down to about 70 kΩ.

AV

DD

CDS_in

DV

DV

DD

DD

Digital
output

*1

DV

DD

Digital
output

Internally
connected
to VRT

ADC_in

DC_in

AV

DD

Internally
connected
to VRT

BLKSH, BLKFB, BLKC

AV

DD

VRT, VRM, VRB

BLKFB

+

−

VRT

+

−

+

−

VRB

AV

BLKSH

BLKC

VRM

DD

+

−

BIAS

AV

DD

BIAS

Rev.1.0, Feb.12.2004, page 4 of 29

HD49335NP/HNP

Block Diagram

XSUB

CH4

CH3

CH2

CH1

XV4

XV3

XV2

XV1

1/4clk_o

H2A

1/2clk_o

H1A

RG

VD_in

HD_in

CLK_in

AVDDDV

1 to 4

DD

SUB_SW

SUB_PD

STROB

ADC_in

CDS_in

BLKSH

BLKC

BLKFB

CDS

DC offset

compensation

circuit

ID

MON

DLL_C

PBLK

CPDM

PGA

Serial

interface

SCK

SDATA

OBP

CS

DLL

SP2

ADCLK

Bias

generator

SP1

BIAS

10bit
ADC

VRT

Timing

generator

VRB

VRM

AV

SS

DV

SS

Reset

D9

D8

D7

D6

D5

D4

D3

Output latch circuit

D2

D1

D0

1 to 4

Rev.1.0, Feb.12.2004, page 5 of 29

HD49335NP/HNP

Internal Functions

Functional Description

• CDS input
 CCD low-frequency noise is suppressed by CDS (correlated double sampling).
 The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *
 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *

• ADC input
 The center level of the input signal is clamped at 512 LSB (Typ).
 Gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57

times (–4.86 dB) to 5.14 times (14.22 dB). *

2

• Automatic offset calibration of PGA and ADC

• DC offset compensation feedback for CCD and CDS

• Pre-blanking
 Digital output is fixed at clamp level

• Digital outputs enable function

Note: 1. It is not covered by warranty when 14LSB settings

2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

Operating Description

1

2

Figure 1 shows CDS/PGA + ADC function block.

C3

ADC_in

CDS
AMP

BLKSH

Gain setting

(register)

Current

DAC

BLKC

C4

PG
AMP

DAC

Clamp data

(register)

10bit
ADC

D0 to D9

Offset

calibration

logic

DC offset
feedback

logic

OBP

CDS_in

SP1

SP1

VRT

BLKFB

SP2

C2

C1

SH
AMP

Figure 1 CDS/PGA Functional Block Diagram

1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The

black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SP2 pulse, and then provided to CDSAMP (see figure 1).
The difference between these two signal levels is extracted by the CDSAMP, which also operates as a
programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK
period, the above sampling and bias operation are paused.

2. PGA Circuit
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain

using 8 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 255.

In CDSIN mode: Gain = (–2.36 dB + 0.033 dB) × N (LOG linear).
In ADCIN mode: Gain = (0.57 times + 0.001784 times) × N (linear).
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

Rev.1.0, Feb.12.2004, page 6 of 29

HD49335NP/HNP

3. Automatic Offset Calibration Function and Black-Level Cla mp Data Settings
The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data
(14 LSB to 76 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).

4. DC Offset Co mpe nsation Feedback Function
Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is
the one cycle of the OBP.

∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example: When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039

When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8
times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain
(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.
The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 16 LSB, the high-speed lead-in operation continues,
and when the offset error is 16 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. (Refer to table 2.)

Table 1 Loop Gain Multiplication Factor during

High-Speed Lead-In Operation

HGain-Nsel

(register settings)

[0]

L
H
L
H

[1]

L

L
H
H

Multiplication

Factor N

4

8
16
32

Table 2 High-Speed Lead-In Operation

Cancellation Time

HGstop-Hsel

(register settings)

[0]

L

H

L

H

[1]

L
L
H
H

Cancellation

Time

1 H
2 H
4 H
8 H

5. Pre-Blanking Function
During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (14 to 76 LSB).

Rev.1.0, Feb.12.2004, page 7 of 29

HD49335NP/HNP

6. ADC Digital Outp ut Control Function
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the cod es.

Table 3 ADC Digital Output Functions

ADC Digital Output

STBYD9TEST0

H
L

Note: 1. STBY, TEST, LINV, and MINV are set by register.

TEST1

LINV

X

X

X
L

H

L

L

L
H
H
X
L

H

L
H
H
X
L

X

L
H
H

MINV

X
L
H
L
H
X
L
H
L
H
X
L
H
L
H

PBLK

Hi-Z

X

Same as in table 4.

L

D9 is inverted in table 4.

L

D8 to D0 are inverted in table 4.

L

D9 to D0 are inverted in table 4.

L

Output code is set up to Clamp Level.

H

Same as in table 5.

L

D9 is inverted in table 5.

L

D8 to D0 are inverted in table 5.

L

D9 to D0 are inverted in table 5.

L

Output code is set up to Clamp Level.

H
X
X
X
X

H

L

L

H

L

H

L

H

H

L

H

L

D0D1D2D3D4D5D6D7D8

L

H

L

H

L

L

H

L

H

L

H

L

H

H

L

H

L

H

L

H

H

L

H

H

L

H

Operating Mode

Low-power wait state
Normal operation

Pre-blanking
Normal operation

Pre-blanking

L

Test mode

L

Table 4 ADC Output Code (Binary)

Output Pin

Output
codes

Steps

3
4
5
6

511
512

1020
1021
1022
1023

Table 5 ADC Output Code (Gray)

Output Pin

Output
codes

Steps

3
4
5
6

511
512

1020
1021
1022
1023

D9

D9

D8

L
L
L
L

L
H

H
H
H
H

D8

L
L
L
L

L
H

H
H
H
H

D7

L
L
L
L

H
L

H
H
H
H

D7

L
L
L
L

H
H

L
L
L
L

D6

L
L
L
L

H
L

H
H
H
H

D6

L
L
L
L

L
L

L
L
L
L

D5

L
L
L
L

H
L

H
H
H
H

L
L
L
L

L
L

L
L
L
L

L
L
L
L

H
L

H
H
H
H

D5

L
L
L
L

L
L

L
L
L
L

D4

H

H
H
H
H

D4

D3

L
L
L
L

L

D3

L
L
L
L

L
L

L
L
L
L

D2

L
L
L
L

H
L

H
H
H
H

D2

L
L
L
L

L
L

L
L
L
L

D1

L
H
H
H

H
L

H
H
H
H

L
H
H
H

L
L

L
L
L
L

H
L
L
H

H
L

L
L
H
H

D1

H
H
H
L

L
L

H
H
L
L

D0

D0

H
L
H
L

H
L

L
H
L
H

L
L
H
H

L
L

L
H
H
L

Rev.1.0, Feb.12.2004, page 8 of 29

HD49335NP/HNP

7. Adjustment of Black-Level S/H Response Frequency Characteristics
The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the
register settings, as shown in tabl e 6.

Table 6 SHSW CR Time Constant Setting

SHSW-fsel (Register setting)

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

L

[1]

L

L

[2]

L

L

H

2.30 nsec
(69 MHz)

[3]

[0]

H

H

4.80 nsec
(33 MHz)

L

[1]

L

L

[2]

L

L

L

2.51 nsec
(63 MHz)

[3]

[0]

H

L

5.87 nsec
(27 MHz)

H

L

L

H

H

L

L

L

2.64 nsec
(60 MHz)

SHSW-fsel (Register setting)

[1]

[2]

[3]

[0]

[1]

H

L

H

H

H

6.60 nsec
(24 MHz)

[2]

L

2.93 nsec
(54 MHz)

[3]

[0]

H

L

8.80 nsec
(18 MHz)

L

[1]

L

H

[2]

H

L

H

3.11 nsec
(51 MHz)

[3]

[0]

H

H

10.6 nsec
(15 MHz)

L

[1]

L

H

[2]

H

L

L

3.52 nsec
(45 MHz)

[3]

[0]

H

L

17.6 nsec
(9 MHz)

H

[1]

H

H

[2]

H

L

CR Time Constant (Typ)
(cutoff frequency conversion)

CR Time Constant (Typ)
(cutoff frequency conversion)

2.20 nsec
(72 MHz)

[0]

L

4.40 nsec
(36 MHz)

[3]

[0]

L

H

3.77 nsec
(42 MHz)

[3]

[0]

H

H

26.4 nsec
(6 MHz)

[1]

H

[1]

H

[3]

[2]

H

L

[2]H[3]

H

The SHAMP frequency characteristics can be adjusted by changing the register settings

8.
and the C4 value of the external pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.

Recommendation value of C is 1000 pF

Table 7 SHAMP Frequency Characteristics Setting

SHA-fsel (Register setting)

LoPwr

(Register setting)

"Lo"

"Hi" 24 MHz

Note: Upper line

Middle line
Lower line

[0]

L

230 MHz

6800 pF

(240 pF)

100 MHz

10000 pF

(560 pF)

: SHAMP cutoff frequency (Typ)
: Standard value of C4 (maximum value is not defined)
: Minimum value of C4 (do not set below this value)

[1]

L

[0]

H

116 MHz

10000 pF

(270 pF)

49 MHz

15000 pF

(620 pF)

[1]

L

[0]

L

75 MHz

13000 pF

(300 pF)

32 MHz

22000 pF

(750 pF)

[1]

H

BLKC

31

[0]

C

H

56 MHz

18000 pF

(360 pF)

27000 pF

(820 pF)

[1]

H

Rev.1.0, Feb.12.2004, page 9 of 29

HD49335NP/HNP

Timing Chart

Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.

012 91011

• When CDS_in input mode is used

CDS_in

SP1

SP2

ADCLK

D0 to D9

• When ADC_in input mode is used

N

ADC_in

N+1 N+2 N+9 N+10 N+11N

N−9N−8N−1 NN−10

N+1

N+2

~

N+8

N+9

N+10

N+11

ADCLK

D0 to D9

N−8N−9N−1

N N+1

Figure 2 Output Timing Chart w hen CDSIN and ADCIN Input Modes are Used

• The ADC output (D0 to D9) i s output at the r ising edge of t he ADCLK in b oth modes.

• Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used.

• In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.

Rev.1.0, Feb.12.2004, page 10 of 29

HD49335NP/HNP

A

Detailed Timing Specifications

Detailed Timing Specifications when CDSIN Input Mode is Used

Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.

Black

level

CDS_in

(2)

SP1 Vth

SP2

DCLK

D0 to D9

H1

(11)

(13)

(7)

(12)

(1)

Signal

(5)

level

(4)

(6)

(8)

(3)

(9)

(10)

Vth

Vth

Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used

Table 8 Timing Specifications when the CDSIN Input Mode is Used

No. Timing Symbol Min Typ Max Unit

(1) Black-level signal fetch time t
(2) SP1 ‘Hi’ period t
(3) Signal-level fetch time t
(4) SP2 ‘Hi’ period t
(5) SP1 falling to SP2 falling time t
(6) SP1 falling to ADCLK rising inhibit time t
(7), (8) ADCLK tWH min./tWL min t
(9) ADCLK rising to digital output holding time t
(10) ADCLK rising to digital output delay time t
(11) H1 rising to ADCLK rising time t
(12) H1 rising to SPSIG falling time t
(13) H1 rising to SPBLK falling time t

— (1.5) — ns

CDS1

Typ × 0.8 1/4f

CDS2

— (1.5) — ns

CDS3

Typ × 0.8 1/4f

CDS4

Typ × 0.85 1/2f

CDS5

— (5) — ns

CDS6

11 — — ns

CDS7, 8

— (7) — ns

CHLD9

— (16) — ns

COD10

— (1/4f

CDS11

— (1/f

CDS12

— (1/2f

CDS13

Typ × 1.2 ns

CLK

Typ × 1.2 ns

CLK

Typ × 1.15 ns

CLK

) — ns

CLK

) — ns

CLK

) — ns

CLK

OBP Detailed Timing Specifications

Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black

signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).

OB period *

CDS_in

OBP

Note:

1. Shifts ±1 clock cycle depending on the OBP input timing.

N N+1 N+5 N+12 N+13

OB pulse > 2 clock cycles

Figure 4 OBP Detailed Timing Specifications

Rev.1.0, Feb.12.2004, page 11 of 29

1

HD49335NP/HNP

A

A

Detailed Timing Specifications at Pre-Blanking

Figure 5 shows the pre-blanking detailed timing specifications.

PBLK

Digital output

(D0 to D9)

ADC

data

Clamp Level

ADCLK × 2 clock ADCLK × 10 clock

ADC
data

Vth

V

V

OH

OL

Figure 5 Detailed Timing Specifications at Pre-Blanking

Detailed Timing Specifications when ADCIN Input Mode is Used

Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.

DC_in

DCLK

D0 to D9

(2)

(3)

(1)

(4)

(5)

Vth

VDD/2

Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used

Table 9 Timing Specifications when ADCIN Input Mode is Used

No. Timing Symbol Min Typ Max Unit

(1) Signal fetch time t
(2), (3) ADCLK tWH min./tWL min. t
(4) ADCLK rising to digital output hold time t
(5) ADCLK rising to digital output delay time t

— (6) — ns

ADC1

Typ × 0.85 1/2f

ADC2, 3

— (14.5) — ns

AHLD4

— (23.5) — ns

AOD5

Typ × 1.15 ns

ADCLK

Rev.1.0, Feb.12.2004, page 12 of 29

HD49335NP/HNP

Dummy Clamp

It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it
woks with the OB clamp, however when black level is out of the range caused by hightlight enter to OB part, it changes
to clamp processing by dummy bit level. Resister settings are follows.

D12, D11, D10 of address H'F7 (Dummy CP)
0, 0, 0 ; OFF
0, 0, 1 ; +32
0, 1, 0 ; +64
0, 1, 1 ; +96
:
:
1, 1, 1 ; +224
The amount of offset are changes automatically
depends on PGA gain in the LSI.

D8, D8 of address H'F7 (DMCG)
The amount of feed back current can be
reduced with only dummy clamp.
Data = 0:1/4
1:1/8
2:1/16
3:1/32

CDS_in

SP1

VRT

BLKFB

SP2

SP1

SH
AMP

CDS
AGC

ADC

D8 to D9 of address H'F7

Current

cell

BLKSH

−

+

Clamp level

Detect 8clk
from OBP edge

(−)

(+)

on/off

D10 to D12 of address H'F7

Note: OB/Dummy switching part has 1/8 hysteresis of threshold value.

Figure 7 Internal Bias Circuitry

OB

DET

+

−

Digital output

Dummy

Detect 4clk

DET

from OPDM edge

+

Rev.1.0, Feb.12.2004, page 13 of 29

HD49335NP/HNP

Absolute Maximum Ratings

(Ta = 25°C)

Item Symbol Ratings Unit

Power supply voltage VDD 4.1 V
Analog input voltage VIN –0.3 to AVDD +0.3 V
Digital input voltage VI –0.3 to DVDD +0.3 V
Operating temperature range Ta –10 to +75 °C
Power dissipation Pt 750 mW
Storage temperature Tstg –55 to +125 °C
Power supply voltage Vopr 2.70 to 3.30 V
Note: AVDD, AVSS are analog power source syste ms of CDS, PGA, and ADC.

DVDD1, DVSS1 are digital power source systems of CDS, PGA and ADC.
DV

2, DVSS2 are buffer power source systems of ADC output.

DD

DV

3, DVSS3 are general digital power source systems of TG.

DD

DV

4, DVSS4 are buffer power source systems of H1 and H2.

DD

• Pin 2 multi bonds the DV

• When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output
When Hi, pin 41 = Vgate input, pin 39 = ADCK input

1 and DVSS2

SS

Electrical Characteristics

(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and R

= 33 kΩ)

BIAS

• Items Common to CDSIN and ADCIN Input Modes

Item Symbol Min Typ Max Unit Test Conditions Remarks

Power supply voltage
range

Digital input voltage

ADC resolution RES 10 10 10 bit
ADC integral linearity INL — (2) — LSBp-p f
ADC differential linearity+ DNL+ — 0.3 0.99 LSB f
ADC differential linearity– DNL– –0.99 –0.3 — LSB f
Sleep current I

Standby current I

Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.

2. 2 divided mode: f

3 divided mode: f

3. Values within parentheses ( ) are for reference.

2.70 3.00 3.30 V

V

DD

f

hi 20 — 36 MHz LoPwr = low *2 HD49335HNP Conversion frequency

CLK

f

low 5.5 — 25 MHz LoPwr = high *2 HD49335NP

CLK

V

IH2

0 —

V

IL2

2.25 ×

DV

3.0

DD

— DV

0.6 ×

V

DD

DV

3.0

V

DD

CS, SCK, SDATA

VOH DVDD –0.5 — — V IOH = –1 mA Digital output voltage
V

— — 0.5 V IOL = +1 mA

OL

IIH — — 50 µA VIH = 3.0 V Digital input current
I

–50 — — µA VIL = 0 V

IL

= 25 MHz

CLK

= 25 MHz *1

CLK

= 25 MHz *1

CLK

–100 0 100 µA

SLP

Digital input pin is
set to 0 V, output
pin is open

— 3 5 mA

STBY

Digital I/O pin is set
to 0 V

= 1/2CLK_in

CLK

= 1/3CLK_in

CLK

Rev.1.0, Feb.12.2004, page 14 of 29

HD49335NP/HNP

Electrical Characteristics (cont.)

(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and R

= 33 kΩ)

BIAS

• Items for CDSIN Input Mode

Item Symbol Min Typ Max Unit Test Conditions Remarks

Consumption current (1) I

Consumption current (2) I

CCD offset tolerance range V
Timing specifications (1) t
Timing specifications (2) t
Timing specifications (3) t
Timing specifications (4) t
Timing specifications (5) t
Timing specifications (6) t
Timing specifications (7) t
Timing specifications (8) t
Timing specifications (9) t
Timing specifications (10) t
Timing specifications (11) t
Timing specifications (12) t
Timing specifications (13) t
Clamp level

— 84 96.6 mA f

DD1

— 58 66.7 mA f

DD2

(–100) — (100) mV

CCD

— (1.5) — ns

CDS1

Typ × 0.8 1/4f

CDS2

— (1.5) — ns

CDS3

Typ × 0.8 1/4f

CDS4

Typ × 0.85 1/2f

CDS5

1 5 9 ns

CDS6

— 1/2f

CDS7

— 1/2f

CDS8

— (7) — ns CL = 10 pF

CHLD9

— (16) — ns CL = 10 pF

COD10

— (1/4f

CDS11

— (1/f

CDS12

— (1/2f

CDS13

Typ × 1.2 ns

CLK

Typ × 1.2 ns

CLK

Typ × 1.15 ns

CLK

— ns

CLK

— ns

CLK

) — ns

CLK

) — ns

CLK

) — ns

CLK

CLP(00) — (14) — LSB
CLP(09) — (32) — LSB
CLP(31) — (76) — LSB

PGA gain at CDS input

AGC(0) –4.4 –2.4 –0.4 dB
AGC(63) 4.1 6.1 8.1 dB
AGC(127) 12.5 14.5 16.5 dB
AGC(191) 21.0 23.0 25.0 dB
AGC(255) 29.4 31.4 33.4 dB

DLL operation frequency

DLL_2 11 — 25 MHz *2
DLL_3 7 — 11 MHz *3
DLL_4 5.5 — 7 MHz *4

T/G 3/1divided operation

CLK_in3 28.6 — 28.6 MHz f

frequency range
H Buffer output voltage

VOH 2.94 2.97 — V 30 mA Buff, IOH = –5 mA
VOL — 22 47 MV 30 mA Buff, IOL = +5 mA
VOH 2.89 2.94 — V 14 mA Buff, IOH = –5 mA
VOL — 50 112 MV 14 mA Buff, IOL = +5 mA
VOH 2.91 2.96 — V 10 mA Buff, IOH = –3 mA
VOL — 36 78 MV 10 mA Buff, IOL = +3 mA
VOH 2.85 2.93 — V 4 mA Buff, IOH = –2 mA
VOL — 60 129 MV 4 mA Buff, IOL = +2 mA
VOH 2.69 2.86 — V 2 mA Buff, IOH = –2 mA

— 115 262 mV 2 mA Buff, IOL = +2 mA

V

OL

VOH 2.81 2.90 — V IOH = –2 mA RG output voltage
V

— 78 141 mV IOL = +2 mA

OL

Notes: 1. Define digital output full scall with 1 V input as 0 dB.

2. Number of master steps: 60 steps, DLL current High

3. Number of master steps: 40 steps, DLL current Low

4. Number of master steps: 60 steps, DLL current Low

5. Values within parentheses ( ) are for reference.

= 36 MHz

CLK

= 20 MHz

CLK

= 1/3CLK_in3

CLK

CDSIN mode
LoPwr = low

CDSIN mode
LoPwr = high

Refer to table 8

*1

Rev.1.0, Feb.12.2004, page 15 of 29

HD49335NP/HNP

Electrical Characteristics (cont.)

(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and R

= 33 kΩ)

BIAS

• Items for ADCIN Input Mode

Item Symbol Min Typ Max Unit Test Conditions Remarks

Consumption current (3) I

Consumption current (4) I

Timing specifications (14) t
Timing specifications (15) t
Timing specifications (16) t
Timing specifications (17) t
Timing specifications (18) t

DD3

DD4

ADC1

ADC2

ADC3

AHLD4

AOD5

Input current at ADC input IIN

— 32 38.4 mA f

— 22 27.5 mA f

— (6) — ns
Typ × 0.85 1/2f
Typ × 0.85 1/2f

Typ × 1.15 ns

ADCLK

Typ × 1.15 ns

ADCLK

— (14.5) — ns CL = 10 pF

— (23.5) — ns CL = 10 pF

–110 — 110 µA VIN = 1.0 to 2.0 V

CIN

= 36 MHz

CLK

= 25 MHz

CLK

Clamp level at ADC input OF2 — (512) — LSB
PGA gain at ADC input

GSL(0) 0.45 0.57 0.72 Times
GSL(63) 1.36 1.71 2.16 Times
GSL(127) 2.27 2.86 3.60 Times
GSL(191) 3.18 4.00 5.04 Times
GSL(255) 4.08 5.14 6.47 Times

Note : Values within parentheses ( ) are for reference.

ADCIN mode
LoPwr = low

ADCIN mode
LoPwr = high

Refer to table 9

Rev.1.0, Feb.12.2004, page 16 of 29

HD49335NP/HNP

Serial Interface Specifications

Timing Specifications

Data is determined
at CS rising edge

t

CS

SCK

SDATA

t

INT1

Latches SDATA
at SCK rising edge

t

su

D9D8 D11D10 D13D12 D15D14 D1D0 D3D2 D5D4 D7D6 D0 D2D1 D4D3 D6D5 D7

STD2(Upper data) STD1(Lower data) address(address)

f

SCK

t

ho

Figure 8 Serial Interface Timing Specifications

Item Min Max

f

— 5 MHz

SCK

t

50 ns —

INT1,2

tsu 50 ns —
tho 50 ns —

Notes: 1. 3 byte continuous communications.

2. Input SCK with 24 clock when CS is Low.

3. It becomes invalid when data communications are stop ped o n the way .

4. Data becomes a default with hardware reset.

5. Input more than double frequency of SCK to the CLK_in when transfer
the serial data.

The Kind of Data

Data address has 256 type. H’00 to H’FF

H’00
:
:
H’EF

H’F0
:
:
H’FF

Data at timing generator part

Data at CDS part

Address map of each data referred to other sheet.
Details of timing generator refer to the timing chart on the other sheet together with this specification.
This specification only explains about the data of CDS part.

INT2

Rev.1.0, Feb.12.2004, page 17 of 29

HD49335NP/HNP

Explanation of Serial Data of CDS Part

Serial data of CDS part are assigned to address H’F0 to H’F8. Functions are follows.

Address STD1[7:0] (L)

1 1 1 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14

PGA gain

test_I1

STD2[15:8] (H)

D13

• PGA gain (D0 to D7 of address H’F0)
Details are referred to page 5 block diagram.

At CDS_in mode: –2.36 dB + 0.132 dB × N (Log linear)
At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear)
∗: Full-scale digital output is defined as 0 dB when 1 V is input.

Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB – 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
on.

(1.0 V) (2.0 V)

(1.0 V)

CDS PGA

(1023)

ADC

0 dB when set N = 18 which correspond to 2.36 dB

(1) Level dia explain

2 V 1023

CDS PGA

(CDS = 0 dB)

3.64 dB + 0.132 dB × N

(2) Level dia on the circuit

ADC

Figure 9 Level Dia of PGA

• Test_I1 (D13 to D15 of address H’F0)
It controls the standard current of analog amplifier systems of CDS, PGA. Use data = 4 (D15 = 1) normally.

When data = 0, 50% current value with default
When data = 4, default
When data = 7, 150% current value with default

Address STD1[7:0] (L) STD2[15:8] (H)

1 1 1 1 0 0 0 1 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8

SHA_fseltest_I2 SHSW_fsel

test0

MINV

LINV

STBY

SLP

• SLP and STBY (D0, D1 of address H’F1)
SLP: Stop the all circuit. Consumption current of CDS part is less than 10 µA.
Start up from offset calibration when recover is needed.
STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.
Allow 50 H time for feedback clamp is stabilized until recover.

Rev.1.0, Feb.12.2004, page 18 of 29

HD49335NP/HNP

• Output mode (D2 to D4 of address H’F1 and address H’F4 of D6)
It is a test mode. Combination details are table 3 to 5. Normally set to all 0.

• SHA-fsel (D8 to D9 of address H’F1)
It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 8. To get rough idea, set the

double cut off freque ncy point with using.

• SHSW-fsel (D10 to D13 of address H’F1)
It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page

8. To get rough idea, set the double c ut off frequency point with using. S/N changes by this data, so find the
appropriate point with set data to up/down.

• Test_I2 (D14 to D15 of address H’F1)
Current of ADC analog part can be set minutely. Normally use data = 0.

0: Default (100%)
1: 150%
2: 50%
3: 80%

Address STD1[7:0] (L)

1 1 1 1 0 0 1 0 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9

Clamp level

Reset

STD2[15:8] (H)

AD_sel

CDS_buff

HGain-Nsel

Low_pwr

• Clamp (D0 to D4 of address H’F2)
Determine the OB part level with digital code of ADC output.

Clamp level = setting data × 2 + 14
Default data is 9 = 32 LSB.

• HGstop-Hsel, HGain-Nsel (D8 to D11 of address H’F2)
Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch

the high speed leading mode. Transfer the gain +1/–1 to previous field, its switch to high speed leading mode.

• Low_PWR (D12 of address H’F2)
Switch cir cuit current and freque ncy characteristic.

Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee

• ADSEL (D14 of address H’F2)

Data = 0: Select CDS_in
Data = 1: Select ADC_in

• Reset (D15 of address H’F2)
Software reset.

Data = 1: Normal
Data = 0: Reset

Offset calibration should be done when starting up with using this bit. Details are referred to page 23.

D8

HGstop-Hsel

Address STD1[7:0] (L) STD2[15:8] (H)

11110011 D4D3D2D7 D6 D5 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8

• Address H'F3 are all testing data.
Normally set to all 0., or do not transfer the data.

Rev.1.0, Feb.12.2004, page 19 of 29

HD49335NP/HNP

Address STD1[7:0] (L) STD2[15:8] (H)

11110100 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8

VD latch MON

H12_Buff

• MON (D0 to D2 of address H’F4)
Select the pulse which output to pin MON (pin 60).

When D0 to D2: 0, Fix to Low When 1, ADCLK
When 2, SP1 When 3, SP2
When 4, OBP When 5, PBLK
When 6, CPDM When 7, DLL_test

• H12Baff (D3 to D6 of address H’F4)
Select the buffer size which output to pin H1A, H2A (pin 22, 26).

D3: 2 mA buffer
D4: 4 mA buffer
D5: 10 mA buffer
D6: 14 mA buffer

Above data can be on/off individually. Default is D6 can be on only. (18 mA buffer)

• VD latch (D7 of address H’F4)

Data = 0: Gain data is determined when CS rising
Data = 1: Gain data is determined when VD falling

Differential Code and Gray Code (D8 to D12 of address H’F4)

• Gray code (D8 to D9 of address H’F4)
DC output code can be change to following type.

Gray Code [1] Gray Code [0] Output Code

0 0 Binary code
0 1 Gray code
1 0 Differential encoded binary
1 1 Differential encoded gray

• Serial data setting items (D10 to D12 of address H’F4)

Setting Bit Setting Contents

Gray_test[0]
Gray_test[1]
Gray_test[2] ADCLK polar with OBP. (Lo→Positive edge, HI→Negative edge)

Standard data output timing control signal
(Refer to the following table)

• Standard data output timing

Gray_test[1] Gray_test[0] Standard Data Output Timing

Low Low Third and fourth
Low High Fourth and fifth
High Low Fifth and sixth
High High Sixth and seventh

Gray_test

Gray code

Rev.1.0, Feb.12.2004, page 20 of 29

HD49335NP/HNP

A

Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in
parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss
quantization) occurs to the image.
Differential code and gray code are recommended for this countermeasure.
Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital
output bit can be reduced and easily to reduce the ripple using this function.
This function is especially effective for longer the settings of sensor more than clk = 30 kHz, and ADC outp ut.
Figure 11 indicates the timing specifications.

Differential SW(D9)

10

ADC

Standard data
control signal
(D12,D11,D10)

2clk_DL

+

−

Carry bit
round

Standard
data
selector

Gray SW(D8)

Gray→Binary
conversion

10-bit
output

Figure 10 Differential Code, Gray Code Circuit

(In case of select the positive edge of ADCLK with D12)

DCLK

OBP

Digital output

(In case of select the positive polar)

Differential data Standard

(Beginning edge of OBP and standard edge of ADCLK should be exept ±5 ns)

1

234567891011

Differential data

data

Figure 11 Differential Code Timing Specifications

To use differential code, complex circuit is necessary at DSP side.

D11 D11

D10

D9

D0

D10

D9

D0

(2) Gray → Binary conversion

From ADC

Standard data
control signal

Carry bit

Gray →
Binary

round

(1) Differential coded

Standard
data
selector

2clk_DL

Figure 12 Complex Circuit Example

Address STD1[7:0] (L) STD2[15:8] (H)

11110101 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8

P_SP1P_SP2P_ADCLKP_RG DLL

DLL

current

steps

Address STD1[7:0] (L) STD2[15:8] (H)

11111000 D4 D2D6 D5 D1 D0 D12 D10D15 D14 D13 D9 D8

P_SP2 P_SP1 P_ADCLKP_RG

2,3 divided

select

Rev.1.0, Feb.12.2004, page 21 of 29

HD49335NP/HNP

• Address H’F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address
H’F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid.

D15 of address H’F8 = 0 D15 of address H’F8 = 1

Divided mode 2 divided, 1/4 phase select 3 divided, 1/6 phase select
D0 to D7 of address H’F5 Valid Invalid
D0 to D14 of address H’F8 Invalid Valid

• Phase settings of high speed pulse (address H’F5 to H’F8)
(1) Select the 1/4 phase from figure 13 at 2 divided mode (D15 = 0 of address H’F8).

Select the 1/6 phase from figure 14 at 3 divided mode (D15 = 1 of address H’F8).

·····P_SP1, P_SP2, P_ADCLK, P_RG

(2) Then select the necessary delay time from figure 15.

·····DL_SP1, DL_SP2, DL_RG, DL_ADCLK
RG can be set both of rising / falling edge optionally.

H1

Data = 0

Data = 1

Data = 2

Data = 3

P_SP1
P_SP2

H1

Data = 0

Data = 1

Data = 2

Data = 3

P_ADCLK
P_RG

Figure 13 2 Divided Mode, 1/4 Phase Select (Valid at D15 = 0 of address H’F8)

P_SP1
P_SP2

H1

Data = 5

Data = 0

Data = 1

Data = 2

Data = 3

Data = 4

P_ADCLK
P_RG

H1

Data = 0

Data = 1

Data = 2

Data = 3

Data = 4

Data = 5

Figure 14 3 Divided Mode, 1/6 Phase Select (Valid at D15 = 1 of address H’F8)

Default Value of Each Phases

P_SP1 P_SP2 P_ADCLK P_RG

2 divided mode 1 2 1 0
3 divided mode 0 3 1 5
Note: 50% of duty pulse makes tr, tf of RG by DLL.

Address STD1[7:0] (L) STD2[15:8] (H)

11110110 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8

DL_SP2 DL_SP1

CDS_test

DL_ADCLK

Address STD1[7:0] (L) STD2[15:8] (H)

11110111 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8

DL_RG_f

DL_RG_r

Dummy

clamp th

Dummy

clamp current

Rev.1.0, Feb.12.2004, page 22 of 29

HD49335NP/HNP

(3) Setting method of DLL

DLL step decides the how many divide the 1

1.
cycle of sensor CLK. For reference,
set 1 ns(when 2 ns DLL_current bit = 0,
when 1 set to 1 ns)
Can be set 16 to 64 steps by 4 steps.
Steps = 4 + (4 × N); possible to set N = 3 to 15
Recommended steps is clk_in = when 11 to 14 MHz: H'0E(60 steps)
when 14 to 22MHz: H'09(40 steps)
when 22 to 50MHz: H'1E(60 steps)
when 50 to 72MHz: H'19(40 steps)
Can be change each 4 type of pulse 0 to 15 steps with

2.
1 step. (1 ns or 2 ns divide)
Select the 2 ns divide when sensor CLK is less than

3.
15 MHz.

ADCLK(0)

(In phase with H1)

P_ADCLK

P_SP1

DLL = 64 steps

DLL = 15 steps

DLL = 15 steps

Control voltage

PC

DL_ADCLK

DLL_C

H1

DL_RG

DL_SP1

10

DL_SP2

DL_ADCLK

28140

42

56

∗Default

Figure 15 Analog Delay (DLL) Circuit Block.

• CDS_test (D12 of address H’F6)
It is testing data. Normally set to 0.

• Dummy clamp current (D9 to 8 of address H’F7)

Data = When 0, 1/4 When 1, 1/8
When 2, 1/16 When 3, 1/32

Details are refer to page 12.

• Dummy clamp threshold (D12 to 10 of address H’F7)

Data = When 0, off When 1, +32
When 2, +64 When 3, +96
When 4, +128 When 5, +160
When 6, +192 When 7, +224

Details are refer to page 12.

P_SP2

ADCLK

(0, 0)

DLL = 15 steps

DLL = 15 steps

(Falling)

(Rising)

DL_SP1

DL_SP2

AND

DL_RG

Rev.1.0, Feb.12.2004, page 23 of 29

HD49335NP/HNP

A

Operation Sequence at Power On

Must be stable within the operating
power supply voltage range

V

DD

CLK_in

3clk or more

Hardware
Reset

6clk or more

HD49335
serial data transfer

(1)

(2) (3) (4)

SP1
Start control
of TG and
camera DSP

RESET bit

utomatic offset

calibration

The following describes the above serial data transfer. For details of resistor settings are referred to serial data
function table.

(1) Resistor transfer of TG part

(2) DLL data transfer of CDS part
(3) Reset=L of CDS part
(4) Reset=H of CDS part
(5) Other data of CDS part

SP2

ADCLK

OBP

etc.

: Wait more than 6clk after release the hardware Reset and then transfer
the necessary data to TG part.
: Transfer the phase data of RG, SP1, SP2, ADCLK of CDS part.
: Transfer Reset bit = 0 of address H'F2.
: Transfer Reset bit = 1 of address H'F2. (Reset release)
: Transfer the SH_SW_fsel and other PGA.

2ms or more

(Charge of external C)

CDS_Reset = Low

Note:

At 2 divided mode: ADCLK = 1/2CLK_in
At 3 divided mode: ADCLK = 1/3CLK_in

40,000ADCLK or more

(offset calibration)

Automatic adjustment taking
40,000ADCLK period after
Reset cancellation

(5)

Before transfer the Reset bit = 0, TG series pulse need to be settled, so address

∗

H'00 to H'EF of TG part and H'F4 to H7F7 of CDS part should transfer in advance.

Rev.1.0, Feb.12.2004, page 24 of 29

HD49335NP/HNP

Timing Specifications of High Speed Pulse

• H1, H2, RG waveform

twhtr

H2

90%

10%

H1

two

tftwhtr

90%

10%

RG

tf

50%

twl

t

H1DL

50%

twl

Item

H1/H2

RG

XV1 to 4

CH1 to 4

XSUB/SUB_SW

Item

H1/H2 overlap

twh

min

typ

max

14

20

—

7

10

—

—

—

—

—

—

—

—

—

—

two Power supply specification of H1, H2, RG are 3.0 V to 3.3 V.

min12typ

max—Unit

20

min

14

—

—

—

—

ns

twl

typ

max

20

—

37

—

—

—

—

—

—

—

Values are sensor CLK = when 18 MHz.

min

—

—

—

—

—

tr

typ

8.0

4.0

20

20

20

max

14

—

—

—

—

min

—

—

—

—

—

tf

typ

8.0

4.0

20

20

20

max

14

—

—

—

—

Unit

ns

ns

ns

ns

ns

Load
capacitance

165 pF

15 pF

15 pF

15 pF

15 pF

Rev.1.0, Feb.12.2004, page 25 of 29

HD49335NP/HNP

A

r

Notice for Use

1. Careful handling is necessary to prevent damage due to static electricity.

2. This product has been developed for consumer applications, and should not be used in non-consumer applications.

3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to
prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or more should be
inserted between the ground and power supply.

4. Common connection of AV
the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.

5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure
below.

and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter,

DD

nalog

+3.0V

AV

AV

Noise filter

DD

SS

DVDD1 to 4

HD49335

DV

SS

Digital
+3.0V

DVDD1 to 4 AV

Noise filter Example of noise filte

HD49335

DV

SS

AV

DD

SS

0.01 µF

100 µH

0.01 µF

6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system
set grounds, connect to the analog system.

7. When V

is specified in the data sheet, this indicates AVDD and DVDD.

DD

8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be connected to power
supply or ground pins or left open to prevent crosstalk in adjacent analog pins.

9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of
bending than Fe-type lead material, careful handling is necessary.

10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as
solder dipping cannot be used.

11. Serial communication should not be performed during the effective video period, since this will result in degraded
picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the
HD49330AF. If ports are to be shared with another IC, picture quality should first be thoroughly checked.

12. At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in
accordance with the power-on operating sequence (see page 24).

13. Ripple noise of DC/DC converter which generates the voltage of analog part should set under –50 dB with power
supply voltage.

Rev.1.0, Feb.12.2004, page 26 of 29

HD49335NP/HNP

Example of Recommended External Circuit

• Slave mode
Pin 57(Test1 = Low)

47µ

3.0V

47µ

to V.Baff

to CCD

47µ

• Master mode
Pin 57(Test1 = Hi)

47µ

3.0V

47µ

to V.Baff

to CCD

47µ

+

0.147/6

33

34

35

36

37

38

39

40

41

42

43

33k

33k

44

45

0.1

46

0.1

47

0.1

48

0.1

CCD signal input

+

0.147/6

33

34

35

36

37

38

39

40

41

42

43

44

45

0.1

46

0.1

47

0.1

48

0.1

CCD signal input

Pin 57

Low

Slave mode

Hi

to CCD

31

XV2

XV1

3

DV

DD

XV3 VD_in

XV4
CH1

4

DV

DD

H2A

1/4clk_o

4

DV

24 23 22 21 20 19 18 1725262728293032

4

SS

SS

H1A

DV

1/2clk_o

CH2
CH3

Master mode

∗ Pin 56 = Low: TESTIN mode. Please do not use.

4

3

RG

DD

DD

HD_in

Reset

DV

DV

CLK_in

DV

DV
CH4
XSUB
SUB_SW/ADCK_in
SUB_PD
STROB/Vgate
DV

3

SS

AV

SS

ADC_in

HD49335

BIAS
VRB

DD

MON

41pin_contCSSdata

Serial data input

4

3

DD

DD

DV

DV

DV

RG

SCK

HD_in

Reset

CLK_in

DV

DV

VRT
VRM

AV

DD

+

XV3 VD_in

XV4
CH1

DD

BLKFB

BLKSH

AV

3

DV

AVSSTest2

1µ

4

DD

DD

H2A

DV

1/4clk_o

BLKC

CDS_in

50 57 58 59 60 61 62 63 6456555453525149

1µ 0.147/6 47/6

1000p 100p

31

XV2

XV1

4

DV

SS

24 23 22 21 20 19 18 1725262728293032

Test1

DLL_C

to CCD

4

SS

DV

1/2clk_o

1

DV

H1A

CH2
CH3
CH4
XSUB
SUB_SW/ADCK_in
SUB_PD
STROB/Vgate
DV

3

SS

AV

SS

ADC_in

HD49335

BIAS
VRB

DD

MON

41pin_contCSSdata

Serial data input

DV

SCK

VRT
VRM

AV

+

DD

DD

BLKFB

BLKC

50 57 58 59 60 61 62 63 6456555453525149

1000p 100p

BLKSH

CDS_in

AV

1µ

1µ 0.147/6 47/6

AVSSTest2

Test1

1

DLL_C

DV

Mode

Reset(Normally Hi)

16

15

14

3

SS

13

2

DD

12

D9

11

D8

10

D7

9

D6

8

D5

7

D4

6

D3

5

D2

4

D1

3

D0

2

1,2

SS

1

ID

Reset(Normally Hi)

16

15

14

3

SS

13

2

DD

12

D9

11

D8

10

D7

9

D6

8

D5

7

D4

6

D3

5

D2

4

D1

3

D0

2

1,2

SS

1

ID

CLK, HD, VD input from SSG.

HD, VD output

+

+

Specification

0.1

from
Pulse generator

to
Camera
signal
processor

ID pulse

∗ 61pin = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
61pin = Hi: Pin 41 is Vgate output
Pin 39 is Hiz

0.1

to
Camera
signal
processor

from
Pulse generator

to
Camera
signal
processor

ID pulse

∗ 61pin = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
61pin = Hi: Pin 41 is Vgate output
Pin 39 is Hiz

Unit: R: Ω

C: F

Rev.1.0, Feb.12.2004, page 27 of 29

HD49335NP/HNP

• CDS single operating mode
Pin 56(Test2 = Low) ∗Pin 57 is "Don't care" in this mode.

3.0V

Serial data when CDS single operation mode are following resister specifications.

(Latch timing specification is same as normal mode)

CS

SCK

SDATA

47µ

47µ

ADC_in

47µ

t

INT1

DD

Reset(Normally Hi)

Reset

DV

3

SS

DV

2

DD

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

DV

1,2

SS

SCK

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

+

0.147/6

33

34

35

36

37

38

39

40

41

42

43

44

33k

45

0.1

46

0.1

47

0.1

48

0.1

CCD signal input

31

3

4

DD

DD

DV

DV

PBLK
OBP
CP_DM
ADCK
SP2
SP1
DV

3

SS

AV

SS

ADC_in
BIAS
VRB
VRT
VRM

AV

+

DD

DD

BLKC

CDS_in

AV

BLKFB

50 57 58 59 60 61 62 63 6456555453525149

1000p 100p

BLKSH

1µ

1µ 0.147/6 47/6

24 23 22 21 20 19 18 1725262728293032

4

SS

DV

HD49335

AVSSTest2

4

SS

DV

Test1

1

DD

DLL_C

DV

4

3

DD

DV

DV

MON

41pin_contCSSdata

Serial data input

fsck

tsu

tho

D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15

0.1

to
Camera
signal
processor

∗

Pin changes are not effective with pin61.

+

Unit: R: Ω

C: F

t

INT2

D00

Low

Low

D01

Low

D02

D03

X

D04

X

D05

PGA(0) LSB

D06

PGA(1)

D07

PGA(2)

D08

PGA(3)

PGA(4)

D09

PGA(5)

D10

PGA(6)

D11

PGA(7) MSB

D12

Test_I1 (0)

D13

D14

Test_I1 (1)

D15 Test_I1 (2)

0

High

0

Low

0

Low

Low: Normal

0

SLP

High: Sleep
Low: Normal

0

STBY

High: Standby

0

Output mode(LINV)

0

Output mode(MINV)

0

Output mode(Test0)

0

SHA-fsel(0)

0

SHA-fsel(1)

0

SHSW-fsel(0)

0

SHSW-fsel(1)

0

SHSW-fsel(2)

SHSW-fsel(3)

0

Test_I2 (0)

0

1

Test_I2 (1)

Low

1

High

0

Low

0

0

Clamp(0)

Clamp(1)

0

Clamp(2)

0

0

Clamp(3)

Clamp(4)

0

HGstop-Hsel(0)

0

HGstop-Hsel(1)

0

HGain-Nsel(0)

0

HGain-Nsel(1)

0

Low: Normal

LoPwr

0

High: Low power

X

0

Low:CDSin

ADSEL

0

High:ADin

Low: Reset

0

Reset

High: Normal

Resister 4Resister 3Resister 0 Resister 1 Resister 7Resister 5 Resister 6Resister 2

High

0

High

1

Low

0

1

0

0

1

0

0

0

test

0

0

1

0

0

1

1

1

0

0

MON(0)

0

MON(1)

0

MON(2)

0

H12Baff(0)

0

H12Baff(1)

0

H12Baff(2)

0

H12Baff(3)

VD latch

0

Gray1

0

Gray2

0

Gray_ts(0)

0

Gray_ts(1)

0

0

Gray_ts(2)

Low

Low

High

High

0

0

Low

1

High

0

P_SP1(0)

0

P_SP1(1)

0

P_SP2(0)

0

P_SP2(1)

P_ADCLK(0)

0

P_ADCLK(1)

0

1

P_RG(0)

P_RG(1)

0

DLL_CK(0)

0

0

DLL_CK(1)

0

DLL_CK(2)

0

DLL_CK(3)

0

DLL_current

Low

1

High

0

High

1

DL_SP1(0)

1

DL_SP1(1)

0

DL_SP1(2)

1

DL_SP1(3)

1

DL_SP2(0)

1

DL_SP2(1)

0

DL_SP2(2)

0

DL_SP2(3)

0

DL_ADCLK(0)

1

DL_ADCLK(1)

0

DL_ADCLK(2)

1

DL_ADCLK(3)

1

1

CDS_test

High

0

High

1

High

1

DL_RG_r(0)

0

DL_RG_r(1)

0

DL_RG_r(2)

0

DL_RG_r(3)

0

DL_RG_f(0)

0

DL_RG_f(1)

0

DL_RG_f(2)

0

DL_RG_f(3)

0

DMCG(0)

0

DMCG(1)

0

Dummy CP(0)

0

Dummy CP(1)

0

0

Dummy CP(2)

1

1

1

0

0

0

0

0

1

0

1

0

0

0

0

0

Rev.1.0, Feb.12.2004, page 28 of 29

HD49335NP/HNP

Package Dimensions

9.00 ± 0.1

8.80

Unit: mm

Part A

C

(0.20)

A B

C0.50
Index

1 9

0.65

S

0.80 Max

0.40 ± 0.1

0.50

S

0.05

0.20 ± 0.05

Enlargement of Part A

8.80

0.65

C0.10

9.00 ± 0.1

0.40 ± 0.1

(3.82)

(φ0.2)

0.05 M

TNP-64AV
—
—

0.14 g

S

A-B C

(0.16)

0.20 ± 0.05

Package Code
JEDEC
JEITA

(reference value)

Mass

Rev.1.0, Feb.12.2004, page 29 of 29

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Keep safety first in your circuit designs!

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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

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